1 //===-- FastISel.h - Definition of the FastISel class ---------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the FastISel class.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_CODEGEN_FASTISEL_H
15 #define LLVM_CODEGEN_FASTISEL_H
17 #include "llvm/ADT/DenseMap.h"
18 #include "llvm/CodeGen/ValueTypes.h"
19 #include "llvm/CodeGen/MachineBasicBlock.h"
26 class FunctionLoweringInfo;
29 class MachineBasicBlock;
30 class MachineConstantPool;
31 class MachineFunction;
33 class MachineFrameInfo;
34 class MachineRegisterInfo;
36 class TargetInstrInfo;
37 class TargetLibraryInfo;
40 class TargetRegisterClass;
41 class TargetRegisterInfo;
45 /// FastISel - This is a fast-path instruction selection class that
46 /// generates poor code and doesn't support illegal types or non-trivial
47 /// lowering, but runs quickly.
50 DenseMap<const Value *, unsigned> LocalValueMap;
51 FunctionLoweringInfo &FuncInfo;
52 MachineRegisterInfo &MRI;
53 MachineFrameInfo &MFI;
54 MachineConstantPool &MCP;
56 const TargetMachine &TM;
58 const TargetInstrInfo &TII;
59 const TargetLowering &TLI;
60 const TargetRegisterInfo &TRI;
61 const TargetLibraryInfo *LibInfo;
63 /// The position of the last instruction for materializing constants
64 /// for use in the current block. It resets to EmitStartPt when it
65 /// makes sense (for example, it's usually profitable to avoid function
66 /// calls between the definition and the use)
67 MachineInstr *LastLocalValue;
69 /// The top most instruction in the current block that is allowed for
70 /// emitting local variables. LastLocalValue resets to EmitStartPt when
71 /// it makes sense (for example, on function calls)
72 MachineInstr *EmitStartPt;
75 /// getLastLocalValue - Return the position of the last instruction
76 /// emitted for materializing constants for use in the current block.
77 MachineInstr *getLastLocalValue() { return LastLocalValue; }
79 /// setLastLocalValue - Update the position of the last instruction
80 /// emitted for materializing constants for use in the current block.
81 void setLastLocalValue(MachineInstr *I) {
86 /// startNewBlock - Set the current block to which generated machine
87 /// instructions will be appended, and clear the local CSE map.
91 /// getCurDebugLoc() - Return current debug location information.
92 DebugLoc getCurDebugLoc() const { return DL; }
94 /// SelectInstruction - Do "fast" instruction selection for the given
95 /// LLVM IR instruction, and append generated machine instructions to
96 /// the current block. Return true if selection was successful.
98 bool SelectInstruction(const Instruction *I);
100 /// SelectOperator - Do "fast" instruction selection for the given
101 /// LLVM IR operator (Instruction or ConstantExpr), and append
102 /// generated machine instructions to the current block. Return true
103 /// if selection was successful.
105 bool SelectOperator(const User *I, unsigned Opcode);
107 /// getRegForValue - Create a virtual register and arrange for it to
108 /// be assigned the value for the given LLVM value.
109 unsigned getRegForValue(const Value *V);
111 /// lookUpRegForValue - Look up the value to see if its value is already
112 /// cached in a register. It may be defined by instructions across blocks or
114 unsigned lookUpRegForValue(const Value *V);
116 /// getRegForGEPIndex - This is a wrapper around getRegForValue that also
117 /// takes care of truncating or sign-extending the given getelementptr
119 std::pair<unsigned, bool> getRegForGEPIndex(const Value *V);
121 /// TryToFoldLoad - The specified machine instr operand is a vreg, and that
122 /// vreg is being provided by the specified load instruction. If possible,
123 /// try to fold the load as an operand to the instruction, returning true if
125 virtual bool TryToFoldLoad(MachineInstr * /*MI*/, unsigned /*OpNo*/,
126 const LoadInst * /*LI*/) {
130 /// recomputeInsertPt - Reset InsertPt to prepare for inserting instructions
131 /// into the current block.
132 void recomputeInsertPt();
134 /// enterLocalValueArea - Prepare InsertPt to begin inserting instructions
135 /// into the local value area and return the old insert position.
136 MachineBasicBlock::iterator enterLocalValueArea();
138 /// leaveLocalValueArea - Reset InsertPt to the given old insert position.
139 void leaveLocalValueArea(MachineBasicBlock::iterator Old);
144 explicit FastISel(FunctionLoweringInfo &funcInfo,
145 const TargetLibraryInfo *libInfo);
147 /// TargetSelectInstruction - This method is called by target-independent
148 /// code when the normal FastISel process fails to select an instruction.
149 /// This gives targets a chance to emit code for anything that doesn't
150 /// fit into FastISel's framework. It returns true if it was successful.
153 TargetSelectInstruction(const Instruction *I) = 0;
155 /// FastEmit_r - This method is called by target-independent code
156 /// to request that an instruction with the given type and opcode
158 virtual unsigned FastEmit_(MVT VT,
162 /// FastEmit_r - This method is called by target-independent code
163 /// to request that an instruction with the given type, opcode, and
164 /// register operand be emitted.
166 virtual unsigned FastEmit_r(MVT VT,
169 unsigned Op0, bool Op0IsKill);
171 /// FastEmit_rr - This method is called by target-independent code
172 /// to request that an instruction with the given type, opcode, and
173 /// register operands be emitted.
175 virtual unsigned FastEmit_rr(MVT VT,
178 unsigned Op0, bool Op0IsKill,
179 unsigned Op1, bool Op1IsKill);
181 /// FastEmit_ri - This method is called by target-independent code
182 /// to request that an instruction with the given type, opcode, and
183 /// register and immediate operands be emitted.
185 virtual unsigned FastEmit_ri(MVT VT,
188 unsigned Op0, bool Op0IsKill,
191 /// FastEmit_rf - This method is called by target-independent code
192 /// to request that an instruction with the given type, opcode, and
193 /// register and floating-point immediate operands be emitted.
195 virtual unsigned FastEmit_rf(MVT VT,
198 unsigned Op0, bool Op0IsKill,
199 const ConstantFP *FPImm);
201 /// FastEmit_rri - This method is called by target-independent code
202 /// to request that an instruction with the given type, opcode, and
203 /// register and immediate operands be emitted.
205 virtual unsigned FastEmit_rri(MVT VT,
208 unsigned Op0, bool Op0IsKill,
209 unsigned Op1, bool Op1IsKill,
212 /// FastEmit_ri_ - This method is a wrapper of FastEmit_ri. It first tries
213 /// to emit an instruction with an immediate operand using FastEmit_ri.
214 /// If that fails, it materializes the immediate into a register and try
215 /// FastEmit_rr instead.
216 unsigned FastEmit_ri_(MVT VT,
218 unsigned Op0, bool Op0IsKill,
219 uint64_t Imm, MVT ImmType);
221 /// FastEmit_i - This method is called by target-independent code
222 /// to request that an instruction with the given type, opcode, and
223 /// immediate operand be emitted.
224 virtual unsigned FastEmit_i(MVT VT,
229 /// FastEmit_f - This method is called by target-independent code
230 /// to request that an instruction with the given type, opcode, and
231 /// floating-point immediate operand be emitted.
232 virtual unsigned FastEmit_f(MVT VT,
235 const ConstantFP *FPImm);
237 /// FastEmitInst_ - Emit a MachineInstr with no operands and a
238 /// result register in the given register class.
240 unsigned FastEmitInst_(unsigned MachineInstOpcode,
241 const TargetRegisterClass *RC);
243 /// FastEmitInst_r - Emit a MachineInstr with one register operand
244 /// and a result register in the given register class.
246 unsigned FastEmitInst_r(unsigned MachineInstOpcode,
247 const TargetRegisterClass *RC,
248 unsigned Op0, bool Op0IsKill);
250 /// FastEmitInst_rr - Emit a MachineInstr with two register operands
251 /// and a result register in the given register class.
253 unsigned FastEmitInst_rr(unsigned MachineInstOpcode,
254 const TargetRegisterClass *RC,
255 unsigned Op0, bool Op0IsKill,
256 unsigned Op1, bool Op1IsKill);
258 /// FastEmitInst_rrr - Emit a MachineInstr with three register operands
259 /// and a result register in the given register class.
261 unsigned FastEmitInst_rrr(unsigned MachineInstOpcode,
262 const TargetRegisterClass *RC,
263 unsigned Op0, bool Op0IsKill,
264 unsigned Op1, bool Op1IsKill,
265 unsigned Op2, bool Op2IsKill);
267 /// FastEmitInst_ri - Emit a MachineInstr with a register operand,
268 /// an immediate, and a result register in the given register class.
270 unsigned FastEmitInst_ri(unsigned MachineInstOpcode,
271 const TargetRegisterClass *RC,
272 unsigned Op0, bool Op0IsKill,
275 /// FastEmitInst_rii - Emit a MachineInstr with one register operand
276 /// and two immediate operands.
278 unsigned FastEmitInst_rii(unsigned MachineInstOpcode,
279 const TargetRegisterClass *RC,
280 unsigned Op0, bool Op0IsKill,
281 uint64_t Imm1, uint64_t Imm2);
283 /// FastEmitInst_rf - Emit a MachineInstr with two register operands
284 /// and a result register in the given register class.
286 unsigned FastEmitInst_rf(unsigned MachineInstOpcode,
287 const TargetRegisterClass *RC,
288 unsigned Op0, bool Op0IsKill,
289 const ConstantFP *FPImm);
291 /// FastEmitInst_rri - Emit a MachineInstr with two register operands,
292 /// an immediate, and a result register in the given register class.
294 unsigned FastEmitInst_rri(unsigned MachineInstOpcode,
295 const TargetRegisterClass *RC,
296 unsigned Op0, bool Op0IsKill,
297 unsigned Op1, bool Op1IsKill,
300 /// FastEmitInst_rrii - Emit a MachineInstr with two register operands,
301 /// two immediates operands, and a result register in the given register
303 unsigned FastEmitInst_rrii(unsigned MachineInstOpcode,
304 const TargetRegisterClass *RC,
305 unsigned Op0, bool Op0IsKill,
306 unsigned Op1, bool Op1IsKill,
307 uint64_t Imm1, uint64_t Imm2);
309 /// FastEmitInst_i - Emit a MachineInstr with a single immediate
310 /// operand, and a result register in the given register class.
311 unsigned FastEmitInst_i(unsigned MachineInstrOpcode,
312 const TargetRegisterClass *RC,
315 /// FastEmitInst_ii - Emit a MachineInstr with a two immediate operands.
316 unsigned FastEmitInst_ii(unsigned MachineInstrOpcode,
317 const TargetRegisterClass *RC,
318 uint64_t Imm1, uint64_t Imm2);
320 /// FastEmitInst_extractsubreg - Emit a MachineInstr for an extract_subreg
321 /// from a specified index of a superregister to a specified type.
322 unsigned FastEmitInst_extractsubreg(MVT RetVT,
323 unsigned Op0, bool Op0IsKill,
326 /// FastEmitZExtFromI1 - Emit MachineInstrs to compute the value of Op
327 /// with all but the least significant bit set to zero.
328 unsigned FastEmitZExtFromI1(MVT VT,
329 unsigned Op0, bool Op0IsKill);
331 /// FastEmitBranch - Emit an unconditional branch to the given block,
332 /// unless it is the immediate (fall-through) successor, and update
334 void FastEmitBranch(MachineBasicBlock *MBB, DebugLoc DL);
336 void UpdateValueMap(const Value* I, unsigned Reg, unsigned NumRegs = 1);
338 unsigned createResultReg(const TargetRegisterClass *RC);
340 /// TargetMaterializeConstant - Emit a constant in a register using
341 /// target-specific logic, such as constant pool loads.
342 virtual unsigned TargetMaterializeConstant(const Constant* C) {
346 /// TargetMaterializeAlloca - Emit an alloca address in a register using
347 /// target-specific logic.
348 virtual unsigned TargetMaterializeAlloca(const AllocaInst* C) {
352 virtual unsigned TargetMaterializeFloatZero(const ConstantFP* CF) {
357 bool SelectBinaryOp(const User *I, unsigned ISDOpcode);
359 bool SelectFNeg(const User *I);
361 bool SelectGetElementPtr(const User *I);
363 bool SelectCall(const User *I);
365 bool SelectBitCast(const User *I);
367 bool SelectCast(const User *I, unsigned Opcode);
369 bool SelectExtractValue(const User *I);
371 bool SelectInsertValue(const User *I);
373 /// HandlePHINodesInSuccessorBlocks - Handle PHI nodes in successor blocks.
374 /// Emit code to ensure constants are copied into registers when needed.
375 /// Remember the virtual registers that need to be added to the Machine PHI
376 /// nodes as input. We cannot just directly add them, because expansion
377 /// might result in multiple MBB's for one BB. As such, the start of the
378 /// BB might correspond to a different MBB than the end.
379 bool HandlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB);
381 /// materializeRegForValue - Helper for getRegForVale. This function is
382 /// called when the value isn't already available in a register and must
383 /// be materialized with new instructions.
384 unsigned materializeRegForValue(const Value *V, MVT VT);
386 /// flushLocalValueMap - clears LocalValueMap and moves the area for the
387 /// new local variables to the beginning of the block. It helps to avoid
388 /// spilling cached variables across heavy instructions like calls.
389 void flushLocalValueMap();
391 /// hasTrivialKill - Test whether the given value has exactly one use.
392 bool hasTrivialKill(const Value *V) const;
394 /// removeDeadCode - Remove all dead instructions between the I and E.
395 void removeDeadCode(MachineBasicBlock::iterator I,
396 MachineBasicBlock::iterator E);