1 //===-- FastISel.h - Definition of the FastISel class ---------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the FastISel class.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_CODEGEN_FASTISEL_H
15 #define LLVM_CODEGEN_FASTISEL_H
17 #include "llvm/ADT/DenseMap.h"
18 #include "llvm/ADT/SmallSet.h"
19 #include "llvm/CodeGen/SelectionDAGNodes.h"
26 class MachineBasicBlock;
27 class MachineConstantPool;
28 class MachineFunction;
29 class MachineFrameInfo;
30 class MachineModuleInfo;
32 class MachineRegisterInfo;
34 class TargetInstrInfo;
37 class TargetRegisterClass;
39 /// FastISel - This is a fast-path instruction selection class that
40 /// generates poor code and doesn't support illegal types or non-trivial
41 /// lowering, but runs quickly.
44 MachineBasicBlock *MBB;
45 DenseMap<const Value *, unsigned> LocalValueMap;
46 DenseMap<const Value *, unsigned> &ValueMap;
47 DenseMap<const BasicBlock *, MachineBasicBlock *> &MBBMap;
48 DenseMap<const AllocaInst *, int> &StaticAllocaMap;
50 SmallSet<Instruction*, 8> &CatchInfoLost;
53 MachineModuleInfo *MMI;
55 MachineRegisterInfo &MRI;
56 MachineFrameInfo &MFI;
57 MachineConstantPool &MCP;
58 const TargetMachine &TM;
60 const TargetInstrInfo &TII;
61 const TargetLowering &TLI;
64 /// startNewBlock - Set the current block, to which generated
65 /// machine instructions will be appended, and clear the local
68 void startNewBlock(MachineBasicBlock *mbb) {
70 LocalValueMap.clear();
73 /// setCurrentBlock - Set the current block, to which generated
74 /// machine instructions will be appended.
76 void setCurrentBlock(MachineBasicBlock *mbb) {
80 /// SelectInstruction - Do "fast" instruction selection for the given
81 /// LLVM IR instruction, and append generated machine instructions to
82 /// the current block. Return true if selection was successful.
84 bool SelectInstruction(Instruction *I);
86 /// SelectInstruction - Do "fast" instruction selection for the given
87 /// LLVM IR operator (Instruction or ConstantExpr), and append
88 /// generated machine instructions to the current block. Return true
89 /// if selection was successful.
91 bool SelectOperator(User *I, unsigned Opcode);
93 /// TargetSelectInstruction - This method is called by target-independent
94 /// code when the normal FastISel process fails to select an instruction.
95 /// This gives targets a chance to emit code for anything that doesn't
96 /// fit into FastISel's framework. It returns true if it was successful.
99 TargetSelectInstruction(Instruction *I) = 0;
101 /// getRegForValue - Create a virtual register and arrange for it to
102 /// be assigned the value for the given LLVM value.
103 unsigned getRegForValue(Value *V);
105 /// lookUpRegForValue - Look up the value to see if its value is already
106 /// cached in a register. It may be defined by instructions across blocks or
108 unsigned lookUpRegForValue(Value *V);
110 /// getRegForGEPIndex - This is a wrapper around getRegForValue that also
111 /// takes care of truncating or sign-extending the given getelementptr
113 unsigned getRegForGEPIndex(Value *V);
118 FastISel(MachineFunction &mf,
119 MachineModuleInfo *mmi,
121 DenseMap<const Value *, unsigned> &vm,
122 DenseMap<const BasicBlock *, MachineBasicBlock *> &bm,
123 DenseMap<const AllocaInst *, int> &am
125 , SmallSet<Instruction*, 8> &cil
129 /// FastEmit_r - This method is called by target-independent code
130 /// to request that an instruction with the given type and opcode
132 virtual unsigned FastEmit_(MVT::SimpleValueType VT,
133 MVT::SimpleValueType RetVT,
134 ISD::NodeType Opcode);
136 /// FastEmit_r - This method is called by target-independent code
137 /// to request that an instruction with the given type, opcode, and
138 /// register operand be emitted.
140 virtual unsigned FastEmit_r(MVT::SimpleValueType VT,
141 MVT::SimpleValueType RetVT,
142 ISD::NodeType Opcode, unsigned Op0);
144 /// FastEmit_rr - This method is called by target-independent code
145 /// to request that an instruction with the given type, opcode, and
146 /// register operands be emitted.
148 virtual unsigned FastEmit_rr(MVT::SimpleValueType VT,
149 MVT::SimpleValueType RetVT,
150 ISD::NodeType Opcode,
151 unsigned Op0, unsigned Op1);
153 /// FastEmit_ri - This method is called by target-independent code
154 /// to request that an instruction with the given type, opcode, and
155 /// register and immediate operands be emitted.
157 virtual unsigned FastEmit_ri(MVT::SimpleValueType VT,
158 MVT::SimpleValueType RetVT,
159 ISD::NodeType Opcode,
160 unsigned Op0, uint64_t Imm);
162 /// FastEmit_rf - This method is called by target-independent code
163 /// to request that an instruction with the given type, opcode, and
164 /// register and floating-point immediate operands be emitted.
166 virtual unsigned FastEmit_rf(MVT::SimpleValueType VT,
167 MVT::SimpleValueType RetVT,
168 ISD::NodeType Opcode,
169 unsigned Op0, ConstantFP *FPImm);
171 /// FastEmit_rri - This method is called by target-independent code
172 /// to request that an instruction with the given type, opcode, and
173 /// register and immediate operands be emitted.
175 virtual unsigned FastEmit_rri(MVT::SimpleValueType VT,
176 MVT::SimpleValueType RetVT,
177 ISD::NodeType Opcode,
178 unsigned Op0, unsigned Op1, uint64_t Imm);
180 /// FastEmit_ri_ - This method is a wrapper of FastEmit_ri. It first tries
181 /// to emit an instruction with an immediate operand using FastEmit_ri.
182 /// If that fails, it materializes the immediate into a register and try
183 /// FastEmit_rr instead.
184 unsigned FastEmit_ri_(MVT::SimpleValueType VT,
185 ISD::NodeType Opcode,
186 unsigned Op0, uint64_t Imm,
187 MVT::SimpleValueType ImmType);
189 /// FastEmit_rf_ - This method is a wrapper of FastEmit_rf. It first tries
190 /// to emit an instruction with an immediate operand using FastEmit_rf.
191 /// If that fails, it materializes the immediate into a register and try
192 /// FastEmit_rr instead.
193 unsigned FastEmit_rf_(MVT::SimpleValueType VT,
194 ISD::NodeType Opcode,
195 unsigned Op0, ConstantFP *FPImm,
196 MVT::SimpleValueType ImmType);
198 /// FastEmit_i - This method is called by target-independent code
199 /// to request that an instruction with the given type, opcode, and
200 /// immediate operand be emitted.
201 virtual unsigned FastEmit_i(MVT::SimpleValueType VT,
202 MVT::SimpleValueType RetVT,
203 ISD::NodeType Opcode,
206 /// FastEmit_f - This method is called by target-independent code
207 /// to request that an instruction with the given type, opcode, and
208 /// floating-point immediate operand be emitted.
209 virtual unsigned FastEmit_f(MVT::SimpleValueType VT,
210 MVT::SimpleValueType RetVT,
211 ISD::NodeType Opcode,
214 /// FastEmitInst_ - Emit a MachineInstr with no operands and a
215 /// result register in the given register class.
217 unsigned FastEmitInst_(unsigned MachineInstOpcode,
218 const TargetRegisterClass *RC);
220 /// FastEmitInst_r - Emit a MachineInstr with one register operand
221 /// and a result register in the given register class.
223 unsigned FastEmitInst_r(unsigned MachineInstOpcode,
224 const TargetRegisterClass *RC,
227 /// FastEmitInst_rr - Emit a MachineInstr with two register operands
228 /// and a result register in the given register class.
230 unsigned FastEmitInst_rr(unsigned MachineInstOpcode,
231 const TargetRegisterClass *RC,
232 unsigned Op0, unsigned Op1);
234 /// FastEmitInst_ri - Emit a MachineInstr with two register operands
235 /// and a result register in the given register class.
237 unsigned FastEmitInst_ri(unsigned MachineInstOpcode,
238 const TargetRegisterClass *RC,
239 unsigned Op0, uint64_t Imm);
241 /// FastEmitInst_rf - Emit a MachineInstr with two register operands
242 /// and a result register in the given register class.
244 unsigned FastEmitInst_rf(unsigned MachineInstOpcode,
245 const TargetRegisterClass *RC,
246 unsigned Op0, ConstantFP *FPImm);
248 /// FastEmitInst_rri - Emit a MachineInstr with two register operands,
249 /// an immediate, and a result register in the given register class.
251 unsigned FastEmitInst_rri(unsigned MachineInstOpcode,
252 const TargetRegisterClass *RC,
253 unsigned Op0, unsigned Op1, uint64_t Imm);
255 /// FastEmitInst_i - Emit a MachineInstr with a single immediate
256 /// operand, and a result register in the given register class.
257 unsigned FastEmitInst_i(unsigned MachineInstrOpcode,
258 const TargetRegisterClass *RC,
261 /// FastEmitInst_extractsubreg - Emit a MachineInstr for an extract_subreg
262 /// from a specified index of a superregister.
263 unsigned FastEmitInst_extractsubreg(unsigned Op0, uint32_t Idx);
265 /// FastEmitBranch - Emit an unconditional branch to the given block,
266 /// unless it is the immediate (fall-through) successor, and update
268 void FastEmitBranch(MachineBasicBlock *MBB);
270 void UpdateValueMap(Value* I, unsigned Reg);
272 unsigned createResultReg(const TargetRegisterClass *RC);
274 /// TargetMaterializeConstant - Emit a constant in a register using
275 /// target-specific logic, such as constant pool loads.
276 virtual unsigned TargetMaterializeConstant(Constant* C) {
280 /// TargetMaterializeAlloca - Emit an alloca address in a register using
281 /// target-specific logic.
282 virtual unsigned TargetMaterializeAlloca(AllocaInst* C) {
287 bool SelectBinaryOp(User *I, ISD::NodeType ISDOpcode);
289 bool SelectGetElementPtr(User *I);
291 bool SelectCall(User *I);
293 bool SelectBitCast(User *I);
295 bool SelectCast(User *I, ISD::NodeType Opcode);