1 //===- CodeGen/Analysis.h - CodeGen LLVM IR Analysis Utilities --*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file declares several CodeGen-specific LLVM IR analysis utilities.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_CODEGEN_ANALYSIS_H
15 #define LLVM_CODEGEN_ANALYSIS_H
17 #include "llvm/ADT/ArrayRef.h"
18 #include "llvm/ADT/SmallVector.h"
19 #include "llvm/CodeGen/ISDOpcodes.h"
20 #include "llvm/IR/CallSite.h"
21 #include "llvm/IR/InlineAsm.h"
22 #include "llvm/IR/Instructions.h"
26 class TargetLoweringBase;
34 /// ComputeLinearIndex - Given an LLVM IR aggregate type and a sequence
35 /// of insertvalue or extractvalue indices that identify a member, return
36 /// the linearized index of the start of the member.
38 unsigned ComputeLinearIndex(Type *Ty,
39 const unsigned *Indices,
40 const unsigned *IndicesEnd,
41 unsigned CurIndex = 0);
43 inline unsigned ComputeLinearIndex(Type *Ty,
44 ArrayRef<unsigned> Indices,
45 unsigned CurIndex = 0) {
46 return ComputeLinearIndex(Ty, Indices.begin(), Indices.end(), CurIndex);
49 /// ComputeValueVTs - Given an LLVM IR type, compute a sequence of
50 /// EVTs that represent all the individual underlying
51 /// non-aggregate types that comprise it.
53 /// If Offsets is non-null, it points to a vector to be filled in
54 /// with the in-memory offsets of each of the individual values.
56 void ComputeValueVTs(const TargetLowering &TLI, Type *Ty,
57 SmallVectorImpl<EVT> &ValueVTs,
58 SmallVectorImpl<uint64_t> *Offsets = nullptr,
59 uint64_t StartingOffset = 0);
61 /// ExtractTypeInfo - Returns the type info, possibly bitcast, encoded in V.
62 GlobalVariable *ExtractTypeInfo(Value *V);
64 /// hasInlineAsmMemConstraint - Return true if the inline asm instruction being
65 /// processed uses a memory 'm' constraint.
66 bool hasInlineAsmMemConstraint(InlineAsm::ConstraintInfoVector &CInfos,
67 const TargetLowering &TLI);
69 /// getFCmpCondCode - Return the ISD condition code corresponding to
70 /// the given LLVM IR floating-point condition code. This includes
71 /// consideration of global floating-point math flags.
73 ISD::CondCode getFCmpCondCode(FCmpInst::Predicate Pred);
75 /// getFCmpCodeWithoutNaN - Given an ISD condition code comparing floats,
76 /// return the equivalent code if we're allowed to assume that NaNs won't occur.
77 ISD::CondCode getFCmpCodeWithoutNaN(ISD::CondCode CC);
79 /// getICmpCondCode - Return the ISD condition code corresponding to
80 /// the given LLVM IR integer condition code.
82 ISD::CondCode getICmpCondCode(ICmpInst::Predicate Pred);
84 /// Test if the given instruction is in a position to be optimized
85 /// with a tail-call. This roughly means that it's in a block with
86 /// a return and there's nothing that needs to be scheduled
87 /// between it and the return.
89 /// This function only tests target-independent requirements.
90 bool isInTailCallPosition(ImmutableCallSite CS, const TargetMachine &TM,
91 const TargetLoweringBase &TLI);
93 /// Test if given that the input instruction is in the tail call position if the
94 /// return type or any attributes of the function will inhibit tail call
96 bool returnTypeIsEligibleForTailCall(const Function *F,
98 const ReturnInst *Ret,
99 const TargetLoweringBase &TLI);
101 } // End llvm namespace