1 //===- CodeGen/Analysis.h - CodeGen LLVM IR Analysis Utilities --*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file declares several CodeGen-specific LLVM IR analysis utilties.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_CODEGEN_ANALYSIS_H
15 #define LLVM_CODEGEN_ANALYSIS_H
17 #include "llvm/Instructions.h"
18 #include "llvm/InlineAsm.h"
19 #include "llvm/ADT/ArrayRef.h"
20 #include "llvm/ADT/SmallVector.h"
21 #include "llvm/CodeGen/ValueTypes.h"
22 #include "llvm/CodeGen/ISDOpcodes.h"
23 #include "llvm/Support/CallSite.h"
33 /// ComputeLinearIndex - Given an LLVM IR aggregate type and a sequence
34 /// of insertvalue or extractvalue indices that identify a member, return
35 /// the linearized index of the start of the member.
37 unsigned ComputeLinearIndex(Type *Ty,
38 const unsigned *Indices,
39 const unsigned *IndicesEnd,
40 unsigned CurIndex = 0);
42 inline unsigned ComputeLinearIndex(Type *Ty,
43 ArrayRef<unsigned> Indices,
44 unsigned CurIndex = 0) {
45 return ComputeLinearIndex(Ty, Indices.begin(), Indices.end(), CurIndex);
48 /// ComputeValueVTs - Given an LLVM IR type, compute a sequence of
49 /// EVTs that represent all the individual underlying
50 /// non-aggregate types that comprise it.
52 /// If Offsets is non-null, it points to a vector to be filled in
53 /// with the in-memory offsets of each of the individual values.
55 void ComputeValueVTs(const TargetLowering &TLI, Type *Ty,
56 SmallVectorImpl<EVT> &ValueVTs,
57 SmallVectorImpl<uint64_t> *Offsets = 0,
58 uint64_t StartingOffset = 0);
60 /// ExtractTypeInfo - Returns the type info, possibly bitcast, encoded in V.
61 GlobalVariable *ExtractTypeInfo(Value *V);
63 /// hasInlineAsmMemConstraint - Return true if the inline asm instruction being
64 /// processed uses a memory 'm' constraint.
65 bool hasInlineAsmMemConstraint(InlineAsm::ConstraintInfoVector &CInfos,
66 const TargetLowering &TLI);
68 /// getFCmpCondCode - Return the ISD condition code corresponding to
69 /// the given LLVM IR floating-point condition code. This includes
70 /// consideration of global floating-point math flags.
72 ISD::CondCode getFCmpCondCode(FCmpInst::Predicate Pred);
74 /// getFCmpCodeWithoutNaN - Given an ISD condition code comparing floats,
75 /// return the equivalent code if we're allowed to assume that NaNs won't occur.
76 ISD::CondCode getFCmpCodeWithoutNaN(ISD::CondCode CC);
78 /// getICmpCondCode - Return the ISD condition code corresponding to
79 /// the given LLVM IR integer condition code.
81 ISD::CondCode getICmpCondCode(ICmpInst::Predicate Pred);
83 /// Test if the given instruction is in a position to be optimized
84 /// with a tail-call. This roughly means that it's in a block with
85 /// a return and there's nothing that needs to be scheduled
86 /// between it and the return.
88 /// This function only tests target-independent requirements.
89 bool isInTailCallPosition(ImmutableCallSite CS, Attributes CalleeRetAttr,
90 const TargetLowering &TLI);
92 bool isInTailCallPosition(SelectionDAG &DAG, SDNode *Node,
93 SDValue &Chain, const TargetLowering &TLI);
95 } // End llvm namespace