2 * Copyright (c) 2015 Heiko Stuebner <heiko@sntech.de>
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
15 #ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3368_H
16 #define _DT_BINDINGS_CLK_ROCKCHIP_RK3368_H
28 /* sclk gates (special clocks) */
29 #define SCLK_GPU_CORE 64
37 #define SCLK_SARADC 73
38 #define SCLK_NANDC0 75
44 #define SCLK_I2S_8CH 82
45 #define SCLK_SPDIF_8CH 83
46 #define SCLK_I2S_2CH 84
47 #define SCLK_TIMER00 85
48 #define SCLK_TIMER01 86
49 #define SCLK_TIMER02 87
50 #define SCLK_TIMER03 88
51 #define SCLK_TIMER04 89
52 #define SCLK_TIMER05 90
53 #define SCLK_OTGPHY0 93
54 #define SCLK_OTG_ADP 96
55 #define SCLK_HSICPHY480M 97
56 #define SCLK_HSICPHY12M 98
57 #define SCLK_MACREF 99
58 #define SCLK_VOP0_PWM 100
59 #define SCLK_MAC_RX 102
60 #define SCLK_MAC_TX 103
61 #define SCLK_EDP_24M 104
66 #define SCLK_HDMI_HDCP 109
67 #define SCLK_HDMI_CEC 110
68 #define SCLK_HEVC_CABAC 111
69 #define SCLK_HEVC_CORE 112
70 #define SCLK_I2S_8CH_OUT 113
71 #define SCLK_SDMMC_DRV 114
72 #define SCLK_SDIO0_DRV 115
73 #define SCLK_EMMC_DRV 117
74 #define SCLK_SDMMC_SAMPLE 118
75 #define SCLK_SDIO0_SAMPLE 119
76 #define SCLK_EMMC_SAMPLE 121
77 #define SCLK_USBPHY480M 122
78 #define SCLK_PVTM_CORE 123
79 #define SCLK_PVTM_GPU 124
80 #define SCLK_PVTM_PMU 125
83 #define SCLK_MACREF_OUT 128
84 #define SCLK_MIPIDSI_24M 129
85 #define SCLK_CRYPTO 130
86 #define SCLK_VIP_SRC 131
87 #define SCLK_VIP_OUT 132
88 #define SCLK_TIMER10 133
89 #define SCLK_TIMER11 134
90 #define SCLK_TIMER12 135
91 #define SCLK_TIMER13 136
92 #define SCLK_TIMER14 137
93 #define SCLK_TIMER15 138
94 #define SCLK_DDRCLK 139
97 #define MCLK_CRYPTO 191
100 #define ACLK_GPU_MEM 192
101 #define ACLK_GPU_CFG 193
102 #define ACLK_DMAC_BUS 194
103 #define ACLK_DMAC_PERI 195
104 #define ACLK_PERI_MMU 196
105 #define ACLK_GMAC 197
107 #define ACLK_VOP_IEP 199
109 #define ACLK_HDCP 201
111 #define ACLK_VIO0_NOC 203
114 #define ACLK_VIO1_NOC 206
115 #define ACLK_VIDEO 208
117 #define ACLK_PERI 210
118 #define ACLK_CCI_PRE 211
121 #define PCLK_GPIO0 320
122 #define PCLK_GPIO1 321
123 #define PCLK_GPIO2 322
124 #define PCLK_GPIO3 323
125 #define PCLK_PMUGRF 324
126 #define PCLK_MAILBOX 325
128 #define PCLK_SGRF 330
130 #define PCLK_I2C0 332
131 #define PCLK_I2C1 333
132 #define PCLK_I2C2 334
133 #define PCLK_I2C3 335
134 #define PCLK_I2C4 336
135 #define PCLK_I2C5 337
136 #define PCLK_SPI0 338
137 #define PCLK_SPI1 339
138 #define PCLK_SPI2 340
139 #define PCLK_UART0 341
140 #define PCLK_UART1 342
141 #define PCLK_UART2 343
142 #define PCLK_UART3 344
143 #define PCLK_UART4 345
144 #define PCLK_TSADC 346
145 #define PCLK_SARADC 347
147 #define PCLK_GMAC 349
148 #define PCLK_PWM0 350
149 #define PCLK_PWM1 351
150 #define PCLK_TIMER0 353
151 #define PCLK_TIMER1 354
152 #define PCLK_EDP_CTRL 355
153 #define PCLK_MIPI_DSI0 356
154 #define PCLK_MIPI_CSI 358
155 #define PCLK_HDCP 359
156 #define PCLK_HDMI_CTRL 360
157 #define PCLK_VIO_H2P 361
159 #define PCLK_PERI 363
160 #define PCLK_DDRUPCTL 364
161 #define PCLK_DDRPHY 365
165 #define PCLK_DPHYRX 369
166 #define PCLK_DPHYTX0 370
167 #define PCLK_EFUSE256 371
168 #define PCLK_EFUSE1024 372
171 #define HCLK_USB_PERI 447
173 #define HCLK_OTG0 449
174 #define HCLK_HOST0 450
175 #define HCLK_HOST1 451
176 #define HCLK_HSIC 452
177 #define HCLK_NANDC0 453
179 #define HCLK_SDMMC 456
180 #define HCLK_SDIO0 457
181 #define HCLK_EMMC 459
182 #define HCLK_HSADC 460
183 #define HCLK_CRYPTO 461
184 #define HCLK_I2S_2CH 462
185 #define HCLK_I2S_8CH 463
186 #define HCLK_SPDIF 464
192 #define HCLK_VIO_AHB_ARBI 471
193 #define HCLK_VIO_NOC 472
195 #define HCLK_VIO_H2P 474
196 #define HCLK_VIO_HDCPMMU 475
197 #define HCLK_VIDEO 476
199 #define HCLK_PERI 478
201 #define CLK_NR_CLKS (HCLK_PERI + 1)
203 /* soft-reset indices */
204 #define SRST_CORE_B0 0
205 #define SRST_CORE_B1 1
206 #define SRST_CORE_B2 2
207 #define SRST_CORE_B3 3
208 #define SRST_CORE_B0_PO 4
209 #define SRST_CORE_B1_PO 5
210 #define SRST_CORE_B2_PO 6
211 #define SRST_CORE_B3_PO 7
214 #define SRST_PD_CORE_B_NIU 10
215 #define SRST_PDBUS_STRSYS 11
216 #define SRST_SOCDBG_B 14
217 #define SRST_CORE_B_DBG 15
219 #define SRST_DMAC1 18
220 #define SRST_INTMEM 19
222 #define SRST_SPDIF8CH 21
223 #define SRST_I2S8CH 23
224 #define SRST_MAILBOX 24
225 #define SRST_I2S2CH 25
226 #define SRST_EFUSE_256 26
227 #define SRST_MCU_SYS 28
228 #define SRST_MCU_PO 29
229 #define SRST_MCU_NOC 30
230 #define SRST_EFUSE 31
232 #define SRST_GPIO0 32
233 #define SRST_GPIO1 33
234 #define SRST_GPIO2 34
235 #define SRST_GPIO3 35
236 #define SRST_GPIO4 36
237 #define SRST_PMUGRF 41
245 #define SRST_DWPWM 48
246 #define SRST_MMC_PERI 49
247 #define SRST_PERIPH_MMU 50
250 #define SRST_PERIPH_AXI 57
251 #define SRST_PERIPH_AHB 58
252 #define SRST_PERIPH_APB 59
253 #define SRST_PERIPH_NIU 60
254 #define SRST_PDPERI_AHB_ARBI 61
256 #define SRST_USB_PERI 63
258 #define SRST_DMAC2 64
261 #define SRST_RKPWM 69
262 #define SRST_USBHOST0 72
264 #define SRST_HSIC_AUX 74
265 #define SRST_HSIC_PHY 75
266 #define SRST_HSADC 76
267 #define SRST_NANDC0 77
273 #define SRST_SARADC 87
274 #define SRST_PDALIVE_NIU 88
275 #define SRST_PDPMU_INTMEM 89
276 #define SRST_PDPMU_NIU 90
279 #define SRST_VIO_ARBI 96
280 #define SRST_RGA_NIU 97
281 #define SRST_VIO0_NIU_AXI 98
282 #define SRST_VIO_NIU_AHB 99
283 #define SRST_LCDC0_AXI 100
284 #define SRST_LCDC0_AHB 101
285 #define SRST_LCDC0_DCLK 102
287 #define SRST_RGA_CORE 105
288 #define SRST_IEP_AXI 106
289 #define SRST_IEP_AHB 107
290 #define SRST_RGA_AXI 108
291 #define SRST_RGA_AHB 109
293 #define SRST_EDP_24M 111
295 #define SRST_VIDEO_AXI 112
296 #define SRST_VIDEO_AHB 113
297 #define SRST_MIPIDPHYTX 114
298 #define SRST_MIPIDSI0 115
299 #define SRST_MIPIDPHYRX 116
300 #define SRST_MIPICSI 117
302 #define SRST_HDMI 121
304 #define SRST_PMU_PVTM 123
305 #define SRST_CORE_PVTM 124
306 #define SRST_GPU_PVTM 125
307 #define SRST_GPU_SYS 126
308 #define SRST_GPU_MEM_NIU 127
310 #define SRST_MMC0 128
311 #define SRST_SDIO0 129
312 #define SRST_EMMC 131
313 #define SRST_USBOTG_AHB 132
314 #define SRST_USBOTG_PHY 133
315 #define SRST_USBOTG_CON 134
316 #define SRST_USBHOST0_AHB 135
317 #define SRST_USBHOST0_PHY 136
318 #define SRST_USBHOST0_CON 137
319 #define SRST_USBOTG_UTMI 138
320 #define SRST_USBHOST1_UTMI 139
321 #define SRST_USB_ADP 141
323 #define SRST_CORESIGHT 144
324 #define SRST_PD_CORE_AHB_NOC 145
325 #define SRST_PD_CORE_APB_NOC 146
327 #define SRST_LCDC_PWM0 149
328 #define SRST_RGA_H2P_BRG 153
329 #define SRST_VIDEO 154
330 #define SRST_GPU_CFG_NIU 157
331 #define SRST_TSADC 159
333 #define SRST_DDRPHY0 160
334 #define SRST_DDRPHY0_APB 161
335 #define SRST_DDRCTRL0 162
336 #define SRST_DDRCTRL0_APB 163
337 #define SRST_VIDEO_NIU 165
338 #define SRST_VIDEO_NIU_AHB 167
339 #define SRST_DDRMSCH0 170
340 #define SRST_PDBUS_AHB 173
341 #define SRST_CRYPTO 174
343 #define SRST_UART0 179
344 #define SRST_UART1 180
345 #define SRST_UART2 181
346 #define SRST_UART3 182
347 #define SRST_UART4 183
348 #define SRST_SIMC 186
350 #define SRST_TSP_CLKIN0 189
352 #define SRST_CORE_L0 192
353 #define SRST_CORE_L1 193
354 #define SRST_CORE_L2 194
355 #define SRST_CORE_L3 195
356 #define SRST_CORE_L0_PO 195
357 #define SRST_CORE_L1_PO 197
358 #define SRST_CORE_L2_PO 198
359 #define SRST_CORE_L3_PO 199
360 #define SRST_L2_L 200
361 #define SRST_ADB_L 201
362 #define SRST_PD_CORE_L_NIU 202
363 #define SRST_CCI_SYS 203
364 #define SRST_CCI_DDR 204
366 #define SRST_SOCDBG_L 206
367 #define SRST_CORE_L_DBG 207
369 #define SRST_CORE_B0_NC 208
370 #define SRST_CORE_B0_PO_NC 209
371 #define SRST_L2_B_NC 210
372 #define SRST_ADB_B_NC 211
373 #define SRST_PD_CORE_B_NIU_NC 212
374 #define SRST_PDBUS_STRSYS_NC 213
375 #define SRST_CORE_L0_NC 214
376 #define SRST_CORE_L0_PO_NC 215
377 #define SRST_L2_L_NC 216
378 #define SRST_ADB_L_NC 217
379 #define SRST_PD_CORE_L_NIU_NC 218
380 #define SRST_CCI_SYS_NC 219
381 #define SRST_CCI_DDR_NC 220
382 #define SRST_CCI_NC 221
383 #define SRST_TRACE_NC 222
385 #define SRST_TIMER00 224
386 #define SRST_TIMER01 225
387 #define SRST_TIMER02 226
388 #define SRST_TIMER03 227
389 #define SRST_TIMER04 228
390 #define SRST_TIMER05 229
391 #define SRST_TIMER10 230
392 #define SRST_TIMER11 231
393 #define SRST_TIMER12 232
394 #define SRST_TIMER13 233
395 #define SRST_TIMER14 234
396 #define SRST_TIMER15 235
397 #define SRST_TIMER0_APB 236
398 #define SRST_TIMER1_APB 237