2 * Copyright (c) 2014 Samsung Electronics Co., Ltd.
3 * Author: Chanwoo Choi <cw00.choi@samsung.com>
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
10 #ifndef _DT_BINDINGS_CLOCK_EXYNOS5433_H
11 #define _DT_BINDINGS_CLOCK_EXYNOS5433_H
14 #define CLK_FOUT_ISP_PLL 1
15 #define CLK_FOUT_AUD_PLL 2
17 #define CLK_MOUT_AUD_PLL 10
18 #define CLK_MOUT_ISP_PLL 11
19 #define CLK_MOUT_AUD_PLL_USER_T 12
20 #define CLK_MOUT_MPHY_PLL_USER 13
21 #define CLK_MOUT_MFC_PLL_USER 14
22 #define CLK_MOUT_BUS_PLL_USER 15
23 #define CLK_MOUT_ACLK_HEVC_400 16
24 #define CLK_MOUT_ACLK_CAM1_333 17
25 #define CLK_MOUT_ACLK_CAM1_552_B 18
26 #define CLK_MOUT_ACLK_CAM1_552_A 19
27 #define CLK_MOUT_ACLK_ISP_DIS_400 20
28 #define CLK_MOUT_ACLK_ISP_400 21
29 #define CLK_MOUT_ACLK_BUS0_400 22
30 #define CLK_MOUT_ACLK_MSCL_400_B 23
31 #define CLK_MOUT_ACLK_MSCL_400_A 24
32 #define CLK_MOUT_ACLK_GSCL_333 25
33 #define CLK_MOUT_ACLK_G2D_400_B 26
34 #define CLK_MOUT_ACLK_G2D_400_A 27
35 #define CLK_MOUT_SCLK_JPEG_C 28
36 #define CLK_MOUT_SCLK_JPEG_B 29
37 #define CLK_MOUT_SCLK_JPEG_A 30
38 #define CLK_MOUT_SCLK_MMC2_B 31
39 #define CLK_MOUT_SCLK_MMC2_A 32
40 #define CLK_MOUT_SCLK_MMC1_B 33
41 #define CLK_MOUT_SCLK_MMC1_A 34
42 #define CLK_MOUT_SCLK_MMC0_D 35
43 #define CLK_MOUT_SCLK_MMC0_C 36
44 #define CLK_MOUT_SCLK_MMC0_B 37
45 #define CLK_MOUT_SCLK_MMC0_A 38
46 #define CLK_MOUT_SCLK_SPI4 39
47 #define CLK_MOUT_SCLK_SPI3 40
48 #define CLK_MOUT_SCLK_UART2 41
49 #define CLK_MOUT_SCLK_UART1 42
50 #define CLK_MOUT_SCLK_UART0 43
51 #define CLK_MOUT_SCLK_SPI2 44
52 #define CLK_MOUT_SCLK_SPI1 45
53 #define CLK_MOUT_SCLK_SPI0 46
54 #define CLK_MOUT_ACLK_MFC_400_C 47
55 #define CLK_MOUT_ACLK_MFC_400_B 48
56 #define CLK_MOUT_ACLK_MFC_400_A 49
57 #define CLK_MOUT_SCLK_ISP_SENSOR2 50
58 #define CLK_MOUT_SCLK_ISP_SENSOR1 51
59 #define CLK_MOUT_SCLK_ISP_SENSOR0 52
60 #define CLK_MOUT_SCLK_ISP_UART 53
61 #define CLK_MOUT_SCLK_ISP_SPI1 54
62 #define CLK_MOUT_SCLK_ISP_SPI0 55
63 #define CLK_MOUT_SCLK_PCIE_100 56
64 #define CLK_MOUT_SCLK_UFSUNIPRO 57
65 #define CLK_MOUT_SCLK_USBHOST30 58
66 #define CLK_MOUT_SCLK_USBDRD30 59
67 #define CLK_MOUT_SCLK_SLIMBUS 60
68 #define CLK_MOUT_SCLK_SPDIF 61
69 #define CLK_MOUT_SCLK_AUDIO1 62
70 #define CLK_MOUT_SCLK_AUDIO0 63
71 #define CLK_MOUT_SCLK_HDMI_SPDIF 64
73 #define CLK_DIV_ACLK_FSYS_200 100
74 #define CLK_DIV_ACLK_IMEM_SSSX_266 101
75 #define CLK_DIV_ACLK_IMEM_200 102
76 #define CLK_DIV_ACLK_IMEM_266 103
77 #define CLK_DIV_ACLK_PERIC_66_B 104
78 #define CLK_DIV_ACLK_PERIC_66_A 105
79 #define CLK_DIV_ACLK_PERIS_66_B 106
80 #define CLK_DIV_ACLK_PERIS_66_A 107
81 #define CLK_DIV_SCLK_MMC1_B 108
82 #define CLK_DIV_SCLK_MMC1_A 109
83 #define CLK_DIV_SCLK_MMC0_B 110
84 #define CLK_DIV_SCLK_MMC0_A 111
85 #define CLK_DIV_SCLK_MMC2_B 112
86 #define CLK_DIV_SCLK_MMC2_A 113
87 #define CLK_DIV_SCLK_SPI1_B 114
88 #define CLK_DIV_SCLK_SPI1_A 115
89 #define CLK_DIV_SCLK_SPI0_B 116
90 #define CLK_DIV_SCLK_SPI0_A 117
91 #define CLK_DIV_SCLK_SPI2_B 118
92 #define CLK_DIV_SCLK_SPI2_A 119
93 #define CLK_DIV_SCLK_UART2 120
94 #define CLK_DIV_SCLK_UART1 121
95 #define CLK_DIV_SCLK_UART0 122
96 #define CLK_DIV_SCLK_SPI4_B 123
97 #define CLK_DIV_SCLK_SPI4_A 124
98 #define CLK_DIV_SCLK_SPI3_B 125
99 #define CLK_DIV_SCLK_SPI3_A 126
100 #define CLK_DIV_SCLK_I2S1 127
101 #define CLK_DIV_SCLK_PCM1 128
102 #define CLK_DIV_SCLK_AUDIO1 129
103 #define CLK_DIV_SCLK_AUDIO0 130
104 #define CLK_DIV_ACLK_GSCL_111 131
105 #define CLK_DIV_ACLK_GSCL_333 132
106 #define CLK_DIV_ACLK_HEVC_400 133
107 #define CLK_DIV_ACLK_MFC_400 134
108 #define CLK_DIV_ACLK_G2D_266 135
109 #define CLK_DIV_ACLK_G2D_400 136
110 #define CLK_DIV_ACLK_G3D_400 137
111 #define CLK_DIV_ACLK_BUS0_400 138
112 #define CLK_DIV_ACLK_BUS1_400 139
113 #define CLK_DIV_SCLK_PCIE_100 140
114 #define CLK_DIV_SCLK_USBHOST30 141
115 #define CLK_DIV_SCLK_UFSUNIPRO 142
116 #define CLK_DIV_SCLK_USBDRD30 143
118 #define CLK_ACLK_PERIC_66 200
119 #define CLK_ACLK_PERIS_66 201
120 #define CLK_ACLK_FSYS_200 202
121 #define CLK_SCLK_MMC2_FSYS 203
122 #define CLK_SCLK_MMC1_FSYS 204
123 #define CLK_SCLK_MMC0_FSYS 205
124 #define CLK_SCLK_SPI4_PERIC 206
125 #define CLK_SCLK_SPI3_PERIC 207
126 #define CLK_SCLK_UART2_PERIC 208
127 #define CLK_SCLK_UART1_PERIC 209
128 #define CLK_SCLK_UART0_PERIC 210
129 #define CLK_SCLK_SPI2_PERIC 211
130 #define CLK_SCLK_SPI1_PERIC 212
131 #define CLK_SCLK_SPI0_PERIC 213
132 #define CLK_SCLK_SPDIF_PERIC 214
133 #define CLK_SCLK_I2S1_PERIC 215
134 #define CLK_SCLK_PCM1_PERIC 216
135 #define CLK_SCLK_SLIMBUS 217
136 #define CLK_SCLK_AUDIO1 218
137 #define CLK_SCLK_AUDIO0 219
138 #define CLK_ACLK_G2D_266 220
139 #define CLK_ACLK_G2D_400 221
140 #define CLK_ACLK_G3D_400 222
141 #define CLK_ACLK_IMEM_SSX_266 223
142 #define CLK_ACLK_BUS0_400 224
143 #define CLK_ACLK_BUS1_400 225
144 #define CLK_ACLK_IMEM_200 226
145 #define CLK_ACLK_IMEM_266 227
146 #define CLK_SCLK_PCIE_100_FSYS 228
147 #define CLK_SCLK_UFSUNIPRO_FSYS 229
148 #define CLK_SCLK_USBHOST30_FSYS 230
149 #define CLK_SCLK_USBDRD30_FSYS 231
150 #define CLK_ACLK_GSCL_111 232
151 #define CLK_ACLK_GSCL_333 233
153 #define TOP_NR_CLK 234
156 #define CLK_FOUT_MPHY_PLL 1
158 #define CLK_MOUT_MPHY_PLL 2
160 #define CLK_DIV_SCLK_MPHY 10
162 #define CLK_SCLK_MPHY_PLL 11
163 #define CLK_SCLK_UFS_MPHY 11
165 #define CPIF_NR_CLK 12
168 #define CLK_FOUT_MEM0_PLL 1
169 #define CLK_FOUT_MEM1_PLL 2
170 #define CLK_FOUT_BUS_PLL 3
171 #define CLK_FOUT_MFC_PLL 4
172 #define CLK_DOUT_MFC_PLL 5
173 #define CLK_DOUT_BUS_PLL 6
174 #define CLK_DOUT_MEM1_PLL 7
175 #define CLK_DOUT_MEM0_PLL 8
177 #define CLK_MOUT_MFC_PLL_DIV2 10
178 #define CLK_MOUT_BUS_PLL_DIV2 11
179 #define CLK_MOUT_MEM1_PLL_DIV2 12
180 #define CLK_MOUT_MEM0_PLL_DIV2 13
181 #define CLK_MOUT_MFC_PLL 14
182 #define CLK_MOUT_BUS_PLL 15
183 #define CLK_MOUT_MEM1_PLL 16
184 #define CLK_MOUT_MEM0_PLL 17
185 #define CLK_MOUT_CLK2X_PHY_C 18
186 #define CLK_MOUT_CLK2X_PHY_B 19
187 #define CLK_MOUT_CLK2X_PHY_A 20
188 #define CLK_MOUT_CLKM_PHY_C 21
189 #define CLK_MOUT_CLKM_PHY_B 22
190 #define CLK_MOUT_CLKM_PHY_A 23
191 #define CLK_MOUT_ACLK_MIFNM_200 24
192 #define CLK_MOUT_ACLK_MIFNM_400 25
193 #define CLK_MOUT_ACLK_DISP_333_B 26
194 #define CLK_MOUT_ACLK_DISP_333_A 27
195 #define CLK_MOUT_SCLK_DECON_VCLK_C 28
196 #define CLK_MOUT_SCLK_DECON_VCLK_B 29
197 #define CLK_MOUT_SCLK_DECON_VCLK_A 30
198 #define CLK_MOUT_SCLK_DECON_ECLK_C 31
199 #define CLK_MOUT_SCLK_DECON_ECLK_B 32
200 #define CLK_MOUT_SCLK_DECON_ECLK_A 33
201 #define CLK_MOUT_SCLK_DECON_TV_ECLK_C 34
202 #define CLK_MOUT_SCLK_DECON_TV_ECLK_B 35
203 #define CLK_MOUT_SCLK_DECON_TV_ECLK_A 36
204 #define CLK_MOUT_SCLK_DSD_C 37
205 #define CLK_MOUT_SCLK_DSD_B 38
206 #define CLK_MOUT_SCLK_DSD_A 39
207 #define CLK_MOUT_SCLK_DSIM0_C 40
208 #define CLK_MOUT_SCLK_DSIM0_B 41
209 #define CLK_MOUT_SCLK_DSIM0_A 42
210 #define CLK_MOUT_SCLK_DECON_TV_VCLK_C 46
211 #define CLK_MOUT_SCLK_DECON_TV_VCLK_B 47
212 #define CLK_MOUT_SCLK_DECON_TV_VCLK_A 48
213 #define CLK_MOUT_SCLK_DSIM1_C 49
214 #define CLK_MOUT_SCLK_DSIM1_B 50
215 #define CLK_MOUT_SCLK_DSIM1_A 51
217 #define CLK_DIV_SCLK_HPM_MIF 55
218 #define CLK_DIV_ACLK_DREX1 56
219 #define CLK_DIV_ACLK_DREX0 57
220 #define CLK_DIV_CLK2XPHY 58
221 #define CLK_DIV_ACLK_MIF_266 59
222 #define CLK_DIV_ACLK_MIFND_133 60
223 #define CLK_DIV_ACLK_MIF_133 61
224 #define CLK_DIV_ACLK_MIFNM_200 62
225 #define CLK_DIV_ACLK_MIF_200 63
226 #define CLK_DIV_ACLK_MIF_400 64
227 #define CLK_DIV_ACLK_BUS2_400 65
228 #define CLK_DIV_ACLK_DISP_333 66
229 #define CLK_DIV_ACLK_CPIF_200 67
230 #define CLK_DIV_SCLK_DSIM1 68
231 #define CLK_DIV_SCLK_DECON_TV_VCLK 69
232 #define CLK_DIV_SCLK_DSIM0 70
233 #define CLK_DIV_SCLK_DSD 71
234 #define CLK_DIV_SCLK_DECON_TV_ECLK 72
235 #define CLK_DIV_SCLK_DECON_VCLK 73
236 #define CLK_DIV_SCLK_DECON_ECLK 74
237 #define CLK_DIV_MIF_PRE 75
239 #define CLK_CLK2X_PHY1 80
240 #define CLK_CLK2X_PHY0 81
241 #define CLK_CLKM_PHY1 82
242 #define CLK_CLKM_PHY0 83
243 #define CLK_RCLK_DREX1 84
244 #define CLK_RCLK_DREX0 85
245 #define CLK_ACLK_DREX1_TZ 86
246 #define CLK_ACLK_DREX0_TZ 87
247 #define CLK_ACLK_DREX1_PEREV 88
248 #define CLK_ACLK_DREX0_PEREV 89
249 #define CLK_ACLK_DREX1_MEMIF 90
250 #define CLK_ACLK_DREX0_MEMIF 91
251 #define CLK_ACLK_DREX1_SCH 92
252 #define CLK_ACLK_DREX0_SCH 93
253 #define CLK_ACLK_DREX1_BUSIF 94
254 #define CLK_ACLK_DREX0_BUSIF 95
255 #define CLK_ACLK_DREX1_BUSIF_RD 96
256 #define CLK_ACLK_DREX0_BUSIF_RD 97
257 #define CLK_ACLK_DREX1 98
258 #define CLK_ACLK_DREX0 99
259 #define CLK_ACLK_ASYNCAXIM_ATLAS_CCIX 100
260 #define CLK_ACLK_ASYNCAXIS_ATLAS_MIF 101
261 #define CLK_ACLK_ASYNCAXIM_ATLAS_MIF 102
262 #define CLK_ACLK_ASYNCAXIS_MIF_IMEM 103
263 #define CLK_ACLK_ASYNCAXIS_NOC_P_CCI 104
264 #define CLK_ACLK_ASYNCAXIM_NOC_P_CCI 105
265 #define CLK_ACLK_ASYNCAXIS_CP1 106
266 #define CLK_ACLK_ASYNCAXIM_CP1 107
267 #define CLK_ACLK_ASYNCAXIS_CP0 108
268 #define CLK_ACLK_ASYNCAXIM_CP0 109
269 #define CLK_ACLK_ASYNCAXIS_DREX1_3 110
270 #define CLK_ACLK_ASYNCAXIM_DREX1_3 111
271 #define CLK_ACLK_ASYNCAXIS_DREX1_1 112
272 #define CLK_ACLK_ASYNCAXIM_DREX1_1 113
273 #define CLK_ACLK_ASYNCAXIS_DREX1_0 114
274 #define CLK_ACLK_ASYNCAXIM_DREX1_0 115
275 #define CLK_ACLK_ASYNCAXIS_DREX0_3 116
276 #define CLK_ACLK_ASYNCAXIM_DREX0_3 117
277 #define CLK_ACLK_ASYNCAXIS_DREX0_1 118
278 #define CLK_ACLK_ASYNCAXIM_DREX0_1 119
279 #define CLK_ACLK_ASYNCAXIS_DREX0_0 120
280 #define CLK_ACLK_ASYNCAXIM_DREX0_0 121
281 #define CLK_ACLK_AHB2APB_MIF2P 122
282 #define CLK_ACLK_AHB2APB_MIF1P 123
283 #define CLK_ACLK_AHB2APB_MIF0P 124
284 #define CLK_ACLK_IXIU_CCI 125
285 #define CLK_ACLK_XIU_MIFSFRX 126
286 #define CLK_ACLK_MIFNP_133 127
287 #define CLK_ACLK_MIFNM_200 128
288 #define CLK_ACLK_MIFND_133 129
289 #define CLK_ACLK_MIFND_400 130
290 #define CLK_ACLK_CCI 131
291 #define CLK_ACLK_MIFND_266 132
292 #define CLK_ACLK_PPMU_DREX1S3 133
293 #define CLK_ACLK_PPMU_DREX1S1 134
294 #define CLK_ACLK_PPMU_DREX1S0 135
295 #define CLK_ACLK_PPMU_DREX0S3 136
296 #define CLK_ACLK_PPMU_DREX0S1 137
297 #define CLK_ACLK_PPMU_DREX0S0 138
298 #define CLK_ACLK_BTS_APOLLO 139
299 #define CLK_ACLK_BTS_ATLAS 140
300 #define CLK_ACLK_ACE_SEL_APOLL 141
301 #define CLK_ACLK_ACE_SEL_ATLAS 142
302 #define CLK_ACLK_AXIDS_CCI_MIFSFRX 143
303 #define CLK_ACLK_AXIUS_ATLAS_CCI 144
304 #define CLK_ACLK_AXISYNCDNS_CCI 145
305 #define CLK_ACLK_AXISYNCDN_CCI 146
306 #define CLK_ACLK_AXISYNCDN_NOC_D 147
307 #define CLK_ACLK_ASYNCACEM_APOLLO_CCI 148
308 #define CLK_ACLK_ASYNCACEM_ATLAS_CCI 149
309 #define CLK_ACLK_ASYNCAPBS_MIF_CSSYS 150
310 #define CLK_ACLK_BUS2_400 151
311 #define CLK_ACLK_DISP_333 152
312 #define CLK_ACLK_CPIF_200 153
313 #define CLK_PCLK_PPMU_DREX1S3 154
314 #define CLK_PCLK_PPMU_DREX1S1 155
315 #define CLK_PCLK_PPMU_DREX1S0 156
316 #define CLK_PCLK_PPMU_DREX0S3 157
317 #define CLK_PCLK_PPMU_DREX0S1 158
318 #define CLK_PCLK_PPMU_DREX0S0 159
319 #define CLK_PCLK_BTS_APOLLO 160
320 #define CLK_PCLK_BTS_ATLAS 161
321 #define CLK_PCLK_ASYNCAXI_NOC_P_CCI 162
322 #define CLK_PCLK_ASYNCAXI_CP1 163
323 #define CLK_PCLK_ASYNCAXI_CP0 164
324 #define CLK_PCLK_ASYNCAXI_DREX1_3 165
325 #define CLK_PCLK_ASYNCAXI_DREX1_1 166
326 #define CLK_PCLK_ASYNCAXI_DREX1_0 167
327 #define CLK_PCLK_ASYNCAXI_DREX0_3 168
328 #define CLK_PCLK_ASYNCAXI_DREX0_1 169
329 #define CLK_PCLK_ASYNCAXI_DREX0_0 170
330 #define CLK_PCLK_MIFSRVND_133 171
331 #define CLK_PCLK_PMU_MIF 172
332 #define CLK_PCLK_SYSREG_MIF 173
333 #define CLK_PCLK_GPIO_ALIVE 174
334 #define CLK_PCLK_ABB 175
335 #define CLK_PCLK_PMU_APBIF 176
336 #define CLK_PCLK_DDR_PHY1 177
337 #define CLK_PCLK_DREX1 178
338 #define CLK_PCLK_DDR_PHY0 179
339 #define CLK_PCLK_DREX0 180
340 #define CLK_PCLK_DREX0_TZ 181
341 #define CLK_PCLK_DREX1_TZ 182
342 #define CLK_PCLK_MONOTONIC_CNT 183
343 #define CLK_PCLK_RTC 184
344 #define CLK_SCLK_DSIM1_DISP 185
345 #define CLK_SCLK_DECON_TV_VCLK_DISP 186
346 #define CLK_SCLK_FREQ_DET_BUS_PLL 187
347 #define CLK_SCLK_FREQ_DET_MFC_PLL 188
348 #define CLK_SCLK_FREQ_DET_MEM0_PLL 189
349 #define CLK_SCLK_FREQ_DET_MEM1_PLL 190
350 #define CLK_SCLK_DSIM0_DISP 191
351 #define CLK_SCLK_DSD_DISP 192
352 #define CLK_SCLK_DECON_TV_ECLK_DISP 193
353 #define CLK_SCLK_DECON_VCLK_DISP 194
354 #define CLK_SCLK_DECON_ECLK_DISP 195
355 #define CLK_SCLK_HPM_MIF 196
356 #define CLK_SCLK_MFC_PLL 197
357 #define CLK_SCLK_BUS_PLL 198
358 #define CLK_SCLK_BUS_PLL_APOLLO 199
359 #define CLK_SCLK_BUS_PLL_ATLAS 200
360 #define CLK_SCLK_HDMI_SPDIF_DISP 201
362 #define MIF_NR_CLK 202
365 #define CLK_PCLK_SPI2 1
366 #define CLK_PCLK_SPI1 2
367 #define CLK_PCLK_SPI0 3
368 #define CLK_PCLK_UART2 4
369 #define CLK_PCLK_UART1 5
370 #define CLK_PCLK_UART0 6
371 #define CLK_PCLK_HSI2C3 7
372 #define CLK_PCLK_HSI2C2 8
373 #define CLK_PCLK_HSI2C1 9
374 #define CLK_PCLK_HSI2C0 10
375 #define CLK_PCLK_I2C7 11
376 #define CLK_PCLK_I2C6 12
377 #define CLK_PCLK_I2C5 13
378 #define CLK_PCLK_I2C4 14
379 #define CLK_PCLK_I2C3 15
380 #define CLK_PCLK_I2C2 16
381 #define CLK_PCLK_I2C1 17
382 #define CLK_PCLK_I2C0 18
383 #define CLK_PCLK_SPI4 19
384 #define CLK_PCLK_SPI3 20
385 #define CLK_PCLK_HSI2C11 21
386 #define CLK_PCLK_HSI2C10 22
387 #define CLK_PCLK_HSI2C9 23
388 #define CLK_PCLK_HSI2C8 24
389 #define CLK_PCLK_HSI2C7 25
390 #define CLK_PCLK_HSI2C6 26
391 #define CLK_PCLK_HSI2C5 27
392 #define CLK_PCLK_HSI2C4 28
393 #define CLK_SCLK_SPI4 29
394 #define CLK_SCLK_SPI3 30
395 #define CLK_SCLK_SPI2 31
396 #define CLK_SCLK_SPI1 32
397 #define CLK_SCLK_SPI0 33
398 #define CLK_SCLK_UART2 34
399 #define CLK_SCLK_UART1 35
400 #define CLK_SCLK_UART0 36
401 #define CLK_ACLK_AHB2APB_PERIC2P 37
402 #define CLK_ACLK_AHB2APB_PERIC1P 38
403 #define CLK_ACLK_AHB2APB_PERIC0P 39
404 #define CLK_ACLK_PERICNP_66 40
405 #define CLK_PCLK_SCI 41
406 #define CLK_PCLK_GPIO_FINGER 42
407 #define CLK_PCLK_GPIO_ESE 43
408 #define CLK_PCLK_PWM 44
409 #define CLK_PCLK_SPDIF 45
410 #define CLK_PCLK_PCM1 46
411 #define CLK_PCLK_I2S1 47
412 #define CLK_PCLK_ADCIF 48
413 #define CLK_PCLK_GPIO_TOUCH 49
414 #define CLK_PCLK_GPIO_NFC 50
415 #define CLK_PCLK_GPIO_PERIC 51
416 #define CLK_PCLK_PMU_PERIC 52
417 #define CLK_PCLK_SYSREG_PERIC 53
418 #define CLK_SCLK_IOCLK_SPI4 54
419 #define CLK_SCLK_IOCLK_SPI3 55
420 #define CLK_SCLK_SCI 56
421 #define CLK_SCLK_SC_IN 57
422 #define CLK_SCLK_PWM 58
423 #define CLK_SCLK_IOCLK_SPI2 59
424 #define CLK_SCLK_IOCLK_SPI1 60
425 #define CLK_SCLK_IOCLK_SPI0 61
426 #define CLK_SCLK_IOCLK_I2S1_BCLK 62
427 #define CLK_SCLK_SPDIF 63
428 #define CLK_SCLK_PCM1 64
429 #define CLK_SCLK_I2S1 65
431 #define CLK_DIV_SCLK_SCI 70
432 #define CLK_DIV_SCLK_SC_IN 71
434 #define PERIC_NR_CLK 72
437 #define CLK_PCLK_HPM_APBIF 1
438 #define CLK_PCLK_TMU1_APBIF 2
439 #define CLK_PCLK_TMU0_APBIF 3
440 #define CLK_PCLK_PMU_PERIS 4
441 #define CLK_PCLK_SYSREG_PERIS 5
442 #define CLK_PCLK_CMU_TOP_APBIF 6
443 #define CLK_PCLK_WDT_APOLLO 7
444 #define CLK_PCLK_WDT_ATLAS 8
445 #define CLK_PCLK_MCT 9
446 #define CLK_PCLK_HDMI_CEC 10
447 #define CLK_ACLK_AHB2APB_PERIS1P 11
448 #define CLK_ACLK_AHB2APB_PERIS0P 12
449 #define CLK_ACLK_PERISNP_66 13
450 #define CLK_PCLK_TZPC12 14
451 #define CLK_PCLK_TZPC11 15
452 #define CLK_PCLK_TZPC10 16
453 #define CLK_PCLK_TZPC9 17
454 #define CLK_PCLK_TZPC8 18
455 #define CLK_PCLK_TZPC7 19
456 #define CLK_PCLK_TZPC6 20
457 #define CLK_PCLK_TZPC5 21
458 #define CLK_PCLK_TZPC4 22
459 #define CLK_PCLK_TZPC3 23
460 #define CLK_PCLK_TZPC2 24
461 #define CLK_PCLK_TZPC1 25
462 #define CLK_PCLK_TZPC0 26
463 #define CLK_PCLK_SECKEY_APBIF 27
464 #define CLK_PCLK_CHIPID_APBIF 28
465 #define CLK_PCLK_TOPRTC 29
466 #define CLK_PCLK_CUSTOM_EFUSE_APBIF 30
467 #define CLK_PCLK_ANTIRBK_CNT_APBIF 31
468 #define CLK_PCLK_OTP_CON_APBIF 32
469 #define CLK_SCLK_ASV_TB 33
470 #define CLK_SCLK_TMU1 34
471 #define CLK_SCLK_TMU0 35
472 #define CLK_SCLK_SECKEY 36
473 #define CLK_SCLK_CHIPID 37
474 #define CLK_SCLK_TOPRTC 38
475 #define CLK_SCLK_CUSTOM_EFUSE 39
476 #define CLK_SCLK_ANTIRBK_CNT 40
477 #define CLK_SCLK_OTP_CON 41
479 #define PERIS_NR_CLK 42
482 #define CLK_MOUT_ACLK_FSYS_200_USER 1
483 #define CLK_MOUT_SCLK_MMC2_USER 2
484 #define CLK_MOUT_SCLK_MMC1_USER 3
485 #define CLK_MOUT_SCLK_MMC0_USER 4
486 #define CLK_MOUT_SCLK_UFS_MPHY_USER 5
487 #define CLK_MOUT_SCLK_PCIE_100_USER 6
488 #define CLK_MOUT_SCLK_UFSUNIPRO_USER 7
489 #define CLK_MOUT_SCLK_USBHOST30_USER 8
490 #define CLK_MOUT_SCLK_USBDRD30_USER 9
491 #define CLK_MOUT_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK_USER 10
492 #define CLK_MOUT_PHYCLK_USBHOST30_UHOST30_PHYCLOCK_USER 11
493 #define CLK_MOUT_PHYCLK_USBHOST20_PHY_HSIC1_USER 12
494 #define CLK_MOUT_PHYCLK_USBHOST20_PHY_CLK48MOHCI_USER 13
495 #define CLK_MOUT_PHYCLK_USBHOST20_PHY_PHYCLOCK_USER 14
496 #define CLK_MOUT_PHYCLK_USBHOST20_PHY_PHY_FREECLK_USER 15
497 #define CLK_MOUT_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK_USER 16
498 #define CLK_MOUT_PHYCLK_USBDRD30_UDRD30_PHYCLOCK_USER 17
499 #define CLK_MOUT_PHYCLK_UFS_RX1_SYMBOL_USER 18
500 #define CLK_MOUT_PHYCLK_UFS_RX0_SYMBOL_USER 19
501 #define CLK_MOUT_PHYCLK_UFS_TX1_SYMBOL_USER 20
502 #define CLK_MOUT_PHYCLK_UFS_TX0_SYMBOL_USER 21
503 #define CLK_MOUT_PHYCLK_LLI_MPHY_TO_UFS_USER 22
504 #define CLK_MOUT_SCLK_MPHY 23
506 #define CLK_PHYCLK_USBDRD30_UDRD30_PHYCLOCK_PHY 25
507 #define CLK_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK_PHY 26
508 #define CLK_PHYCLK_USBHOST30_UHOST30_PHYCLOCK_PHY 27
509 #define CLK_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK_PHY 28
510 #define CLK_PHYCLK_USBHOST20_PHY_FREECLK_PHY 29
511 #define CLK_PHYCLK_USBHOST20_PHY_PHYCLOCK_PHY 30
512 #define CLK_PHYCLK_USBHOST20_PHY_CLK48MOHCI_PHY 31
513 #define CLK_PHYCLK_USBHOST20_PHY_HSIC1_PHY 32
514 #define CLK_PHYCLK_UFS_TX0_SYMBOL_PHY 33
515 #define CLK_PHYCLK_UFS_RX0_SYMBOL_PHY 34
516 #define CLK_PHYCLK_UFS_TX1_SYMBOL_PHY 35
517 #define CLK_PHYCLK_UFS_RX1_SYMBOL_PHY 36
518 #define CLK_PHYCLK_LLI_MPHY_TO_UFS_PHY 37
520 #define CLK_ACLK_PCIE 50
521 #define CLK_ACLK_PDMA1 51
522 #define CLK_ACLK_TSI 52
523 #define CLK_ACLK_MMC2 53
524 #define CLK_ACLK_MMC1 54
525 #define CLK_ACLK_MMC0 55
526 #define CLK_ACLK_UFS 56
527 #define CLK_ACLK_USBHOST20 57
528 #define CLK_ACLK_USBHOST30 58
529 #define CLK_ACLK_USBDRD30 59
530 #define CLK_ACLK_PDMA0 60
531 #define CLK_SCLK_MMC2 61
532 #define CLK_SCLK_MMC1 62
533 #define CLK_SCLK_MMC0 63
536 #define CLK_ACLK_XIU_FSYSPX 66
537 #define CLK_ACLK_AHB_USBLINKH1 67
538 #define CLK_ACLK_SMMU_PDMA1 68
539 #define CLK_ACLK_BTS_PCIE 69
540 #define CLK_ACLK_AXIUS_PDMA1 70
541 #define CLK_ACLK_SMMU_PDMA0 71
542 #define CLK_ACLK_BTS_UFS 72
543 #define CLK_ACLK_BTS_USBHOST30 73
544 #define CLK_ACLK_BTS_USBDRD30 74
545 #define CLK_ACLK_AXIUS_PDMA0 75
546 #define CLK_ACLK_AXIUS_USBHS 76
547 #define CLK_ACLK_AXIUS_FSYSSX 77
548 #define CLK_ACLK_AHB2APB_FSYSP 78
549 #define CLK_ACLK_AHB2AXI_USBHS 79
550 #define CLK_ACLK_AHB_USBLINKH0 80
551 #define CLK_ACLK_AHB_USBHS 81
552 #define CLK_ACLK_AHB_FSYSH 82
553 #define CLK_ACLK_XIU_FSYSX 83
554 #define CLK_ACLK_XIU_FSYSSX 84
555 #define CLK_ACLK_FSYSNP_200 85
556 #define CLK_ACLK_FSYSND_200 86
557 #define CLK_PCLK_PCIE_CTRL 87
558 #define CLK_PCLK_SMMU_PDMA1 88
559 #define CLK_PCLK_PCIE_PHY 89
560 #define CLK_PCLK_BTS_PCIE 90
561 #define CLK_PCLK_SMMU_PDMA0 91
562 #define CLK_PCLK_BTS_UFS 92
563 #define CLK_PCLK_BTS_USBHOST30 93
564 #define CLK_PCLK_BTS_USBDRD30 94
565 #define CLK_PCLK_GPIO_FSYS 95
566 #define CLK_PCLK_PMU_FSYS 96
567 #define CLK_PCLK_SYSREG_FSYS 97
568 #define CLK_SCLK_PCIE_100 98
569 #define CLK_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK 99
570 #define CLK_PHYCLK_USBHOST30_UHOST30_PHYCLOCK 100
571 #define CLK_PHYCLK_UFS_RX1_SYMBOL 101
572 #define CLK_PHYCLK_UFS_RX0_SYMBOL 102
573 #define CLK_PHYCLK_UFS_TX1_SYMBOL 103
574 #define CLK_PHYCLK_UFS_TX0_SYMBOL 104
575 #define CLK_PHYCLK_USBHOST20_PHY_HSIC1 105
576 #define CLK_PHYCLK_USBHOST20_PHY_CLK48MOHCI 106
577 #define CLK_PHYCLK_USBHOST20_PHY_PHYCLOCK 107
578 #define CLK_PHYCLK_USBHOST20_PHY_FREECLK 108
579 #define CLK_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK 109
580 #define CLK_PHYCLK_USBDRD30_UDRD30_PHYCLOCK 110
581 #define CLK_SCLK_MPHY 111
582 #define CLK_SCLK_UFSUNIPRO 112
583 #define CLK_SCLK_USBHOST30 113
584 #define CLK_SCLK_USBDRD30 114
586 #define FSYS_NR_CLK 115
589 #define CLK_MUX_ACLK_G2D_266_USER 1
590 #define CLK_MUX_ACLK_G2D_400_USER 2
592 #define CLK_DIV_PCLK_G2D 3
594 #define CLK_ACLK_SMMU_MDMA1 4
595 #define CLK_ACLK_BTS_MDMA1 5
596 #define CLK_ACLK_BTS_G2D 6
597 #define CLK_ACLK_ALB_G2D 7
598 #define CLK_ACLK_AXIUS_G2DX 8
599 #define CLK_ACLK_ASYNCAXI_SYSX 9
600 #define CLK_ACLK_AHB2APB_G2D1P 10
601 #define CLK_ACLK_AHB2APB_G2D0P 11
602 #define CLK_ACLK_XIU_G2DX 12
603 #define CLK_ACLK_G2DNP_133 13
604 #define CLK_ACLK_G2DND_400 14
605 #define CLK_ACLK_MDMA1 15
606 #define CLK_ACLK_G2D 16
607 #define CLK_ACLK_SMMU_G2D 17
608 #define CLK_PCLK_SMMU_MDMA1 18
609 #define CLK_PCLK_BTS_MDMA1 19
610 #define CLK_PCLK_BTS_G2D 20
611 #define CLK_PCLK_ALB_G2D 21
612 #define CLK_PCLK_ASYNCAXI_SYSX 22
613 #define CLK_PCLK_PMU_G2D 23
614 #define CLK_PCLK_SYSREG_G2D 24
615 #define CLK_PCLK_G2D 25
616 #define CLK_PCLK_SMMU_G2D 26
618 #define G2D_NR_CLK 27
621 #define CLK_FOUT_DISP_PLL 1
623 #define CLK_MOUT_DISP_PLL 2
624 #define CLK_MOUT_SCLK_DSIM1_USER 3
625 #define CLK_MOUT_SCLK_DSIM0_USER 4
626 #define CLK_MOUT_SCLK_DSD_USER 5
627 #define CLK_MOUT_SCLK_DECON_TV_ECLK_USER 6
628 #define CLK_MOUT_SCLK_DECON_VCLK_USER 7
629 #define CLK_MOUT_SCLK_DECON_ECLK_USER 8
630 #define CLK_MOUT_SCLK_DECON_TV_VCLK_USER 9
631 #define CLK_MOUT_ACLK_DISP_333_USER 10
632 #define CLK_MOUT_PHYCLK_MIPIDPHY1_BITCLKDIV8_USER 11
633 #define CLK_MOUT_PHYCLK_MIPIDPHY1_RXCLKESC0_USER 12
634 #define CLK_MOUT_PHYCLK_MIPIDPHY0_BITCLKDIV8_USER 13
635 #define CLK_MOUT_PHYCLK_MIPIDPHY0_RXCLKESC0_USER 14
636 #define CLK_MOUT_PHYCLK_HDMIPHY_TMDS_CLKO_USER 15
637 #define CLK_MOUT_PHYCLK_HDMIPHY_PIXEL_CLKO_USER 16
638 #define CLK_MOUT_SCLK_DSIM0 17
639 #define CLK_MOUT_SCLK_DECON_TV_ECLK 18
640 #define CLK_MOUT_SCLK_DECON_VCLK 19
641 #define CLK_MOUT_SCLK_DECON_ECLK 20
642 #define CLK_MOUT_SCLK_DSIM1_B_DISP 21
643 #define CLK_MOUT_SCLK_DSIM1_A_DISP 22
644 #define CLK_MOUT_SCLK_DECON_TV_VCLK_C_DISP 23
645 #define CLK_MOUT_SCLK_DECON_TV_VCLK_B_DISP 24
646 #define CLK_MOUT_SCLK_DECON_TV_VCLK_A_DISP 25
648 #define CLK_DIV_SCLK_DSIM1_DISP 30
649 #define CLK_DIV_SCLK_DECON_TV_VCLK_DISP 31
650 #define CLK_DIV_SCLK_DSIM0_DISP 32
651 #define CLK_DIV_SCLK_DECON_TV_ECLK_DISP 33
652 #define CLK_DIV_SCLK_DECON_VCLK_DISP 34
653 #define CLK_DIV_SCLK_DECON_ECLK_DISP 35
654 #define CLK_DIV_PCLK_DISP 36
656 #define CLK_ACLK_DECON_TV 40
657 #define CLK_ACLK_DECON 41
658 #define CLK_ACLK_SMMU_TV1X 42
659 #define CLK_ACLK_SMMU_TV0X 43
660 #define CLK_ACLK_SMMU_DECON1X 44
661 #define CLK_ACLK_SMMU_DECON0X 45
662 #define CLK_ACLK_BTS_DECON_TV_M3 46
663 #define CLK_ACLK_BTS_DECON_TV_M2 47
664 #define CLK_ACLK_BTS_DECON_TV_M1 48
665 #define CLK_ACLK_BTS_DECON_TV_M0 49
666 #define CLK_ACLK_BTS_DECON_NM4 50
667 #define CLK_ACLK_BTS_DECON_NM3 51
668 #define CLK_ACLK_BTS_DECON_NM2 52
669 #define CLK_ACLK_BTS_DECON_NM1 53
670 #define CLK_ACLK_BTS_DECON_NM0 54
671 #define CLK_ACLK_AHB2APB_DISPSFR2P 55
672 #define CLK_ACLK_AHB2APB_DISPSFR1P 56
673 #define CLK_ACLK_AHB2APB_DISPSFR0P 57
674 #define CLK_ACLK_AHB_DISPH 58
675 #define CLK_ACLK_XIU_TV1X 59
676 #define CLK_ACLK_XIU_TV0X 60
677 #define CLK_ACLK_XIU_DECON1X 61
678 #define CLK_ACLK_XIU_DECON0X 62
679 #define CLK_ACLK_XIU_DISP1X 63
680 #define CLK_ACLK_XIU_DISPNP_100 64
681 #define CLK_ACLK_DISP1ND_333 65
682 #define CLK_ACLK_DISP0ND_333 66
683 #define CLK_PCLK_SMMU_TV1X 67
684 #define CLK_PCLK_SMMU_TV0X 68
685 #define CLK_PCLK_SMMU_DECON1X 69
686 #define CLK_PCLK_SMMU_DECON0X 70
687 #define CLK_PCLK_BTS_DECON_TV_M3 71
688 #define CLK_PCLK_BTS_DECON_TV_M2 72
689 #define CLK_PCLK_BTS_DECON_TV_M1 73
690 #define CLK_PCLK_BTS_DECON_TV_M0 74
691 #define CLK_PCLK_BTS_DECONM4 75
692 #define CLK_PCLK_BTS_DECONM3 76
693 #define CLK_PCLK_BTS_DECONM2 77
694 #define CLK_PCLK_BTS_DECONM1 78
695 #define CLK_PCLK_BTS_DECONM0 79
696 #define CLK_PCLK_MIC1 80
697 #define CLK_PCLK_PMU_DISP 81
698 #define CLK_PCLK_SYSREG_DISP 82
699 #define CLK_PCLK_HDMIPHY 83
700 #define CLK_PCLK_HDMI 84
701 #define CLK_PCLK_MIC0 85
702 #define CLK_PCLK_DSIM1 86
703 #define CLK_PCLK_DSIM0 87
704 #define CLK_PCLK_DECON_TV 88
705 #define CLK_PHYCLK_MIPIDPHY1_BITCLKDIV8 89
706 #define CLK_PHYCLK_MIPIDPHY1_RXCLKESC0 90
707 #define CLK_SCLK_RGB_TV_VCLK_TO_DSIM1 91
708 #define CLK_SCLK_RGB_TV_VCLK_TO_MIC1 92
709 #define CLK_SCLK_DSIM1 93
710 #define CLK_SCLK_DECON_TV_VCLK 94
711 #define CLK_PHYCLK_MIPIDPHY0_BITCLKDIV8 95
712 #define CLK_PHYCLK_MIPIDPHY0_RXCLKESC0 96
713 #define CLK_PHYCLK_HDMIPHY_TMDS_CLKO 97
714 #define CLK_PHYCLK_HDMI_PIXEL 98
715 #define CLK_SCLK_RGB_VCLK_TO_SMIES 99
716 #define CLK_SCLK_FREQ_DET_DISP_PLL 100
717 #define CLK_SCLK_RGB_VCLK_TO_DSIM0 101
718 #define CLK_SCLK_RGB_VCLK_TO_MIC0 102
719 #define CLK_SCLK_DSD 103
720 #define CLK_SCLK_HDMI_SPDIF 104
721 #define CLK_SCLK_DSIM0 105
722 #define CLK_SCLK_DECON_TV_ECLK 106
723 #define CLK_SCLK_DECON_VCLK 107
724 #define CLK_SCLK_DECON_ECLK 108
725 #define CLK_SCLK_RGB_VCLK 109
726 #define CLK_SCLK_RGB_TV_VCLK 110
728 #define DISP_NR_CLK 111
731 #define CLK_MOUT_AUD_PLL_USER 1
732 #define CLK_MOUT_SCLK_AUD_PCM 2
733 #define CLK_MOUT_SCLK_AUD_I2S 3
735 #define CLK_DIV_ATCLK_AUD 4
736 #define CLK_DIV_PCLK_DBG_AUD 5
737 #define CLK_DIV_ACLK_AUD 6
738 #define CLK_DIV_AUD_CA5 7
739 #define CLK_DIV_SCLK_AUD_SLIMBUS 8
740 #define CLK_DIV_SCLK_AUD_UART 9
741 #define CLK_DIV_SCLK_AUD_PCM 10
742 #define CLK_DIV_SCLK_AUD_I2S 11
744 #define CLK_ACLK_INTR_CTRL 12
745 #define CLK_ACLK_AXIDS2_LPASSP 13
746 #define CLK_ACLK_AXIDS1_LPASSP 14
747 #define CLK_ACLK_AXI2APB1_LPASSP 15
748 #define CLK_ACLK_AXI2APH_LPASSP 16
749 #define CLK_ACLK_SMMU_LPASSX 17
750 #define CLK_ACLK_AXIDS0_LPASSP 18
751 #define CLK_ACLK_AXI2APB0_LPASSP 19
752 #define CLK_ACLK_XIU_LPASSX 20
753 #define CLK_ACLK_AUDNP_133 21
754 #define CLK_ACLK_AUDND_133 22
755 #define CLK_ACLK_SRAMC 23
756 #define CLK_ACLK_DMAC 24
757 #define CLK_PCLK_WDT1 25
758 #define CLK_PCLK_WDT0 26
759 #define CLK_PCLK_SFR1 27
760 #define CLK_PCLK_SMMU_LPASSX 28
761 #define CLK_PCLK_GPIO_AUD 29
762 #define CLK_PCLK_PMU_AUD 30
763 #define CLK_PCLK_SYSREG_AUD 31
764 #define CLK_PCLK_AUD_SLIMBUS 32
765 #define CLK_PCLK_AUD_UART 33
766 #define CLK_PCLK_AUD_PCM 34
767 #define CLK_PCLK_AUD_I2S 35
768 #define CLK_PCLK_TIMER 36
769 #define CLK_PCLK_SFR0_CTRL 37
770 #define CLK_ATCLK_AUD 38
771 #define CLK_PCLK_DBG_AUD 39
772 #define CLK_SCLK_AUD_CA5 40
773 #define CLK_SCLK_JTAG_TCK 41
774 #define CLK_SCLK_SLIMBUS_CLKIN 42
775 #define CLK_SCLK_AUD_SLIMBUS 43
776 #define CLK_SCLK_AUD_UART 44
777 #define CLK_SCLK_AUD_PCM 45
778 #define CLK_SCLK_I2S_BCLK 46
779 #define CLK_SCLK_AUD_I2S 47
781 #define AUD_NR_CLK 48
784 #define CLK_DIV_PCLK_BUS_133 1
786 #define CLK_ACLK_AHB2APB_BUSP 2
787 #define CLK_ACLK_BUSNP_133 3
788 #define CLK_ACLK_BUSND_400 4
789 #define CLK_PCLK_BUSSRVND_133 5
790 #define CLK_PCLK_PMU_BUS 6
791 #define CLK_PCLK_SYSREG_BUS 7
793 #define CLK_MOUT_ACLK_BUS2_400_USER 8 /* Only CMU_BUS2 */
794 #define CLK_ACLK_BUS2BEND_400 9 /* Only CMU_BUS2 */
795 #define CLK_ACLK_BUS2RTND_400 10 /* Only CMU_BUS2 */
797 #define BUSx_NR_CLK 11
800 #define CLK_FOUT_G3D_PLL 1
802 #define CLK_MOUT_ACLK_G3D_400 2
803 #define CLK_MOUT_G3D_PLL 3
805 #define CLK_DIV_SCLK_HPM_G3D 4
806 #define CLK_DIV_PCLK_G3D 5
807 #define CLK_DIV_ACLK_G3D 6
808 #define CLK_ACLK_BTS_G3D1 7
809 #define CLK_ACLK_BTS_G3D0 8
810 #define CLK_ACLK_ASYNCAPBS_G3D 9
811 #define CLK_ACLK_ASYNCAPBM_G3D 10
812 #define CLK_ACLK_AHB2APB_G3DP 11
813 #define CLK_ACLK_G3DNP_150 12
814 #define CLK_ACLK_G3DND_600 13
815 #define CLK_ACLK_G3D 14
816 #define CLK_PCLK_BTS_G3D1 15
817 #define CLK_PCLK_BTS_G3D0 16
818 #define CLK_PCLK_PMU_G3D 17
819 #define CLK_PCLK_SYSREG_G3D 18
820 #define CLK_SCLK_HPM_G3D 19
822 #define G3D_NR_CLK 20
825 #define CLK_MOUT_ACLK_GSCL_111_USER 1
826 #define CLK_MOUT_ACLK_GSCL_333_USER 2
828 #define CLK_ACLK_BTS_GSCL2 3
829 #define CLK_ACLK_BTS_GSCL1 4
830 #define CLK_ACLK_BTS_GSCL0 5
831 #define CLK_ACLK_AHB2APB_GSCLP 6
832 #define CLK_ACLK_XIU_GSCLX 7
833 #define CLK_ACLK_GSCLNP_111 8
834 #define CLK_ACLK_GSCLRTND_333 9
835 #define CLK_ACLK_GSCLBEND_333 10
836 #define CLK_ACLK_GSD 11
837 #define CLK_ACLK_GSCL2 12
838 #define CLK_ACLK_GSCL1 13
839 #define CLK_ACLK_GSCL0 14
840 #define CLK_ACLK_SMMU_GSCL0 15
841 #define CLK_ACLK_SMMU_GSCL1 16
842 #define CLK_ACLK_SMMU_GSCL2 17
843 #define CLK_PCLK_BTS_GSCL2 18
844 #define CLK_PCLK_BTS_GSCL1 19
845 #define CLK_PCLK_BTS_GSCL0 20
846 #define CLK_PCLK_PMU_GSCL 21
847 #define CLK_PCLK_SYSREG_GSCL 22
848 #define CLK_PCLK_GSCL2 23
849 #define CLK_PCLK_GSCL1 24
850 #define CLK_PCLK_GSCL0 25
851 #define CLK_PCLK_SMMU_GSCL0 26
852 #define CLK_PCLK_SMMU_GSCL1 27
853 #define CLK_PCLK_SMMU_GSCL2 28
855 #define GSCL_NR_CLK 29
858 #define CLK_FOUT_APOLLO_PLL 1
860 #define CLK_MOUT_APOLLO_PLL 2
861 #define CLK_MOUT_BUS_PLL_APOLLO_USER 3
862 #define CLK_MOUT_APOLLO 4
864 #define CLK_DIV_CNTCLK_APOLLO 5
865 #define CLK_DIV_PCLK_DBG_APOLLO 6
866 #define CLK_DIV_ATCLK_APOLLO 7
867 #define CLK_DIV_PCLK_APOLLO 8
868 #define CLK_DIV_ACLK_APOLLO 9
869 #define CLK_DIV_APOLLO2 10
870 #define CLK_DIV_APOLLO1 11
871 #define CLK_DIV_SCLK_HPM_APOLLO 12
872 #define CLK_DIV_APOLLO_PLL 13
874 #define CLK_ACLK_ATBDS_APOLLO_3 14
875 #define CLK_ACLK_ATBDS_APOLLO_2 15
876 #define CLK_ACLK_ATBDS_APOLLO_1 16
877 #define CLK_ACLK_ATBDS_APOLLO_0 17
878 #define CLK_ACLK_ASATBSLV_APOLLO_3_CSSYS 18
879 #define CLK_ACLK_ASATBSLV_APOLLO_2_CSSYS 19
880 #define CLK_ACLK_ASATBSLV_APOLLO_1_CSSYS 20
881 #define CLK_ACLK_ASATBSLV_APOLLO_0_CSSYS 21
882 #define CLK_ACLK_ASYNCACES_APOLLO_CCI 22
883 #define CLK_ACLK_AHB2APB_APOLLOP 23
884 #define CLK_ACLK_APOLLONP_200 24
885 #define CLK_PCLK_ASAPBMST_CSSYS_APOLLO 25
886 #define CLK_PCLK_PMU_APOLLO 26
887 #define CLK_PCLK_SYSREG_APOLLO 27
888 #define CLK_CNTCLK_APOLLO 28
889 #define CLK_SCLK_HPM_APOLLO 29
890 #define CLK_SCLK_APOLLO 30
892 #define APOLLO_NR_CLK 31
894 #endif /* _DT_BINDINGS_CLOCK_EXYNOS5433_H */
projects / firefly-linux-kernel-4.4.55.git / blob