1 #ifndef _RK3288_HDMI_HW_H
2 #define _RK3288_HDMI_HW_H
3 #include <linux/interrupt.h>
4 #include "../rockchip-hdmi.h"
6 /*#define HDMI_INT_USE_POLL 1*/
18 /* Color Space Convertion Mode */
20 CSC_RGB_0_255_TO_RGB_16_235_8BIT, /* RGB 0-255 input to RGB
21 16-235 output that is 8bit
23 CSC_RGB_0_255_TO_RGB_16_235_10BIT, /* RGB 0-255 input to RGB
24 16-235 output that is 8bit
26 CSC_RGB_0_255_TO_ITU601_16_235_8BIT, /* RGB 0-255 input to YCbCr
27 16-235 output according
28 BT601 that is 8bit clolor
30 CSC_RGB_0_255_TO_ITU601_16_235_10BIT, /* RGB 0-255 input to YCbCr
31 16-235 output according
32 BT601 that is 10bit clolor
34 CSC_RGB_0_255_TO_ITU709_16_235_8BIT, /* RGB 0-255 input to YCbCr
35 16-235 output accroding
36 BT709 that is 8bit clolor
38 CSC_RGB_0_255_TO_ITU709_16_235_10BIT, /* RGB 0-255 input to YCbCr
39 16-235 output accroding
40 BT709 that is 10bit clolor
42 CSC_ITU601_16_235_TO_RGB_0_255_8BIT, /* YCbCr 16-235 input to RGB
43 0-255 output according
44 BT601 that is 8bit clolor
46 CSC_ITU709_16_235_TO_RGB_0_255_8BIT, /* YCbCr 16-235 input to RGB
47 0-255 output according
48 BT709 that is 8bit clolor
50 CSC_ITU601_16_235_TO_RGB_16_235_8BIT, /* YCbCr 16-235 input to RGB
51 16-235 output according
52 BT601 that is 8bit clolor
54 CSC_ITU709_16_235_TO_RGB_16_235_8BIT /* YCbCr 16-235 input to RGB
55 16-235 output according
56 BT709 that is 8bit clolor
60 #define HDMI_SCL_RATE (100*1000)
61 #define DDC_I2C_EDID_ADDR 0x50 /* 0xA0/2 = 0x50 */
62 #define DDC_I2C_SEG_ADDR 0x30 /* 0x60/2 = 0x30 */
63 #define DDC_I2C_SCDC_ADDR 0x54 /* 0xa8/2 = 0x54 */
65 /* Register and Field Descriptions */
66 /* Identification Registers */
67 #define IDENTIFICATION_BASE 0x0000
69 #define DESIGN_ID 0x0000
70 #define REVISION_ID 0x0001
71 #define PRODUCT_ID0 0x0002
72 #define PRODUCT_ID1 0x0003
74 #define CONFIG0_ID 0x0004
75 #define m_PREPEN (1 << 7)
76 #define m_AUDSPDIF (1 << 5)
77 #define m_AUDI2S (1 << 4)
78 #define m_HDMI14 (1 << 3)
79 #define m_CSC (1 << 2)
80 #define m_CEC (1 << 1)
81 #define m_HDCP (1 << 0)
83 #define CONFIG1_ID 0x0005
84 #define m_HDMI20 (1 << 5)
85 #define m_CONFAPB (1 << 1)
87 #define CONFIG2_ID 0x0006
90 HDMI_MHL_WITH_HEAC_PHY = 0xb2,
92 HDMI_3D_TX_WITH_HEAC_PHY = 0xe2,
93 HDMI_3D_TX_PHY = 0xf2,
97 #define CONFIG3_ID 0x0007
98 #define m_AHB_AUD_DMA (1 << 1)
99 #define m_GP_AUD (1 << 0)
101 /* Interrupt Registers */
102 #define INTERRUPT_BASE 0x0100
104 #define IH_FC_STAT0 0x0100
105 #define m_AUD_INFOFRAME (1 << 7)
106 #define m_AUD_CONTENT_PROTECT (1 << 6)
107 #define m_AUD_HBR (1 << 5)
108 #define m_AUD_SAMPLE (1 << 2)
109 #define m_AUD_CLK_REGEN (1 << 1)
110 #define m_NULL_PACKET (1 << 0)
112 #define IH_FC_STAT1 0x0101
113 #define m_GMD (1 << 7)
114 #define m_ISCR1 (1 << 6)
115 #define m_ISCR2 (1 << 5)
116 #define m_VSD (1 << 4)
117 #define m_SPD (1 << 3)
118 #define m_AVI_INFOFRAME (1 << 1)
119 #define m_GCP (1 << 0)
121 #define IH_FC_STAT2 0x0102
122 #define m_LOWPRIO_OVERFLOW (1 << 1)
123 #define m_HIGHPRIO_OVERFLOW (1 << 0)
125 #define IH_AS_SATA0 0x0103
126 #define m_FIFO_UNDERRUN (1 << 4)
127 #define m_FIFO_OVERRUN (1 << 3)
128 #define m_AUD_FIFO_UDFLOW_THR (1 << 2)
129 #define m_AUD_FIFO_UDFLOW (1 << 1)
130 #define m_AUD_FIFO_OVERFLOW (1 << 0)
132 #define IH_PHY_STAT0 0x0104
133 #define m_RX_SENSE3 (1 << 5)
134 #define m_RX_SENSE2 (1 << 4)
135 #define m_RX_SENSE1 (1 << 3)
136 #define m_RX_SENSE0 (1 << 2)
137 #define m_TX_PHY_LOCK (1 << 1)
138 #define m_HPD (1 << 0)
140 #define IH_I2CM_STAT0 0x0105
141 #define m_SCDC_READREQ (1 << 2)
142 #define m_I2CM_DONE (1 << 1)
143 #define m_I2CM_ERROR (1 << 0)
145 #define IH_CEC_STAT0 0x0106
146 #define m_WAKEUP (1 << 6)
147 #define m_ERR_FOLLOW (1 << 5)
148 #define m_ERR_INITIATOR (1 << 4)
149 #define m_ARB_LOST (1 << 3)
150 #define m_NACK (1 << 2)
151 #define m_EOM (1 << 1)
152 #define m_DONE (1 << 0)
154 #define IH_VP_STAT0 0x0107
155 #define m_FIFOFULL_REPET (1 << 7)
156 #define m_FIFOEMPTY_REPET (1 << 6)
157 #define m_FIFOFULL_PACK (1 << 5)
158 #define m_FIFOEMPTY_PACK (1 << 4)
159 #define m_FIFOFULL_REMAP (1 << 3)
160 #define m_FIFOEMPTY_REMAP (1 << 2)
161 #define m_FIFOFULL_BYPASS (1 << 1)
162 #define m_FIFOEMPTY_BYPASS (1 << 0)
164 #define IH_I2CMPHY_STAT0 0x0108
165 #define m_I2CMPHY_DONE (1 << 1)
166 #define m_I2CMPHY_ERR (1 << 0)
168 #define IH_AHBDMAAUD_STAT0 0x0109
169 #define m_AUDDMA_INT_BUFOVERRUN (1 << 6)
170 #define m_AUDDMA_INT_ERR (1 << 5)
171 #define m_AUDDMA_INT_LOST (1 << 4)
172 #define m_AUDDMA_INT_RETRYSPLIT (1 << 3)
173 #define m_AUDDMA_INT_DONE (1 << 2)
174 #define m_AUDDMA_INT_BUFFULL (1 << 1)
175 #define m_AUDDMA_INT_BUFEMPTY (1 << 0)
177 #define IH_DECODE 0x0170
178 #define m_IH_FC_STAT0 (1 << 7)
179 #define m_IH_FC_STAT1 (1 << 6)
180 #define m_IH_FC_STAT2_VP (1 << 5)
181 #define m_IH_AS_STAT0 (1 << 4)
182 #define m_IH_PHY (1 << 3)
183 #define m_IH_I2CM_STAT0 (1 << 2)
184 #define m_IH_CEC_STAT0 (1 << 1)
185 #define m_IH_AHBDMAAUD_STAT0 (1 << 0)
187 #define IH_MUTE_FC_STAT0 0x0180
188 #define m_AUDI_MUTE (1 << 7)
189 #define m_ACP_MUTE (1 << 6)
190 #define m_DST_MUTE (1 << 4)
191 #define m_OBA_MUTE (1 << 3)
192 #define m_AUDS_MUTE (1 << 2)
193 #define m_ACR_MUTE (1 << 1)
194 #define m_NULL_MUTE (1 << 0)
196 #define IH_MUTE_FC_STAT1 0x0181
197 #define m_GMD_MUTE (1 << 7)
198 #define m_ISCR1_MUTE (1 << 6)
199 #define m_ISCR2_MUTE (1 << 5)
200 #define m_VSD_MUTE (1 << 4)
201 #define m_SPD_MUTE (1 << 3)
202 #define m_AVI_MUTE (1 << 1)
203 #define m_GCP_MUTE (1 << 0)
205 #define IH_MUTE_FC_STAT2 0x0182
206 #define m_LPRIO_OVERFLOW_MUTE (1 << 1)
207 #define m_HPRIO_OVERFLOW_MUTE (1 << 0)
209 #define IH_MUTE_AS_STAT0 0x0183
210 #define m_FIFO_UNDERRUN_MUTE (1 << 4)
211 #define m_FIFO_OVERRUN_MUTE (1 << 3)
212 #define m_AUD_FIFO_UDF_THR_MUTE (1 << 2)
213 #define m_AUD_FIFO_UDF_MUTE (1 << 1)
214 #define m_AUD_FIFO_OVF_MUTE (1 << 0)
216 #define IH_MUTE_PHY_STAT0 0x0184
217 #define m_RX_SENSE3_MUTE (1 << 5)
218 #define m_RX_SENSE2_MUTE (1 << 4)
219 #define m_RX_SENSE1_MUTE (1 << 3)
220 #define m_RX_SENSE0_MUTE (1 << 2)
221 #define m_TX_PHY_LOCK_MUTE (1 << 1)
222 #define m_HPD_MUTE (1 << 0)
224 #define IH_MUTE_I2CM_STAT0 0x0185
225 #define m_SCDC_READREQ_MUTE (1 << 2)
226 #define v_SCDC_READREQ_MUTE(n) (((n)&0x01) << 2)
227 #define m_I2CM_DONE_MUTE (1 << 1)
228 #define v_I2CM_DONE_MUTE(n) (((n)&0x01) << 1)
229 #define m_I2CM_ERR_MUTE (1 << 0)
230 #define v_I2CM_ERR_MUTE(n) (((n)&0x01) << 0)
232 #define IH_MUTE_CEC_STAT0 0x0186
233 #define m_WAKEUP_MUTE (1 << 6)
234 #define m_ERR_FOLLOW_MUTE (1 << 5)
235 #define m_ERR_INITIATOR_MUTE (1 << 4)
236 #define m_ARB_LOST_MUTE (1 << 3)
237 #define m_NACK_MUTE (1 << 2)
238 #define m_EOM_MUTE (1 << 1)
239 #define m_DONE_MUTE (1 << 0)
241 #define IH_MUTE_VP_STAT0 0x0187
242 #define m_FIFOFULL_REP_MUTE (1 << 7)
243 #define m_FIFOEMPTY_REP_MUTE (1 << 6)
244 #define m_FIFOFULL_PACK_MUTE (1 << 5)
245 #define m_FIFOEMPTY_PACK_MUTE (1 << 4)
246 #define m_FIFOFULL_REMAP_MUTE (1 << 3)
247 #define m_FIFOEMPTY_REMAP_MUTE (1 << 2)
248 #define m_FIFOFULL_BYP_MUTE (1 << 1)
249 #define m_FIFOEMPTY_BYP_MUTE (1 << 0)
251 #define IH_MUTE_I2CMPHY_STAT0 0x0188
252 #define m_I2CMPHY_DONE_MUTE (1 << 1)
253 #define m_I2CMPHY_ERR_MUTE (1 << 0)
255 #define IH_MUTE_AHBDMAAUD_STAT0 0x0189
256 #define IH_MUTE 0x01ff
258 /* Video Sampler Registers */
259 #define VIDEO_SAMPLER_BASE 0x0200
261 #define TX_INVID0 0x0200
262 #define m_INTERNAL_DE_GEN (1 << 7)
263 #define v_INTERNAL_DE_GEN(n) (((n)&0x01) << 7)
265 VIDEO_RGB444_8BIT = 0x01,
266 VIDEO_RGB444_10BIT = 0x03,
267 VIDEO_RGB444_12BIT = 0x05,
268 VIDEO_RGB444_16BIT = 0x07,
269 VIDEO_YCBCR444_8BIT = 0x09, /* or YCbCr420 */
270 VIDEO_YCBCR444_10BIT = 0x0b, /* or YCbCr420 */
271 VIDEO_YCBCR444_12BIT = 0x0d, /* or YCbCr420 */
272 VIDEO_YCBCR444_16BIT = 0x0f, /* or YCbCr420 */
273 VIDEO_YCBCR422_12BIT = 0x12,
274 VIDEO_YCBCR422_10BIT = 0x14,
275 VIDEO_YCBCR422_8BIT = 0x16
277 #define m_VIDEO_MAPPING (0x1f << 0)
278 #define v_VIDEO_MAPPING(n) ((n)&0x1f)
280 #define TX_INSTUFFING 0x0201
281 #define m_BCBDATA_STUFF (1 << 2)
282 #define v_BCBDATA_STUFF(n) (((n)&0x01) << 2)
283 #define m_RCRDATA_STUFF (1 << 1)
284 #define v_RCRDATA_STUFF(n) (((n)&0x01) << 1)
285 #define m_GYDATA_STUFF (1 << 0)
286 #define v_GYDATA_STUFF(n) (((n)&0x01) << 0)
288 #define TX_GYDATA0 0x0202
289 #define TX_GYDATA1 0x0203
290 #define TX_RCRDATA0 0x0204
291 #define TX_RCRDATA1 0x0205
292 #define TX_BCBDATA0 0x0206
293 #define TX_BCBDATA1 0x0207
295 /* Video Packetizer Registers */
296 #define VIDEO_PACKETIZER_BASE 0x0800
298 #define VP_STATUS 0x0800
299 #define m_PACKING_PHASE (0x0f << 0)
301 #define VP_PR_CD 0x0801
303 COLOR_DEPTH_24BIT_DEFAULT = 0,
304 COLOR_DEPTH_24BIT = 0x04,
309 #define m_COLOR_DEPTH (0x0f << 4)
310 #define v_COLOR_DEPTH(n) (((n)&0x0f) << 4)
323 #define m_DESIRED_PR_FACTOR (0x0f << 0)
324 #define v_DESIRED_PR_FACTOR(n) (((n)&0x0f) << 0)
326 #define VP_STUFF 0x0802
327 #define m_IDEFAULT_PHASE (1 << 5)
328 #define v_IDEFAULT_PHASE(n) (((n)&0x01) << 5)
329 #define m_IFIX_PP_TO_LAST (1 << 4)
330 #define m_ICX_GOTO_P0_ST (1 << 3)
335 #define m_YCC422_STUFFING (1 << 2)
336 #define v_YCC422_STUFFING(n) (((n)&0x01) << 2)
337 #define m_PP_STUFFING (1 << 1)
338 #define v_PP_STUFFING(n) (((n)&0x01) << 1)
339 #define m_PR_STUFFING (1 << 0)
340 #define v_PR_STUFFING(n) (((n)&0x01) << 0)
342 #define VP_REMAP 0x0803
348 #define m_YCC422_SIZE (0x03 << 0)
349 #define v_YCC422_SIZE(n) (((n)&0x03) << 0)
351 #define VP_CONF 0x0804
352 #define m_BYPASS_EN (1 << 6)
353 #define v_BYPASS_EN(n) (((n)&0x01) << 6)
354 #define m_PIXEL_PACK_EN (1 << 5)
355 #define v_PIXEL_PACK_EN(n) (((n)&0x01) << 5)
356 #define m_PIXEL_REPET_EN (1 << 4)
357 #define v_PIXEL_REPET_EN(n) (((n)&0x01) << 4)
358 #define m_YCC422_EN (1 << 3)
359 #define v_YCC422_EN(n) (((n)&0x01) << 3)
360 #define m_BYPASS_SEL (1 << 2)
361 #define v_BYPASS_SEL(n) (((n)&0x01) << 2)
363 OUT_FROM_PIXEL_PACKING = 0,
364 OUT_FROM_YCC422_REMAP,
367 #define m_OUTPUT_SEL (0x03 << 0)
368 #define v_OUTPUT_SEL(n) ((n&0x03) << 0)
370 #define VP_MASK 0x0807
371 #define m_OINTFULL_REPET (1 << 7)
372 #define m_OINTEMPTY_REPET (1 << 6)
373 #define m_OINTFULL_PACK (1 << 5)
374 #define m_OINTEMPTY_PACK (1 << 4)
375 #define m_OINTFULL_REMAP (1 << 3)
376 #define m_OINTEMPTY_REMAP (1 << 2)
377 #define m_OINTFULL_BYPASS (1 << 1)
378 #define m_OINTEMPTY_BYPASS (1 << 0)
380 /* Frame Composer Registers */
381 #define FRAME_COMPOSER_BASE 0x1000
383 #define FC_INVIDCONF 0x1000
384 #define m_FC_HDCP_KEEPOUT (1 << 7)
385 #define v_FC_HDCP_KEEPOUT(n) (((n)&0x01) << 7)
386 #define m_FC_VSYNC_POL (1 << 6)
387 #define v_FC_VSYNC_POL(n) (((n)&0x01) << 6)
388 #define m_FC_HSYNC_POL (1 << 5)
389 #define v_FC_HSYNC_POL(n) (((n)&0x01) << 5)
390 #define m_FC_DE_POL (1 << 4)
391 #define v_FC_DE_POL(n) (((n)&0x01) << 4)
392 #define m_FC_HDMI_DVI (1 << 3)
393 #define v_FC_HDMI_DVI(n) (((n)&0x01) << 3)
394 #define m_FC_VBLANK (1 << 1)
395 #define v_FC_VBLANK(n) (((n)&0x01) << 1)
396 #define m_FC_INTERLACE_MODE (1 << 0)
397 #define v_FC_INTERLACE_MODE(n) (((n)&0x01) << 0)
399 #define FC_INHACTIV0 0x1001
401 #define FC_INHACTIV1 0x1002
402 #define v_FC_HACTIVE1(n) ((n) & 0x3f)
403 #define m_FC_H_ACTIVE_13 (1 << 5)
404 #define v_FC_H_ACTIVE_13(n) (((n)&0x01) << 5)
405 #define m_FC_H_ACTIVE_12 (1 << 4)
406 #define v_FC_H_ACTIVE_12(n) (((n)&0x01) << 4)
407 #define m_FC_H_ACTIVE (0x0f << 0)
408 #define v_FC_H_ACTIVE(n) (((n)&0x0f) << 0)
410 #define FC_INHBLANK0 0x1003
412 #define FC_INHBLANK1 0x1004
413 #define v_FC_HBLANK1(n) ((n) & 0x1f)
414 #define m_FC_H_BLANK_12_11 (0x07 << 2)
415 #define v_FC_H_BLANK_12_11(n) (((n)&0x07) << 2)
416 #define m_FC_H_BLANK (0x03 << 0)
417 #define v_FC_H_BLANK(n) (((n)&0x03) << 0)
419 #define FC_INVACTIV0 0x1005
421 #define FC_INVACTIV1 0x1006
422 #define v_FC_VACTIVE1(n) ((n) & 0x1f)
423 #define m_FC_V_ACTIVE_12_11 (0x03 << 3)
424 #define v_FC_V_ACTIVE_12_11(n) (((n)&0x03) << 3)
425 #define m_FC_V_ACTIVE (0x07 << 0)
426 #define v_FC_V_ACTIVE(n) (((n)&0x07) << 0)
428 #define FC_INVBLANK 0x1007
429 #define FC_HSYNCINDELAY0 0x1008
431 #define FC_HSYNCINDELAY1 0x1009
432 #define v_FC_HSYNCINDEAY1(n) ((n) & 0x1f)
433 #define m_FC_H_SYNCFP_12_11 (0x03 << 3)
434 #define v_FC_H_SYNCFP_12_11(n) (((n)&0x03) << 3)
435 #define m_FC_H_SYNCFP (0x07 << 0)
436 #define v_FC_H_SYNCFP(n) (((n)&0x07) << 0)
438 #define FC_HSYNCINWIDTH0 0x100a
440 #define FC_HSYNCINWIDTH1 0x100b
441 #define v_FC_HSYNCWIDTH1(n) ((n) & 0x03)
442 #define m_FC_HSYNC_9 (1 << 1)
443 #define v_FC_HSYNC_9(n) (((n)&0x01) << 1)
444 #define m_FC_HSYNC (1 << 0)
445 #define v_FC_HSYNC(n) (((n)&0x01) << 0)
447 #define FC_VSYNCINDELAY 0x100c
448 #define FC_VSYNCINWIDTH 0x100d
449 #define FC_INFREQ0 0x100e
450 #define FC_INFREQ1 0x100f
451 #define FC_INFREQ2 0x1010
452 #define FC_CTRLDUR 0x1011
453 #define FC_EXCTRLDUR 0x1012
454 #define FC_EXCTRLSPAC 0x1013
455 #define FC_CH0PREAM 0x1014
456 #define FC_CH1PREAM 0x1015
457 #define FC_CH2PREAM 0x1016
459 #define FC_AVICONF3 0x1017
460 enum YCC_QUAN_RANGE {
461 YQ_LIMITED_RANGE = 0,
465 #define m_FC_YQ (0x03 << 2)
466 #define v_FC_YQ(n) (((n)&0x03) << 2)
467 enum IT_CONTENT_TYPE {
473 #define m_FC_CN (0x03 << 0)
474 #define v_FC_CN(n) (((n)&0x03) << 0)
476 #define FC_GCP 0x1018
477 #define m_FC_DEFAULT_PHASE (1 << 2)
478 #define v_FC_DEFAULT_PHASE(n) (((n)&0x01) << 2)
479 #define m_FC_SET_AVMUTE (1 << 1)
480 #define v_FC_SET_AVMUTE(n) (((n)&0x01) << 1)
481 #define m_FC_CLR_AVMUTE (1 << 0)
482 #define v_FC_CLR_AVMUTE(n) (((n)&0x01) << 0)
485 AVI_COLOR_MODE_RGB = 0,
486 AVI_COLOR_MODE_YCBCR422,
487 AVI_COLOR_MODE_YCBCR444,
488 AVI_COLOR_MODE_YCBCR420
491 AVI_COLORIMETRY_NO_DATA = 0,
492 AVI_COLORIMETRY_SMPTE_170M,
493 AVI_COLORIMETRY_ITU709,
494 AVI_COLORIMETRY_EXTENDED
497 AVI_CODED_FRAME_ASPECT_NO_DATA,
498 AVI_CODED_FRAME_ASPECT_4_3,
499 AVI_CODED_FRAME_ASPECT_16_9
502 ACTIVE_ASPECT_RATE_DEFAULT = 0x08,
503 ACTIVE_ASPECT_RATE_4_3,
504 ACTIVE_ASPECT_RATE_16_9,
505 ACTIVE_ASPECT_RATE_14_9
508 AVI_QUANTIZATION_RANGE_DEFAULT = 0,
509 AVI_QUANTIZATION_RANGE_LIMITED,
510 AVI_QUANTIZATION_RANGE_FULL
513 #define FC_AVICONF0 0x1019
514 #define m_FC_RGC_YCC_2 (1 << 7) /* use for HDMI2.0 TX */
515 #define v_FC_RGC_YCC_2(n) (((n)&0x01) << 7)
516 #define m_FC_ACTIV_FORMAT (1 << 6)
517 #define v_FC_ACTIV_FORMAT(n) (((n)&0x01) << 6)
518 #define m_FC_SCAN_INFO (0x03 << 4)
519 #define v_FC_SCAN_INFO(n) (((n)&0x03) << 4)
520 #define m_FC_BAR_FORMAT (0x03 << 2)
521 #define v_FC_BAR_FORMAT(n) (((n)&0x03) << 2)
522 #define m_FC_RGC_YCC (0x03 << 0)
523 #define v_FC_RGC_YCC(n) (((n)&0x03) << 0)
525 #define FC_AVICONF1 0x101a
526 #define m_FC_COLORIMETRY (0x03 << 6)
527 #define v_FC_COLORIMETRY(n) (((n)&0x03) << 6)
528 #define m_FC_PIC_ASPEC_RATIO (0x03 << 4)
529 #define v_FC_PIC_ASPEC_RATIO(n) (((n)&0x03) << 4)
530 #define m_FC_ACT_ASPEC_RATIO (0x0f << 0)
531 #define v_FC_ACT_ASPEC_RATIO(n) (((n)&0x0f) << 0)
533 #define FC_AVICONF2 0x101b
534 #define m_FC_IT_CONTENT (1 << 7)
535 #define v_FC_IT_CONTENT(n) (((n)&0x01) << 7)
536 #define m_FC_EXT_COLORIMETRY (0x07 << 4)
537 #define v_FC_EXT_COLORIMETRY(n) (((n)&0x07) << 4)
538 #define m_FC_QUAN_RANGE (0x03 << 2)
539 #define v_FC_QUAN_RANGE(n) (((n)&0x03) << 2)
540 #define m_FC_NUN_PIC_SCALE (0x03 << 0)
541 #define v_FC_NUN_PIC_SCALE(n) (((n)&0x03) << 0)
543 #define FC_AVIVID 0x101c
544 #define m_FC_AVIVID_H (1 << 7) /* use for HDMI2.0 TX */
545 #define v_FC_AVIVID_H(n) (((n)&0x01) << 7)
546 #define m_FC_AVIVID (0x7f << 0)
547 #define v_FC_AVIVID(n) (((n)&0x7f) << 0)
549 #define FC_AVIETB0 0x101d
550 #define FC_AVIETB1 0x101e
551 #define FC_AVISBB0 0x101f
552 #define FC_AVISBB1 0x1020
553 #define FC_AVIELB0 0x1021
554 #define FC_AVIELB1 0x1022
555 #define FC_AVISRB0 0x1023
556 #define FC_AVISRB1 0x1024
558 #define FC_AUDICONF0 0x1025
559 #define m_FC_CHN_CNT (0x07 << 4)
560 #define v_FC_CHN_CNT(n) (((n)&0x07) << 4)
561 #define m_FC_CODING_TYEP (0x0f << 0)
562 #define v_FC_CODING_TYEP(n) (((n)&0x0f) << 0)
564 #define FC_AUDICONF1 0x1026
565 #define m_FC_SAMPLE_SIZE (0x03 << 4)
566 #define v_FC_SAMPLE_SIZE(n) (((n)&0x03) << 4)
567 #define m_FC_SAMPLE_FREQ (0x07 << 0)
568 #define v_FC_SAMPLE_FREQ(n) (((n)&0x07) << 0)
570 #define FC_AUDICONF2 0x1027
572 #define FC_AUDICONF3 0x1028
573 #define m_FC_LFE_PBL (0x03 << 5) /*only use for HDMI1.4 TX*/
574 #define v_FC_LFE_PBL(n) (((n)&0x03) << 5)
575 #define m_FC_DM_INH (1 << 4)
576 #define v_FC_DM_INH(n) (((n)&0x01) << 4)
577 #define m_FC_LSV (0x0f << 0)
578 #define v_FC_LSV(n) (((n)&0x0f) << 0)
580 #define FC_VSDIEEEID2 0x1029
581 #define FC_VSDSIZE 0x102a
582 #define FC_VSDIEEEID1 0x1030
583 #define FC_VSDIEEEID0 0x1031
584 #define FC_VSDPAYLOAD0 0x1032 /* 0~23 */
585 #define FC_SPDVENDORNAME0 0x104a /* 0~7 */
586 #define FC_SPDPRODUCTNAME0 0x1052 /* 0~15 */
587 #define FC_SPDDEVICEINF 0x1062
589 #define FC_AUDSCONF 0x1063
590 #define m_AUD_PACK_SAMPFIT (0x0f << 4)
591 #define v_AUD_PACK_SAMPFIT(n) (((n)&0x0f) << 4)
592 #define m_AUD_PACK_LAYOUT (1 << 0)
593 #define v_AUD_PACK_LAYOUT(n) (((n)&0x01) << 0)
595 #define FC_AUDSSTAT 0x1064
596 #define FC_AUDSV 0x1065
597 #define FC_AUDSU 0x1066
598 #define FC_AUDSCHNLS0 0x1067 /*0~8*/
599 #define FC_AUDSCHNLS1 0x1068
600 #define FC_AUDSCHNLS2 0x1069
601 #define FC_AUDSCHNLS3 0x106a
602 #define FC_AUDSCHNLS4 0x106b
603 #define FC_AUDSCHNLS5 0x106c
604 #define FC_AUDSCHNLS6 0x106d
605 #define FC_AUDSCHNLS7 0x106e
606 #define FC_AUDSCHNLS8 0x106f
618 #define m_AUDIO_SAMPLE_RATE (0x0f << 0)
619 #define v_AUDIO_SAMPLE_RATE(n) (((n)&0x0f) << 0)
620 #define m_AUDIO_ORI_SAMPLE_RATE (0x0f << 4)
621 #define v_AUDIO_ORI_SAMPLE_RATE(n) (((~n)&0x0f) << 4)
622 #define m_AUDIO_WORD_LENGTH (0x0f << 0)
623 #define v_AUDIO_WORD_LENGTH(n) (((n)&0x0f) << 0)
625 #define FC_CTRLQHIGH 0x1073
626 #define FC_CTRLQLOW 0x1074
627 #define FC_ACP0 0x1075
628 #define FC_ACP16 0x1082 /* 16~1 */
629 #define FC_ISCR1_0 0x1092
630 #define FC_ISCR1_16 0x1093 /* 16~1 */
631 #define FC_ISCR2_15 0x10a3 /* 15~0 */
633 #define FC_DATAUTO0 0x10b3
634 #define m_SPD_AUTO (1 << 4)
635 #define v_SPD_AUTO(n) (((n)&0x01) << 4)
636 #define m_VSD_AUTO (1 << 3)
637 #define v_VSD_AUTO(n) (((n)&0x01) << 3)
638 #define m_ISCR2_AUTO (1 << 2)
639 #define v_ISCR2_AUTO(n) (((n)&0x01) << 2)
640 #define m_ISCR1_AUTO (1 << 1)
641 #define v_ISCR1_AUTO(n) (((n)&0x01) << 1)
642 #define m_ACP_AUTO (1 << 0)
643 #define v_ACP_AUTO(n) (((n)&0x01) << 0)
645 #define FC_DATAUTO1 0x10b4
646 #define FC_DATAUTO2 0x10b5
648 #define FC_DATMAN 0x10b6
649 #define m_SPD_MAN (1 << 4)
650 #define v_SPD_MAN(n) (((n)&0x01) << 4)
651 #define m_VSD_MAN (1 << 3)
652 #define v_VSD_MAN(n) (((n)&0x01) << 3)
653 #define m_ISCR2_MAN (1 << 2)
654 #define v_ISCR2_MAN(n) (((n)&0x01) << 2)
655 #define m_ISCR1_MAN (1 << 1)
656 #define v_ISCR1_MAN(n) (((n)&0x01) << 1)
657 #define m_ACP_MAN (1 << 0)
658 #define v_ACP_MAN(n) (((n)&0x01) << 0)
660 #define FC_DATAUTO3 0x10b7
661 #define m_AVI_AUTO (1 << 3)
662 #define v_AVI_AUTO(n) (((n)&0x01) << 3)
663 #define m_GCP_AUTO (1 << 2)
664 #define v_GCP_AUTO(n) (((n)&0x01) << 2)
665 #define m_AAI_AUTO (1 << 1)
666 #define v_AAI_AUTO(n) (((n)&0x01) << 1)
667 #define m_ACR_AUTO (1 << 0)
668 #define v_ACR_AUTO(n) (((n)&0x01) << 0)
669 #define FC_RDRB0 0x10b8
670 #define FC_RDRB1 0x10b9
671 #define FC_RDRB2 0x10ba
672 #define FC_RDRB3 0x10bb
673 #define FC_RDRB4 0x10bc
674 #define FC_RDRB5 0x10bd
675 #define FC_RDRB6 0x10be
676 #define FC_RDRB7 0x10bf
677 #define m_AVI_PACKETS_PER_FRAME (0xf << 4)
678 #define m_AVI_PACKERS_LINE_SPACING (0xf)
679 #define v_AVI_PACKETS_PER_FRAME(n) (((n) & 0x0f) << 4)
680 #define v_AVI_PACKERS_LINE_SPACING(n) (((n) & 0x0f) << 0)
681 #define FC_MASK0 0x10d2
682 #define FC_MASK1 0x10d6
683 #define FC_MASK2 0x10da
685 #define FC_PRCONF 0x10e0
686 #define m_FC_PR_FACTOR (0x0f << 4)
687 #define v_FC_PR_FACTOR(n) (((n)&0x0f) << 4)
689 #define FC_SCRAMBLER_CTRL 0x10e1
690 #define m_FC_SCRAMBLE_UCP (1 << 4)
691 #define v_FC_SCRAMBLE_UCP(n) (((n)&0x01) << 4)
692 #define m_FC_SCRAMBLE_EN (1 << 0)
693 #define v_FC_SCRAMBLE_EN(n) (((n)&0x01) << 0)
695 #define FC_GMD_STAT 0x1100
696 #define FC_GMD_EN 0x1101
697 #define FC_GMD_UP 0x1102
698 #define FC_GMD_CONF 0x1103
699 #define FC_GMD_HB 0x1104
700 #define FC_GMD_PB0 0x1105 /*0~27*/
702 #define FC_DBGFORCE 0x1200
703 #define m_FC_FORCEAUDIO (1 << 4)
704 #define v_FC_FORCEAUDIO(n) (((n)&0x01) << 4)
705 #define m_FC_FORCEVIDEO (1 << 0)
706 #define v_FC_FORCEVIDEO(n) (((n)&0x01) << 0)
708 #define FC_DBGAUD0CH0 0x1201 /* aud0~aud2 ch0 */
709 #define FC_DBGAUD0CH1 0x1204 /* aud0~aud2 ch1 */
710 #define FC_DBGAUD0CH2 0x1207 /* aud0~aud2 ch2 */
711 #define FC_DBGAUD0CH3 0x120a /* aud0~aud2 ch3 */
712 #define FC_DBGAUD0CH4 0x120d /* aud0~aud2 ch4 */
713 #define FC_DBGAUD0CH5 0x1210 /* aud0~aud2 ch5 */
714 #define FC_DBGAUD0CH6 0x1213 /* aud0~aud2 ch6 */
715 #define FC_DBGAUD0CH7 0x1216 /* aud0~aud2 ch7 */
716 #define FC_DBGTMDS0 0x1219
717 #define FC_DBGTMDS1 0x121a
718 #define FC_DBGTMDS2 0x121b
720 /* HDMI Source PHY Registers */
721 #define HDMI_SOURCE_PHY_BASE 0x3000
723 #define PHY_CONF0 0x3000
724 #define m_POWER_DOWN_EN (1 << 7)/* no use */
725 #define v_POWER_DOWN_EN(n) (((n)&0x01) << 7)
726 #define m_TMDS_EN (1 << 6)/* no use */
727 #define v_TMDS_EN(n) (((n)&0x01) << 6)
728 #define m_SVSRET_SIG (1 << 5)/* depend on PHY_MHL_COMB0=1 */
729 #define v_SVSRET_SIG(n) (((n)&0x01) << 5)
730 #define m_PDDQ_SIG (1 << 4)
731 /*1: power down phy; 0: power on phy */
732 #define v_PDDQ_SIG(n) (((n)&0x01) << 4)
733 #define m_TXPWRON_SIG (1 << 3)
734 /*1: power on transmitter; 0: power down transmitter */
735 #define v_TXPWRON_SIG(n) (((n)&0x01) << 3)
736 #define m_ENHPD_RXSENSE_SIG (1 << 2)
737 /*1: enable detect hdp & rx sense */
738 #define v_ENHPD_RXSENSE_SIG(n) (((n)&0x01) << 2)
739 #define m_SEL_DATAEN_POL (1 << 1)
740 #define v_SEL_DATAEN_POL(n) (((n)&0x01) << 1)
741 #define m_SEL_INTERFACE (1 << 0)
742 #define v_SEL_INTERFACE(n) (((n)&0x01) << 0)
744 #define PHY_TST0 0x3001
745 #define m_TEST_CLR_SIG (1 << 5)
746 #define m_TEST_EN_SIG (1 << 4)
747 #define m_TEST_CLK_SIG (1 << 0)
749 #define PHY_TST1 0x3002
750 #define PHY_TST2 0x3003
751 #define PHY_STAT0 0x3004
752 #define PHY_INI0 0x3005
753 #define PHY_MASK 0x3006
754 #define PHY_POL0 0x3007
755 #define m_PHY_RX_SENSE3 (1 << 7)
756 #define v_PHY_TX_SENSE3(n) (((n)&0x01) << 7)
757 #define m_PHY_RX_SENSE2 (1 << 6)
758 #define v_PHY_TX_SENSE2(n) (((n)&0x01) << 6)
759 #define m_PHY_RX_SENSE1 (1 << 5)
760 #define v_PHY_TX_SENSE1(n) (((n)&0x01) << 5)
761 #define m_PHY_RX_SENSE0 (1 << 4)
762 #define v_PHY_TX_SENSE0(n) (((n)&0x01) << 4)
763 #define m_PHY_HPD (1 << 1)
764 #define v_PHY_HPD (((n)&0x01) << 1)
765 #define m_PHY_LOCK (1 << 0)
766 #define v_PHY_LOCK(n) (((n)&0x01) << 0)
768 #define PHY_PCLFREQ0 0x3008
769 #define PHY_PCLFREQ1 0x3009
770 #define PHY_PLLCFGFREQ0 0x300a
771 #define PHY_PLLCFGFREQ1 0x300b
772 #define PHY_PLLCFGFREQ2 0x300c
774 /* I2C Master PHY Registers */
775 #define I2C_MASTER_PHY_BASE 0x3020
777 #define PHY_I2CM_SLAVE 0x3020
778 #define PHY_GEN2_ADDR 0x69
779 #define PHY_HEAC_ADDR 0x49
780 #define PHY_I2C_SLAVE_ADDR 0x54
782 #define PHY_I2CM_ADDRESS 0x3021
783 #define PHY_I2CM_DATAO_1 0x3022
784 #define PHY_I2CM_DATAO_0 0x3023
785 #define PHY_I2CM_DATAI_1 0x3024
786 #define PHY_I2CM_DATAI_0 0x3025
788 #define PHY_I2CM_OPERATION 0x3026
789 #define m_PHY_I2CM_WRITE (1 << 4)
790 #define m_PHY_I2CM_READ (1 << 0)
792 #define PHY_I2CM_INT 0x3027
793 #define m_PHY_I2CM_DONE_INT_POL (1 << 3)
794 #define v_PHY_I2CM_DONE_INT_POL(n) (((n)&0x01) << 3)
795 #define m_PHY_I2CM_DONE_MASK (1 << 2)
796 #define v_PHY_I2CM_DONE_MASK(n) (((n)&0x01) << 2)
797 #define m_PHY_I2CM_DONE_INT (1 << 1)
798 #define m_PHY_I2CM_DONE_STATUS (1 << 0)
800 #define PHY_I2CM_CTLINT 0x3028
801 #define m_PHY_I2CM_NACK_POL (1 << 7)
802 #define v_PHY_I2CM_NACK_POL(n) (((n)&0x01) << 7)
803 #define m_PHY_I2CM_NACK_MASK (1 << 6)
804 #define v_PHY_I2CM_NACK_MASK(n) (((n)&0x01) << 6)
805 #define m_PHY_I2CM_NACK_INT (1 << 5)
806 #define m_PHY_I2CM_NACK_STATUS (1 << 4)
807 #define m_PHY_I2CM_ARB_POL (1 << 3)
808 #define v_PHY_I2CM_ARB_POL(n) (((n)&0x01) << 3)
809 #define m_PHY_I2CM_ARB_MASK (1 << 2)
810 #define v_PHY_I2CM_ARB_MASK(n) (((n)&0x01) << 2)
811 #define m_PHY_I2CM_ARB_INT (1 << 1)
812 #define m_PHY_I2CM_ARB_STATUS (1 << 0)
814 #define PHY_I2CM_DIV 0x3029
815 #define m_PHY_I2CM_FAST_STD (1 << 3)
816 #define v_PHY_I2CM_FAST_STD(n) (((n)&0x01) << 3)
818 #define PHY_I2CM_SOFTRSTZ 0x302a
819 #define m_PHY_I2CM_SOFTRST (1 << 0)
820 #define v_PHY_I2CM_SOFTRST(n) (((n)&0x01) << 0)
822 #define PHY_I2CM_SS_SCL_HCNT_1_ADDR 0x302b
823 #define PHY_I2CM_SS_SCL_HCNT_0_ADDR 0x302c
824 #define PHY_I2CM_SS_SCL_LCNT_1_ADDR 0x302d
825 #define PHY_I2CM_SS_SCL_LCNT_0_ADDR 0x302e
826 #define PHY_I2CM_FS_SCL_HCNT_1_ADDR 0x302f
827 #define PHY_I2CM_FS_SCL_HCNT_0_ADDR 0x3030
828 #define PHY_I2CM_FS_SCL_LCNT_1_ADDR 0x3031
829 #define PHY_I2CM_FS_SCL_LCNT_0_ADDR 0x3032
830 #define PHY_I2CM_SDA_HOLD 0x3033
832 /* Audio Sampler Registers */
833 #define AUDIO_SAMPLER_BASE 0x3100
835 #define AUD_CONF0 0x3100
836 #define m_SW_AUD_FIFO_RST (1 << 7)
837 #define v_SW_AUD_FIFO_RST(n) (((n)&0x01) << 7)
842 #define m_I2S_SEL (1 << 5)
843 #define v_I2S_SEL(n) (((n)&0x01) << 5)
848 I2S_CHANNEL_7_8 = 0xf
850 #define m_I2S_IN_EN (0x0f << 0)
851 #define v_I2S_IN_EN(n) (((n)&0x0f) << 0)
853 #define AUD_CONF1 0x3101
855 I2S_STANDARD_MODE = 0,
856 I2S_RIGHT_JUSTIFIED_MODE,
857 I2S_LEFT_JUSTIFIED_MODE,
861 #define m_I2S_MODE (0x07 << 5)
862 #define v_I2S_MODE(n) (((n)&0x07) << 5)
864 I2S_16BIT_SAMPLE = 16,
874 #define m_I2S_WIDTH (0x1f << 0)
875 #define v_I2S_WIDTH(n) (((n)&0x1f) << 0)
877 #define AUD_INT 0x3102
878 #define AUD_SPDIFINT 0x3302
879 #define m_FIFO_EMPTY_MASK (1 << 3)
880 #define v_FIFO_EMPTY_MASK(n) (((n)&0x01) << 3)
881 #define m_FIFO_FULL_MASK (1 << 2)
882 #define v_FIFO_FULL_MASK(n) (((n)&0x01) << 2)
884 #define AUD_CONF2 0x3103
885 #define m_NLPCM_EN (1 << 1)
886 #define v_NLPCM_EN(n) (((n)&0x01) << 1)
887 #define m_HBR_EN (1 << 0)
888 #define v_HBR_EN(n) (((n)&0x01) << 0)
890 #define AUD_INT1 0x3104
891 #define AUD_SPDIFINT1 0x3303
892 #define m_FIFO_OVERRUN_MASK (1 << 4)
893 #define v_FIFO_OVERRUN_MASK(n) (((n)&0x01) << 4)
895 /***************N-CTS Table**************/
896 /* TMDS LOWCLK: <=148.5M */
897 /* TMDS MIDCLK: 297M */
898 /* TMDS HIGHCLK: 594M */
899 #define N_32K_LOWCLK 0x1000
900 #define N_32K_MIDCLK 0x0c00
901 #define N_32K_HIGHCLK 0x0c00
902 #define N_441K_LOWCLK 0x1880
903 #define N_441K_MIDCLK 0x1260
904 #define N_441K_HIGHCLK 0x24c0
905 #define N_48K_LOWCLK 0x1800
906 #define N_48K_MIDCLK 0x1400
907 #define N_48K_HIGHCLK 0x1800
908 #define N_882K_LOWCLK 0x3100
909 #define N_882K_MIDCLK 0x24c0
910 #define N_882K_HIGHCLK 0x4980
911 #define N_96K_LOWCLK 0x3000
912 #define N_96K_MIDCLK 0x2800
913 #define N_96K_HIGHCLK 0x3000
914 #define N_1764K_LOWCLK 0x6200
915 #define N_1764K_MIDCLK 0x4980
916 #define N_1764K_HIGHCLK 0x9300
917 #define N_192K_LOWCLK 0x6000
918 #define N_192K_MIDCLK 0x5000
919 #define N_192K_HIGHCLK 0x6000
921 #define CALC_CTS(N, TMDSCLK, FS) (((N) / 32) * (TMDSCLK) / ((FS) * 4))
922 /****************************************/
924 #define AUD_N1 0x3200
925 #define AUD_N2 0x3201
927 #define AUD_N3 0x3202
928 #define m_NCTS_ATOMIC_WR (1 << 7)
929 #define v_NCTS_ATOMIC_WR(n) (((n)&0x01) << 7)
930 #define m_AUD_N3 (0x0f << 0)
931 #define v_AUD_N3(n) (((n)&0x0f) << 0)
933 #define AUD_CTS1 0x3203
934 #define AUD_CTS2 0x3204
936 #define AUD_CTS3 0x3205
946 #define m_N_SHIFT (0x07 << 5)
947 #define v_N_SHIFT(n) (((n)&0x07) << 5)
948 #define m_CTS_MANUAL (1 << 4)
949 #define v_CTS_MANUAL(n) (((n)&0x01) << 4)
950 #define m_AUD_CTS3 (0x0f << 0)
951 #define v_AUD_CTS3(n) (((n)&0x0f) << 0)
953 #define AUD_INPUTCLKFS 0x3206
961 #define m_LFS_FACTOR (0x07 << 0)
962 #define v_LFS_FACTOR(n) (((n)&0x07) << 0)
964 #define AUD_SPDIF0 0x3300
965 #define m_SW_SAUD_FIFO_RST (1 << 7)
966 #define v_SW_SAUD_FIFO_RST(n) (((n)&0x01) << 7)
968 #define AUD_SPDIF1 0x3301
973 #define m_SET_NLPCM (1 << 7)
974 #define v_SET_NLPCM(n) (((n)&0x01) << 7)
975 #define m_SPDIF_HBR_MODE (1 << 6)
976 #define v_SPDIF_HBR_MODE(n) (((n)&0x01) << 6)
977 #define m_SPDIF_WIDTH (0x1f << 0)
978 #define v_SPDIF_WIDTH(n) (((n)&0x1f) << 0)
980 /* Generic Parallel Audio Interface Registers */
981 #define GP_AUDIO_INTERFACE_BASE 0x3500
983 #define GP_CONF0 0x3500
984 #define GP_CONF1 0x3501
985 #define GP_CONF2 0x3502
986 #define GP_MASK 0x3506
988 /* Audio DMA Registers */
989 #define AUDIO_DMA_BASE 0x3600
991 #define AHB_DMA_CONF0 0x3600
992 #define AHB_DMA_START 0x3601
993 #define AHB_DMA_STOP 0x3602
994 #define AHB_DMA_THRSLD 0x3603
995 #define AHB_DMA_STRADDR_SET0_0 0x3604 /* 0~3 */
996 #define AHB_DMA_STPADDR_SET0_0 0x3608 /* 0~3 */
997 #define AHB_DMA_BSTADDR0 0x360c /* 0~3 */
998 #define AHB_DMA_MBLENGTH0 0x3610 /* 0~3 */
999 #define AHB_DMA_MASK 0x3614
1000 #define AHB_DMA_CONF1 0x3616
1001 #define AHB_DMA_BUFFMASK 0x3619
1002 #define AHB_DMA_MASK1 0x361b
1003 #define AHB_DMA_STATUS 0x361c
1004 #define AHB_DMA_CONF2 0x361d
1005 #define AHB_DMA_STRADDR_SET1_0 0x3620 /* 0~3 */
1006 #define AHB_DMA_STPADDR_SET1_0 0x3624 /* 0~3 */
1008 /* Main Controller Registers */
1009 #define MAIN_CONTROLLER_BASE 0x4000
1011 #define MC_CLKDIS 0x4001
1012 #define m_HDCPCLK_DISABLE (1 << 6)
1013 #define v_HDCPCLK_DISABLE(n) (((n)&0x01) << 6)
1014 #define m_CECCLK_DISABLE (1 << 5)
1015 #define v_CECCLK_DISABLE(n) (((n)&0x01) << 5)
1016 #define m_CSCCLK_DISABLE (1 << 4)
1017 #define v_CSCCLK_DISABLE(n) (((n)&0x01) << 4)
1018 #define m_AUDCLK_DISABLE (1 << 3)
1019 #define v_AUDCLK_DISABLE(n) (((n)&0x01) << 3)
1020 #define m_PREPCLK_DISABLE (1 << 2)
1021 #define v_PREPCLK_DISABLE(n) (((n)&0x01) << 2)
1022 #define m_TMDSCLK_DISABLE (1 << 1)
1023 #define v_TMDSCLK_DISABLE(n) (((n)&0x01) << 1)
1024 #define m_PIXELCLK_DISABLE (1 << 0)
1025 #define v_PIXELCLK_DISABLE(n) (((n)&0x01) << 0)
1027 #define MC_SWRSTZREQ 0x4002
1028 #define m_IGPA_SWRST (1 << 7)
1029 #define v_IGPA_SWRST(n) (((n)&0x01) << 7)
1030 #define m_CEC_SWRST (1 << 6)
1031 #define v_CEC_SWRST(n) (((n)&0x01) << 6)
1032 #define m_ISPDIF_SWRST (1 << 4)
1033 #define v_ISPDIF_SWRST(n) (((n)&0x01) << 4)
1034 #define m_II2S_SWRST (1 << 3)
1035 #define v_II2S_SWRST(n) (((n)&0x01) << 3)
1036 #define m_PREP_SWRST (1 << 2)
1037 #define v_PREP_SWRST(n) (((n)&0x01) << 2)
1038 #define m_TMDS_SWRST (1 << 1)
1039 #define v_TMDS_SWRST(n) (((n)&0x01) << 1)
1040 #define m_PIXEL_SWRST (1 << 0)
1041 #define v_PIXEL_SWRST(n) (((n)&0x01) << 0)
1043 #define MC_OPCTRL 0x4003
1044 #define m_HDCP_BLOCK_BYP (1 << 0)
1045 #define v_HDCP_BLOCK_BYP(n) (((n)&0x01) << 0)
1047 #define MC_FLOWCTRL 0x4004
1048 #define m_FEED_THROUGH_OFF (1 << 0)
1049 #define v_FEED_THROUGH_OFF(n) (((n)&0x01) << 0)
1051 #define MC_PHYRSTZ 0x4005
1052 #define m_PHY_RSTZ (1 << 0)
1053 #define v_PHY_RSTZ(n) (((n)&0x01) << 0)
1055 #define MC_LOCKONCLOCK 0x4006
1056 #define m_IGPACLK_ON (1 << 7)
1057 #define v_IGPACLK_ON(n) (((n)&0x01) << 7)
1058 #define m_PCLK_ON (1 << 6)
1059 #define v_PCLK_ON(n) (((n)&0x01) << 6)
1060 #define m_TMDSCLK_ON (1 << 5)
1061 #define v_TMDSCLK_ON(n) (((n)&0x01) << 5)
1062 #define m_PREPCLK_ON (1 << 4)
1063 #define v_PREPCLK_ON(n) (((n)&0x01) << 4)
1064 #define m_I2SCLK_ON (1 << 3)
1065 #define v_I2SCLK_ON(n) (((n)&0x01) << 3)
1066 #define m_SPDIFCLK_ON (1 << 2)
1067 #define v_SPDIFCLK_ON(n) (((n)&0x01) << 2)
1068 #define m_CECCLK_ON (1 << 0)
1069 #define v_CECCLK_ON(n) (((n)&0x01) << 0)
1071 #define MC_HEACPHY_RST 0x4007
1072 #define m_HEAC_PHY_RST (1 << 0)
1073 #define v_HEAC_PHY_RST(n) (((n)&0x01) << 0)
1075 #define MC_LOCKONCLOCK_2 0x4009
1076 #define m_AHB_AUD_DMA_CLK (1 << 0)
1077 #define v_AHB_AUD_DMA_CLK(n) (((n)&0x01) << 0)
1079 #define MC_SWRSTZREQ_2 0x400a
1080 #define m_AHB_AUD_DMA_RST (1 << 7)
1081 #define v_AHB_AUD_DMA_RST(n) (((n)&0x01) << 7)
1083 /* Color Space Converter Registers */
1084 #define COLOR_SPACE_CONVERTER_BASE 0x4100
1086 #define CSC_CFG 0x4100
1087 #define m_CSC_INTPMODE (0x03 << 4)
1088 #define v_CSC_INTPMODE(n) (((n)&0x03) << 4)
1089 #define m_CSC_DECIMODE (0x03 << 0)
1090 #define v_CSC_DECIMODE(n) (((n)&0x03) << 0)
1092 #define CSC_SCALE 0x4101
1093 #define m_CSC_COLOR_DEPTH (0x0f << 4)
1094 #define v_CSC_COLOR_DEPTH(n) (((n)&0x0f) << 4)
1095 #define m_CSC_SCALE (0x03 << 0)
1096 #define v_CSC_SCALE(n) (((n)&0x03) << 0)
1098 #define CSC_COEF_A1_MSB 0x4102
1099 #define CSC_COEF_A1_LSB 0x4103
1100 #define CSC_COEF_A2_MSB 0x4104
1101 #define CSC_COEF_A2_LSB 0x4105
1102 #define CSC_COEF_A3_MSB 0x4106
1103 #define CSC_COEF_A3_LSB 0x4107
1104 #define CSC_COEF_A4_MSB 0x4108
1105 #define CSC_COEF_A4_LSB 0x4109
1106 #define CSC_COEF_B1_MSB 0x410a
1107 #define CSC_COEF_B1_LSB 0x410b
1108 #define CSC_COEF_B2_MSB 0x410c
1109 #define CSC_COEF_B2_LSB 0x410d
1110 #define CSC_COEF_B3_MSB 0x410e
1111 #define CSC_COEF_B3_LSB 0x410f
1112 #define CSC_COEF_B4_MSB 0x4110
1113 #define CSC_COEF_B4_LSB 0x4111
1114 #define CSC_COEF_C1_MSB 0x4112
1115 #define CSC_COEF_C1_LSB 0x4113
1116 #define CSC_COEF_C2_MSB 0x4114
1117 #define CSC_COEF_C2_LSB 0x4115
1118 #define CSC_COEF_C3_MSB 0x4116
1119 #define CSC_COEF_C3_LSB 0x4117
1120 #define CSC_COEF_C4_MSB 0x4118
1121 #define CSC_COEF_C4_LSB 0x4119
1122 #define CSC_SPARE_1 0x411a
1123 #define CSC_SPARE_2 0x411b
1125 /* HDCP Encryption Engine Registers */
1126 #define HDCP_ENCRYPTION_ENGINE_BASE 0x5000
1128 #define A_HDCPCFG0 0x5000
1129 #define m_HDCP_ENHANCE_LIKE (1 << 7)
1130 #define v_HDCP_ENHANCE_LIKE(n) (((n)&0x01) << 7)
1131 #define m_I2C_FAST_MODE (1 << 6)
1132 #define v_I2C_FAST_MODE(n) (((n)&0x01) << 6)
1133 #define m_ENCRYPT_BYPASS (1 << 5)
1134 #define v_ENCRYPT_BYPASS(n) (((n)&0x01) << 5)
1135 #define m_SYNC_RI_CHECK (1 << 4)
1136 #define v_SYNC_RI_CHECK(n) (((n)&0x01) << 4)
1137 #define m_AVMUTE (1 << 3)
1138 #define m_RX_DETECT (1 << 2)
1139 #define v_RX_DETECT(n) (((n)&0x01) << 2)
1140 #define m_FEATURE11_EN (1 << 1)
1141 #define v_FEATURE11_EN(n) (((n)&0x01) << 1)
1142 #define m_HDMI_DVI (1 << 0)
1143 #define v_HDMI_DVI(n) (((n)&0x01) << 0)
1145 #define A_HDCPCFG1 0x5001
1146 #define m_HDCP_LOCK (1 << 4)
1147 #define v_HDCP_LOCK(n) (((n)&0x01) << 4)
1148 #define m_SHA1_CHECK_DISABLE (1 << 3)
1149 #define v_SHA1_CHECK_DISBALE(n) (((n)&0x01) << 3)
1150 #define m_PH2UPSHFTENC (1 << 2)
1151 #define v_PH2UPSHFTENC(n) (((n)&0x01) << 2)
1152 #define m_ENCRYPT_DISBALE (1 << 1)
1153 #define v_ENCRYPT_DISBALE(n) (((n)&0x01) << 1)
1154 #define m_HDCP_SW_RST (1 << 0)
1155 #define v_HDCP_SW_RST(n) (((n)&0x01) << 0)
1157 #define A_HDCPOBS0 0x5002
1158 #define m_STATE_AUTH (0x0f << 4)
1159 #define m_SUB_STATE_AUTH (0x07 << 1)
1160 #define m_STATE_HDCP_ENGAGED (1 << 0)
1162 #define A_HDCPOBS1 0x5003
1163 #define m_STATE_OESS (0x07 << 3)
1164 #define m_STATE_REVO (0x07 << 0)
1166 #define A_HDCPOBS2 0x5004
1167 #define m_STATE_CIPHER (0x07 << 3)
1168 #define m_STATE_EESS (0x07 << 0)
1170 #define A_HDCPOBS3 0x5005
1171 #define m_BCAP_REPEATER (1 << 6)
1172 #define m_BCAP_KSVFIFO_READY (1 << 5)
1173 #define m_BCAP_FAST_I2C (1 << 4)
1174 #define m_BCAP_HDMI_MODE (1 << 2)
1175 #define m_BCAP_FEATURES11 (1 << 1)
1176 #define m_BCAP_FAST_REAUTH (1 << 0)
1178 #define A_APIINTCLR 0x5006
1179 #define A_APIINTSTAT 0x5007
1180 #define A_APIINTMSK 0x5008
1181 #define m_HDCP_ENGAGED (1 << 7)
1182 #define m_HDCP_FAILED (1 << 6)
1183 #define m_HDCP_I2C_NOACK (1 << 4)
1184 #define m_HDCP_LOST_ARBI (1 << 3)
1185 #define m_KEEP_ERR_INT (1 << 2)
1186 #define m_KSVSHA1_CALC_INT (1 << 1)
1187 #define m_KSV_ACCESS_INT (1 << 0)
1188 #define v_HDCP_ENGAGED(n) (((n)&0x01) << 7)
1189 #define v_HDCP_FAILED(n) (((n)&0x01) << 6)
1190 #define v_HDCP_I2C_NOACK(n) (((n)&0x01) << 4)
1191 #define v_HDCP_LOST_ARBI(n) (((n)&0x01) << 3)
1192 #define v_KEEP_ERR_INT(n) (((n)&0x01) << 1)
1193 #define v_KSVSHA1_CALC_INT(n) (((n)&0x01) << 1)
1194 #define v_KSV_ACCESS_INT(n) (((n)&0x01) << 0)
1196 #define A_VIDPOLCFG 0x5009
1197 #define m_UNENCRYT_CONF (0x03 << 5)
1198 #define v_UNENCRYT_CONF(n) (((n)&0x03) << 5)
1199 #define m_DATAEN_POL (1 << 4)
1200 #define v_DATAEN_POL(n) (((n)&0x01) << 4)
1201 #define m_VSYNC_POL (1 << 3)
1202 #define v_VSYNC_POL(n) (((n)&0x01) << 3)
1203 #define m_HSYNC_POL (1 << 1)
1204 #define v_HSYNC_POL(n) (((n)&0x01) << 1)
1206 #define A_OESSWCFG 0x500a
1207 #define A_COREVERLSB 0x5014
1208 #define A_COREVERMSB 0x5015
1210 #define A_KSVMEMCTRL 0x5016
1211 #define m_SHA1_FAIL (1 << 3)
1212 #define v_SHA1_FAIL(n) (((n)&0x01) << 3)
1213 #define m_KSV_UPDATE (1 << 2)
1214 #define v_KSV_UPDATE(n) (((n)&0x01) << 2)
1215 #define m_KSV_MEM_ACCESS (1 << 1)
1216 #define m_KSV_MEM_REQ (1 << 0)
1217 #define v_KSV_MEM_REQ(n) (((n)&0x01) << 0)
1219 #define HDCP_BSTATUS_0 0x5020
1220 #define m_MAX_DEVS_EXCEEDED (1 << 7)
1221 #define m_DEVICE_COUNT (0x7f << 0)
1223 #define HDCP_BSTATUS_1 0x5021
1224 #define HDCP_M0_0 0x5022
1225 #define HDCP_M0_1 0x5023
1226 #define HDCP_M0_2 0x5024
1227 #define HDCP_M0_3 0x5025
1228 #define HDCP_M0_4 0x5026
1229 #define HDCP_M0_5 0x5027
1230 #define HDCP_M0_6 0x5028
1231 #define HDCP_M0_7 0x5029
1232 #define HDCP_KSV 0x502a /* 0~634 */
1233 #define HDCP_VH 0x52a5 /* 0~19 */
1234 #define HDCP_REVOC_SIZE_0 0x52b9
1235 #define HDCP_REVOC_SIZE_1 0x52ba
1236 #define HDCP_REVOC_LIST 0x52bb /* 0~5059 */
1238 /* HDCP BKSV Registers */
1239 #define HDCP_BKSV_BASE 0x7800
1241 #define HDCPREG_BKSV0 0x7800
1242 #define HDCPREG_BKSV1 0x7801
1243 #define HDCPREG_BKSV2 0x7802
1244 #define HDCPREG_BKSV3 0x7803
1245 #define HDCPREG_BKSV4 0x7804
1247 /* HDCP AN Registers */
1248 #define HDCP_AN_BASE 0x7805
1250 #define HDCPREG_ANCONF 0x7805
1251 #define m_OAN_BYPASS (1 << 0)
1252 #define v_OAN_BYPASS(n) (((n)&0x01) << 0)
1254 #define HDCPREG_AN0 0x7806
1255 #define HDCPREG_AN1 0x7807
1256 #define HDCPREG_AN2 0x7808
1257 #define HDCPREG_AN3 0x7809
1258 #define HDCPREG_AN4 0x780a
1259 #define HDCPREG_AN5 0x780b
1260 #define HDCPREG_AN6 0x780c
1261 #define HDCPREG_AN7 0x780d
1263 /* Encrypted DPK Embedded Storage Registers */
1264 #define ENCRYPTED_DPK_EMBEDDED_BASE 0x780e
1266 #define HDCPREG_RMCTL 0x780e
1267 #define m_DPK_DECRYPT_EN (1 << 0)
1268 #define v_DPK_DECRYPT_EN(n) (((n)&0x01) << 0)
1270 #define HDCPREG_RMSTS 0x780f
1271 #define m_DPK_WR_OK_STS (1 << 6)
1272 #define m_DPK_DATA_INDEX (0x3f << 6)
1274 #define HDCPREG_SEED0 0x7810
1275 #define HDCPREG_SEED1 0x7811
1276 #define HDCPREG_DPK0 0x7812
1277 #define HDCPREG_DPK1 0x7813
1278 #define HDCPREG_DPK2 0x7814
1279 #define HDCPREG_DPK3 0x7815
1280 #define HDCPREG_DPK4 0x7816
1281 #define HDCPREG_DPK5 0x7817
1282 #define HDCPREG_DPK6 0x7818
1284 #define HDCP2REG_BASE 0x7900
1285 #define HDCP2REG_ID 0x7900
1286 #define HDCP2REG_CTRL 0x7904
1287 #define m_HDCP2_HDP_OVR_VAL (1 << 5)
1288 #define m_HDCP2_HDP_OVR_EN (1 << 4)
1289 #define m_HDCP2_FORCE (1 << 2)
1290 #define m_HDCP2_OVR_EN (1 << 1)
1291 #define m_HDCP2_SWITCH_EN (1 << 0)
1293 #define v_HDCP2_HDP_OVR_VAL(n) (((n)&0x01) << 5)
1294 #define v_HDCP2_HDP_OVR_EN(n) (((n)&0x01) << 4)
1295 #define v_HDCP2_FORCE(n) (((n)&0x01) << 2)
1296 #define v_HDCP2_OVR_EN(n) (((n)&0x01) << 1)
1297 #define v_HDCP2_SWITCH_EN(n) (((n)&0x01) << 0)
1298 #define HDCP2REG_CTRL1 0x7905
1299 #define m_HDCP2_CD_VAL (0xf << 4)
1300 #define m_HDCP2_CD_EN (1 << 3)
1301 #define m_HDCP2_AVMUTE_OVR_VAL (1 << 1)
1302 #define m_HDCP2_AVMUTE_OVR_EN (1 << 0)
1304 #define v_HDCP2_CD_VAL(n) (((n)&0x0f) << 4)
1305 #define v_HDCP2_CD_EN(n) (((n)&0x01) << 3)
1306 #define v_HDCP2_AVMUTE_OVR_VAL(n) (((n)&0x01) << 1)
1307 #define v_HDCP2_AVMUTE_OVR_EN(n) (((n)&0x01) << 0)
1308 #define HDCP2REG_STAS 0x7908
1309 #define HDCP2REG_MASK 0x790c
1310 #define HDCP2REG_STAT 0x790d
1311 #define HDCP2REG_MUTE 0x790e
1312 #define m_HDCP2_CAPABLE (1 << 0)
1313 #define m_HDCP2_NOTCAPABLE (1 << 1)
1314 #define m_HDCP2_AUTH_LOST (1 << 2)
1315 #define m_HDCP2_AUTH_OK (1 << 3)
1316 #define m_HDCP2_AUTH_FAIL (1 << 4)
1317 #define m_HDCP2_DECRYPTED_CHG (1 << 5)
1319 /* CEC Engine Registers */
1320 #define CEC_ENGINE_BASE 0x7d00
1322 #define CEC_CTRL 0x7d00
1323 #define m_CEC_STANBY (1 << 4)
1324 #define m_CEC_BC_NCK (1 << 3)
1325 #define m_CEC_FRAME_TYPE (3 << 1)
1326 #define m_CEC_SEND (1 << 0)
1327 #define v_CEC_STANBY(n) ((n & 0x1) << 4)
1328 #define v_CEC_BC_NCK(n) ((n & 0x1) << 3)
1329 #define v_CEC_FRAME_TYPE(n) ((n & 0x3) << 1)
1330 #define v_CEC_SEND(n) (n & 0x1)
1331 #define CEC_MASK 0x7d02
1332 #define CEC_ADDR_L 0x7d05
1333 #define CEC_ADDR_H 0x7d06
1334 #define CEC_TX_CNT 0x7d07
1335 #define CEC_RX_CNT 0x7d08
1336 #define CEC_TX_DATA0 0x7d10 /* txdata0~txdata15 */
1337 #define CEC_RX_DATA0 0x7d20 /* rxdata0~rxdata15 */
1338 #define CEC_LOCK 0x7d30
1339 #define CEC_WKUPCTRL 0x7d31
1341 /* I2C Master Registers */
1342 #define I2C_MASTER_BASE 0x7e00
1344 #define I2CM_SLAVE 0x7e00
1345 #define I2CM_ADDRESS 0x7e01
1346 #define I2CM_DATAO 0x7e02
1347 #define I2CM_DATAI 0x7e03
1349 #define I2CM_OPERATION 0x7e04
1350 #define m_I2CM_WR (1 << 4)
1351 #define v_I2CM_WR(n) (((n)&0x01) << 4)
1352 #define m_I2CM_RD8_EXT (1 << 3)
1353 #define v_I2CM_RD8_EXT(n) (((n)&0x01) << 3)
1354 #define m_I2CM_RD8 (1 << 2)
1355 #define v_I2CM_RD8(n) (((n)&0x01) << 2)
1356 #define m_I2CM_RD_EXT (1 << 1)
1357 #define v_I2CM_RD_EXT(n) (((n)&0x01) << 1)
1358 #define m_I2CM_RD (1 << 0)
1359 #define v_I2CM_RD(n) (((n)&0x01) << 0)
1361 #define I2CM_INT 0x7e05
1362 #define m_I2CM_RD_REQ_MASK (1 << 6)
1363 #define v_I2CM_RD_REQ_MASK(n) (((n)&0x01) << 6)
1364 #define m_I2CM_DONE_MASK (1 << 2)
1365 #define v_I2CM_DONE_MASK(n) (((n)&0x01) << 2)
1367 #define I2CM_CTLINT 0x7e06
1368 #define m_I2CM_NACK_MASK (1 << 6)
1369 #define v_I2CM_NACK_MASK(n) (((n)&0x01) << 6)
1370 #define m_I2CM_ARB_MASK (1 << 2)
1371 #define v_I2CM_ARB_MASK(n) (((n)&0x01) << 2)
1373 #define I2CM_DIV 0x7e07
1378 #define m_I2CM_FAST_STD_MODE (1 << 3)
1379 #define v_I2CM_FAST_STD_MODE(n) (((n)&0x01) << 3)
1381 #define I2CM_SEGADDR 0x7e08
1382 #define m_I2CM_SEG_ADDR (0x7f << 0)
1383 #define v_I2CM_SEG_ADDR(n) (((n)&0x7f) << 0)
1385 #define I2CM_SOFTRSTZ 0x7e09
1386 #define m_I2CM_SOFTRST (1 << 0)
1387 #define v_I2CM_SOFTRST(n) (((n)&0x01) << 0)
1389 #define I2CM_SEGPTR 0x7e0a
1390 #define I2CM_SS_SCL_HCNT_1_ADDR 0x7e0b
1391 #define I2CM_SS_SCL_HCNT_0_ADDR 0x7e0c
1392 #define I2CM_SS_SCL_LCNT_1_ADDR 0x7e0d
1393 #define I2CM_SS_SCL_LCNT_0_ADDR 0x7e0e
1394 #define I2CM_FS_SCL_HCNT_1_ADDR 0x7e0f
1395 #define I2CM_FS_SCL_HCNT_0_ADDR 0x7e10
1396 #define I2CM_FS_SCL_LCNT_1_ADDR 0x7e11
1397 #define I2CM_FS_SCL_LCNT_0_ADDR 0x7e12
1398 #define I2CM_SDA_HOLD 0x7e13
1400 #define I2CM_SCDC_READ_UPDATE 0x7e14
1401 #define m_I2CM_UPRD_VSYNC_EN (1 << 5)
1402 #define v_I2CM_UPRD_VSYNC_EN(n) (((n)&0x01) << 5)
1403 #define m_I2CM_READ_REQ_EN (1 << 4)
1404 #define v_I2CM_READ_REQ_EN(n) (((n)&0x01) << 4)
1405 #define m_I2CM_READ_UPDATE (1 << 0)
1406 #define v_I2CM_READ_UPDATE(n) (((n)&0x01) << 0)
1408 #define I2CM_READ_BUFF0 0x7e20 /* buff0~buff7 */
1409 #define I2CM_SCDC_UPDATE0 0x7e30
1410 #define I2CM_SCDC_UPDATE1 0x7e31
1413 * HDMI TX PHY Define Start
1415 #define PHYTX_OPMODE_PLLCFG 0x06
1417 PREP_DIV_BY_2 = 0, /* 16 bits */
1418 PREP_DIV_BY_15, /* 12 bits */
1419 PREP_DIV_BY_125, /* 10 bits */
1420 PREP_DIV_BY_1, /* 8 bits */
1422 #define m_PREP_DIV (0x03 << 13)
1423 #define v_PREP_DIV(n) (((n)&0x03) << 13)
1430 #define m_TMDS_CNTRL (0x03 << 11)
1431 #define v_TMDS_CNTRL(n) (((n)&0x03) << 11)
1436 #define m_OPMODE (0x03 << 9)
1437 #define v_OPMODE(n) (((n)&0x03) << 9)
1446 #define m_FBDIV2_CNTRL (0x07 << 6)
1447 #define v_FBDIV2_CNTRL(n) (((n)&0x07) << 6)
1454 #define m_FBDIV1_CNTRL (0x03 << 4)
1455 #define v_FBDIV1_CNTRL(n) (((n)&0x03) << 4)
1462 #define m_REF_CNTRL (0x03 << 2)
1463 #define v_REF_CNTRL(n) (((n)&0x03) << 2)
1464 #define m_MPLL_N_CNTRL (0x03 << 0)
1465 #define v_MPLL_N_CNTRL(n) (((n)&0x03) << 0)
1467 #define PHYTX_CLKSYMCTRL 0x09
1468 #define v_OVERRIDE(n) (0x01 << 15)
1469 #define m_SLOPEBOOST (0x03 << 4)
1470 #define v_SLOPEBOOST(n) (((n)&0x03) << 4)
1471 #define m_TX_SYMON (0x01 << 3)
1472 #define v_TX_SYMON(n) (((n)&0x01) << 3)
1473 #define m_TX_TRAON (0x01 << 2)
1474 #define v_TX_TRAON(n) (((n)&0x01) << 2)
1475 #define m_TX_TRBON (0x01 << 1)
1476 #define v_TX_TRBON(n) (((n)&0x01) << 1)
1477 #define m_CLK_SYMON (0x01 << 0)
1478 #define v_CLK_SYMON(n) (((n)&0x01) << 0)
1480 #define PHYTX_VLEVCTRL 0x0e
1481 #define m_SUP_TXLVL (0x1f << 5)
1482 #define v_SUP_TXLVL(n) (((n)&0x1f) << 5)
1483 #define m_SUP_CLKLVL (0x1f << 0)
1484 #define v_SUP_CLKLVL(n) (((n)&0x1f) << 0)
1486 #define PHYTX_PLLCURRCTRL 0x10
1487 #define m_MPLL_PROP_CNTRL (0x07 << 3)
1488 #define v_MPLL_PROP_CNTRL(n) (((n)&0x07) << 3)
1489 #define m_MPLL_INT_CNTRL (0x07 << 0)
1490 #define v_MPLL_INT_CNTRL(n) (((n)&0x07) << 0)
1492 #define PHYTX_PLLGMPCTRL 0x15
1493 #define m_MPLL_GMP_CNTRL (0x03 << 0)
1494 #define v_MPLL_GMP_CNTRL(n) (((n)&0x03) << 0)
1506 #define PHYTX_TERM_RESIS 0x19
1507 #define m_TX_TERM (0x07 << 0)
1508 #define v_TX_TERM(n) (((n)&0x07) << 0)
1511 struct phy_mpll_config_tab {
1529 * HDMI TX PHY Define End
1532 struct rockchip_hdmiv2_reg_table {
1537 static inline u32 hdmi_readl(struct hdmi_dev *hdmi_dev, u16 offset)
1539 return readl_relaxed(hdmi_dev->regbase + (offset) * 0x04);
1542 static inline int hdmi_writel(struct hdmi_dev *hdmi_dev, u16 offset, u32 val)
1546 writel_relaxed(val, hdmi_dev->regbase + (offset) * 0x04);
1550 static inline int hdmi_msk_reg(struct hdmi_dev *hdmi_dev,
1551 u16 offset, u32 msk, u32 val)
1556 temp = readl_relaxed(hdmi_dev->regbase +
1557 (offset) * 0x04) & (0xFF - (msk));
1558 writel_relaxed(temp | ((val) & (msk)),
1559 hdmi_dev->regbase + (offset) * 0x04);
1562 irqreturn_t rockchip_hdmiv2_dev_irq(int irq, void *priv);
1563 void rockchip_hdmiv2_dev_init_ops(struct hdmi_ops *ops);
1564 void rockchip_hdmiv2_dev_initial(struct hdmi_dev *hdmi_dev);
1565 void rockchip_hdmiv2_cec_init(struct hdmi *hdmi);
1566 void rockchip_hdmiv2_cec_isr(struct hdmi_dev *hdmi_dev, char cec_int);
1567 void rockchip_hdmiv2_dump_phy_regs(struct hdmi_dev *hdmi_dev);
1568 void rockchip_hdmiv2_hdcp_init(struct hdmi *hdmi);
1569 void rockchip_hdmiv2_hdcp2_enable(int enable);
1570 void rockchip_hdmiv2_hdcp_isr(struct hdmi_dev *hdmi_dev, int hdcp_int);
1571 int rockchip_hdmiv2_write_phy(struct hdmi_dev *hdmi_dev,
1572 int reg_addr, int val);
1573 int rockchip_hdmiv2_read_phy(struct hdmi_dev *hdmi_dev,