drivers/video/rockchip/hdmi/rockchip-hdmiv2/rockchip_hdmiv2_hw.c

   1 #include <linux/delay.h>
   2 #include <linux/interrupt.h>
   3 #include <linux/rockchip/grf.h>
   4 #include <linux/rockchip/iomap.h>
   5 #include "rockchip_hdmiv2.h"
   6 #include "rockchip_hdmiv2_hw.h"
   7
   8 static const struct phy_mpll_config_tab PHY_MPLL_TABLE[] = {
   9         /*tmdsclk = (pixclk / ref_cntrl ) * (fbdiv2 * fbdiv1) / nctrl / tmdsmhl
  10           opmode: 0:HDMI1.4     1:HDMI2.0
  11         */
  12 /*      |pixclock|      tmdsclock|pixrepet|colordepth|prepdiv|tmdsmhl|opmode|
  13                 fbdiv2|fbdiv1|ref_cntrl|nctrl|propctrl|intctrl|gmpctrl| */
  14         {27000000,      27000000,       0,      8,      0,      0,      0,
  15                 2,      3,      0,      3,      3,      0,      0},
  16         {27000000,      33750000,       0,      10,     1,      0,      0,
  17                 5,      1,      0,      3,      3,      0,      0},
  18         {27000000,      40500000,       0,      12,     2,      0,      0,
  19                 3,      3,      0,      3,      3,      0,      0},
  20         {27000000,      54000000,       0,      16,     3,      0,      0,
  21                 2,      3,      0,      2,      5,      0,      1},
  22 /*      {74250000,      74250000,       0,      8,      0,      0,      0,
  23         1,      3,      0,      2,      5,      0,      1}, */
  24         {74250000,      74250000,       0,      8,      0,      0,      0,
  25                 4,      3,      3,      2,      7,      0,      3},
  26         {74250000,      92812500,       0,      10,     1,      0,      0,
  27                 5,      0,      1,      1,      7,      0,      2},
  28         {74250000,      111375000,      0,      12,     2,      0,      0,
  29                 1,      2,      0,      1,      7,      0,      2},
  30         {74250000,      148500000,      0,      16,     3,      0,      0,
  31                 1,      3,      0,      1,      7,      0,      2},
  32         {148500000,     74250000,       0,      8,      0,      0,      0,
  33                 1,      1,      1,      1,      0,      0,      3},
  34         {148500000,     148500000,      0,      8,      0,      0,      0,
  35                 1,      1,      0,      1,      0,      0,      3},
  36         {148500000,     185625000,      0,      10,     1,      0,      0,
  37                 5,      0,      3,      0,      7,      0,      3},
  38         {148500000,     222750000,      0,      12,     2,      0,      0,
  39                 1,      2,      1,      0,      7,      0,      3},
  40         {148500000,     297000000,      0,      16,     3,      0,      0,
  41                 1,      1,      0,      0,      7,      0,      3},
  42         {297000000,     148500000,      0,      8,      0,      0,      0,
  43                 1,      0,      1,      0,      0,      0,      3},
  44         {297000000,     297000000,      0,      8,      0,      0,      0,
  45                 1,      0,      0,      0,      0,      0,      3},
  46         {297000000,     371250000,      0,      10,     1,      3,      1,
  47                 5,      1,      3,      1,      7,      0,      3},
  48         {297000000,     445500000,      0,      12,     2,      3,      1,
  49                 1,      2,      0,      1,      7,      0,      3},
  50         {297000000,     594000000,      0,      16,     3,      3,      1,
  51                 1,      3,      1,      0,      0,      0,      3},
  52 /*      {594000000,     297000000,      0,      8,      0,      0,      0,
  53                 1,      3,      3,      1,      0,      0,      3},*/
  54         {594000000,     297000000,      0,      8,      0,      0,      0,
  55                 1,      0,      1,      0,      0,      0,      3},
  56         {594000000,     371250000,      0,      10,     1,      3,      1,
  57                 5,      0,      3,      0,      7,      0,      3},
  58         {594000000,     445500000,      0,      12,     2,      3,      1,
  59                 1,      2,      1,      1,      7,      0,      3},
  60         {594000000,     594000000,      0,      16,     3,      3,      1,
  61                 1,      3,      3,      0,      0,      0,      3},
  62         {594000000,     594000000,      0,      8,      0,      3,      1,
  63                 1,      3,      3,      0,      0,      0,      3},
  64 };
  65 /* ddc i2c master reset */
  66 static void rockchip_hdmiv2_i2cm_reset(struct hdmi_dev *hdmi_dev)
  67 {
  68         hdmi_msk_reg(hdmi_dev, I2CM_SOFTRSTZ,
  69                      m_I2CM_SOFTRST, v_I2CM_SOFTRST(0));
  70         usleep_range(90, 100);
  71 }
  72
  73 /*set read/write offset,set read/write mode*/
  74 static void rockchip_hdmiv2_i2cm_write_request(struct hdmi_dev *hdmi_dev,
  75                                                u8 offset, u8 data)
  76 {
  77         hdmi_writel(hdmi_dev, I2CM_ADDRESS, offset);
  78         hdmi_writel(hdmi_dev, I2CM_DATAO, data);
  79         hdmi_msk_reg(hdmi_dev, I2CM_OPERATION, m_I2CM_WR, v_I2CM_WR(1));
  80 }
  81
  82 static void rockchip_hdmiv2_i2cm_read_request(struct hdmi_dev *hdmi_dev,
  83                                               u8 offset)
  84 {
  85         hdmi_writel(hdmi_dev, I2CM_ADDRESS, offset);
  86         hdmi_msk_reg(hdmi_dev, I2CM_OPERATION, m_I2CM_RD, v_I2CM_RD(1));
  87 }
  88
  89 static void rockchip_hdmiv2_i2cm_write_data(struct hdmi_dev *hdmi_dev,
  90                                             u8 data, u8 offset)
  91 {
  92         u8 interrupt;
  93         int trytime = 2;
  94         int i = 20;
  95
  96         while (trytime-- > 0) {
  97                 rockchip_hdmiv2_i2cm_write_request(hdmi_dev, offset, data);
  98                 while (i--) {
  99                         usleep_range(900, 1000);
 100                         interrupt = hdmi_readl(hdmi_dev, IH_I2CM_STAT0);
 101                         if (interrupt)
 102                                 hdmi_writel(hdmi_dev,
 103                                             IH_I2CM_STAT0, interrupt);
 104
 105                         if (interrupt & (m_SCDC_READREQ |
 106                                          m_I2CM_DONE | m_I2CM_ERROR))
 107                                 break;
 108                 }
 109
 110                 if (interrupt & m_I2CM_DONE) {
 111                         dev_dbg(hdmi_dev->hdmi->dev,
 112                                 "[%s] write offset %02x data %02x success\n",
 113                                 __func__, offset, data);
 114                         trytime = 0;
 115                 } else if ((interrupt & m_I2CM_ERROR) || (i == -1)) {
 116                         dev_err(hdmi_dev->hdmi->dev,
 117                                 "[%s] write data error\n", __func__);
 118                         rockchip_hdmiv2_i2cm_reset(hdmi_dev);
 119                 }
 120         }
 121 }
 122
 123 static int rockchip_hdmiv2_i2cm_read_data(struct hdmi_dev *hdmi_dev, u8 offset)
 124 {
 125         u8 interrupt, val;
 126         int trytime = 2;
 127         int i = 20;
 128
 129         while (trytime-- > 0) {
 130                 rockchip_hdmiv2_i2cm_read_request(hdmi_dev, offset);
 131                 while (i--) {
 132                         usleep_range(900, 1000);
 133                         interrupt = hdmi_readl(hdmi_dev, IH_I2CM_STAT0);
 134                         if (interrupt)
 135                                 hdmi_writel(hdmi_dev, IH_I2CM_STAT0, interrupt);
 136
 137                         if (interrupt & (m_SCDC_READREQ |
 138                                 m_I2CM_DONE | m_I2CM_ERROR))
 139                                 break;
 140                 }
 141
 142                 if (interrupt & m_I2CM_DONE) {
 143                         val = hdmi_readl(hdmi_dev, I2CM_DATAI);
 144                         trytime = 0;
 145                 } else if ((interrupt & m_I2CM_ERROR) || (i == -1)) {
 146                         pr_err("[%s] read data error\n", __func__);
 147                         rockchip_hdmiv2_i2cm_reset(hdmi_dev);
 148                 }
 149         }
 150         return val;
 151 }
 152
 153 static void rockchip_hdmiv2_i2cm_mask_int(struct hdmi_dev *hdmi_dev, int mask)
 154 {
 155         if (0 == mask) {
 156                 hdmi_msk_reg(hdmi_dev, I2CM_INT,
 157                              m_I2CM_DONE_MASK, v_I2CM_DONE_MASK(0));
 158                 hdmi_msk_reg(hdmi_dev, I2CM_CTLINT,
 159                              m_I2CM_NACK_MASK | m_I2CM_ARB_MASK,
 160                              v_I2CM_NACK_MASK(0) | v_I2CM_ARB_MASK(0));
 161         } else {
 162                 hdmi_msk_reg(hdmi_dev, I2CM_INT,
 163                              m_I2CM_DONE_MASK, v_I2CM_DONE_MASK(1));
 164                 hdmi_msk_reg(hdmi_dev, I2CM_CTLINT,
 165                              m_I2CM_NACK_MASK | m_I2CM_ARB_MASK,
 166                              v_I2CM_NACK_MASK(1) | v_I2CM_ARB_MASK(1));
 167         }
 168 }
 169
 170 #define I2C_DIV_FACTOR 100000
 171 static u16 i2c_count(u16 sfrclock, u16 sclmintime)
 172 {
 173         unsigned long tmp_scl_period = 0;
 174
 175         if (((sfrclock * sclmintime) % I2C_DIV_FACTOR) != 0)
 176                 tmp_scl_period = (unsigned long)((sfrclock * sclmintime) +
 177                                 (I2C_DIV_FACTOR - ((sfrclock * sclmintime) %
 178                                 I2C_DIV_FACTOR))) / I2C_DIV_FACTOR;
 179         else
 180                 tmp_scl_period = (unsigned long)(sfrclock * sclmintime) /
 181                                 I2C_DIV_FACTOR;
 182
 183         return (u16)(tmp_scl_period);
 184 }
 185
 186 #define EDID_I2C_MIN_SS_SCL_HIGH_TIME   50000
 187 #define EDID_I2C_MIN_SS_SCL_LOW_TIME    50000
 188
 189 static void rockchip_hdmiv2_i2cm_clk_init(struct hdmi_dev *hdmi_dev)
 190 {
 191         /* Set DDC I2C CLK which devided from DDC_CLK. */
 192         hdmi_writel(hdmi_dev, I2CM_SS_SCL_HCNT_0_ADDR,
 193                     i2c_count(24000, EDID_I2C_MIN_SS_SCL_HIGH_TIME));
 194         hdmi_writel(hdmi_dev, I2CM_SS_SCL_LCNT_0_ADDR,
 195                     i2c_count(24000, EDID_I2C_MIN_SS_SCL_LOW_TIME));
 196         hdmi_msk_reg(hdmi_dev, I2CM_DIV, m_I2CM_FAST_STD_MODE,
 197                      v_I2CM_FAST_STD_MODE(STANDARD_MODE));
 198 }
 199
 200 static int rockchip_hdmiv2_scdc_get_sink_version(struct hdmi_dev *hdmi_dev)
 201 {
 202         return rockchip_hdmiv2_i2cm_read_data(hdmi_dev, SCDC_SINK_VER);
 203 }
 204
 205 static void rockchip_hdmiv2_scdc_set_source_version(struct hdmi_dev *hdmi_dev,
 206                                                     u8 version)
 207 {
 208         rockchip_hdmiv2_i2cm_write_data(hdmi_dev, version, SCDC_SOURCE_VER);
 209 }
 210
 211
 212 static void rockchip_hdmiv2_scdc_read_request(struct hdmi_dev *hdmi_dev,
 213                                               int enable)
 214 {
 215         hdmi_msk_reg(hdmi_dev, I2CM_SCDC_READ_UPDATE,
 216                      m_I2CM_READ_REQ_EN, v_I2CM_READ_REQ_EN(enable));
 217         rockchip_hdmiv2_i2cm_write_data(hdmi_dev, enable, SCDC_CONFIG_0);
 218 }
 219
 220 #ifdef HDMI_20_SCDC
 221 static void rockchip_hdmiv2_scdc_update_read(struct hdmi_dev *hdmi_dev)
 222 {
 223         hdmi_msk_reg(hdmi_dev, I2CM_SCDC_READ_UPDATE,
 224                      m_I2CM_READ_UPDATE, v_I2CM_READ_UPDATE(1));
 225 }
 226
 227
 228 static int rockchip_hdmiv2_scdc_get_scambling_status(struct hdmi_dev *hdmi_dev)
 229 {
 230         int val;
 231
 232         val = rockchip_hdmiv2_i2cm_read_data(hdmi_dev, SCDC_SCRAMBLER_STAT);
 233         return val;
 234 }
 235
 236 static void rockchip_hdmiv2_scdc_enable_polling(struct hdmi_dev *hdmi_dev,
 237                                                 int enable)
 238 {
 239         rockchip_hdmiv2_scdc_read_request(hdmi_dev, enable);
 240         hdmi_msk_reg(hdmi_dev, I2CM_SCDC_READ_UPDATE,
 241                      m_I2CM_UPRD_VSYNC_EN, v_I2CM_UPRD_VSYNC_EN(enable));
 242 }
 243
 244 static int rockchip_hdmiv2_scdc_get_status_reg0(struct hdmi_dev *hdmi_dev)
 245 {
 246         rockchip_hdmiv2_scdc_read_request(hdmi_dev, 1);
 247         rockchip_hdmiv2_scdc_update_read(hdmi_dev);
 248         return hdmi_readl(hdmi_dev, I2CM_SCDC_UPDATE0);
 249 }
 250
 251 static int rockchip_hdmiv2_scdc_get_status_reg1(struct hdmi_dev *hdmi_dev)
 252 {
 253         rockchip_hdmiv2_scdc_read_request(hdmi_dev, 1);
 254         rockchip_hdmiv2_scdc_update_read(hdmi_dev);
 255         return hdmi_readl(hdmi_dev, I2CM_SCDC_UPDATE1);
 256 }
 257 #endif
 258
 259 static void rockchip_hdmiv2_scdc_init(struct hdmi_dev *hdmi_dev)
 260 {
 261         rockchip_hdmiv2_i2cm_reset(hdmi_dev);
 262         rockchip_hdmiv2_i2cm_mask_int(hdmi_dev, 1);
 263         rockchip_hdmiv2_i2cm_clk_init(hdmi_dev);
 264         /* set scdc i2c addr */
 265         hdmi_writel(hdmi_dev, I2CM_SLAVE, DDC_I2C_SCDC_ADDR);
 266         rockchip_hdmiv2_i2cm_mask_int(hdmi_dev, 0);/*enable interrupt*/
 267 }
 268
 269
 270 static int rockchip_hdmiv2_scrambling_enable(struct hdmi_dev *hdmi_dev,
 271                                              int enable)
 272 {
 273         HDMIDBG("%s enable %d\n", __func__, enable);
 274         if (1 == enable) {
 275                 /* Write on Rx the bit Scrambling_Enable, register 0x20 */
 276                 rockchip_hdmiv2_i2cm_write_data(hdmi_dev, 1, SCDC_TMDS_CONFIG);
 277                 /* TMDS software reset request */
 278                 hdmi_msk_reg(hdmi_dev, MC_SWRSTZREQ,
 279                              m_TMDS_SWRST, v_TMDS_SWRST(0));
 280                 /* Enable/Disable Scrambling */
 281                 hdmi_msk_reg(hdmi_dev, FC_SCRAMBLER_CTRL,
 282                              m_FC_SCRAMBLE_EN, v_FC_SCRAMBLE_EN(1));
 283         } else {
 284                 /* Enable/Disable Scrambling */
 285                 hdmi_msk_reg(hdmi_dev, FC_SCRAMBLER_CTRL,
 286                              m_FC_SCRAMBLE_EN, v_FC_SCRAMBLE_EN(0));
 287                 /* TMDS software reset request */
 288                 hdmi_msk_reg(hdmi_dev, MC_SWRSTZREQ,
 289                              m_TMDS_SWRST, v_TMDS_SWRST(0));
 290                 /* Write on Rx the bit Scrambling_Enable, register 0x20 */
 291                 rockchip_hdmiv2_i2cm_write_data(hdmi_dev, 0, SCDC_TMDS_CONFIG);
 292         }
 293         return 0;
 294 }
 295
 296
 297
 298 static const struct phy_mpll_config_tab *get_phy_mpll_tab(
 299                 unsigned int pixclock, unsigned int tmdsclk,
 300                 char pixrepet, char colordepth)
 301 {
 302         int i;
 303
 304         if (pixclock == 0)
 305                 return NULL;
 306         HDMIDBG("%s pixClock %u tmdsclk %u pixRepet %d colorDepth %d\n",
 307                 __func__, pixclock, tmdsclk, pixrepet, colordepth);
 308         for (i = 0; i < ARRAY_SIZE(PHY_MPLL_TABLE); i++) {
 309                 if ((PHY_MPLL_TABLE[i].pix_clock == pixclock) &&
 310                     (PHY_MPLL_TABLE[i].tmdsclock == tmdsclk) &&
 311                     (PHY_MPLL_TABLE[i].pix_repet == pixrepet) &&
 312                     (PHY_MPLL_TABLE[i].color_depth == colordepth))
 313                         return &PHY_MPLL_TABLE[i];
 314         }
 315         return NULL;
 316 }
 317
 318 static void rockchip_hdmiv2_powerdown(struct hdmi_dev *hdmi_dev)
 319 {
 320         hdmi_msk_reg(hdmi_dev, PHY_CONF0,
 321                      m_PDDQ_SIG | m_TXPWRON_SIG |
 322                      m_ENHPD_RXSENSE_SIG | m_SVSRET_SIG,
 323                      v_PDDQ_SIG(1) | v_TXPWRON_SIG(0) |
 324                      v_ENHPD_RXSENSE_SIG(1)) | v_SVSRET_SIG(0);
 325         hdmi_writel(hdmi_dev, MC_CLKDIS, 0x7f);
 326 }
 327
 328 int rockchip_hdmiv2_write_phy(struct hdmi_dev *hdmi_dev,
 329                               int reg_addr, int val)
 330 {
 331         int trytime = 2, i = 0, op_status = 0;
 332
 333         while (trytime--) {
 334                 hdmi_writel(hdmi_dev, PHY_I2CM_ADDRESS, reg_addr);
 335                 hdmi_writel(hdmi_dev, PHY_I2CM_DATAO_1, (val >> 8) & 0xff);
 336                 hdmi_writel(hdmi_dev, PHY_I2CM_DATAO_0, val & 0xff);
 337                 hdmi_writel(hdmi_dev, PHY_I2CM_OPERATION, m_PHY_I2CM_WRITE);
 338
 339                 i = 20;
 340                 while (i--) {
 341                         usleep_range(900, 1000);
 342                         op_status = hdmi_readl(hdmi_dev, IH_I2CMPHY_STAT0);
 343                         if (op_status)
 344                                 hdmi_writel(hdmi_dev,
 345                                             IH_I2CMPHY_STAT0,
 346                                             op_status);
 347
 348                         if (op_status & (m_I2CMPHY_DONE | m_I2CMPHY_ERR))
 349                                 break;
 350                 }
 351
 352                 if (op_status & m_I2CMPHY_DONE)
 353                         return 0;
 354                 else
 355                         dev_err(hdmi_dev->hdmi->dev,
 356                                 "[%s] operation error,trytime=%d\n",
 357                                 __func__, trytime);
 358                 msleep(100);
 359         }
 360
 361         return -1;
 362 }
 363
 364 int rockchip_hdmiv2_read_phy(struct hdmi_dev *hdmi_dev,
 365                              int reg_addr)
 366 {
 367         int trytime = 2, i = 0, op_status = 0;
 368         int val = 0;
 369
 370         while (trytime--) {
 371                 hdmi_writel(hdmi_dev, PHY_I2CM_ADDRESS, reg_addr);
 372                 hdmi_writel(hdmi_dev, PHY_I2CM_DATAI_1, 0x00);
 373                 hdmi_writel(hdmi_dev, PHY_I2CM_DATAI_0, 0x00);
 374                 hdmi_writel(hdmi_dev, PHY_I2CM_OPERATION, m_PHY_I2CM_READ);
 375
 376                 i = 20;
 377                 while (i--) {
 378                         usleep_range(900, 1000);
 379                         op_status = hdmi_readl(hdmi_dev, IH_I2CMPHY_STAT0);
 380                         if (op_status)
 381                                 hdmi_writel(hdmi_dev, IH_I2CMPHY_STAT0,
 382                                             op_status);
 383
 384                         if (op_status & (m_I2CMPHY_DONE | m_I2CMPHY_ERR))
 385                                 break;
 386                 }
 387
 388                 if (op_status & m_I2CMPHY_DONE) {
 389                         val = hdmi_readl(hdmi_dev, PHY_I2CM_DATAI_1);
 390                         val = (val & 0xff) << 8;
 391                         val += (hdmi_readl(hdmi_dev, PHY_I2CM_DATAI_0) & 0xff);
 392                         pr_debug("phy_reg0x%02x: 0x%04x",
 393                                  reg_addr, val);
 394                         return val;
 395                 } else {
 396                         pr_err("[%s] operation error,trytime=%d\n",
 397                                __func__, trytime);
 398                 }
 399                 msleep(100);
 400         }
 401
 402         return -1;
 403 }
 404
 405 static int rockchip_hdmiv2_config_phy(struct hdmi_dev *hdmi_dev)
 406 {
 407         int stat = 0, i = 0;
 408         const struct phy_mpll_config_tab *phy_mpll = NULL;
 409
 410         hdmi_msk_reg(hdmi_dev, PHY_I2CM_DIV,
 411                      m_PHY_I2CM_FAST_STD, v_PHY_I2CM_FAST_STD(0));
 412         /* power off PHY */
 413         /* hdmi_writel(hdmi_dev, PHY_CONF0, 0x1e); */
 414         hdmi_msk_reg(hdmi_dev, PHY_CONF0,
 415                      m_PDDQ_SIG | m_TXPWRON_SIG | m_SVSRET_SIG,
 416                      v_PDDQ_SIG(1) | v_TXPWRON_SIG(0) | v_SVSRET_SIG(1));
 417
 418         if (hdmi_dev->tmdsclk_ratio_change &&
 419             hdmi_dev->hdmi->edid.scdc_present == 1) {
 420                 mutex_lock(&hdmi_dev->ddc_lock);
 421                 rockchip_hdmiv2_scdc_init(hdmi_dev);
 422                 stat = rockchip_hdmiv2_i2cm_read_data(hdmi_dev,
 423                                                       SCDC_TMDS_CONFIG);
 424                 if (hdmi_dev->tmdsclk > 340000000)
 425                         stat |= 2;
 426                 else
 427                         stat &= 0x1;
 428                 rockchip_hdmiv2_i2cm_write_data(hdmi_dev,
 429                                                 stat, SCDC_TMDS_CONFIG);
 430                 mutex_unlock(&hdmi_dev->ddc_lock);
 431         }
 432         /* reset PHY */
 433         hdmi_writel(hdmi_dev, MC_PHYRSTZ, v_PHY_RSTZ(1));
 434         usleep_range(1000, 2000);
 435         hdmi_writel(hdmi_dev, MC_PHYRSTZ, v_PHY_RSTZ(0));
 436
 437         /* Set slave address as PHY GEN2 address */
 438         hdmi_writel(hdmi_dev, PHY_I2CM_SLAVE, PHY_GEN2_ADDR);
 439
 440         /* config the required PHY I2C register */
 441         phy_mpll = get_phy_mpll_tab(hdmi_dev->pixelclk,
 442                                     hdmi_dev->tmdsclk,
 443                                     hdmi_dev->pixelrepeat - 1,
 444                                     hdmi_dev->colordepth);
 445         if (phy_mpll) {
 446                 rockchip_hdmiv2_write_phy(hdmi_dev, PHYTX_OPMODE_PLLCFG,
 447                                           v_PREP_DIV(phy_mpll->prep_div) |
 448                                           v_TMDS_CNTRL(
 449                                           phy_mpll->tmdsmhl_cntrl) |
 450                                           v_OPMODE(phy_mpll->opmode) |
 451                                           v_FBDIV2_CNTRL(
 452                                           phy_mpll->fbdiv2_cntrl) |
 453                                           v_FBDIV1_CNTRL(
 454                                           phy_mpll->fbdiv1_cntrl) |
 455                                           v_REF_CNTRL(phy_mpll->ref_cntrl) |
 456                                           v_MPLL_N_CNTRL(phy_mpll->n_cntrl));
 457                 rockchip_hdmiv2_write_phy(hdmi_dev, PHYTX_PLLCURRCTRL,
 458                                           v_MPLL_PROP_CNTRL(
 459                                           phy_mpll->prop_cntrl) |
 460                                           v_MPLL_INT_CNTRL(
 461                                           phy_mpll->int_cntrl));
 462                 rockchip_hdmiv2_write_phy(hdmi_dev, PHYTX_PLLGMPCTRL,
 463                                           v_MPLL_GMP_CNTRL(
 464                                           phy_mpll->gmp_cntrl));
 465         }
 466
 467         rockchip_hdmiv2_write_phy(hdmi_dev, PHYTX_CLKSYMCTRL,
 468                                   v_OVERRIDE(1) | v_SLOPEBOOST(0) |
 469                                   v_TX_SYMON(1) | v_TX_TRAON(0) |
 470                                   v_TX_TRBON(0) | v_CLK_SYMON(1));
 471         if (hdmi_dev->tmdsclk > 340000000) {
 472                 rockchip_hdmiv2_write_phy(hdmi_dev, PHYTX_TERM_RESIS,
 473                                           v_TX_TERM(R50_OHMS));
 474                 rockchip_hdmiv2_write_phy(hdmi_dev, PHYTX_VLEVCTRL,
 475                                           v_SUP_TXLVL(9) |
 476                                           v_SUP_CLKLVL(17));
 477         } else {
 478                 rockchip_hdmiv2_write_phy(hdmi_dev, PHYTX_TERM_RESIS,
 479                                           v_TX_TERM(R100_OHMS));
 480                 if (hdmi_dev->tmdsclk > 165000000)
 481                         rockchip_hdmiv2_write_phy(hdmi_dev, PHYTX_VLEVCTRL,
 482                                                   v_SUP_TXLVL(14) |
 483                                                   v_SUP_CLKLVL(17));
 484                 else
 485                         rockchip_hdmiv2_write_phy(hdmi_dev, PHYTX_VLEVCTRL,
 486                                                   v_SUP_TXLVL(18) |
 487                                                   v_SUP_CLKLVL(17));
 488         }
 489         /* rockchip_hdmiv2_write_phy(hdmi_dev, 0x05, 0x8000); */
 490         if (hdmi_dev->tmdsclk_ratio_change)
 491                 msleep(100);
 492         /* power on PHY */
 493         hdmi_writel(hdmi_dev, PHY_CONF0, 0x2e);
 494         /*
 495         hdmi_msk_reg(hdmi_dev, PHY_CONF0,
 496                      m_PDDQ_SIG | m_TXPWRON_SIG | m_ENHPD_RXSENSE_SIG,
 497                      v_PDDQ_SIG(0) | v_TXPWRON_SIG(1) |
 498                      v_ENHPD_RXSENSE_SIG(1));
 499         */
 500         /* check if the PHY PLL is locked */
 501         #define PHY_TIMEOUT     10000
 502         while (i++ < PHY_TIMEOUT) {
 503                 if ((i % 10) == 0) {
 504                         stat = hdmi_readl(hdmi_dev, PHY_STAT0);
 505                         if (stat & m_PHY_LOCK)
 506                                 break;
 507                         usleep_range(1000, 2000);
 508                 }
 509         }
 510         if ((stat & m_PHY_LOCK) == 0) {
 511                 stat = hdmi_readl(hdmi_dev, MC_LOCKONCLOCK);
 512                 dev_err(hdmi_dev->hdmi->dev,
 513                         "PHY PLL not locked: PCLK_ON=%d,TMDSCLK_ON=%d\n",
 514                         (stat & m_PCLK_ON) >> 6, (stat & m_TMDSCLK_ON) >> 5);
 515                 return -1;
 516         }
 517
 518         return 0;
 519 }
 520
 521 static int rockchip_hdmiv2_video_framecomposer(struct hdmi *hdmi_drv,
 522                                                struct hdmi_video *vpara)
 523 {
 524         struct hdmi_dev *hdmi_dev = hdmi_drv->property->priv;
 525         int value, vsync_pol, hsync_pol, de_pol;
 526         struct hdmi_video_timing *timing = NULL;
 527         struct fb_videomode *mode = NULL;
 528         u32 sink_version, tmdsclk;
 529
 530         vsync_pol = hdmi_drv->lcdc->cur_screen->pin_vsync;
 531         hsync_pol = hdmi_drv->lcdc->cur_screen->pin_hsync;
 532         de_pol = (hdmi_drv->lcdc->cur_screen->pin_den == 0) ? 1 : 0;
 533
 534         hdmi_msk_reg(hdmi_dev, A_VIDPOLCFG,
 535                      m_DATAEN_POL | m_VSYNC_POL | m_HSYNC_POL,
 536                      v_DATAEN_POL(de_pol) |
 537                      v_VSYNC_POL(vsync_pol) |
 538                      v_HSYNC_POL(hsync_pol));
 539
 540         timing = (struct hdmi_video_timing *)hdmi_vic2timing(vpara->vic);
 541         if (timing == NULL) {
 542                 dev_err(hdmi_drv->dev,
 543                         "[%s] not found vic %d\n", __func__, vpara->vic);
 544                 return -ENOENT;
 545         }
 546         mode = &(timing->mode);
 547         if (vpara->color_input == HDMI_COLOR_YCBCR420)
 548                 tmdsclk = mode->pixclock / 2;
 549         else if (vpara->format_3d == HDMI_3D_FRAME_PACKING)
 550                 tmdsclk = 2 * mode->pixclock;
 551         else
 552                 tmdsclk = mode->pixclock;
 553         switch (vpara->color_output_depth) {
 554         case 10:
 555                 tmdsclk += tmdsclk / 4;
 556                 break;
 557         case 12:
 558                 tmdsclk += tmdsclk / 2;
 559                 break;
 560         case 16:
 561                 tmdsclk += tmdsclk;
 562                 break;
 563         case 8:
 564         default:
 565                 break;
 566         }
 567
 568         if (tmdsclk > 594000000) {
 569                 vpara->color_output_depth = 8;
 570                 tmdsclk = mode->pixclock;
 571         }
 572
 573         if ((tmdsclk > 340000000 && hdmi_dev->tmdsclk < 340000000) ||
 574             (tmdsclk < 340000000 && hdmi_dev->tmdsclk > 340000000))
 575                 hdmi_dev->tmdsclk_ratio_change = true;
 576         else
 577                 hdmi_dev->tmdsclk_ratio_change = false;
 578
 579         hdmi_dev->tmdsclk = tmdsclk;
 580         if (vpara->format_3d == HDMI_3D_FRAME_PACKING)
 581                 hdmi_dev->pixelclk = 2 * mode->pixclock;
 582         else
 583                 hdmi_dev->pixelclk = mode->pixclock;
 584         hdmi_dev->pixelrepeat = timing->pixelrepeat;
 585         hdmi_dev->colordepth = vpara->color_output_depth;
 586
 587         pr_info("pixel clk is %lu tmds clk is %u\n",
 588                 hdmi_dev->pixelclk, hdmi_dev->tmdsclk);
 589         /* Start/stop HDCP keepout window generation */
 590         hdmi_msk_reg(hdmi_dev, FC_INVIDCONF,
 591                      m_FC_HDCP_KEEPOUT, v_FC_HDCP_KEEPOUT(1));
 592         if (hdmi_drv->edid.scdc_present == 1) {
 593                 if (tmdsclk > 340000000) {/* used for HDMI 2.0 TX */
 594                         mutex_lock(&hdmi_dev->ddc_lock);
 595                         rockchip_hdmiv2_scdc_init(hdmi_dev);
 596                         sink_version =
 597                         rockchip_hdmiv2_scdc_get_sink_version(hdmi_dev);
 598                         pr_info("sink scdc version is %d\n", sink_version);
 599                         sink_version = hdmi_drv->edid.hf_vsdb_version;
 600                         rockchip_hdmiv2_scdc_set_source_version(hdmi_dev,
 601                                                                 sink_version);
 602                         if (hdmi_drv->edid.rr_capable == 1)
 603                                 rockchip_hdmiv2_scdc_read_request(hdmi_dev, 1);
 604                         rockchip_hdmiv2_scrambling_enable(hdmi_dev, 1);
 605                         mutex_unlock(&hdmi_dev->ddc_lock);
 606                 } else {
 607                         mutex_lock(&hdmi_dev->ddc_lock);
 608                         rockchip_hdmiv2_scdc_init(hdmi_dev);
 609                         rockchip_hdmiv2_scrambling_enable(hdmi_dev, 0);
 610                         mutex_unlock(&hdmi_dev->ddc_lock);
 611                 }
 612         }
 613
 614         hdmi_msk_reg(hdmi_dev, FC_INVIDCONF,
 615                      m_FC_VSYNC_POL | m_FC_HSYNC_POL | m_FC_DE_POL |
 616                      m_FC_HDMI_DVI | m_FC_INTERLACE_MODE,
 617                      v_FC_VSYNC_POL(vsync_pol) | v_FC_HSYNC_POL(hsync_pol) |
 618                      v_FC_DE_POL(de_pol) | v_FC_HDMI_DVI(vpara->sink_hdmi) |
 619                      v_FC_INTERLACE_MODE(mode->vmode));
 620         if (mode->vmode == FB_VMODE_INTERLACED &&
 621             vpara->format_3d != HDMI_3D_FRAME_PACKING)
 622                 hdmi_msk_reg(hdmi_dev, FC_INVIDCONF,
 623                              m_FC_VBLANK, v_FC_VBLANK(1));
 624         else
 625                 hdmi_msk_reg(hdmi_dev, FC_INVIDCONF,
 626                              m_FC_VBLANK, v_FC_VBLANK(0));
 627
 628         value = mode->xres;
 629         if (vpara->color_input == HDMI_COLOR_YCBCR420)
 630                 value = value / 2;
 631         hdmi_writel(hdmi_dev, FC_INHACTIV1, v_FC_HACTIVE1(value >> 8));
 632         hdmi_writel(hdmi_dev, FC_INHACTIV0, (value & 0xff));
 633
 634         if (vpara->format_3d == HDMI_3D_FRAME_PACKING) {
 635                 if (mode->vmode == 0)
 636                         value = 2 * mode->yres +
 637                                 mode->upper_margin +
 638                                 mode->lower_margin +
 639                                 mode->vsync_len;
 640                 else
 641                         value = 2 * mode->yres +
 642                                 3 * (mode->upper_margin +
 643                                      mode->lower_margin +
 644                                      mode->vsync_len) + 2;
 645         } else {
 646                 value = mode->yres;
 647         }
 648         hdmi_writel(hdmi_dev, FC_INVACTIV1, v_FC_VACTIVE1(value >> 8));
 649         hdmi_writel(hdmi_dev, FC_INVACTIV0, (value & 0xff));
 650
 651         value = mode->hsync_len + mode->left_margin + mode->right_margin;
 652         if (vpara->color_input == HDMI_COLOR_YCBCR420)
 653                 value = value / 2;
 654         hdmi_writel(hdmi_dev, FC_INHBLANK1, v_FC_HBLANK1(value >> 8));
 655         hdmi_writel(hdmi_dev, FC_INHBLANK0, (value & 0xff));
 656
 657         value = mode->vsync_len + mode->upper_margin + mode->lower_margin;
 658         hdmi_writel(hdmi_dev, FC_INVBLANK, (value & 0xff));
 659
 660         value = mode->right_margin;
 661         if (vpara->color_input == HDMI_COLOR_YCBCR420)
 662                 value = value / 2;
 663         hdmi_writel(hdmi_dev, FC_HSYNCINDELAY1, v_FC_HSYNCINDEAY1(value >> 8));
 664         hdmi_writel(hdmi_dev, FC_HSYNCINDELAY0, (value & 0xff));
 665
 666         value = mode->lower_margin;
 667         hdmi_writel(hdmi_dev, FC_VSYNCINDELAY, (value & 0xff));
 668
 669         value = mode->hsync_len;
 670         if (vpara->color_input == HDMI_COLOR_YCBCR420)
 671                 value = value / 2;
 672         hdmi_writel(hdmi_dev, FC_HSYNCINWIDTH1, v_FC_HSYNCWIDTH1(value >> 8));
 673         hdmi_writel(hdmi_dev, FC_HSYNCINWIDTH0, (value & 0xff));
 674
 675         value = mode->vsync_len;
 676         hdmi_writel(hdmi_dev, FC_VSYNCINWIDTH, (value & 0xff));
 677
 678         /*Set the control period minimum duration
 679          (min. of 12 pixel clock cycles, refer to HDMI 1.4b specification)*/
 680         hdmi_writel(hdmi_dev, FC_CTRLDUR, 12);
 681         hdmi_writel(hdmi_dev, FC_EXCTRLDUR, 32);
 682
 683         /* spacing < 256^2 * config / tmdsClock, spacing <= 50ms
 684          * worst case: tmdsClock == 25MHz => config <= 19
 685          */
 686         hdmi_writel(hdmi_dev, FC_EXCTRLSPAC,
 687                     (hdmi_dev->tmdsclk/1000) * 50 / (256 * 512));
 688         hdmi_msk_reg(hdmi_dev, MC_SWRSTZREQ,
 689                      m_TMDS_SWRST, v_TMDS_SWRST(0));
 690 #if 0
 691         /*Set PreambleFilter*/
 692         for (i = 0; i < 3; i++) {
 693                 value = (i + 1) * 11;
 694                 if (i == 0)             /*channel 0*/
 695                         hdmi_writel(hdmi_dev, FC_CH0PREAM, value);
 696                 else if (i == 1)        /*channel 1*/
 697                         hdmi_writel(hdmi_dev, FC_CH1PREAM, value & 0x3f);
 698                 else if (i == 2)        /*channel 2*/
 699                         hdmi_writel(hdmi_dev, FC_CH2PREAM, value & 0x3f);
 700         }
 701 #endif
 702
 703         hdmi_writel(hdmi_dev, FC_PRCONF, v_FC_PR_FACTOR(timing->pixelrepeat));
 704
 705         return 0;
 706 }
 707
 708 static int rockchip_hdmiv2_video_packetizer(struct hdmi_dev *hdmi_dev,
 709                                             struct hdmi_video *vpara)
 710 {
 711         unsigned char color_depth = 0;
 712         unsigned char output_select = 0;
 713         unsigned char remap_size = 0;
 714
 715         if (vpara->color_output == HDMI_COLOR_YCBCR422) {
 716                 switch (vpara->color_output_depth) {
 717                 case 8:
 718                         remap_size = YCC422_16BIT;
 719                         break;
 720                 case 10:
 721                         remap_size = YCC422_20BIT;
 722                         break;
 723                 case 12:
 724                         remap_size = YCC422_24BIT;
 725                         break;
 726                 default:
 727                         remap_size = YCC422_16BIT;
 728                         break;
 729                 }
 730
 731                 output_select = OUT_FROM_YCC422_REMAP;
 732                 /*Config remap size for the different color Depth*/
 733                 hdmi_msk_reg(hdmi_dev, VP_REMAP,
 734                              m_YCC422_SIZE, v_YCC422_SIZE(remap_size));
 735         } else {
 736                 switch (vpara->color_output_depth) {
 737                 case 10:
 738                         color_depth = COLOR_DEPTH_30BIT;
 739                         output_select = OUT_FROM_PIXEL_PACKING;
 740                         break;
 741                 case 12:
 742                         color_depth = COLOR_DEPTH_36BIT;
 743                         output_select = OUT_FROM_PIXEL_PACKING;
 744                         break;
 745                 case 16:
 746                         color_depth = COLOR_DEPTH_48BIT;
 747                         output_select = OUT_FROM_PIXEL_PACKING;
 748                         break;
 749                 case 8:
 750                 default:
 751                         color_depth = COLOR_DEPTH_24BIT_DEFAULT;
 752                         output_select = OUT_FROM_8BIT_BYPASS;
 753                         break;
 754                 }
 755
 756                 /*Config Color Depth*/
 757                 hdmi_msk_reg(hdmi_dev, VP_PR_CD,
 758                              m_COLOR_DEPTH, v_COLOR_DEPTH(color_depth));
 759         }
 760
 761         /*Config pixel repettion*/
 762         hdmi_msk_reg(hdmi_dev, VP_PR_CD, m_DESIRED_PR_FACTOR,
 763                      v_DESIRED_PR_FACTOR(hdmi_dev->pixelrepeat - 1));
 764         if (hdmi_dev->pixelrepeat > 1)
 765                 hdmi_msk_reg(hdmi_dev, VP_CONF,
 766                              m_PIXEL_REPET_EN | m_BYPASS_SEL,
 767                              v_PIXEL_REPET_EN(1) | v_BYPASS_SEL(0));
 768         else
 769                 hdmi_msk_reg(hdmi_dev, VP_CONF,
 770                              m_PIXEL_REPET_EN | m_BYPASS_SEL,
 771                              v_PIXEL_REPET_EN(0) | v_BYPASS_SEL(1));
 772
 773         /*config output select*/
 774         if (output_select == OUT_FROM_PIXEL_PACKING) { /* pixel packing */
 775                 hdmi_msk_reg(hdmi_dev, VP_CONF,
 776                              m_BYPASS_EN | m_PIXEL_PACK_EN |
 777                              m_YCC422_EN | m_OUTPUT_SEL,
 778                              v_BYPASS_EN(0) | v_PIXEL_PACK_EN(1) |
 779                              v_YCC422_EN(0) | v_OUTPUT_SEL(output_select));
 780         } else if (output_select == OUT_FROM_YCC422_REMAP) { /* YCC422 */
 781                 hdmi_msk_reg(hdmi_dev, VP_CONF,
 782                              m_BYPASS_EN | m_PIXEL_PACK_EN |
 783                              m_YCC422_EN | m_OUTPUT_SEL,
 784                              v_BYPASS_EN(0) | v_PIXEL_PACK_EN(0) |
 785                              v_YCC422_EN(1) | v_OUTPUT_SEL(output_select));
 786         } else if (output_select == OUT_FROM_8BIT_BYPASS ||
 787                    output_select == 3) { /* bypass */
 788                 hdmi_msk_reg(hdmi_dev, VP_CONF,
 789                              m_BYPASS_EN | m_PIXEL_PACK_EN |
 790                              m_YCC422_EN | m_OUTPUT_SEL,
 791                              v_BYPASS_EN(1) | v_PIXEL_PACK_EN(0) |
 792                              v_YCC422_EN(0) | v_OUTPUT_SEL(output_select));
 793         }
 794
 795 #if defined(HDMI_VIDEO_STUFFING)
 796         /* YCC422 and pixel packing stuffing*/
 797         hdmi_msk_reg(hdmi_dev, VP_STUFF, m_PR_STUFFING, v_PR_STUFFING(1));
 798         hdmi_msk_reg(hdmi_dev, VP_STUFF,
 799                      m_YCC422_STUFFING | m_PP_STUFFING,
 800                      v_YCC422_STUFFING(1) | v_PP_STUFFING(1));
 801 #endif
 802         return 0;
 803 }
 804
 805 static int rockchip_hdmiv2_video_sampler(struct hdmi_dev *hdmi_dev,
 806                                          struct hdmi_video *vpara)
 807 {
 808         int map_code = 0;
 809
 810         if (vpara->color_input == HDMI_COLOR_YCBCR422) {
 811                 /* YCC422 mapping is discontinued - only map 1 is supported */
 812                 switch (vpara->color_output_depth) {
 813                 case 8:
 814                         map_code = VIDEO_YCBCR422_8BIT;
 815                         break;
 816                 case 10:
 817                         map_code = VIDEO_YCBCR422_10BIT;
 818                         break;
 819                 case 12:
 820                         map_code = VIDEO_YCBCR422_12BIT;
 821                         break;
 822                 default:
 823                         map_code = VIDEO_YCBCR422_8BIT;
 824                         break;
 825                 }
 826         } else if (vpara->color_input == HDMI_COLOR_YCBCR420 ||
 827                    vpara->color_input == HDMI_COLOR_YCBCR444) {
 828                 switch (vpara->color_output_depth) {
 829                 case 10:
 830                         map_code = VIDEO_YCBCR444_10BIT;
 831                         break;
 832                 case 12:
 833                         map_code = VIDEO_YCBCR444_12BIT;
 834                         break;
 835                 case 16:
 836                         map_code = VIDEO_YCBCR444_16BIT;
 837                         break;
 838                 case 8:
 839                 default:
 840                         map_code = VIDEO_YCBCR444_8BIT;
 841                         break;
 842                 }
 843         } else {
 844                 switch (vpara->color_output_depth) {
 845                 case 10:
 846                         map_code = VIDEO_RGB444_10BIT;
 847                         break;
 848                 case 12:
 849                         map_code = VIDEO_RGB444_12BIT;
 850                         break;
 851                 case 16:
 852                         map_code = VIDEO_RGB444_16BIT;
 853                         break;
 854                 case 8:
 855                 default:
 856                         map_code = VIDEO_RGB444_8BIT;
 857                         break;
 858                 }
 859                 map_code += (vpara->color_input == HDMI_COLOR_YCBCR444) ?
 860                             8 : 0;
 861         }
 862
 863         /* Set Data enable signal from external
 864            and set video sample input mapping */
 865         hdmi_msk_reg(hdmi_dev, TX_INVID0,
 866                      m_INTERNAL_DE_GEN | m_VIDEO_MAPPING,
 867                      v_INTERNAL_DE_GEN(0) | v_VIDEO_MAPPING(map_code));
 868
 869 #if defined(HDMI_VIDEO_STUFFING)
 870         hdmi_writel(hdmi_dev, TX_GYDATA0, 0x00);
 871         hdmi_writel(hdmi_dev, TX_GYDATA1, 0x00);
 872         hdmi_msk_reg(hdmi_dev, TX_INSTUFFING,
 873                      m_GYDATA_STUFF, v_GYDATA_STUFF(1));
 874         hdmi_writel(hdmi_dev, TX_RCRDATA0, 0x00);
 875         hdmi_writel(hdmi_dev, TX_RCRDATA1, 0x00);
 876         hdmi_msk_reg(hdmi_dev, TX_INSTUFFING,
 877                      m_RCRDATA_STUFF, v_RCRDATA_STUFF(1));
 878         hdmi_writel(hdmi_dev, TX_BCBDATA0, 0x00);
 879         hdmi_writel(hdmi_dev, TX_BCBDATA1, 0x00);
 880         hdmi_msk_reg(hdmi_dev, TX_INSTUFFING,
 881                      m_BCBDATA_STUFF, v_BCBDATA_STUFF(1));
 882 #endif
 883         return 0;
 884 }
 885
 886 static const char coeff_csc[][24] = {
 887                 /*   G          R           B           Bias
 888                      A1    |    A2     |    A3     |    A4    |
 889                      B1    |    B2     |    B3     |    B4    |
 890                      C1    |    C2     |    C3     |    C4    | */
 891         {       /* CSC_RGB_0_255_TO_RGB_16_235_8BIT */
 892                 0x36, 0xf7, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40,         /*G*/
 893                 0x00, 0x00, 0x36, 0xf7, 0x00, 0x00, 0x00, 0x40,         /*R*/
 894                 0x00, 0x00, 0x00, 0x00, 0x36, 0xf7, 0x00, 0x40,         /*B*/
 895         },
 896         {       /* CSC_RGB_0_255_TO_RGB_16_235_10BIT */
 897                 0x36, 0xf7, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00,         /*G*/
 898                 0x00, 0x00, 0x36, 0xf7, 0x00, 0x00, 0x01, 0x00,         /*R*/
 899                 0x00, 0x00, 0x00, 0x00, 0x36, 0xf7, 0x01, 0x00,         /*B*/
 900         },
 901         {       /* CSC_RGB_0_255_TO_ITU601_16_235_8BIT */
 902                 0x20, 0x40, 0x10, 0x80, 0x06, 0x40, 0x00, 0x40,         /*Y*/
 903                 0xe8, 0x80, 0x1c, 0x00, 0xfb, 0x80, 0x02, 0x00,         /*Cr*/
 904                 0xed, 0x80, 0xf6, 0x80, 0x1c, 0x00, 0x02, 0x00,         /*Cb*/
 905         },
 906         {       /* CSC_RGB_0_255_TO_ITU601_16_235_10BIT */
 907                 0x20, 0x40, 0x10, 0x80, 0x06, 0x40, 0x01, 0x00,         /*Y*/
 908                 0xe8, 0x80, 0x1c, 0x00, 0xfb, 0x80, 0x08, 0x00,         /*Cr*/
 909                 0xed, 0x80, 0xf6, 0x80, 0x1c, 0x00, 0x08, 0x00,         /*Cb*/
 910         },
 911         {       /* CSC_RGB_0_255_TO_ITU709_16_235_8BIT */
 912                 0x27, 0x40, 0x0b, 0xc0, 0x04, 0x00, 0x00, 0x40,         /*Y*/
 913                 0xe6, 0x80, 0x1c, 0x00, 0xfd, 0x80, 0x02, 0x00,         /*Cr*/
 914                 0xea, 0x40, 0xf9, 0x80, 0x1c, 0x00, 0x02, 0x00,         /*Cb*/
 915         },
 916         {       /* CSC_RGB_0_255_TO_ITU709_16_235_10BIT */
 917                 0x27, 0x40, 0x0b, 0xc0, 0x04, 0x00, 0x01, 0x00,         /*Y*/
 918                 0xe6, 0x80, 0x1c, 0x00, 0xfd, 0x80, 0x08, 0x00,         /*Cr*/
 919                 0xea, 0x40, 0xf9, 0x80, 0x1c, 0x00, 0x08, 0x00,         /*Cb*/
 920         },
 921                 /* Y            Cr          Cb          Bias */
 922         {       /* CSC_ITU601_16_235_TO_RGB_0_255_8BIT */
 923                 0x20, 0x00, 0x69, 0x26, 0x74, 0xfd, 0x01, 0x0e,         /*G*/
 924                 0x20, 0x00, 0x2c, 0xdd, 0x00, 0x00, 0x7e, 0x9a,         /*R*/
 925                 0x20, 0x00, 0x00, 0x00, 0x38, 0xb4, 0x7e, 0x3b,         /*B*/
 926         },
 927         {       /* CSC_ITU709_16_235_TO_RGB_0_255_8BIT */
 928                 0x20, 0x00, 0x71, 0x06, 0x7a, 0x02, 0x00, 0xa7,         /*G*/
 929                 0x20, 0x00, 0x32, 0x64, 0x00, 0x00, 0x7e, 0x6d,         /*R*/
 930                 0x20, 0x00, 0x00, 0x00, 0x3b, 0x61, 0x7e, 0x25,         /*B*/
 931         },
 932 };
 933
 934 static int rockchip_hdmiv2_video_csc(struct hdmi_dev *hdmi_dev,
 935                                      struct hdmi_video *vpara)
 936 {
 937         int i, mode, interpolation, decimation, csc_scale;
 938         const char *coeff = NULL;
 939         unsigned char color_depth = 0;
 940
 941         if (vpara->color_input == vpara->color_output) {
 942                 hdmi_msk_reg(hdmi_dev, MC_FLOWCTRL,
 943                              m_FEED_THROUGH_OFF, v_FEED_THROUGH_OFF(0));
 944                 return 0;
 945         }
 946
 947         if (vpara->color_input == HDMI_COLOR_YCBCR422 &&
 948             vpara->color_output != HDMI_COLOR_YCBCR422 &&
 949             vpara->color_output != HDMI_COLOR_YCBCR420) {
 950                 interpolation = 1;
 951                 hdmi_msk_reg(hdmi_dev, CSC_CFG,
 952                              m_CSC_INTPMODE, v_CSC_INTPMODE(interpolation));
 953         }
 954
 955         if ((vpara->color_input == HDMI_COLOR_RGB_0_255 ||
 956              vpara->color_input == HDMI_COLOR_YCBCR444) &&
 957              vpara->color_output == HDMI_COLOR_YCBCR422) {
 958                 decimation = 1;
 959                 hdmi_msk_reg(hdmi_dev, CSC_CFG,
 960                              m_CSC_DECIMODE, v_CSC_DECIMODE(decimation));
 961         }
 962
 963         switch (vpara->vic) {
 964         case HDMI_720X480I_60HZ_4_3:
 965         case HDMI_720X576I_50HZ_4_3:
 966         case HDMI_720X480P_60HZ_4_3:
 967         case HDMI_720X576P_50HZ_4_3:
 968         case HDMI_720X480I_60HZ_16_9:
 969         case HDMI_720X576I_50HZ_16_9:
 970         case HDMI_720X480P_60HZ_16_9:
 971         case HDMI_720X576P_50HZ_16_9:
 972                 if (vpara->color_input == HDMI_COLOR_RGB_0_255 &&
 973                     vpara->color_output >= HDMI_COLOR_YCBCR444) {
 974                         mode = CSC_RGB_0_255_TO_ITU601_16_235_8BIT;
 975                         csc_scale = 0;
 976                 } else if (vpara->color_input >= HDMI_COLOR_YCBCR444 &&
 977                            vpara->color_output == HDMI_COLOR_RGB_0_255) {
 978                         mode = CSC_ITU601_16_235_TO_RGB_0_255_8BIT;
 979                         csc_scale = 1;
 980                 }
 981                 break;
 982         default:
 983                 if (vpara->color_input == HDMI_COLOR_RGB_0_255 &&
 984                     vpara->color_output >= HDMI_COLOR_YCBCR444) {
 985                         mode = CSC_RGB_0_255_TO_ITU709_16_235_8BIT;
 986                         csc_scale = 0;
 987                 } else if (vpara->color_input >= HDMI_COLOR_YCBCR444 &&
 988                            vpara->color_output == HDMI_COLOR_RGB_0_255) {
 989                         mode = CSC_ITU709_16_235_TO_RGB_0_255_8BIT;
 990                         csc_scale = 1;
 991                 }
 992                 break;
 993         }
 994
 995         if ((vpara->color_input == HDMI_COLOR_RGB_0_255) &&
 996             (vpara->color_output == HDMI_COLOR_RGB_16_235)) {
 997                 mode = CSC_RGB_0_255_TO_RGB_16_235_8BIT;
 998                 csc_scale = 0;
 999         }
1000
1001         switch (vpara->color_output_depth) {
1002         case 10:
1003                 color_depth = COLOR_DEPTH_30BIT;
1004                 mode += 1;
1005                 break;
1006         case 12:
1007                 color_depth = COLOR_DEPTH_36BIT;
1008                 mode += 2;
1009                 break;
1010         case 16:
1011                 color_depth = COLOR_DEPTH_48BIT;
1012                 mode += 3;
1013                 break;
1014         case 8:
1015         default:
1016                 color_depth = COLOR_DEPTH_24BIT;
1017                 break;
1018         }
1019
1020         coeff = coeff_csc[mode];
1021         for (i = 0; i < 24; i++)
1022                 hdmi_writel(hdmi_dev, CSC_COEF_A1_MSB + i, coeff[i]);
1023
1024         hdmi_msk_reg(hdmi_dev, CSC_SCALE,
1025                      m_CSC_SCALE, v_CSC_SCALE(csc_scale));
1026         /*config CSC_COLOR_DEPTH*/
1027         hdmi_msk_reg(hdmi_dev, CSC_SCALE,
1028                      m_CSC_COLOR_DEPTH, v_CSC_COLOR_DEPTH(color_depth));
1029
1030         /* enable CSC */
1031         hdmi_msk_reg(hdmi_dev, MC_FLOWCTRL,
1032                      m_FEED_THROUGH_OFF, v_FEED_THROUGH_OFF(1));
1033
1034         return 0;
1035 }
1036
1037
1038 static int hdmi_dev_detect_hotplug(struct hdmi *hdmi)
1039 {
1040         struct hdmi_dev *hdmi_dev = hdmi->property->priv;
1041         u32 value = hdmi_readl(hdmi_dev, PHY_STAT0);
1042
1043         HDMIDBG("[%s] reg%x value %02x\n", __func__, PHY_STAT0, value);
1044
1045         if (value & m_PHY_HPD)
1046                 return HDMI_HPD_ACTIVED;
1047         else
1048                 return HDMI_HPD_REMOVED;
1049 }
1050
1051 static int hdmi_dev_read_edid(struct hdmi *hdmi, int block, unsigned char *buff)
1052 {
1053         struct hdmi_dev *hdmi_dev = hdmi->property->priv;
1054         int i = 0, n = 0, index = 0, ret = -1, trytime = 5;
1055         int offset = (block % 2) * 0x80;
1056         int interrupt = 0;
1057
1058         HDMIDBG("[%s] block %d\n", __func__, block);
1059
1060         rockchip_hdmiv2_i2cm_reset(hdmi_dev);
1061
1062         /* Set DDC I2C CLK which devided from DDC_CLK to 100KHz. */
1063         rockchip_hdmiv2_i2cm_clk_init(hdmi_dev);
1064
1065         /* Enable I2C interrupt for reading edid */
1066         rockchip_hdmiv2_i2cm_mask_int(hdmi_dev, 0);
1067
1068         hdmi_writel(hdmi_dev, I2CM_SLAVE, DDC_I2C_EDID_ADDR);
1069         hdmi_writel(hdmi_dev, I2CM_SEGADDR, DDC_I2C_SEG_ADDR);
1070         hdmi_writel(hdmi_dev, I2CM_SEGPTR, block / 2);
1071         for (n = 0; n < HDMI_EDID_BLOCK_SIZE / 8; n++) {
1072                 for (trytime = 0; trytime < 5; trytime++) {
1073                         hdmi_writel(hdmi_dev, I2CM_ADDRESS, offset + 8 * n);
1074                         /* enable extend sequential read operation */
1075                         if (block == 0)
1076                                 hdmi_msk_reg(hdmi_dev, I2CM_OPERATION,
1077                                              m_I2CM_RD8, v_I2CM_RD8(1));
1078                         else
1079                                 hdmi_msk_reg(hdmi_dev, I2CM_OPERATION,
1080                                              m_I2CM_RD8_EXT,
1081                                              v_I2CM_RD8_EXT(1));
1082
1083                         i = 20;
1084                         while (i--) {
1085                                 usleep_range(900, 1000);
1086                                 interrupt = hdmi_readl(hdmi_dev,
1087                                                        IH_I2CM_STAT0);
1088                                 if (interrupt)
1089                                         hdmi_writel(hdmi_dev,
1090                                                     IH_I2CM_STAT0, interrupt);
1091
1092                                 if (interrupt &
1093                                     (m_SCDC_READREQ | m_I2CM_DONE |
1094                                      m_I2CM_ERROR))
1095                                         break;
1096                         }
1097
1098                         if (interrupt & m_I2CM_DONE) {
1099                                 for (index = 0; index < 8; index++)
1100                                         buff[8 * n + index] =
1101                                                 hdmi_readl(hdmi_dev,
1102                                                            I2CM_READ_BUFF0 +
1103                                                            index);
1104
1105                                 if (n == HDMI_EDID_BLOCK_SIZE / 8 - 1) {
1106                                         ret = 0;
1107                                         goto exit;
1108                                 }
1109                                 break;
1110                         } else if ((interrupt & m_I2CM_ERROR) || (i == -1)) {
1111                                 dev_err(hdmi->dev,
1112                                         "[%s] edid read %d error\n",
1113                                         __func__, offset + 8 * n);
1114                         }
1115                 }
1116                 if (trytime == 5) {
1117                         dev_err(hdmi->dev,
1118                                 "[%s] edid read error\n", __func__);
1119                         break;
1120                 }
1121         }
1122
1123 exit:
1124         /* Disable I2C interrupt */
1125         rockchip_hdmiv2_i2cm_mask_int(hdmi_dev, 1);
1126         return ret;
1127 }
1128
1129 static void hdmi_dev_config_avi(struct hdmi_dev *hdmi_dev,
1130                                 struct hdmi_video *vpara)
1131 {
1132         unsigned char colorimetry, ext_colorimetry, aspect_ratio, y1y0;
1133         unsigned char rgb_quan_range = AVI_QUANTIZATION_RANGE_DEFAULT;
1134
1135         hdmi_msk_reg(hdmi_dev, FC_DATAUTO3, m_AVI_AUTO, v_AVI_AUTO(0));
1136         hdmi_msk_reg(hdmi_dev, IH_FC_STAT1,
1137                      m_AVI_INFOFRAME, v_AVI_INFOFRAME(1));
1138         /* Set AVI infoFrame Data byte1 */
1139         if (vpara->color_output == HDMI_COLOR_YCBCR444)
1140                 y1y0 = AVI_COLOR_MODE_YCBCR444;
1141         else if (vpara->color_output == HDMI_COLOR_YCBCR422)
1142                 y1y0 = AVI_COLOR_MODE_YCBCR422;
1143         else if (vpara->color_output == HDMI_COLOR_YCBCR420)
1144                 y1y0 = AVI_COLOR_MODE_YCBCR420;
1145         else
1146                 y1y0 = AVI_COLOR_MODE_RGB;
1147
1148         hdmi_msk_reg(hdmi_dev, FC_AVICONF0,
1149                      m_FC_ACTIV_FORMAT | m_FC_RGC_YCC,
1150                      v_FC_RGC_YCC(y1y0) | v_FC_ACTIV_FORMAT(1));
1151
1152         /* Set AVI infoFrame Data byte2 */
1153         switch (vpara->vic) {
1154         case HDMI_720X480I_60HZ_4_3:
1155         case HDMI_720X576I_50HZ_4_3:
1156         case HDMI_720X480P_60HZ_4_3:
1157         case HDMI_720X576P_50HZ_4_3:
1158                 aspect_ratio = AVI_CODED_FRAME_ASPECT_4_3;
1159                 if (vpara->colorimetry == HDMI_COLORIMETRY_NO_DATA)
1160                         colorimetry = AVI_COLORIMETRY_SMPTE_170M;
1161                 break;
1162         case HDMI_720X480I_60HZ_16_9:
1163         case HDMI_720X576I_50HZ_16_9:
1164         case HDMI_720X480P_60HZ_16_9:
1165         case HDMI_720X576P_50HZ_16_9:
1166                 aspect_ratio = AVI_CODED_FRAME_ASPECT_16_9;
1167                 if (vpara->colorimetry == HDMI_COLORIMETRY_NO_DATA)
1168                         colorimetry = AVI_COLORIMETRY_SMPTE_170M;
1169                 break;
1170         default:
1171                 aspect_ratio = AVI_CODED_FRAME_ASPECT_16_9;
1172                 if (vpara->colorimetry == HDMI_COLORIMETRY_NO_DATA)
1173                         colorimetry = AVI_COLORIMETRY_ITU709;
1174         }
1175
1176         if (vpara->colorimetry > HDMI_COLORIMETRY_ITU709) {
1177                 colorimetry = AVI_COLORIMETRY_EXTENDED;
1178                 ext_colorimetry = vpara->colorimetry;
1179         } else if (vpara->color_output == HDMI_COLOR_RGB_16_235 ||
1180                  vpara->color_output == HDMI_COLOR_RGB_0_255) {
1181                 colorimetry = AVI_COLORIMETRY_NO_DATA;
1182                 ext_colorimetry = 0;
1183         } else if (vpara->colorimetry != HDMI_COLORIMETRY_NO_DATA) {
1184                 colorimetry = vpara->colorimetry;
1185         }
1186
1187         hdmi_writel(hdmi_dev, FC_AVICONF1,
1188                     v_FC_COLORIMETRY(colorimetry) |
1189                     v_FC_PIC_ASPEC_RATIO(aspect_ratio) |
1190                     v_FC_ACT_ASPEC_RATIO(ACTIVE_ASPECT_RATE_DEFAULT));
1191
1192         /* Set AVI infoFrame Data byte3 */
1193         hdmi_msk_reg(hdmi_dev, FC_AVICONF2,
1194                      m_FC_EXT_COLORIMETRY | m_FC_QUAN_RANGE,
1195                      v_FC_EXT_COLORIMETRY(ext_colorimetry) |
1196                      v_FC_QUAN_RANGE(rgb_quan_range));
1197
1198         /* Set AVI infoFrame Data byte4 */
1199         if ((vpara->vic > 92 && vpara->vic < 96) || (vpara->vic == 98))
1200                 hdmi_writel(hdmi_dev, FC_AVIVID, 0);
1201         else
1202                 hdmi_writel(hdmi_dev, FC_AVIVID, vpara->vic & 0xff);
1203         /* Set AVI infoFrame Data byte5 */
1204         hdmi_msk_reg(hdmi_dev, FC_AVICONF3, m_FC_YQ | m_FC_CN,
1205                      v_FC_YQ(YQ_LIMITED_RANGE) | v_FC_CN(CN_GRAPHICS));
1206         hdmi_msk_reg(hdmi_dev, FC_DATAUTO3, m_AVI_AUTO, v_AVI_AUTO(1));
1207 }
1208
1209 static int hdmi_dev_config_vsi(struct hdmi *hdmi,
1210                                unsigned char vic_3d, unsigned char format)
1211 {
1212         int i = 0, id = 0x000c03;
1213         unsigned char data[3] = {0};
1214
1215         struct hdmi_dev *hdmi_dev = hdmi->property->priv;
1216
1217         HDMIDBG("[%s] vic %d format %d.\n", __func__, vic_3d, format);
1218
1219         hdmi_msk_reg(hdmi_dev, FC_DATAUTO0, m_VSD_AUTO, v_VSD_AUTO(0));
1220         hdmi_writel(hdmi_dev, FC_VSDIEEEID2, id & 0xff);
1221         hdmi_writel(hdmi_dev, FC_VSDIEEEID1, (id >> 8) & 0xff);
1222         hdmi_writel(hdmi_dev, FC_VSDIEEEID0, (id >> 16) & 0xff);
1223
1224         data[0] = format << 5;  /* PB4 --HDMI_Video_Format */
1225         switch (format) {
1226         case HDMI_VIDEO_FORMAT_4KX2K:
1227                 data[1] = vic_3d;       /* PB5--HDMI_VIC */
1228                 data[2] = 0;
1229                 break;
1230         case HDMI_VIDEO_FORMAT_3D:
1231                 data[1] = vic_3d << 4;  /* PB5--3D_Structure field */
1232                 data[2] = 0;            /* PB6--3D_Ext_Data field */
1233                 break;
1234         default:
1235                 data[1] = 0;
1236                 data[2] = 0;
1237                 break;
1238         }
1239
1240         for (i = 0; i < 3; i++)
1241                 hdmi_writel(hdmi_dev, FC_VSDPAYLOAD0 + i, data[i]);
1242         hdmi_writel(hdmi_dev, FC_VSDSIZE, 0x6);
1243 /*      if (auto_send) { */
1244         hdmi_writel(hdmi_dev, FC_DATAUTO1, 0);
1245         hdmi_writel(hdmi_dev, FC_DATAUTO2, 0x11);
1246         hdmi_msk_reg(hdmi_dev, FC_DATAUTO0, m_VSD_AUTO, v_VSD_AUTO(1));
1247 /*      }
1248         else {
1249                 hdmi_msk_reg(hdmi_dev, FC_DATMAN, m_VSD_MAN, v_VSD_MAN(1));
1250         }
1251 */
1252         return 0;
1253 }
1254
1255 static int hdmi_dev_config_video(struct hdmi *hdmi, struct hdmi_video *vpara)
1256 {
1257         struct hdmi_dev *hdmi_dev = hdmi->property->priv;
1258
1259         HDMIDBG("%s vic %d 3dformat %d color mode %d color depth %d\n",
1260                 __func__, vpara->vic, vpara->format_3d,
1261                 vpara->color_output, vpara->color_output_depth);
1262
1263         if (hdmi_dev->soctype == HDMI_SOC_RK3288)
1264                 vpara->color_input = HDMI_COLOR_RGB_0_255;
1265
1266         if (!hdmi->uboot) {
1267                 /* befor configure video, we power off phy */
1268                 hdmi_msk_reg(hdmi_dev, PHY_CONF0,
1269                              m_PDDQ_SIG | m_TXPWRON_SIG,
1270                              v_PDDQ_SIG(1) | v_TXPWRON_SIG(0));
1271
1272                 /* force output blue */
1273                 if (vpara->color_output == HDMI_COLOR_RGB_0_255) {
1274                         hdmi_writel(hdmi_dev, FC_DBGTMDS2, 0x00);       /*R*/
1275                         hdmi_writel(hdmi_dev, FC_DBGTMDS1, 0x00);       /*G*/
1276                         hdmi_writel(hdmi_dev, FC_DBGTMDS0, 0x00);       /*B*/
1277                 } else if (vpara->color_output == HDMI_COLOR_RGB_16_235) {
1278                         hdmi_writel(hdmi_dev, FC_DBGTMDS2, 0x10);       /*R*/
1279                         hdmi_writel(hdmi_dev, FC_DBGTMDS1, 0x10);       /*G*/
1280                         hdmi_writel(hdmi_dev, FC_DBGTMDS0, 0x10);       /*B*/
1281                 } else {
1282                         hdmi_writel(hdmi_dev, FC_DBGTMDS2, 0x80);       /*R*/
1283                         hdmi_writel(hdmi_dev, FC_DBGTMDS1, 0x10);       /*G*/
1284                         hdmi_writel(hdmi_dev, FC_DBGTMDS0, 0x80);       /*B*/
1285                 }
1286                 hdmi_msk_reg(hdmi_dev, FC_DBGFORCE,
1287                              m_FC_FORCEVIDEO, v_FC_FORCEVIDEO(1));
1288                 hdmi_writel(hdmi_dev, MC_CLKDIS, m_HDCPCLK_DISABLE);
1289         }
1290
1291         if (rockchip_hdmiv2_video_framecomposer(hdmi, vpara) < 0)
1292                 return -1;
1293
1294         if (rockchip_hdmiv2_video_packetizer(hdmi_dev, vpara) < 0)
1295                 return -1;
1296         /* Color space convert */
1297         if (rockchip_hdmiv2_video_csc(hdmi_dev, vpara) < 0)
1298                 return -1;
1299         if (rockchip_hdmiv2_video_sampler(hdmi_dev, vpara) < 0)
1300                 return -1;
1301
1302         if (vpara->sink_hdmi == OUTPUT_HDMI) {
1303                 hdmi_dev_config_avi(hdmi_dev, vpara);
1304                 if (vpara->format_3d != HDMI_3D_NONE) {
1305                         hdmi_dev_config_vsi(hdmi,
1306                                             vpara->format_3d,
1307                                             HDMI_VIDEO_FORMAT_3D);
1308                 } else if ((vpara->vic > 92 && vpara->vic < 96) ||
1309                          (vpara->vic == 98)) {
1310                         vpara->vic = (vpara->vic == 98) ?
1311                                      4 : (96 - vpara->vic);
1312                         hdmi_dev_config_vsi(hdmi,
1313                                             vpara->vic,
1314                                             HDMI_VIDEO_FORMAT_4KX2K);
1315                 } else {
1316                         hdmi_dev_config_vsi(hdmi,
1317                                             vpara->vic,
1318                                             HDMI_VIDEO_FORMAT_NORMAL);
1319                 }
1320                 dev_info(hdmi->dev, "[%s] sucess output HDMI.\n", __func__);
1321         } else {
1322                 dev_info(hdmi->dev, "[%s] sucess output DVI.\n", __func__);
1323         }
1324
1325         if (!hdmi->uboot)
1326                 rockchip_hdmiv2_config_phy(hdmi_dev);
1327         return 0;
1328 }
1329
1330 static void hdmi_dev_config_aai(struct hdmi_dev *hdmi_dev,
1331                                 struct hdmi_audio *audio)
1332 {
1333         /*Refer to CEA861-E Audio infoFrame*/
1334         /*Set both Audio Channel Count and Audio Coding
1335           Type Refer to Stream Head for HDMI*/
1336         hdmi_msk_reg(hdmi_dev, FC_AUDICONF0,
1337                      m_FC_CHN_CNT | m_FC_CODING_TYEP,
1338                      v_FC_CHN_CNT(audio->channel-1) | v_FC_CODING_TYEP(0));
1339
1340         /*Set both Audio Sample Size and Sample Frequency
1341           Refer to Stream Head for HDMI*/
1342         hdmi_msk_reg(hdmi_dev, FC_AUDICONF1,
1343                      m_FC_SAMPLE_SIZE | m_FC_SAMPLE_FREQ,
1344                      v_FC_SAMPLE_SIZE(0) | v_FC_SAMPLE_FREQ(0));
1345
1346         /*Set Channel Allocation*/
1347         hdmi_writel(hdmi_dev, FC_AUDICONF2, 0x00);
1348
1349         /*Set LFEPBL¡¢DOWN-MIX INH and LSV*/
1350         hdmi_writel(hdmi_dev, FC_AUDICONF3, 0x00);
1351 }
1352
1353 static int hdmi_dev_config_audio(struct hdmi *hdmi, struct hdmi_audio *audio)
1354 {
1355         struct hdmi_dev *hdmi_dev = hdmi->property->priv;
1356         int word_length = 0, channel = 0, mclk_fs;
1357         unsigned int N = 0, CTS = 0;
1358         int rate = 0;
1359
1360         HDMIDBG("%s\n", __func__);
1361
1362         if (audio->channel < 3)
1363                 channel = I2S_CHANNEL_1_2;
1364         else if (audio->channel < 5)
1365                 channel = I2S_CHANNEL_3_4;
1366         else if (audio->channel < 7)
1367                 channel = I2S_CHANNEL_5_6;
1368         else
1369                 channel = I2S_CHANNEL_7_8;
1370
1371         switch (audio->rate) {
1372         case HDMI_AUDIO_FS_32000:
1373                 mclk_fs = FS_128;
1374                 rate = AUDIO_32K;
1375                 if (hdmi_dev->tmdsclk >= 594000000)
1376                         N = N_32K_HIGHCLK;
1377                 else if (hdmi_dev->tmdsclk >= 297000000)
1378                         N = N_32K_MIDCLK;
1379                 else
1380                         N = N_32K_LOWCLK;
1381                 /*div a num to avoid the value is exceed 2^32(int)*/
1382                 CTS = CALC_CTS(N, hdmi_dev->tmdsclk/1000, 32);
1383                 break;
1384         case HDMI_AUDIO_FS_44100:
1385                 mclk_fs = FS_128;
1386                 rate = AUDIO_441K;
1387                 if (hdmi_dev->tmdsclk >= 594000000)
1388                         N = N_441K_HIGHCLK;
1389                 else if (hdmi_dev->tmdsclk >= 297000000)
1390                         N = N_441K_MIDCLK;
1391                 else
1392                         N = N_441K_LOWCLK;
1393
1394                 CTS = CALC_CTS(N, hdmi_dev->tmdsclk/100, 441);
1395                 break;
1396         case HDMI_AUDIO_FS_48000:
1397                 mclk_fs = FS_128;
1398                 rate = AUDIO_48K;
1399                 if (hdmi_dev->tmdsclk >= 594000000)     /*FS_153.6*/
1400                         N = N_48K_HIGHCLK;
1401                 else if (hdmi_dev->tmdsclk >= 297000000)
1402                         N = N_48K_MIDCLK;
1403                 else
1404                         N = N_48K_LOWCLK;
1405
1406                 CTS = CALC_CTS(N, hdmi_dev->tmdsclk/1000, 48);
1407                 break;
1408         case HDMI_AUDIO_FS_88200:
1409                 mclk_fs = FS_128;
1410                 rate = AUDIO_882K;
1411                 if (hdmi_dev->tmdsclk >= 594000000)
1412                         N = N_882K_HIGHCLK;
1413                 else if (hdmi_dev->tmdsclk >= 297000000)
1414                         N = N_882K_MIDCLK;
1415                 else
1416                         N = N_882K_LOWCLK;
1417
1418                 CTS = CALC_CTS(N, hdmi_dev->tmdsclk/100, 882);
1419                 break;
1420         case HDMI_AUDIO_FS_96000:
1421                 mclk_fs = FS_128;
1422                 rate = AUDIO_96K;
1423                 if (hdmi_dev->tmdsclk >= 594000000)     /*FS_153.6*/
1424                         N = N_96K_HIGHCLK;
1425                 else if (hdmi_dev->tmdsclk >= 297000000)
1426                         N = N_96K_MIDCLK;
1427                 else
1428                         N = N_96K_LOWCLK;
1429
1430                 CTS = CALC_CTS(N, hdmi_dev->tmdsclk/1000, 96);
1431                 break;
1432         case HDMI_AUDIO_FS_176400:
1433                 mclk_fs = FS_128;
1434                 rate = AUDIO_1764K;
1435                 if (hdmi_dev->tmdsclk >= 594000000)
1436                         N = N_1764K_HIGHCLK;
1437                 else if (hdmi_dev->tmdsclk >= 297000000)
1438                         N = N_1764K_MIDCLK;
1439                 else
1440                         N = N_1764K_LOWCLK;
1441
1442                 CTS = CALC_CTS(N, hdmi_dev->tmdsclk/100, 1764);
1443                 break;
1444         case HDMI_AUDIO_FS_192000:
1445                 mclk_fs = FS_128;
1446                 rate = AUDIO_192K;
1447                 if (hdmi_dev->tmdsclk >= 594000000)     /*FS_153.6*/
1448                         N = N_192K_HIGHCLK;
1449                 else if (hdmi_dev->tmdsclk >= 297000000)
1450                         N = N_192K_MIDCLK;
1451                 else
1452                         N = N_192K_LOWCLK;
1453
1454                 CTS = CALC_CTS(N, hdmi_dev->tmdsclk/1000, 192);
1455                 break;
1456         default:
1457                 dev_err(hdmi_dev->hdmi->dev,
1458                         "[%s] not support such sample rate %d\n",
1459                         __func__, audio->rate);
1460                 return -ENOENT;
1461         }
1462
1463         switch (audio->word_length) {
1464         case HDMI_AUDIO_WORD_LENGTH_16bit:
1465                 word_length = I2S_16BIT_SAMPLE;
1466                 break;
1467         case HDMI_AUDIO_WORD_LENGTH_20bit:
1468                 word_length = I2S_20BIT_SAMPLE;
1469                 break;
1470         case HDMI_AUDIO_WORD_LENGTH_24bit:
1471                 word_length = I2S_24BIT_SAMPLE;
1472                 break;
1473         default:
1474                 word_length = I2S_16BIT_SAMPLE;
1475         }
1476
1477         HDMIDBG("rate = %d, tmdsclk = %u, N = %d, CTS = %d\n",
1478                 audio->rate, hdmi_dev->tmdsclk, N, CTS);
1479         /* more than 2 channels => layout 1 else layout 0 */
1480         hdmi_msk_reg(hdmi_dev, FC_AUDSCONF,
1481                      m_AUD_PACK_LAYOUT,
1482                      v_AUD_PACK_LAYOUT((audio->channel > 2) ? 1 : 0));
1483
1484         if (hdmi_dev->audiosrc == HDMI_AUDIO_SRC_SPDIF) {
1485                 mclk_fs = FS_128;
1486                 hdmi_msk_reg(hdmi_dev, AUD_CONF0,
1487                              m_I2S_SEL, v_I2S_SEL(AUDIO_SPDIF_GPA));
1488                 hdmi_msk_reg(hdmi_dev, AUD_SPDIF1,
1489                              m_SET_NLPCM | m_SPDIF_WIDTH,
1490                              v_SET_NLPCM(PCM_LINEAR) |
1491                              v_SPDIF_WIDTH(word_length));
1492                 /*Mask fifo empty and full int and reset fifo*/
1493                 hdmi_msk_reg(hdmi_dev, AUD_SPDIFINT,
1494                              m_FIFO_EMPTY_MASK | m_FIFO_FULL_MASK,
1495                              v_FIFO_EMPTY_MASK(1) | v_FIFO_FULL_MASK(1));
1496                 hdmi_msk_reg(hdmi_dev, AUD_SPDIF0,
1497                              m_SW_SAUD_FIFO_RST, v_SW_SAUD_FIFO_RST(1));
1498         } else {
1499                 /*Mask fifo empty and full int and reset fifo*/
1500                 hdmi_msk_reg(hdmi_dev, AUD_INT,
1501                              m_FIFO_EMPTY_MASK | m_FIFO_FULL_MASK,
1502                              v_FIFO_EMPTY_MASK(1) | v_FIFO_FULL_MASK(1));
1503                 hdmi_msk_reg(hdmi_dev, AUD_CONF0,
1504                              m_SW_AUD_FIFO_RST, v_SW_AUD_FIFO_RST(1));
1505                 hdmi_writel(hdmi_dev, MC_SWRSTZREQ, 0xF7);
1506                 hdmi_writel(hdmi_dev, AUD_CONF2, 0x0);
1507                 usleep_range(90, 100);
1508                 if (I2S_CHANNEL_7_8 == channel) {
1509                         HDMIDBG("hbr mode.\n");
1510                         hdmi_writel(hdmi_dev, AUD_CONF2, 0x1);
1511                         word_length = I2S_24BIT_SAMPLE;
1512                 } else if ((HDMI_AUDIO_FS_48000 == audio->rate) ||
1513                            (HDMI_AUDIO_FS_192000 == audio->rate)) {
1514                         HDMIDBG("nlpcm mode.\n");
1515                         hdmi_writel(hdmi_dev, AUD_CONF2, 0x2);
1516                         word_length = I2S_24BIT_SAMPLE;
1517                 } else {
1518                         hdmi_writel(hdmi_dev, AUD_CONF2, 0x0);
1519                 }
1520                 hdmi_msk_reg(hdmi_dev, AUD_CONF0,
1521                              m_I2S_SEL | m_I2S_IN_EN,
1522                              v_I2S_SEL(AUDIO_I2S) | v_I2S_IN_EN(channel));
1523                 hdmi_writel(hdmi_dev, AUD_CONF1,
1524                             v_I2S_MODE(I2S_STANDARD_MODE) |
1525                             v_I2S_WIDTH(word_length));
1526         }
1527
1528         hdmi_msk_reg(hdmi_dev, AUD_INPUTCLKFS,
1529                      m_LFS_FACTOR, v_LFS_FACTOR(mclk_fs));
1530
1531         /*Set N value*/
1532         hdmi_msk_reg(hdmi_dev, AUD_N3, m_NCTS_ATOMIC_WR, v_NCTS_ATOMIC_WR(1));
1533         /*Set CTS by manual*/
1534         hdmi_msk_reg(hdmi_dev, AUD_CTS3,
1535                      m_N_SHIFT | m_CTS_MANUAL | m_AUD_CTS3,
1536                      v_N_SHIFT(N_SHIFT_1) |
1537                      v_CTS_MANUAL(1) |
1538                      v_AUD_CTS3(CTS >> 16));
1539         hdmi_writel(hdmi_dev, AUD_CTS2, (CTS >> 8) & 0xff);
1540         hdmi_writel(hdmi_dev, AUD_CTS1, CTS & 0xff);
1541
1542         hdmi_msk_reg(hdmi_dev, AUD_N3, m_AUD_N3, v_AUD_N3(N >> 16));
1543         hdmi_writel(hdmi_dev, AUD_N2, (N >> 8) & 0xff);
1544         hdmi_writel(hdmi_dev, AUD_N1, N & 0xff);
1545
1546         /* set channel status register */
1547         hdmi_msk_reg(hdmi_dev, FC_AUDSCHNLS7,
1548                      m_AUDIO_SAMPLE_RATE, v_AUDIO_SAMPLE_RATE(rate));
1549         hdmi_writel(hdmi_dev, FC_AUDSCHNLS8, ((~rate) << 4) | 0x2);
1550
1551         hdmi_msk_reg(hdmi_dev, AUD_CONF0,
1552                      m_SW_AUD_FIFO_RST, v_SW_AUD_FIFO_RST(1));
1553
1554         hdmi_dev_config_aai(hdmi_dev, audio);
1555
1556         return 0;
1557 }
1558
1559 static int hdmi_dev_control_output(struct hdmi *hdmi, int enable)
1560 {
1561         struct hdmi_dev *hdmi_dev = hdmi->property->priv;
1562         struct hdmi_video vpara;
1563
1564         HDMIDBG("[%s] %d\n", __func__, enable);
1565         if (enable == HDMI_AV_UNMUTE) {
1566                 hdmi_writel(hdmi_dev, FC_DBGFORCE, 0x00);
1567                 if (hdmi->edid.sink_hdmi == OUTPUT_HDMI)
1568                         hdmi_msk_reg(hdmi_dev, FC_GCP,
1569                                      m_FC_SET_AVMUTE | m_FC_CLR_AVMUTE,
1570                                      v_FC_SET_AVMUTE(0) | v_FC_CLR_AVMUTE(1));
1571         } else {
1572                 if (enable & HDMI_VIDEO_MUTE) {
1573                         hdmi_msk_reg(hdmi_dev, FC_DBGFORCE,
1574                                      m_FC_FORCEVIDEO, v_FC_FORCEVIDEO(1));
1575                         if (hdmi->edid.sink_hdmi == OUTPUT_HDMI) {
1576                                 hdmi_msk_reg(hdmi_dev, FC_GCP,
1577                                              m_FC_SET_AVMUTE |
1578                                              m_FC_CLR_AVMUTE,
1579                                              v_FC_SET_AVMUTE(1) |
1580                                              v_FC_CLR_AVMUTE(0));
1581                                 vpara.vic = hdmi->vic;
1582                                 vpara.color_output = HDMI_COLOR_RGB_0_255;
1583                                 hdmi_dev_config_avi(hdmi_dev, &vpara);
1584                                 while ((!hdmi_readl(hdmi_dev, IH_FC_STAT1)) &
1585                                        m_AVI_INFOFRAME) {
1586                                         usleep_range(900, 1000);
1587                                 }
1588                         }
1589                 }
1590 /*              if (enable & HDMI_AUDIO_MUTE) {
1591                         hdmi_msk_reg(hdmi_dev, FC_AUDSCONF,
1592                                      m_AUD_PACK_SAMPFIT,
1593                                      v_AUD_PACK_SAMPFIT(0x0F));
1594                 }
1595 */              if (enable == (HDMI_VIDEO_MUTE | HDMI_AUDIO_MUTE)) {
1596                         if (hdmi->ops->hdcp_power_off_cb)
1597                                 hdmi->ops->hdcp_power_off_cb(hdmi);
1598                         rockchip_hdmiv2_powerdown(hdmi_dev);
1599                         hdmi_dev->tmdsclk = 0;
1600 /*
1601                         hdmi_msk_reg(hdmi_dev, PHY_CONF0,
1602                                      m_PDDQ_SIG | m_TXPWRON_SIG,
1603                                      v_PDDQ_SIG(1) | v_TXPWRON_SIG(0));
1604                         hdmi_writel(hdmi_dev, MC_CLKDIS, 0x7f);
1605 */              }
1606         }
1607         return 0;
1608 }
1609
1610 static int hdmi_dev_insert(struct hdmi *hdmi)
1611 {
1612         struct hdmi_dev *hdmi_dev = hdmi->property->priv;
1613
1614         HDMIDBG("%s\n", __func__);
1615         if (!hdmi->uboot)
1616                 hdmi_writel(hdmi_dev, MC_CLKDIS, m_HDCPCLK_DISABLE);
1617         return HDMI_ERROR_SUCESS;
1618 }
1619
1620 static int hdmi_dev_remove(struct hdmi *hdmi)
1621 {
1622         struct hdmi_dev *hdmi_dev = hdmi->property->priv;
1623
1624         HDMIDBG("%s\n", __func__);
1625         if (hdmi->ops->hdcp_power_off_cb)
1626                 hdmi->ops->hdcp_power_off_cb(hdmi);
1627         rockchip_hdmiv2_powerdown(hdmi_dev);
1628         hdmi_dev->tmdsclk = 0;
1629         return HDMI_ERROR_SUCESS;
1630 }
1631
1632 static int hdmi_dev_enable(struct hdmi *hdmi)
1633 {
1634         struct hdmi_dev *hdmi_dev = hdmi->property->priv;
1635
1636         HDMIDBG("%s\n", __func__);
1637         if (!hdmi_dev->enable) {
1638                 hdmi_writel(hdmi_dev, IH_MUTE, 0x00);
1639                 hdmi_dev->enable = 1;
1640         }
1641         hdmi_submit_work(hdmi, HDMI_HPD_CHANGE, 10, 0);
1642         return 0;
1643 }
1644
1645 static int hdmi_dev_disable(struct hdmi *hdmi)
1646 {
1647         struct hdmi_dev *hdmi_dev = hdmi->property->priv;
1648
1649         HDMIDBG("%s\n", __func__);
1650         if (hdmi_dev->enable) {
1651                 hdmi_dev->enable = 0;
1652                 hdmi_writel(hdmi_dev, IH_MUTE, 0x1);
1653         }
1654         return 0;
1655 }
1656
1657 void rockchip_hdmiv2_dev_init_ops(struct hdmi_ops *ops)
1658 {
1659         if (ops) {
1660                 ops->enable     = hdmi_dev_enable;
1661                 ops->disable    = hdmi_dev_disable;
1662                 ops->getstatus  = hdmi_dev_detect_hotplug;
1663                 ops->insert     = hdmi_dev_insert;
1664                 ops->remove     = hdmi_dev_remove;
1665                 ops->getedid    = hdmi_dev_read_edid;
1666                 ops->setvideo   = hdmi_dev_config_video;
1667                 ops->setaudio   = hdmi_dev_config_audio;
1668                 ops->setmute    = hdmi_dev_control_output;
1669                 ops->setvsi     = hdmi_dev_config_vsi;
1670         }
1671 }
1672
1673 void rockchip_hdmiv2_dev_initial(struct hdmi_dev *hdmi_dev)
1674 {
1675         struct hdmi *hdmi = hdmi_dev->hdmi;
1676
1677         if (!hdmi->uboot) {
1678                 /* reset hdmi */
1679                 if (hdmi_dev->soctype == HDMI_SOC_RK3288) {
1680                         writel_relaxed((1 << 9) | (1 << 25),
1681                                        RK_CRU_VIRT + 0x01d4);
1682                         udelay(1);
1683                         writel_relaxed((0 << 9) | (1 << 25),
1684                                        RK_CRU_VIRT + 0x01d4);
1685                 } else if (hdmi_dev->soctype == HDMI_SOC_RK3368) {
1686                         pr_info("reset hdmi\n");
1687                         regmap_write(hdmi_dev->grf_base, 0x031c,
1688                                      (1 << 9) | (1 << 25));
1689                         udelay(5);
1690                         regmap_write(hdmi_dev->grf_base, 0x031c,
1691                                      (0 << 9) | (1 << 25));
1692                 }
1693                 rockchip_hdmiv2_powerdown(hdmi_dev);
1694         }
1695         /*mute unnecessary interrrupt, only enable hpd*/
1696         hdmi_writel(hdmi_dev, IH_MUTE_FC_STAT0, 0xff);
1697         hdmi_writel(hdmi_dev, IH_MUTE_FC_STAT1, 0xff);
1698         hdmi_writel(hdmi_dev, IH_MUTE_FC_STAT2, 0xff);
1699         hdmi_writel(hdmi_dev, IH_MUTE_AS_STAT0, 0xff);
1700         hdmi_writel(hdmi_dev, IH_MUTE_PHY_STAT0, 0xfe);
1701         hdmi_writel(hdmi_dev, IH_MUTE_I2CM_STAT0, 0xff);
1702         hdmi_writel(hdmi_dev, IH_MUTE_CEC_STAT0, 0xff);
1703         hdmi_writel(hdmi_dev, IH_MUTE_VP_STAT0, 0xff);
1704         hdmi_writel(hdmi_dev, IH_MUTE_I2CMPHY_STAT0, 0xff);
1705         hdmi_writel(hdmi_dev, IH_MUTE_AHBDMAAUD_STAT0, 0xff);
1706
1707         /* disable hdcp interrup */
1708         hdmi_writel(hdmi_dev, A_APIINTMSK, 0xff);
1709         hdmi_writel(hdmi_dev, PHY_MASK, 0xf1);
1710
1711         if (hdmi->property->feature & SUPPORT_CEC)
1712                 rockchip_hdmiv2_cec_init(hdmi);
1713         if (hdmi->property->feature & SUPPORT_HDCP)
1714                 rockchip_hdmiv2_hdcp_init(hdmi);
1715 }
1716
1717 irqreturn_t rockchip_hdmiv2_dev_irq(int irq, void *priv)
1718 {
1719         struct hdmi_dev *hdmi_dev = priv;
1720         struct hdmi *hdmi = hdmi_dev->hdmi;
1721         char phy_pol = hdmi_readl(hdmi_dev, PHY_POL0);
1722         char phy_status = hdmi_readl(hdmi_dev, PHY_STAT0);
1723         char phy_int0 = hdmi_readl(hdmi_dev, PHY_INI0);
1724         /*read interrupt*/
1725         char fc_stat0 = hdmi_readl(hdmi_dev, IH_FC_STAT0);
1726         char fc_stat1 = hdmi_readl(hdmi_dev, IH_FC_STAT1);
1727         char fc_stat2 = hdmi_readl(hdmi_dev, IH_FC_STAT2);
1728         char aud_int = hdmi_readl(hdmi_dev, IH_AS_SATA0);
1729         char phy_int = hdmi_readl(hdmi_dev, IH_PHY_STAT0);
1730         char vp_stat0 = hdmi_readl(hdmi_dev, IH_VP_STAT0);
1731         char cec_int = hdmi_readl(hdmi_dev, IH_CEC_STAT0);
1732         char hdcp_int = hdmi_readl(hdmi_dev, A_APIINTSTAT);
1733         char hdcp2_int = hdmi_readl(hdmi_dev, HDCP2REG_STAT);
1734
1735         /*clear interrupt*/
1736         hdmi_writel(hdmi_dev, IH_FC_STAT0, fc_stat0);
1737         hdmi_writel(hdmi_dev, IH_FC_STAT1, fc_stat1);
1738         hdmi_writel(hdmi_dev, IH_FC_STAT2, fc_stat2);
1739         hdmi_writel(hdmi_dev, IH_VP_STAT0, vp_stat0);
1740
1741         if (phy_int0 || phy_int) {
1742                 phy_pol = (phy_int0 & (~phy_status)) | ((~phy_int0) & phy_pol);
1743                 hdmi_writel(hdmi_dev, PHY_POL0, phy_pol);
1744                 hdmi_writel(hdmi_dev, IH_PHY_STAT0, phy_int);
1745                 if ((phy_int & m_HPD) || ((phy_int & 0x3c) == 0x3c))
1746                         hdmi_submit_work(hdmi, HDMI_HPD_CHANGE, 20, 0);
1747         }
1748
1749         /* Audio error */
1750         if (aud_int) {
1751                 hdmi_writel(hdmi_dev, IH_AS_SATA0, aud_int);
1752                 hdmi_msk_reg(hdmi_dev, AUD_CONF0,
1753                              m_SW_AUD_FIFO_RST, v_SW_AUD_FIFO_RST(1));
1754                 hdmi_writel(hdmi_dev, MC_SWRSTZREQ, 0xF7);
1755         }
1756         /* CEC */
1757         if (cec_int) {
1758                 hdmi_writel(hdmi_dev, IH_CEC_STAT0, cec_int);
1759                 rockchip_hdmiv2_cec_isr(hdmi_dev, cec_int);
1760         }
1761         /* HDCP */
1762         if (hdcp_int) {
1763                 hdmi_writel(hdmi_dev, A_APIINTCLR, hdcp_int);
1764                 rockchip_hdmiv2_hdcp_isr(hdmi_dev, hdcp_int);
1765         }
1766
1767         /* HDCP2 */
1768         if (hdcp2_int) {
1769                 hdmi_writel(hdmi_dev, HDCP2REG_STAT, hdcp2_int);
1770                 pr_info("hdcp2_int is 0x%02x\n", hdcp2_int);
1771                 if ((hdcp2_int & m_HDCP2_AUTH_FAIL ||
1772                      hdcp2_int & m_HDCP2_AUTH_LOST) &&
1773                     hdmi_dev->hdcp2_start) {
1774                         pr_info("hdcp2 failed or lost\n");
1775                         hdmi_dev->hdcp2_start();
1776                 }
1777         }
1778         return IRQ_HANDLED;
1779 }