1 #include <linux/delay.h>
2 #include <linux/interrupt.h>
3 #include <linux/rockchip/grf.h>
4 #include <linux/rockchip/iomap.h>
5 #include "rockchip_hdmiv2.h"
6 #include "rockchip_hdmiv2_hw.h"
8 static const struct phy_mpll_config_tab PHY_MPLL_TABLE[] = {
9 /*tmdsclk = (pixclk / ref_cntrl ) * (fbdiv2 * fbdiv1) / nctrl / tmdsmhl
10 opmode: 0:HDMI1.4 1:HDMI2.0
12 /* |pixclock| tmdsclock|pixrepet|colordepth|prepdiv|tmdsmhl|opmode|
13 fbdiv2|fbdiv1|ref_cntrl|nctrl|propctrl|intctrl|gmpctrl| */
14 {27000000, 27000000, 0, 8, 0, 0, 0,
16 {27000000, 33750000, 0, 10, 1, 0, 0,
18 {27000000, 40500000, 0, 12, 2, 0, 0,
20 {27000000, 54000000, 0, 16, 3, 0, 0,
22 /* {74250000, 74250000, 0, 8, 0, 0, 0,
23 1, 3, 0, 2, 5, 0, 1}, */
24 {74250000, 74250000, 0, 8, 0, 0, 0,
26 {74250000, 92812500, 0, 10, 1, 0, 0,
28 {74250000, 111375000, 0, 12, 2, 0, 0,
30 {74250000, 148500000, 0, 16, 3, 0, 0,
32 {148500000, 74250000, 0, 8, 0, 0, 0,
34 {148500000, 148500000, 0, 8, 0, 0, 0,
36 {148500000, 185625000, 0, 10, 1, 0, 0,
38 {148500000, 222750000, 0, 12, 2, 0, 0,
40 {148500000, 297000000, 0, 16, 3, 0, 0,
42 {297000000, 148500000, 0, 8, 0, 0, 0,
44 {297000000, 297000000, 0, 8, 0, 0, 0,
46 {297000000, 371250000, 0, 10, 1, 3, 1,
48 {297000000, 445500000, 0, 12, 2, 3, 1,
50 {297000000, 594000000, 0, 16, 1, 3, 1,
52 /* {594000000, 297000000, 0, 8, 0, 0, 0,
53 1, 3, 3, 1, 0, 0, 3},*/
54 {594000000, 297000000, 0, 8, 0, 0, 0,
56 {594000000, 594000000, 0, 8, 0, 3, 1,
59 /* ddc i2c master reset */
60 static void rockchip_hdmiv2_i2cm_reset(struct hdmi_dev *hdmi_dev)
62 hdmi_msk_reg(hdmi_dev, I2CM_SOFTRSTZ,
63 m_I2CM_SOFTRST, v_I2CM_SOFTRST(0));
64 usleep_range(90, 100);
67 /*set read/write offset,set read/write mode*/
68 static void rockchip_hdmiv2_i2cm_write_request(struct hdmi_dev *hdmi_dev,
71 hdmi_writel(hdmi_dev, I2CM_ADDRESS, offset);
72 hdmi_writel(hdmi_dev, I2CM_DATAO, data);
73 hdmi_msk_reg(hdmi_dev, I2CM_OPERATION, m_I2CM_WR, v_I2CM_WR(1));
76 static void rockchip_hdmiv2_i2cm_read_request(struct hdmi_dev *hdmi_dev,
79 hdmi_writel(hdmi_dev, I2CM_ADDRESS, offset);
80 hdmi_msk_reg(hdmi_dev, I2CM_OPERATION, m_I2CM_RD, v_I2CM_RD(1));
83 static void rockchip_hdmiv2_i2cm_write_data(struct hdmi_dev *hdmi_dev,
90 while (trytime-- > 0) {
91 rockchip_hdmiv2_i2cm_write_request(hdmi_dev, offset, data);
93 usleep_range(900, 1000);
94 interrupt = hdmi_readl(hdmi_dev, IH_I2CM_STAT0);
97 IH_I2CM_STAT0, interrupt);
99 if (interrupt & (m_SCDC_READREQ |
100 m_I2CM_DONE | m_I2CM_ERROR))
104 if (interrupt & m_I2CM_DONE) {
105 dev_dbg(hdmi_dev->hdmi->dev,
106 "[%s] write offset %02x data %02x success\n",
107 __func__, offset, data);
109 } else if ((interrupt & m_I2CM_ERROR) || (i == -1)) {
110 dev_err(hdmi_dev->hdmi->dev,
111 "[%s] write data error\n", __func__);
112 rockchip_hdmiv2_i2cm_reset(hdmi_dev);
117 static int rockchip_hdmiv2_i2cm_read_data(struct hdmi_dev *hdmi_dev, u8 offset)
123 while (trytime-- > 0) {
124 rockchip_hdmiv2_i2cm_read_request(hdmi_dev, offset);
126 usleep_range(900, 1000);
127 interrupt = hdmi_readl(hdmi_dev, IH_I2CM_STAT0);
129 hdmi_writel(hdmi_dev, IH_I2CM_STAT0, interrupt);
131 if (interrupt & (m_SCDC_READREQ |
132 m_I2CM_DONE | m_I2CM_ERROR))
136 if (interrupt & m_I2CM_DONE) {
137 val = hdmi_readl(hdmi_dev, I2CM_DATAI);
139 } else if ((interrupt & m_I2CM_ERROR) || (i == -1)) {
140 pr_err("[%s] read data error\n", __func__);
141 rockchip_hdmiv2_i2cm_reset(hdmi_dev);
147 static void rockchip_hdmiv2_i2cm_mask_int(struct hdmi_dev *hdmi_dev, int mask)
150 hdmi_msk_reg(hdmi_dev, I2CM_INT,
151 m_I2CM_DONE_MASK, v_I2CM_DONE_MASK(0));
152 hdmi_msk_reg(hdmi_dev, I2CM_CTLINT,
153 m_I2CM_NACK_MASK | m_I2CM_ARB_MASK,
154 v_I2CM_NACK_MASK(0) | v_I2CM_ARB_MASK(0));
156 hdmi_msk_reg(hdmi_dev, I2CM_INT,
157 m_I2CM_DONE_MASK, v_I2CM_DONE_MASK(1));
158 hdmi_msk_reg(hdmi_dev, I2CM_CTLINT,
159 m_I2CM_NACK_MASK | m_I2CM_ARB_MASK,
160 v_I2CM_NACK_MASK(1) | v_I2CM_ARB_MASK(1));
164 #define I2C_DIV_FACTOR 100000
165 static u16 i2c_count(u16 sfrclock, u16 sclmintime)
167 unsigned long tmp_scl_period = 0;
169 if (((sfrclock * sclmintime) % I2C_DIV_FACTOR) != 0)
170 tmp_scl_period = (unsigned long)((sfrclock * sclmintime) +
171 (I2C_DIV_FACTOR - ((sfrclock * sclmintime) %
172 I2C_DIV_FACTOR))) / I2C_DIV_FACTOR;
174 tmp_scl_period = (unsigned long)(sfrclock * sclmintime) /
177 return (u16)(tmp_scl_period);
180 #define EDID_I2C_MIN_SS_SCL_HIGH_TIME 50000
181 #define EDID_I2C_MIN_SS_SCL_LOW_TIME 50000
183 static void rockchip_hdmiv2_i2cm_clk_init(struct hdmi_dev *hdmi_dev)
185 /* Set DDC I2C CLK which devided from DDC_CLK. */
186 hdmi_writel(hdmi_dev, I2CM_SS_SCL_HCNT_0_ADDR,
187 i2c_count(24000, EDID_I2C_MIN_SS_SCL_HIGH_TIME));
188 hdmi_writel(hdmi_dev, I2CM_SS_SCL_LCNT_0_ADDR,
189 i2c_count(24000, EDID_I2C_MIN_SS_SCL_LOW_TIME));
190 hdmi_msk_reg(hdmi_dev, I2CM_DIV, m_I2CM_FAST_STD_MODE,
191 v_I2CM_FAST_STD_MODE(STANDARD_MODE));
194 static int rockchip_hdmiv2_scdc_get_sink_version(struct hdmi_dev *hdmi_dev)
196 return rockchip_hdmiv2_i2cm_read_data(hdmi_dev, SCDC_SINK_VER);
199 static void rockchip_hdmiv2_scdc_set_source_version(struct hdmi_dev *hdmi_dev,
202 rockchip_hdmiv2_i2cm_write_data(hdmi_dev, version, SCDC_SOURCE_VER);
206 static void rockchip_hdmiv2_scdc_read_request(struct hdmi_dev *hdmi_dev,
209 hdmi_msk_reg(hdmi_dev, I2CM_SCDC_READ_UPDATE,
210 m_I2CM_READ_REQ_EN, v_I2CM_READ_REQ_EN(enable));
211 rockchip_hdmiv2_i2cm_write_data(hdmi_dev, enable, SCDC_CONFIG_0);
215 static void rockchip_hdmiv2_scdc_update_read(struct hdmi_dev *hdmi_dev)
217 hdmi_msk_reg(hdmi_dev, I2CM_SCDC_READ_UPDATE,
218 m_I2CM_READ_UPDATE, v_I2CM_READ_UPDATE(1));
222 static int rockchip_hdmiv2_scdc_get_scambling_status(struct hdmi_dev *hdmi_dev)
226 val = rockchip_hdmiv2_i2cm_read_data(hdmi_dev, SCDC_SCRAMBLER_STAT);
230 static void rockchip_hdmiv2_scdc_enable_polling(struct hdmi_dev *hdmi_dev,
233 rockchip_hdmiv2_scdc_read_request(hdmi_dev, enable);
234 hdmi_msk_reg(hdmi_dev, I2CM_SCDC_READ_UPDATE,
235 m_I2CM_UPRD_VSYNC_EN, v_I2CM_UPRD_VSYNC_EN(enable));
238 static int rockchip_hdmiv2_scdc_get_status_reg0(struct hdmi_dev *hdmi_dev)
240 rockchip_hdmiv2_scdc_read_request(hdmi_dev, 1);
241 rockchip_hdmiv2_scdc_update_read(hdmi_dev);
242 return hdmi_readl(hdmi_dev, I2CM_SCDC_UPDATE0);
245 static int rockchip_hdmiv2_scdc_get_status_reg1(struct hdmi_dev *hdmi_dev)
247 rockchip_hdmiv2_scdc_read_request(hdmi_dev, 1);
248 rockchip_hdmiv2_scdc_update_read(hdmi_dev);
249 return hdmi_readl(hdmi_dev, I2CM_SCDC_UPDATE1);
253 static void rockchip_hdmiv2_scdc_init(struct hdmi_dev *hdmi_dev)
255 rockchip_hdmiv2_i2cm_reset(hdmi_dev);
256 rockchip_hdmiv2_i2cm_mask_int(hdmi_dev, 1);
257 rockchip_hdmiv2_i2cm_clk_init(hdmi_dev);
258 /* set scdc i2c addr */
259 hdmi_writel(hdmi_dev, I2CM_SLAVE, DDC_I2C_SCDC_ADDR);
260 rockchip_hdmiv2_i2cm_mask_int(hdmi_dev, 0);/*enable interrupt*/
264 static int rockchip_hdmiv2_scrambling_enable(struct hdmi_dev *hdmi_dev,
267 HDMIDBG("%s enable %d\n", __func__, enable);
269 /* Write on Rx the bit Scrambling_Enable, register 0x20 */
270 rockchip_hdmiv2_i2cm_write_data(hdmi_dev, 1, SCDC_TMDS_CONFIG);
271 /* TMDS software reset request */
272 hdmi_msk_reg(hdmi_dev, MC_SWRSTZREQ,
273 m_TMDS_SWRST, v_TMDS_SWRST(0));
274 /* Enable/Disable Scrambling */
275 hdmi_msk_reg(hdmi_dev, FC_SCRAMBLER_CTRL,
276 m_FC_SCRAMBLE_EN, v_FC_SCRAMBLE_EN(1));
278 /* Enable/Disable Scrambling */
279 hdmi_msk_reg(hdmi_dev, FC_SCRAMBLER_CTRL,
280 m_FC_SCRAMBLE_EN, v_FC_SCRAMBLE_EN(0));
281 /* TMDS software reset request */
282 hdmi_msk_reg(hdmi_dev, MC_SWRSTZREQ,
283 m_TMDS_SWRST, v_TMDS_SWRST(0));
284 /* Write on Rx the bit Scrambling_Enable, register 0x20 */
285 rockchip_hdmiv2_i2cm_write_data(hdmi_dev, 0, SCDC_TMDS_CONFIG);
292 static const struct phy_mpll_config_tab *get_phy_mpll_tab(
293 unsigned int pixclock, unsigned int tmdsclk,
294 char pixrepet, char colordepth)
300 HDMIDBG("%s pixClock %u pixRepet %d colorDepth %d\n",
301 __func__, pixclock, pixrepet, colordepth);
302 for (i = 0; i < ARRAY_SIZE(PHY_MPLL_TABLE); i++) {
303 if ((PHY_MPLL_TABLE[i].pix_clock == pixclock) &&
304 (PHY_MPLL_TABLE[i].tmdsclock == tmdsclk) &&
305 (PHY_MPLL_TABLE[i].pix_repet == pixrepet) &&
306 (PHY_MPLL_TABLE[i].color_depth == colordepth))
307 return &PHY_MPLL_TABLE[i];
312 static void rockchip_hdmiv2_powerdown(struct hdmi_dev *hdmi_dev)
314 hdmi_msk_reg(hdmi_dev, PHY_CONF0,
315 m_PDDQ_SIG | m_TXPWRON_SIG | m_ENHPD_RXSENSE_SIG,
316 v_PDDQ_SIG(1) | v_TXPWRON_SIG(0) |
317 v_ENHPD_RXSENSE_SIG(1));
318 hdmi_writel(hdmi_dev, MC_CLKDIS, 0x7f);
321 static int rockchip_hdmiv2_write_phy(struct hdmi_dev *hdmi_dev,
322 int reg_addr, int val)
324 int trytime = 2, i = 0, op_status = 0;
327 hdmi_writel(hdmi_dev, PHY_I2CM_ADDRESS, reg_addr);
328 hdmi_writel(hdmi_dev, PHY_I2CM_DATAO_1, (val >> 8) & 0xff);
329 hdmi_writel(hdmi_dev, PHY_I2CM_DATAO_0, val & 0xff);
330 hdmi_writel(hdmi_dev, PHY_I2CM_OPERATION, m_PHY_I2CM_WRITE);
334 usleep_range(900, 1000);
335 op_status = hdmi_readl(hdmi_dev, IH_I2CMPHY_STAT0);
337 hdmi_writel(hdmi_dev,
341 if (op_status & (m_I2CMPHY_DONE | m_I2CMPHY_ERR))
345 if (op_status & m_I2CMPHY_DONE)
348 dev_err(hdmi_dev->hdmi->dev,
349 "[%s] operation error,trytime=%d\n",
357 static int __maybe_unused rockchip_hdmiv2_read_phy(struct hdmi_dev *hdmi_dev,
360 int trytime = 2, i = 0, op_status = 0;
364 hdmi_writel(hdmi_dev, PHY_I2CM_ADDRESS, reg_addr);
365 hdmi_writel(hdmi_dev, PHY_I2CM_DATAI_1, 0x00);
366 hdmi_writel(hdmi_dev, PHY_I2CM_DATAI_0, 0x00);
367 hdmi_writel(hdmi_dev, PHY_I2CM_OPERATION, m_PHY_I2CM_READ);
371 usleep_range(900, 1000);
372 op_status = hdmi_readl(hdmi_dev, IH_I2CMPHY_STAT0);
374 hdmi_writel(hdmi_dev, IH_I2CMPHY_STAT0,
377 if (op_status & (m_I2CMPHY_DONE | m_I2CMPHY_ERR))
381 if (op_status & m_I2CMPHY_DONE) {
382 val = hdmi_readl(hdmi_dev, PHY_I2CM_DATAI_1);
383 val = (val & 0xff) << 8;
384 val += (hdmi_readl(hdmi_dev, PHY_I2CM_DATAI_0) & 0xff);
385 pr_debug("phy_reg0x%02x: 0x%04x",
389 pr_err("[%s] operation error,trytime=%d\n",
398 void rockchip_hdmiv2_dump_phy_regs(struct hdmi_dev *hdmi_dev)
402 for (i = 0; i < 0x28; i++)
403 pr_info("phy reg %02x val %04x\n",
404 i, rockchip_hdmiv2_read_phy(hdmi_dev, i));
407 static int rockchip_hdmiv2_config_phy(struct hdmi_dev *hdmi_dev)
410 const struct phy_mpll_config_tab *phy_mpll = NULL;
412 hdmi_msk_reg(hdmi_dev, PHY_I2CM_DIV,
413 m_PHY_I2CM_FAST_STD, v_PHY_I2CM_FAST_STD(0));
415 /* hdmi_writel(hdmi_dev, PHY_CONF0, 0x1e); */
416 hdmi_msk_reg(hdmi_dev, PHY_CONF0,
417 m_PDDQ_SIG | m_TXPWRON_SIG | m_SVSRET_SIG,
418 v_PDDQ_SIG(1) | v_TXPWRON_SIG(0) | v_SVSRET_SIG(1));
420 if (hdmi_dev->tmdsclk_ratio_change &&
421 hdmi_dev->hdmi->edid.scdc_present == 1) {
422 mutex_lock(&hdmi_dev->ddc_lock);
423 rockchip_hdmiv2_scdc_init(hdmi_dev);
424 stat = rockchip_hdmiv2_i2cm_read_data(hdmi_dev,
426 if (hdmi_dev->tmdsclk > 340000000)
430 rockchip_hdmiv2_i2cm_write_data(hdmi_dev,
431 stat, SCDC_TMDS_CONFIG);
432 mutex_unlock(&hdmi_dev->ddc_lock);
435 hdmi_writel(hdmi_dev, MC_PHYRSTZ, v_PHY_RSTZ(1));
436 usleep_range(1000, 2000);
437 hdmi_writel(hdmi_dev, MC_PHYRSTZ, v_PHY_RSTZ(0));
439 /* Set slave address as PHY GEN2 address */
440 hdmi_writel(hdmi_dev, PHY_I2CM_SLAVE, PHY_GEN2_ADDR);
442 /* config the required PHY I2C register */
443 phy_mpll = get_phy_mpll_tab(hdmi_dev->pixelclk,
445 hdmi_dev->pixelrepeat - 1,
446 hdmi_dev->colordepth);
448 rockchip_hdmiv2_write_phy(hdmi_dev, PHYTX_OPMODE_PLLCFG,
449 v_PREP_DIV(phy_mpll->prep_div) |
451 phy_mpll->tmdsmhl_cntrl) |
452 v_OPMODE(phy_mpll->opmode) |
454 phy_mpll->fbdiv2_cntrl) |
456 phy_mpll->fbdiv1_cntrl) |
457 v_REF_CNTRL(phy_mpll->ref_cntrl) |
458 v_MPLL_N_CNTRL(phy_mpll->n_cntrl));
459 rockchip_hdmiv2_write_phy(hdmi_dev, PHYTX_PLLCURRCTRL,
461 phy_mpll->prop_cntrl) |
463 phy_mpll->int_cntrl));
464 rockchip_hdmiv2_write_phy(hdmi_dev, PHYTX_PLLGMPCTRL,
466 phy_mpll->gmp_cntrl));
468 if (hdmi_dev->tmdsclk <= 74250000) {
469 rockchip_hdmiv2_write_phy(hdmi_dev, PHYTX_CLKSYMCTRL,
470 v_OVERRIDE(1) | v_SLOPEBOOST(0) |
471 v_TX_SYMON(1) | v_TX_TRAON(0) |
472 v_TX_TRBON(0) | v_CLK_SYMON(1));
473 rockchip_hdmiv2_write_phy(hdmi_dev, PHYTX_TERM_RESIS,
474 v_TX_TERM(R100_OHMS));
475 } else if (hdmi_dev->tmdsclk <= 148500000) {
476 rockchip_hdmiv2_write_phy(hdmi_dev, PHYTX_CLKSYMCTRL,
477 v_OVERRIDE(1) | v_SLOPEBOOST(1) |
478 v_TX_SYMON(1) | v_TX_TRAON(0) |
479 v_TX_TRBON(0) | v_CLK_SYMON(1));
480 rockchip_hdmiv2_write_phy(hdmi_dev, PHYTX_TERM_RESIS,
481 v_TX_TERM(R100_OHMS));
482 } else if (hdmi_dev->tmdsclk <= 340000000) {
483 rockchip_hdmiv2_write_phy(hdmi_dev, PHYTX_CLKSYMCTRL,
484 v_OVERRIDE(1) | v_SLOPEBOOST(1) |
485 v_TX_SYMON(1) | v_TX_TRAON(0) |
486 v_TX_TRBON(0) | v_CLK_SYMON(1));
487 rockchip_hdmiv2_write_phy(hdmi_dev, PHYTX_TERM_RESIS,
488 v_TX_TERM(R100_OHMS));
489 } else if (hdmi_dev->tmdsclk > 340000000) {
490 rockchip_hdmiv2_write_phy(hdmi_dev, PHYTX_CLKSYMCTRL,
491 v_OVERRIDE(1) | v_SLOPEBOOST(0) |
492 v_TX_SYMON(1) | v_TX_TRAON(0) |
493 v_TX_TRBON(0) | v_CLK_SYMON(1));
494 rockchip_hdmiv2_write_phy(hdmi_dev, PHYTX_TERM_RESIS,
495 v_TX_TERM(R100_OHMS));
498 if (hdmi_dev->tmdsclk < 297000000)
499 rockchip_hdmiv2_write_phy(hdmi_dev, PHYTX_VLEVCTRL,
500 v_SUP_TXLVL(18) | v_SUP_CLKLVL(17));
502 rockchip_hdmiv2_write_phy(hdmi_dev, PHYTX_VLEVCTRL,
503 v_SUP_TXLVL(14) | v_SUP_CLKLVL(13));
505 rockchip_hdmiv2_write_phy(hdmi_dev, 0x05, 0x8000);
506 if (hdmi_dev->tmdsclk_ratio_change)
509 hdmi_writel(hdmi_dev, PHY_CONF0, 0x2e);
511 hdmi_msk_reg(hdmi_dev, PHY_CONF0,
512 m_PDDQ_SIG | m_TXPWRON_SIG | m_ENHPD_RXSENSE_SIG,
513 v_PDDQ_SIG(0) | v_TXPWRON_SIG(1) |
514 v_ENHPD_RXSENSE_SIG(1));
516 /* check if the PHY PLL is locked */
517 #define PHY_TIMEOUT 10000
518 while (i++ < PHY_TIMEOUT) {
520 stat = hdmi_readl(hdmi_dev, PHY_STAT0);
521 if (stat & m_PHY_LOCK)
523 usleep_range(1000, 2000);
526 if ((stat & m_PHY_LOCK) == 0) {
527 stat = hdmi_readl(hdmi_dev, MC_LOCKONCLOCK);
528 dev_err(hdmi_dev->hdmi->dev,
529 "PHY PLL not locked: PCLK_ON=%d,TMDSCLK_ON=%d\n",
530 (stat & m_PCLK_ON) >> 6, (stat & m_TMDSCLK_ON) >> 5);
537 static int rockchip_hdmiv2_video_framecomposer(struct hdmi *hdmi_drv,
538 struct hdmi_video *vpara)
540 struct hdmi_dev *hdmi_dev = hdmi_drv->property->priv;
541 int value, vsync_pol, hsync_pol, de_pol;
542 struct hdmi_video_timing *timing = NULL;
543 struct fb_videomode *mode = NULL;
544 u32 sink_version, tmdsclk;
546 vsync_pol = hdmi_drv->lcdc->cur_screen->pin_vsync;
547 hsync_pol = hdmi_drv->lcdc->cur_screen->pin_hsync;
548 de_pol = (hdmi_drv->lcdc->cur_screen->pin_den == 0) ? 1 : 0;
550 hdmi_msk_reg(hdmi_dev, A_VIDPOLCFG,
551 m_DATAEN_POL | m_VSYNC_POL | m_HSYNC_POL,
552 v_DATAEN_POL(de_pol) |
553 v_VSYNC_POL(vsync_pol) |
554 v_HSYNC_POL(hsync_pol));
556 timing = (struct hdmi_video_timing *)hdmi_vic2timing(vpara->vic);
557 if (timing == NULL) {
558 dev_err(hdmi_drv->dev,
559 "[%s] not found vic %d\n", __func__, vpara->vic);
562 mode = &(timing->mode);
563 if (vpara->color_input == HDMI_COLOR_YCBCR420)
564 tmdsclk = mode->pixclock / 2;
566 tmdsclk = mode->pixclock;
567 switch (vpara->color_output_depth) {
569 tmdsclk += tmdsclk / 4;
572 tmdsclk += tmdsclk / 2;
582 if (tmdsclk > 594000000) {
583 vpara->color_output_depth = 8;
584 tmdsclk = mode->pixclock;
586 pr_info("pixel clk is %u tmds clk is %u\n", mode->pixclock, tmdsclk);
587 if ((tmdsclk > 340000000 && hdmi_dev->tmdsclk < 340000000) ||
588 (tmdsclk < 340000000 && hdmi_dev->tmdsclk > 340000000))
589 hdmi_dev->tmdsclk_ratio_change = true;
591 hdmi_dev->tmdsclk_ratio_change = false;
593 hdmi_dev->tmdsclk = tmdsclk;
594 hdmi_dev->pixelclk = mode->pixclock;
595 hdmi_dev->pixelrepeat = timing->pixelrepeat;
596 hdmi_dev->colordepth = vpara->color_output_depth;
598 /* Video Register has already been set in uboot,
599 so we no need to set again */
604 /* Start/stop HDCP keepout window generation */
605 hdmi_msk_reg(hdmi_dev, FC_INVIDCONF,
606 m_FC_HDCP_KEEPOUT, v_FC_HDCP_KEEPOUT(1));
607 if (hdmi_drv->edid.scdc_present == 1) {
608 if (tmdsclk > 340000000) {/* used for HDMI 2.0 TX */
609 mutex_lock(&hdmi_dev->ddc_lock);
610 rockchip_hdmiv2_scdc_init(hdmi_dev);
612 rockchip_hdmiv2_scdc_get_sink_version(hdmi_dev);
613 pr_info("sink scdc version is %d\n", sink_version);
614 sink_version = hdmi_drv->edid.hf_vsdb_version;
615 rockchip_hdmiv2_scdc_set_source_version(hdmi_dev,
617 if (hdmi_drv->edid.rr_capable == 1)
618 rockchip_hdmiv2_scdc_read_request(hdmi_dev, 1);
619 rockchip_hdmiv2_scrambling_enable(hdmi_dev, 1);
620 mutex_unlock(&hdmi_dev->ddc_lock);
622 mutex_lock(&hdmi_dev->ddc_lock);
623 rockchip_hdmiv2_scdc_init(hdmi_dev);
624 rockchip_hdmiv2_scrambling_enable(hdmi_dev, 0);
625 mutex_unlock(&hdmi_dev->ddc_lock);
629 hdmi_msk_reg(hdmi_dev, FC_INVIDCONF,
630 m_FC_VSYNC_POL | m_FC_HSYNC_POL | m_FC_DE_POL |
631 m_FC_HDMI_DVI | m_FC_INTERLACE_MODE,
632 v_FC_VSYNC_POL(vsync_pol) | v_FC_HSYNC_POL(hsync_pol) |
633 v_FC_DE_POL(de_pol) | v_FC_HDMI_DVI(vpara->sink_hdmi) |
634 v_FC_INTERLACE_MODE(mode->vmode));
635 if (mode->vmode == FB_VMODE_INTERLACED)
636 hdmi_msk_reg(hdmi_dev, FC_INVIDCONF,
637 m_FC_VBLANK, v_FC_VBLANK(1));
639 hdmi_msk_reg(hdmi_dev, FC_INVIDCONF,
640 m_FC_VBLANK, v_FC_VBLANK(0));
643 if (vpara->color_input == HDMI_COLOR_YCBCR420)
645 hdmi_writel(hdmi_dev, FC_INHACTIV1, v_FC_HACTIVE1(value >> 8));
646 hdmi_writel(hdmi_dev, FC_INHACTIV0, (value & 0xff));
649 hdmi_writel(hdmi_dev, FC_INVACTIV1, v_FC_VACTIVE1(value >> 8));
650 hdmi_writel(hdmi_dev, FC_INVACTIV0, (value & 0xff));
652 value = mode->hsync_len + mode->left_margin + mode->right_margin;
653 if (vpara->color_input == HDMI_COLOR_YCBCR420)
655 hdmi_writel(hdmi_dev, FC_INHBLANK1, v_FC_HBLANK1(value >> 8));
656 hdmi_writel(hdmi_dev, FC_INHBLANK0, (value & 0xff));
658 value = mode->vsync_len + mode->upper_margin + mode->lower_margin;
659 hdmi_writel(hdmi_dev, FC_INVBLANK, (value & 0xff));
661 value = mode->right_margin;
662 if (vpara->color_input == HDMI_COLOR_YCBCR420)
664 hdmi_writel(hdmi_dev, FC_HSYNCINDELAY1, v_FC_HSYNCINDEAY1(value >> 8));
665 hdmi_writel(hdmi_dev, FC_HSYNCINDELAY0, (value & 0xff));
667 value = mode->lower_margin;
668 hdmi_writel(hdmi_dev, FC_VSYNCINDELAY, (value & 0xff));
670 value = mode->hsync_len;
671 if (vpara->color_input == HDMI_COLOR_YCBCR420)
673 hdmi_writel(hdmi_dev, FC_HSYNCINWIDTH1, v_FC_HSYNCWIDTH1(value >> 8));
674 hdmi_writel(hdmi_dev, FC_HSYNCINWIDTH0, (value & 0xff));
676 value = mode->vsync_len;
677 hdmi_writel(hdmi_dev, FC_VSYNCINWIDTH, (value & 0xff));
679 /*Set the control period minimum duration
680 (min. of 12 pixel clock cycles, refer to HDMI 1.4b specification)*/
681 hdmi_writel(hdmi_dev, FC_CTRLDUR, 12);
682 hdmi_writel(hdmi_dev, FC_EXCTRLDUR, 32);
684 hdmi_writel(hdmi_dev, FC_EXCTRLSPAC,
685 (hdmi_dev->tmdsclk/1000) * 50 / (256 * 512));
688 /* spacing < 256^2 * config / tmdsClock, spacing <= 50ms
689 * worst case: tmdsClock == 25MHz => config <= 19
691 hdmi_writel(hdmi_dev, FC_EXCTRLSPAC, 1);
693 /*Set PreambleFilter*/
694 for (i = 0; i < 3; i++) {
695 value = (i + 1) * 11;
696 if (i == 0) /*channel 0*/
697 hdmi_writel(hdmi_dev, FC_CH0PREAM, value);
698 else if (i == 1) /*channel 1*/
699 hdmi_writel(hdmi_dev, FC_CH1PREAM, value & 0x3f);
700 else if (i == 2) /*channel 2*/
701 hdmi_writel(hdmi_dev, FC_CH2PREAM, value & 0x3f);
705 hdmi_writel(hdmi_dev, FC_PRCONF, v_FC_PR_FACTOR(timing->pixelrepeat));
710 static int rockchip_hdmiv2_video_packetizer(struct hdmi_dev *hdmi_dev,
711 struct hdmi_video *vpara)
713 unsigned char color_depth = 0;
714 unsigned char output_select = 0;
715 unsigned char remap_size = 0;
717 if (vpara->color_output == HDMI_COLOR_YCBCR422) {
718 switch (vpara->color_output_depth) {
720 remap_size = YCC422_16BIT;
723 remap_size = YCC422_20BIT;
726 remap_size = YCC422_24BIT;
729 remap_size = YCC422_16BIT;
733 output_select = OUT_FROM_YCC422_REMAP;
734 /*Config remap size for the different color Depth*/
735 hdmi_msk_reg(hdmi_dev, VP_REMAP,
736 m_YCC422_SIZE, v_YCC422_SIZE(remap_size));
738 switch (vpara->color_output_depth) {
740 color_depth = COLOR_DEPTH_30BIT;
741 output_select = OUT_FROM_PIXEL_PACKING;
744 color_depth = COLOR_DEPTH_36BIT;
745 output_select = OUT_FROM_PIXEL_PACKING;
748 color_depth = COLOR_DEPTH_48BIT;
749 output_select = OUT_FROM_PIXEL_PACKING;
753 color_depth = COLOR_DEPTH_24BIT_DEFAULT;
754 output_select = OUT_FROM_8BIT_BYPASS;
758 /*Config Color Depth*/
759 hdmi_msk_reg(hdmi_dev, VP_PR_CD,
760 m_COLOR_DEPTH, v_COLOR_DEPTH(color_depth));
763 /*Config pixel repettion*/
764 hdmi_msk_reg(hdmi_dev, VP_PR_CD, m_DESIRED_PR_FACTOR,
765 v_DESIRED_PR_FACTOR(hdmi_dev->pixelrepeat - 1));
766 if (hdmi_dev->pixelrepeat > 1)
767 hdmi_msk_reg(hdmi_dev, VP_CONF,
768 m_PIXEL_REPET_EN | m_BYPASS_SEL,
769 v_PIXEL_REPET_EN(1) | v_BYPASS_SEL(0));
771 hdmi_msk_reg(hdmi_dev, VP_CONF,
772 m_PIXEL_REPET_EN | m_BYPASS_SEL,
773 v_PIXEL_REPET_EN(0) | v_BYPASS_SEL(1));
775 /*config output select*/
776 if (output_select == OUT_FROM_PIXEL_PACKING) { /* pixel packing */
777 hdmi_msk_reg(hdmi_dev, VP_CONF,
778 m_BYPASS_EN | m_PIXEL_PACK_EN |
779 m_YCC422_EN | m_OUTPUT_SEL,
780 v_BYPASS_EN(0) | v_PIXEL_PACK_EN(1) |
781 v_YCC422_EN(0) | v_OUTPUT_SEL(output_select));
782 } else if (output_select == OUT_FROM_YCC422_REMAP) { /* YCC422 */
783 hdmi_msk_reg(hdmi_dev, VP_CONF,
784 m_BYPASS_EN | m_PIXEL_PACK_EN |
785 m_YCC422_EN | m_OUTPUT_SEL,
786 v_BYPASS_EN(0) | v_PIXEL_PACK_EN(0) |
787 v_YCC422_EN(1) | v_OUTPUT_SEL(output_select));
788 } else if (output_select == OUT_FROM_8BIT_BYPASS ||
789 output_select == 3) { /* bypass */
790 hdmi_msk_reg(hdmi_dev, VP_CONF,
791 m_BYPASS_EN | m_PIXEL_PACK_EN |
792 m_YCC422_EN | m_OUTPUT_SEL,
793 v_BYPASS_EN(1) | v_PIXEL_PACK_EN(0) |
794 v_YCC422_EN(0) | v_OUTPUT_SEL(output_select));
797 #if defined(HDMI_VIDEO_STUFFING)
798 /* YCC422 and pixel packing stuffing*/
799 hdmi_msk_reg(hdmi_dev, VP_STUFF, m_PR_STUFFING, v_PR_STUFFING(1));
800 hdmi_msk_reg(hdmi_dev, VP_STUFF,
801 m_YCC422_STUFFING | m_PP_STUFFING,
802 v_YCC422_STUFFING(1) | v_PP_STUFFING(1));
807 static int rockchip_hdmiv2_video_sampler(struct hdmi_dev *hdmi_dev,
808 struct hdmi_video *vpara)
812 if (vpara->color_input == HDMI_COLOR_YCBCR422) {
813 /* YCC422 mapping is discontinued - only map 1 is supported */
814 switch (vpara->color_output_depth) {
816 map_code = VIDEO_YCBCR422_8BIT;
819 map_code = VIDEO_YCBCR422_10BIT;
822 map_code = VIDEO_YCBCR422_12BIT;
825 map_code = VIDEO_YCBCR422_8BIT;
828 } else if (vpara->color_input == HDMI_COLOR_YCBCR420 ||
829 vpara->color_input == HDMI_COLOR_YCBCR444) {
830 switch (vpara->color_output_depth) {
832 map_code = VIDEO_YCBCR444_10BIT;
835 map_code = VIDEO_YCBCR444_12BIT;
838 map_code = VIDEO_YCBCR444_16BIT;
842 map_code = VIDEO_YCBCR444_8BIT;
846 switch (vpara->color_output_depth) {
848 map_code = VIDEO_RGB444_10BIT;
851 map_code = VIDEO_RGB444_12BIT;
854 map_code = VIDEO_RGB444_16BIT;
858 map_code = VIDEO_RGB444_8BIT;
861 map_code += (vpara->color_input == HDMI_COLOR_YCBCR444) ?
865 /* Set Data enable signal from external
866 and set video sample input mapping */
867 hdmi_msk_reg(hdmi_dev, TX_INVID0,
868 m_INTERNAL_DE_GEN | m_VIDEO_MAPPING,
869 v_INTERNAL_DE_GEN(0) | v_VIDEO_MAPPING(map_code));
871 #if defined(HDMI_VIDEO_STUFFING)
872 hdmi_writel(hdmi_dev, TX_GYDATA0, 0x00);
873 hdmi_writel(hdmi_dev, TX_GYDATA1, 0x00);
874 hdmi_msk_reg(hdmi_dev, TX_INSTUFFING,
875 m_GYDATA_STUFF, v_GYDATA_STUFF(1));
876 hdmi_writel(hdmi_dev, TX_RCRDATA0, 0x00);
877 hdmi_writel(hdmi_dev, TX_RCRDATA1, 0x00);
878 hdmi_msk_reg(hdmi_dev, TX_INSTUFFING,
879 m_RCRDATA_STUFF, v_RCRDATA_STUFF(1));
880 hdmi_writel(hdmi_dev, TX_BCBDATA0, 0x00);
881 hdmi_writel(hdmi_dev, TX_BCBDATA1, 0x00);
882 hdmi_msk_reg(hdmi_dev, TX_INSTUFFING,
883 m_BCBDATA_STUFF, v_BCBDATA_STUFF(1));
888 static const char coeff_csc[][24] = {
892 C1 | C2 | C3 | C4 | */
893 { /* CSC_RGB_0_255_TO_RGB_16_235_8BIT */
894 0x36, 0xf7, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, /*G*/
895 0x00, 0x00, 0x36, 0xf7, 0x00, 0x00, 0x00, 0x40, /*R*/
896 0x00, 0x00, 0x00, 0x00, 0x36, 0xf7, 0x00, 0x40, /*B*/
898 { /* CSC_RGB_0_255_TO_RGB_16_235_10BIT */
899 0x36, 0xf7, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, /*G*/
900 0x00, 0x00, 0x36, 0xf7, 0x00, 0x00, 0x01, 0x00, /*R*/
901 0x00, 0x00, 0x00, 0x00, 0x36, 0xf7, 0x01, 0x00, /*B*/
903 { /* CSC_RGB_0_255_TO_ITU601_16_235_8BIT */
904 0x20, 0x40, 0x10, 0x80, 0x06, 0x40, 0x00, 0x40, /*Y*/
905 0xe8, 0x80, 0x1c, 0x00, 0xfb, 0x80, 0x02, 0x00, /*Cr*/
906 0xed, 0x80, 0xf6, 0x80, 0x1c, 0x00, 0x02, 0x00, /*Cb*/
908 { /* CSC_RGB_0_255_TO_ITU601_16_235_10BIT */
909 0x20, 0x40, 0x10, 0x80, 0x06, 0x40, 0x01, 0x00, /*Y*/
910 0xe8, 0x80, 0x1c, 0x00, 0xfb, 0x80, 0x08, 0x00, /*Cr*/
911 0xed, 0x80, 0xf6, 0x80, 0x1c, 0x00, 0x08, 0x00, /*Cb*/
913 { /* CSC_RGB_0_255_TO_ITU709_16_235_8BIT */
914 0x27, 0x40, 0x0b, 0xc0, 0x04, 0x00, 0x00, 0x40, /*Y*/
915 0xe6, 0x80, 0x1c, 0x00, 0xfd, 0x80, 0x02, 0x00, /*Cr*/
916 0xea, 0x40, 0xf9, 0x80, 0x1c, 0x00, 0x02, 0x00, /*Cb*/
918 { /* CSC_RGB_0_255_TO_ITU709_16_235_10BIT */
919 0x27, 0x40, 0x0b, 0xc0, 0x04, 0x00, 0x01, 0x00, /*Y*/
920 0xe6, 0x80, 0x1c, 0x00, 0xfd, 0x80, 0x08, 0x00, /*Cr*/
921 0xea, 0x40, 0xf9, 0x80, 0x1c, 0x00, 0x08, 0x00, /*Cb*/
924 { /* CSC_ITU601_16_235_TO_RGB_0_255_8BIT */
925 0x20, 0x00, 0x69, 0x26, 0x74, 0xfd, 0x01, 0x0e, /*G*/
926 0x20, 0x00, 0x2c, 0xdd, 0x00, 0x00, 0x7e, 0x9a, /*R*/
927 0x20, 0x00, 0x00, 0x00, 0x38, 0xb4, 0x7e, 0x3b, /*B*/
929 { /* CSC_ITU709_16_235_TO_RGB_0_255_8BIT */
930 0x20, 0x00, 0x71, 0x06, 0x7a, 0x02, 0x00, 0xa7, /*G*/
931 0x20, 0x00, 0x32, 0x64, 0x00, 0x00, 0x7e, 0x6d, /*R*/
932 0x20, 0x00, 0x00, 0x00, 0x3b, 0x61, 0x7e, 0x25, /*B*/
936 static int rockchip_hdmiv2_video_csc(struct hdmi_dev *hdmi_dev,
937 struct hdmi_video *vpara)
939 int i, mode, interpolation, decimation, csc_scale;
940 const char *coeff = NULL;
941 unsigned char color_depth = 0;
943 if (vpara->color_input == vpara->color_output) {
944 hdmi_msk_reg(hdmi_dev, MC_FLOWCTRL,
945 m_FEED_THROUGH_OFF, v_FEED_THROUGH_OFF(0));
949 if (vpara->color_input == HDMI_COLOR_YCBCR422 &&
950 vpara->color_output != HDMI_COLOR_YCBCR422 &&
951 vpara->color_output != HDMI_COLOR_YCBCR420) {
953 hdmi_msk_reg(hdmi_dev, CSC_CFG,
954 m_CSC_INTPMODE, v_CSC_INTPMODE(interpolation));
957 if ((vpara->color_input == HDMI_COLOR_RGB_0_255 ||
958 vpara->color_input == HDMI_COLOR_YCBCR444) &&
959 vpara->color_output == HDMI_COLOR_YCBCR422) {
961 hdmi_msk_reg(hdmi_dev, CSC_CFG,
962 m_CSC_DECIMODE, v_CSC_DECIMODE(decimation));
965 switch (vpara->vic) {
966 case HDMI_720X480I_60HZ_4_3:
967 case HDMI_720X576I_50HZ_4_3:
968 case HDMI_720X480P_60HZ_4_3:
969 case HDMI_720X576P_50HZ_4_3:
970 case HDMI_720X480I_60HZ_16_9:
971 case HDMI_720X576I_50HZ_16_9:
972 case HDMI_720X480P_60HZ_16_9:
973 case HDMI_720X576P_50HZ_16_9:
974 if (vpara->color_input == HDMI_COLOR_RGB_0_255 &&
975 vpara->color_output >= HDMI_COLOR_YCBCR444) {
976 mode = CSC_RGB_0_255_TO_ITU601_16_235_8BIT;
978 } else if (vpara->color_input >= HDMI_COLOR_YCBCR444 &&
979 vpara->color_output == HDMI_COLOR_RGB_0_255) {
980 mode = CSC_ITU601_16_235_TO_RGB_0_255_8BIT;
985 if (vpara->color_input == HDMI_COLOR_RGB_0_255 &&
986 vpara->color_output >= HDMI_COLOR_YCBCR444) {
987 mode = CSC_RGB_0_255_TO_ITU709_16_235_8BIT;
989 } else if (vpara->color_input >= HDMI_COLOR_YCBCR444 &&
990 vpara->color_output == HDMI_COLOR_RGB_0_255) {
991 mode = CSC_ITU709_16_235_TO_RGB_0_255_8BIT;
997 if ((vpara->color_input == HDMI_COLOR_RGB_0_255) &&
998 (vpara->color_output == HDMI_COLOR_RGB_16_235)) {
999 mode = CSC_RGB_0_255_TO_RGB_16_235_8BIT;
1003 switch (vpara->color_output_depth) {
1005 color_depth = COLOR_DEPTH_30BIT;
1009 color_depth = COLOR_DEPTH_36BIT;
1013 color_depth = COLOR_DEPTH_48BIT;
1018 color_depth = COLOR_DEPTH_24BIT;
1022 coeff = coeff_csc[mode];
1023 for (i = 0; i < 24; i++)
1024 hdmi_writel(hdmi_dev, CSC_COEF_A1_MSB + i, coeff[i]);
1026 hdmi_msk_reg(hdmi_dev, CSC_SCALE,
1027 m_CSC_SCALE, v_CSC_SCALE(csc_scale));
1028 /*config CSC_COLOR_DEPTH*/
1029 hdmi_msk_reg(hdmi_dev, CSC_SCALE,
1030 m_CSC_COLOR_DEPTH, v_CSC_COLOR_DEPTH(color_depth));
1033 hdmi_msk_reg(hdmi_dev, MC_FLOWCTRL,
1034 m_FEED_THROUGH_OFF, v_FEED_THROUGH_OFF(1));
1040 static int hdmi_dev_detect_hotplug(struct hdmi *hdmi)
1042 struct hdmi_dev *hdmi_dev = hdmi->property->priv;
1043 u32 value = hdmi_readl(hdmi_dev, PHY_STAT0);
1045 HDMIDBG("[%s] reg%x value %02x\n", __func__, PHY_STAT0, value);
1047 if (value & m_PHY_HPD)
1048 return HDMI_HPD_ACTIVED;
1050 return HDMI_HPD_REMOVED;
1053 static int hdmi_dev_read_edid(struct hdmi *hdmi, int block, unsigned char *buff)
1055 struct hdmi_dev *hdmi_dev = hdmi->property->priv;
1056 int i = 0, n = 0, index = 0, ret = -1, trytime = 5;
1057 int offset = (block % 2) * 0x80;
1060 HDMIDBG("[%s] block %d\n", __func__, block);
1062 rockchip_hdmiv2_i2cm_reset(hdmi_dev);
1064 /* Set DDC I2C CLK which devided from DDC_CLK to 100KHz. */
1065 rockchip_hdmiv2_i2cm_clk_init(hdmi_dev);
1067 /* Enable I2C interrupt for reading edid */
1068 rockchip_hdmiv2_i2cm_mask_int(hdmi_dev, 0);
1070 hdmi_writel(hdmi_dev, I2CM_SLAVE, DDC_I2C_EDID_ADDR);
1071 hdmi_writel(hdmi_dev, I2CM_SEGADDR, DDC_I2C_SEG_ADDR);
1072 hdmi_writel(hdmi_dev, I2CM_SEGPTR, block / 2);
1073 for (n = 0; n < HDMI_EDID_BLOCK_SIZE / 8; n++) {
1074 for (trytime = 0; trytime < 5; trytime++) {
1075 hdmi_writel(hdmi_dev, I2CM_ADDRESS, offset + 8 * n);
1076 /* enable extend sequential read operation */
1078 hdmi_msk_reg(hdmi_dev, I2CM_OPERATION,
1079 m_I2CM_RD8, v_I2CM_RD8(1));
1081 hdmi_msk_reg(hdmi_dev, I2CM_OPERATION,
1087 usleep_range(900, 1000);
1088 interrupt = hdmi_readl(hdmi_dev,
1091 hdmi_writel(hdmi_dev,
1092 IH_I2CM_STAT0, interrupt);
1095 (m_SCDC_READREQ | m_I2CM_DONE |
1100 if (interrupt & m_I2CM_DONE) {
1101 for (index = 0; index < 8; index++)
1102 buff[8 * n + index] =
1103 hdmi_readl(hdmi_dev,
1107 if (n == HDMI_EDID_BLOCK_SIZE / 8 - 1) {
1112 } else if ((interrupt & m_I2CM_ERROR) || (i == -1)) {
1114 "[%s] edid read %d error\n",
1115 __func__, offset + 8 * n);
1120 "[%s] edid read error\n", __func__);
1126 /* Disable I2C interrupt */
1127 rockchip_hdmiv2_i2cm_mask_int(hdmi_dev, 1);
1131 for (index = 0; index < 128; index++) {
1132 printk("0x%02x ,", buff[index]);
1133 if ((index + 1) % 16 == 0)
1141 static void hdmi_dev_config_avi(struct hdmi_dev *hdmi_dev,
1142 struct hdmi_video *vpara)
1144 unsigned char colorimetry, ext_colorimetry, aspect_ratio, y1y0;
1145 unsigned char rgb_quan_range = AVI_QUANTIZATION_RANGE_DEFAULT;
1147 /* Set AVI infoFrame Data byte1 */
1148 if (vpara->color_output == HDMI_COLOR_YCBCR444)
1149 y1y0 = AVI_COLOR_MODE_YCBCR444;
1150 else if (vpara->color_output == HDMI_COLOR_YCBCR422)
1151 y1y0 = AVI_COLOR_MODE_YCBCR422;
1152 else if (vpara->color_output == HDMI_COLOR_YCBCR420)
1153 y1y0 = AVI_COLOR_MODE_YCBCR420;
1155 y1y0 = AVI_COLOR_MODE_RGB;
1157 hdmi_msk_reg(hdmi_dev, FC_AVICONF0,
1158 m_FC_ACTIV_FORMAT | m_FC_RGC_YCC,
1159 v_FC_RGC_YCC(y1y0) | v_FC_ACTIV_FORMAT(1));
1161 /* Set AVI infoFrame Data byte2 */
1162 switch (vpara->vic) {
1163 case HDMI_720X480I_60HZ_4_3:
1164 case HDMI_720X576I_50HZ_4_3:
1165 case HDMI_720X480P_60HZ_4_3:
1166 case HDMI_720X576P_50HZ_4_3:
1167 aspect_ratio = AVI_CODED_FRAME_ASPECT_4_3;
1168 colorimetry = AVI_COLORIMETRY_SMPTE_170M;
1170 case HDMI_720X480I_60HZ_16_9:
1171 case HDMI_720X576I_50HZ_16_9:
1172 case HDMI_720X480P_60HZ_16_9:
1173 case HDMI_720X576P_50HZ_16_9:
1174 aspect_ratio = AVI_CODED_FRAME_ASPECT_16_9;
1175 colorimetry = AVI_COLORIMETRY_SMPTE_170M;
1178 aspect_ratio = AVI_CODED_FRAME_ASPECT_16_9;
1179 colorimetry = AVI_COLORIMETRY_ITU709;
1182 if (vpara->color_output_depth > 8) {
1183 colorimetry = AVI_COLORIMETRY_EXTENDED;
1184 ext_colorimetry = 6;
1185 } else if (vpara->color_output == HDMI_COLOR_RGB_16_235 ||
1186 vpara->color_output == HDMI_COLOR_RGB_0_255) {
1187 colorimetry = AVI_COLORIMETRY_NO_DATA;
1188 ext_colorimetry = 0;
1191 hdmi_writel(hdmi_dev, FC_AVICONF1,
1192 v_FC_COLORIMETRY(colorimetry) |
1193 v_FC_PIC_ASPEC_RATIO(aspect_ratio) |
1194 v_FC_ACT_ASPEC_RATIO(ACTIVE_ASPECT_RATE_DEFAULT));
1196 /* Set AVI infoFrame Data byte3 */
1197 hdmi_msk_reg(hdmi_dev, FC_AVICONF2,
1198 m_FC_EXT_COLORIMETRY | m_FC_QUAN_RANGE,
1199 v_FC_EXT_COLORIMETRY(ext_colorimetry) |
1200 v_FC_QUAN_RANGE(rgb_quan_range));
1202 /* Set AVI infoFrame Data byte4 */
1203 if ((vpara->vic > 92 && vpara->vic < 96) || (vpara->vic == 98))
1204 hdmi_writel(hdmi_dev, FC_AVIVID, 0);
1206 hdmi_writel(hdmi_dev, FC_AVIVID, vpara->vic & 0xff);
1207 /* Set AVI infoFrame Data byte5 */
1208 hdmi_msk_reg(hdmi_dev, FC_AVICONF3, m_FC_YQ | m_FC_CN,
1209 v_FC_YQ(YQ_LIMITED_RANGE) | v_FC_CN(CN_GRAPHICS));
1212 static int hdmi_dev_config_vsi(struct hdmi *hdmi,
1213 unsigned char vic_3d, unsigned char format)
1215 int i = 0, id = 0x000c03;
1216 unsigned char data[3] = {0};
1218 struct hdmi_dev *hdmi_dev = hdmi->property->priv;
1220 HDMIDBG("[%s] vic %d format %d.\n", __func__, vic_3d, format);
1222 hdmi_msk_reg(hdmi_dev, FC_DATAUTO0, m_VSD_AUTO, v_VSD_AUTO(0));
1223 hdmi_writel(hdmi_dev, FC_VSDIEEEID2, id & 0xff);
1224 hdmi_writel(hdmi_dev, FC_VSDIEEEID1, (id >> 8) & 0xff);
1225 hdmi_writel(hdmi_dev, FC_VSDIEEEID0, (id >> 16) & 0xff);
1227 data[0] = format << 5; /* PB4 --HDMI_Video_Format */
1229 case HDMI_VIDEO_FORMAT_4KX2K:
1230 data[1] = vic_3d; /* PB5--HDMI_VIC */
1233 case HDMI_VIDEO_FORMAT_3D:
1234 data[1] = vic_3d << 4; /* PB5--3D_Structure field */
1235 data[2] = 0; /* PB6--3D_Ext_Data field */
1243 for (i = 0; i < 3; i++)
1244 hdmi_writel(hdmi_dev, FC_VSDPAYLOAD0 + i, data[i]);
1245 hdmi_writel(hdmi_dev, FC_VSDSIZE, 0x6);
1246 /* if (auto_send) { */
1247 hdmi_writel(hdmi_dev, FC_DATAUTO1, 0);
1248 hdmi_writel(hdmi_dev, FC_DATAUTO2, 0x11);
1249 hdmi_msk_reg(hdmi_dev, FC_DATAUTO0, m_VSD_AUTO, v_VSD_AUTO(1));
1252 hdmi_msk_reg(hdmi_dev, FC_DATMAN, m_VSD_MAN, v_VSD_MAN(1));
1258 static int hdmi_dev_config_video(struct hdmi *hdmi, struct hdmi_video *vpara)
1260 struct hdmi_dev *hdmi_dev = hdmi->property->priv;
1262 HDMIDBG("%s vic %d 3dformat %d color mode %d color depth %d\n",
1263 __func__, vpara->vic, vpara->format_3d,
1264 vpara->color_output, vpara->color_output_depth);
1266 if (hdmi_dev->soctype == HDMI_SOC_RK3288)
1267 vpara->color_input = HDMI_COLOR_RGB_0_255;
1270 /* befor configure video, we power off phy */
1271 hdmi_msk_reg(hdmi_dev, PHY_CONF0,
1272 m_PDDQ_SIG | m_TXPWRON_SIG,
1273 v_PDDQ_SIG(1) | v_TXPWRON_SIG(0));
1275 /* force output blue */
1276 if (vpara->color_output == HDMI_COLOR_RGB_0_255) {
1277 hdmi_writel(hdmi_dev, FC_DBGTMDS2, 0x00); /*R*/
1278 hdmi_writel(hdmi_dev, FC_DBGTMDS1, 0x00); /*G*/
1279 hdmi_writel(hdmi_dev, FC_DBGTMDS0, 0x00); /*B*/
1280 } else if (vpara->color_output == HDMI_COLOR_RGB_16_235) {
1281 hdmi_writel(hdmi_dev, FC_DBGTMDS2, 0x10); /*R*/
1282 hdmi_writel(hdmi_dev, FC_DBGTMDS1, 0x10); /*G*/
1283 hdmi_writel(hdmi_dev, FC_DBGTMDS0, 0x10); /*B*/
1285 hdmi_writel(hdmi_dev, FC_DBGTMDS2, 0x80); /*R*/
1286 hdmi_writel(hdmi_dev, FC_DBGTMDS1, 0x10); /*G*/
1287 hdmi_writel(hdmi_dev, FC_DBGTMDS0, 0x80); /*B*/
1289 hdmi_msk_reg(hdmi_dev, FC_DBGFORCE,
1290 m_FC_FORCEVIDEO, v_FC_FORCEVIDEO(1));
1293 hdmi_writel(hdmi_dev, MC_CLKDIS, m_HDCPCLK_DISABLE);
1294 if (rockchip_hdmiv2_video_framecomposer(hdmi, vpara) < 0)
1297 if (rockchip_hdmiv2_video_packetizer(hdmi_dev, vpara) < 0)
1299 /* Color space convert */
1300 if (rockchip_hdmiv2_video_csc(hdmi_dev, vpara) < 0)
1302 if (rockchip_hdmiv2_video_sampler(hdmi_dev, vpara) < 0)
1305 if (vpara->sink_hdmi == OUTPUT_HDMI) {
1306 hdmi_dev_config_avi(hdmi_dev, vpara);
1307 if (vpara->format_3d != HDMI_3D_NONE) {
1308 hdmi_dev_config_vsi(hdmi,
1310 HDMI_VIDEO_FORMAT_3D);
1311 } else if ((vpara->vic > 92 && vpara->vic < 96) ||
1312 (vpara->vic == 98)) {
1313 vpara->vic = (vpara->vic == 98) ?
1314 4 : (96 - vpara->vic);
1315 hdmi_dev_config_vsi(hdmi,
1317 HDMI_VIDEO_FORMAT_4KX2K);
1319 hdmi_dev_config_vsi(hdmi,
1321 HDMI_VIDEO_FORMAT_NORMAL);
1323 dev_info(hdmi->dev, "[%s] sucess output HDMI.\n", __func__);
1325 dev_info(hdmi->dev, "[%s] sucess output DVI.\n", __func__);
1328 rockchip_hdmiv2_config_phy(hdmi_dev);
1332 static void hdmi_dev_config_aai(struct hdmi_dev *hdmi_dev,
1333 struct hdmi_audio *audio)
1335 /*Refer to CEA861-E Audio infoFrame*/
1336 /*Set both Audio Channel Count and Audio Coding
1337 Type Refer to Stream Head for HDMI*/
1338 hdmi_msk_reg(hdmi_dev, FC_AUDICONF0,
1339 m_FC_CHN_CNT | m_FC_CODING_TYEP,
1340 v_FC_CHN_CNT(audio->channel-1) | v_FC_CODING_TYEP(0));
1342 /*Set both Audio Sample Size and Sample Frequency
1343 Refer to Stream Head for HDMI*/
1344 hdmi_msk_reg(hdmi_dev, FC_AUDICONF1,
1345 m_FC_SAMPLE_SIZE | m_FC_SAMPLE_FREQ,
1346 v_FC_SAMPLE_SIZE(0) | v_FC_SAMPLE_FREQ(0));
1348 /*Set Channel Allocation*/
1349 hdmi_writel(hdmi_dev, FC_AUDICONF2, 0x00);
1351 /*Set LFEPBL¡¢DOWN-MIX INH and LSV*/
1352 hdmi_writel(hdmi_dev, FC_AUDICONF3, 0x00);
1355 static int hdmi_dev_config_audio(struct hdmi *hdmi, struct hdmi_audio *audio)
1357 struct hdmi_dev *hdmi_dev = hdmi->property->priv;
1358 int word_length = 0, channel = 0, mclk_fs;
1359 unsigned int N = 0, CTS = 0;
1362 HDMIDBG("%s\n", __func__);
1364 if (audio->channel < 3)
1365 channel = I2S_CHANNEL_1_2;
1366 else if (audio->channel < 5)
1367 channel = I2S_CHANNEL_3_4;
1368 else if (audio->channel < 7)
1369 channel = I2S_CHANNEL_5_6;
1371 channel = I2S_CHANNEL_7_8;
1373 switch (audio->rate) {
1374 case HDMI_AUDIO_FS_32000:
1377 if (hdmi_dev->tmdsclk >= 594000000)
1379 else if (hdmi_dev->tmdsclk >= 297000000)
1383 /*div a num to avoid the value is exceed 2^32(int)*/
1384 CTS = CALC_CTS(N, hdmi_dev->tmdsclk/1000, 32);
1386 case HDMI_AUDIO_FS_44100:
1389 if (hdmi_dev->tmdsclk >= 594000000)
1391 else if (hdmi_dev->tmdsclk >= 297000000)
1396 CTS = CALC_CTS(N, hdmi_dev->tmdsclk/100, 441);
1398 case HDMI_AUDIO_FS_48000:
1401 if (hdmi_dev->tmdsclk >= 594000000) /*FS_153.6*/
1403 else if (hdmi_dev->tmdsclk >= 297000000)
1408 CTS = CALC_CTS(N, hdmi_dev->tmdsclk/1000, 48);
1410 case HDMI_AUDIO_FS_88200:
1413 if (hdmi_dev->tmdsclk >= 594000000)
1415 else if (hdmi_dev->tmdsclk >= 297000000)
1420 CTS = CALC_CTS(N, hdmi_dev->tmdsclk/100, 882);
1422 case HDMI_AUDIO_FS_96000:
1425 if (hdmi_dev->tmdsclk >= 594000000) /*FS_153.6*/
1427 else if (hdmi_dev->tmdsclk >= 297000000)
1432 CTS = CALC_CTS(N, hdmi_dev->tmdsclk/1000, 96);
1434 case HDMI_AUDIO_FS_176400:
1437 if (hdmi_dev->tmdsclk >= 594000000)
1438 N = N_1764K_HIGHCLK;
1439 else if (hdmi_dev->tmdsclk >= 297000000)
1444 CTS = CALC_CTS(N, hdmi_dev->tmdsclk/100, 1764);
1446 case HDMI_AUDIO_FS_192000:
1449 if (hdmi_dev->tmdsclk >= 594000000) /*FS_153.6*/
1451 else if (hdmi_dev->tmdsclk >= 297000000)
1456 CTS = CALC_CTS(N, hdmi_dev->tmdsclk/1000, 192);
1459 dev_err(hdmi_dev->hdmi->dev,
1460 "[%s] not support such sample rate %d\n",
1461 __func__, audio->rate);
1465 switch (audio->word_length) {
1466 case HDMI_AUDIO_WORD_LENGTH_16bit:
1467 word_length = I2S_16BIT_SAMPLE;
1469 case HDMI_AUDIO_WORD_LENGTH_20bit:
1470 word_length = I2S_20BIT_SAMPLE;
1472 case HDMI_AUDIO_WORD_LENGTH_24bit:
1473 word_length = I2S_24BIT_SAMPLE;
1476 word_length = I2S_16BIT_SAMPLE;
1479 HDMIDBG("rate = %d, tmdsclk = %u, N = %d, CTS = %d\n",
1480 audio->rate, hdmi_dev->tmdsclk, N, CTS);
1481 /* more than 2 channels => layout 1 else layout 0 */
1482 hdmi_msk_reg(hdmi_dev, FC_AUDSCONF,
1484 v_AUD_PACK_LAYOUT((audio->channel > 2) ? 1 : 0));
1486 if (hdmi_dev->audiosrc == HDMI_AUDIO_SRC_SPDIF) {
1488 hdmi_msk_reg(hdmi_dev, AUD_CONF0,
1489 m_I2S_SEL, v_I2S_SEL(AUDIO_SPDIF_GPA));
1490 hdmi_msk_reg(hdmi_dev, AUD_SPDIF1,
1491 m_SET_NLPCM | m_SPDIF_WIDTH,
1492 v_SET_NLPCM(PCM_LINEAR) |
1493 v_SPDIF_WIDTH(word_length));
1494 /*Mask fifo empty and full int and reset fifo*/
1495 hdmi_msk_reg(hdmi_dev, AUD_SPDIFINT,
1496 m_FIFO_EMPTY_MASK | m_FIFO_FULL_MASK,
1497 v_FIFO_EMPTY_MASK(1) | v_FIFO_FULL_MASK(1));
1498 hdmi_msk_reg(hdmi_dev, AUD_SPDIF0,
1499 m_SW_SAUD_FIFO_RST, v_SW_SAUD_FIFO_RST(1));
1501 /*Mask fifo empty and full int and reset fifo*/
1502 hdmi_msk_reg(hdmi_dev, AUD_INT,
1503 m_FIFO_EMPTY_MASK | m_FIFO_FULL_MASK,
1504 v_FIFO_EMPTY_MASK(1) | v_FIFO_FULL_MASK(1));
1505 hdmi_msk_reg(hdmi_dev, AUD_CONF0,
1506 m_SW_AUD_FIFO_RST, v_SW_AUD_FIFO_RST(1));
1507 hdmi_writel(hdmi_dev, MC_SWRSTZREQ, 0xF7);
1508 hdmi_writel(hdmi_dev, AUD_CONF2, 0x0);
1509 usleep_range(90, 100);
1510 if (I2S_CHANNEL_7_8 == channel) {
1511 HDMIDBG("hbr mode.\n");
1512 hdmi_writel(hdmi_dev, AUD_CONF2, 0x1);
1513 word_length = I2S_24BIT_SAMPLE;
1514 } else if ((HDMI_AUDIO_FS_48000 == audio->rate)
1515 || (HDMI_AUDIO_FS_192000 == audio->rate)) {
1516 HDMIDBG("nlpcm mode.\n");
1517 hdmi_writel(hdmi_dev, AUD_CONF2, 0x2);
1518 word_length = I2S_24BIT_SAMPLE;
1520 hdmi_writel(hdmi_dev, AUD_CONF2, 0x0);
1522 hdmi_msk_reg(hdmi_dev, AUD_CONF0,
1523 m_I2S_SEL | m_I2S_IN_EN,
1524 v_I2S_SEL(AUDIO_I2S) | v_I2S_IN_EN(channel));
1525 hdmi_writel(hdmi_dev, AUD_CONF1,
1526 v_I2S_MODE(I2S_STANDARD_MODE) |
1527 v_I2S_WIDTH(word_length));
1530 hdmi_msk_reg(hdmi_dev, AUD_INPUTCLKFS,
1531 m_LFS_FACTOR, v_LFS_FACTOR(mclk_fs));
1534 hdmi_msk_reg(hdmi_dev, AUD_N3, m_NCTS_ATOMIC_WR, v_NCTS_ATOMIC_WR(1));
1535 /*Set CTS by manual*/
1536 hdmi_msk_reg(hdmi_dev, AUD_CTS3,
1537 m_N_SHIFT | m_CTS_MANUAL | m_AUD_CTS3,
1538 v_N_SHIFT(N_SHIFT_1) |
1540 v_AUD_CTS3(CTS >> 16));
1541 hdmi_writel(hdmi_dev, AUD_CTS2, (CTS >> 8) & 0xff);
1542 hdmi_writel(hdmi_dev, AUD_CTS1, CTS & 0xff);
1544 hdmi_msk_reg(hdmi_dev, AUD_N3, m_AUD_N3, v_AUD_N3(N >> 16));
1545 hdmi_writel(hdmi_dev, AUD_N2, (N >> 8) & 0xff);
1546 hdmi_writel(hdmi_dev, AUD_N1, N & 0xff);
1548 /* set channel status register */
1549 hdmi_msk_reg(hdmi_dev, FC_AUDSCHNLS7,
1550 m_AUDIO_SAMPLE_RATE, v_AUDIO_SAMPLE_RATE(rate));
1551 hdmi_writel(hdmi_dev, FC_AUDSCHNLS8, ((~rate) << 4) | 0x2);
1553 hdmi_dev_config_aai(hdmi_dev, audio);
1558 static int hdmi_dev_control_output(struct hdmi *hdmi, int enable)
1560 struct hdmi_dev *hdmi_dev = hdmi->property->priv;
1562 HDMIDBG("[%s] %d\n", __func__, enable);
1564 if (enable == HDMI_AV_UNMUTE) {
1565 hdmi_writel(hdmi_dev, FC_DBGFORCE, 0x00);
1566 hdmi_msk_reg(hdmi_dev, FC_GCP,
1567 m_FC_SET_AVMUTE | m_FC_CLR_AVMUTE,
1568 v_FC_SET_AVMUTE(0) | v_FC_CLR_AVMUTE(1));
1570 if (enable & HDMI_VIDEO_MUTE) {
1571 hdmi_msk_reg(hdmi_dev, FC_DBGFORCE,
1572 m_FC_FORCEVIDEO, v_FC_FORCEVIDEO(1));
1573 hdmi_msk_reg(hdmi_dev, FC_GCP,
1574 m_FC_SET_AVMUTE | m_FC_CLR_AVMUTE,
1575 v_FC_SET_AVMUTE(1) | v_FC_CLR_AVMUTE(0));
1577 /* if (enable & HDMI_AUDIO_MUTE) {
1578 hdmi_msk_reg(hdmi_dev, FC_AUDSCONF,
1580 v_AUD_PACK_SAMPFIT(0x0F));
1582 */ if (enable == (HDMI_VIDEO_MUTE | HDMI_AUDIO_MUTE)) {
1584 rockchip_hdmiv2_powerdown(hdmi_dev);
1585 hdmi_dev->tmdsclk = 0;
1587 hdmi_msk_reg(hdmi_dev, PHY_CONF0,
1588 m_PDDQ_SIG | m_TXPWRON_SIG,
1589 v_PDDQ_SIG(1) | v_TXPWRON_SIG(0));
1590 hdmi_writel(hdmi_dev, MC_CLKDIS, 0x7f);
1596 static int hdmi_dev_insert(struct hdmi *hdmi)
1598 struct hdmi_dev *hdmi_dev = hdmi->property->priv;
1600 HDMIDBG("%s\n", __func__);
1601 hdmi_writel(hdmi_dev, MC_CLKDIS, m_HDCPCLK_DISABLE);
1602 return HDMI_ERROR_SUCESS;
1605 static int hdmi_dev_remove(struct hdmi *hdmi)
1607 struct hdmi_dev *hdmi_dev = hdmi->property->priv;
1609 HDMIDBG("%s\n", __func__);
1610 rockchip_hdmiv2_powerdown(hdmi_dev);
1611 hdmi_dev->tmdsclk = 0;
1612 return HDMI_ERROR_SUCESS;
1615 static int hdmi_dev_enable(struct hdmi *hdmi)
1617 struct hdmi_dev *hdmi_dev = hdmi->property->priv;
1619 HDMIDBG("%s\n", __func__);
1620 if (!hdmi_dev->enable) {
1621 hdmi_writel(hdmi_dev, IH_MUTE, 0x00);
1622 hdmi_dev->enable = 1;
1624 hdmi_submit_work(hdmi, HDMI_HPD_CHANGE, 10, NULL);
1628 static int hdmi_dev_disable(struct hdmi *hdmi)
1630 struct hdmi_dev *hdmi_dev = hdmi->property->priv;
1632 HDMIDBG("%s\n", __func__);
1633 if (hdmi_dev->enable) {
1634 hdmi_dev->enable = 0;
1635 hdmi_writel(hdmi_dev, IH_MUTE, 0x1);
1640 void rockchip_hdmiv2_dev_init_ops(struct hdmi_ops *ops)
1643 ops->enable = hdmi_dev_enable;
1644 ops->disable = hdmi_dev_disable;
1645 ops->getstatus = hdmi_dev_detect_hotplug;
1646 ops->insert = hdmi_dev_insert;
1647 ops->remove = hdmi_dev_remove;
1648 ops->getedid = hdmi_dev_read_edid;
1649 ops->setvideo = hdmi_dev_config_video;
1650 ops->setaudio = hdmi_dev_config_audio;
1651 ops->setmute = hdmi_dev_control_output;
1652 ops->setvsi = hdmi_dev_config_vsi;
1656 void rockchip_hdmiv2_dev_initial(struct hdmi_dev *hdmi_dev)
1658 struct hdmi *hdmi = hdmi_dev->hdmi;
1662 if (hdmi_dev->soctype == HDMI_SOC_RK3288) {
1663 writel_relaxed((1 << 9) | (1 << 25),
1664 RK_CRU_VIRT + 0x01d4);
1666 writel_relaxed((0 << 9) | (1 << 25),
1667 RK_CRU_VIRT + 0x01d4);
1668 } else if (hdmi_dev->soctype == HDMI_SOC_RK3368) {
1669 pr_info("reset hdmi\n");
1670 regmap_write(hdmi_dev->grf_base, 0x031c,
1671 (1 << 9) | (1 << 25));
1673 regmap_write(hdmi_dev->grf_base, 0x031c,
1674 (0 << 9) | (1 << 25));
1676 rockchip_hdmiv2_powerdown(hdmi_dev);
1678 /*mute unnecessary interrrupt, only enable hpd*/
1679 hdmi_writel(hdmi_dev, IH_MUTE_FC_STAT0, 0xff);
1680 hdmi_writel(hdmi_dev, IH_MUTE_FC_STAT1, 0xff);
1681 hdmi_writel(hdmi_dev, IH_MUTE_FC_STAT2, 0xff);
1682 hdmi_writel(hdmi_dev, IH_MUTE_AS_STAT0, 0xff);
1683 hdmi_writel(hdmi_dev, IH_MUTE_PHY_STAT0, 0xfe);
1684 hdmi_writel(hdmi_dev, IH_MUTE_I2CM_STAT0, 0xff);
1685 hdmi_writel(hdmi_dev, IH_MUTE_CEC_STAT0, 0xff);
1686 hdmi_writel(hdmi_dev, IH_MUTE_VP_STAT0, 0xff);
1687 hdmi_writel(hdmi_dev, IH_MUTE_I2CMPHY_STAT0, 0xff);
1688 hdmi_writel(hdmi_dev, IH_MUTE_AHBDMAAUD_STAT0, 0xff);
1690 /* disable hdcp interrup */
1691 hdmi_writel(hdmi_dev, A_APIINTMSK, 0xff);
1692 hdmi_writel(hdmi_dev, PHY_MASK, 0xf1);
1694 if (hdmi->property->feature & SUPPORT_CEC)
1695 rockchip_hdmiv2_cec_init(hdmi);
1696 if (hdmi->property->feature & SUPPORT_HDCP)
1697 rockchip_hdmiv2_hdcp_init(hdmi);
1700 irqreturn_t rockchip_hdmiv2_dev_irq(int irq, void *priv)
1702 struct hdmi_dev *hdmi_dev = priv;
1703 struct hdmi *hdmi = hdmi_dev->hdmi;
1704 char phy_pol = hdmi_readl(hdmi_dev, PHY_POL0);
1705 char phy_status = hdmi_readl(hdmi_dev, PHY_STAT0);
1706 char phy_int0 = hdmi_readl(hdmi_dev, PHY_INI0);
1708 char fc_stat0 = hdmi_readl(hdmi_dev, IH_FC_STAT0);
1709 char fc_stat1 = hdmi_readl(hdmi_dev, IH_FC_STAT1);
1710 char fc_stat2 = hdmi_readl(hdmi_dev, IH_FC_STAT2);
1711 char aud_int = hdmi_readl(hdmi_dev, IH_AS_SATA0);
1712 char phy_int = hdmi_readl(hdmi_dev, IH_PHY_STAT0);
1713 char vp_stat0 = hdmi_readl(hdmi_dev, IH_VP_STAT0);
1714 char cec_int = hdmi_readl(hdmi_dev, IH_CEC_STAT0);
1715 char hdcp_int = hdmi_readl(hdmi_dev, A_APIINTSTAT);
1716 char hdcp2_int = hdmi_readl(hdmi_dev, HDCP2REG_STAT);
1719 hdmi_writel(hdmi_dev, IH_FC_STAT0, fc_stat0);
1720 hdmi_writel(hdmi_dev, IH_FC_STAT1, fc_stat1);
1721 hdmi_writel(hdmi_dev, IH_FC_STAT2, fc_stat2);
1722 hdmi_writel(hdmi_dev, IH_VP_STAT0, vp_stat0);
1724 if (phy_int0 || phy_int) {
1725 phy_pol = (phy_int0 & (~phy_status)) | ((~phy_int0) & phy_pol);
1726 hdmi_writel(hdmi_dev, PHY_POL0, phy_pol);
1727 hdmi_writel(hdmi_dev, IH_PHY_STAT0, phy_int);
1728 if ((phy_int & m_HPD) || ((phy_int & 0x3c) == 0x3c))
1729 hdmi_submit_work(hdmi, HDMI_HPD_CHANGE, 20, NULL);
1734 hdmi_writel(hdmi_dev, IH_AS_SATA0, aud_int);
1735 hdmi_msk_reg(hdmi_dev, AUD_CONF0,
1736 m_SW_AUD_FIFO_RST, v_SW_AUD_FIFO_RST(1));
1737 hdmi_writel(hdmi_dev, MC_SWRSTZREQ, 0xF7);
1741 hdmi_writel(hdmi_dev, IH_CEC_STAT0, cec_int);
1742 rockchip_hdmiv2_cec_isr(hdmi_dev, cec_int);
1746 hdmi_writel(hdmi_dev, A_APIINTCLR, hdcp_int);
1747 pr_info("hdcp_int is 0x%02x\n", hdcp_int);
1752 hdmi_writel(hdmi_dev, HDCP2REG_STAT, hdcp2_int);
1753 pr_info("hdcp2_int is 0x%02x\n", hdcp2_int);