1 #include <linux/delay.h>
2 #include <linux/interrupt.h>
3 #include <linux/rockchip/grf.h>
4 #include <linux/rockchip/iomap.h>
5 #include "rockchip_hdmiv2.h"
6 #include "rockchip_hdmiv2_hw.h"
8 static const struct phy_mpll_config_tab PHY_MPLL_TABLE[] = {
9 /*tmdsclk = (pixclk / ref_cntrl ) * (fbdiv2 * fbdiv1) / nctrl / tmdsmhl
10 opmode: 0:HDMI1.4 1:HDMI2.0
12 /* |pixclock| tmdsclock|pixrepet|colordepth|prepdiv|tmdsmhl|opmode|
13 fbdiv2|fbdiv1|ref_cntrl|nctrl|propctrl|intctrl|gmpctrl| */
14 {27000000, 27000000, 0, 8, 0, 0, 0,
16 {27000000, 33750000, 0, 10, 1, 0, 0,
18 {27000000, 40500000, 0, 12, 2, 0, 0,
20 {27000000, 54000000, 0, 16, 3, 0, 0,
22 /* {74250000, 74250000, 0, 8, 0, 0, 0,
23 1, 3, 0, 2, 5, 0, 1}, */
24 {74250000, 74250000, 0, 8, 0, 0, 0,
26 {74250000, 92812500, 0, 10, 1, 0, 0,
28 {74250000, 111375000, 0, 12, 2, 0, 0,
30 {74250000, 148500000, 0, 16, 3, 0, 0,
32 {148500000, 74250000, 0, 8, 0, 0, 0,
34 {148500000, 148500000, 0, 8, 0, 0, 0,
36 {148500000, 185625000, 0, 10, 1, 0, 0,
38 {148500000, 222750000, 0, 12, 2, 0, 0,
40 {148500000, 297000000, 0, 16, 3, 0, 0,
42 {297000000, 148500000, 0, 8, 0, 0, 0,
44 {297000000, 297000000, 0, 8, 0, 0, 0,
46 {297000000, 371250000, 0, 10, 1, 3, 1,
48 {297000000, 445500000, 0, 12, 2, 3, 1,
50 {297000000, 594000000, 0, 16, 3, 3, 1,
52 /* {594000000, 297000000, 0, 8, 0, 0, 0,
53 1, 3, 3, 1, 0, 0, 3},*/
54 {594000000, 297000000, 0, 8, 0, 0, 0,
56 {594000000, 371250000, 0, 10, 1, 3, 1,
58 {594000000, 445500000, 0, 12, 2, 3, 1,
60 {594000000, 594000000, 0, 16, 3, 3, 1,
62 {594000000, 594000000, 0, 8, 0, 3, 1,
65 /* ddc i2c master reset */
66 static void rockchip_hdmiv2_i2cm_reset(struct hdmi_dev *hdmi_dev)
68 hdmi_msk_reg(hdmi_dev, I2CM_SOFTRSTZ,
69 m_I2CM_SOFTRST, v_I2CM_SOFTRST(0));
70 usleep_range(90, 100);
73 /*set read/write offset,set read/write mode*/
74 static void rockchip_hdmiv2_i2cm_write_request(struct hdmi_dev *hdmi_dev,
77 hdmi_writel(hdmi_dev, I2CM_ADDRESS, offset);
78 hdmi_writel(hdmi_dev, I2CM_DATAO, data);
79 hdmi_msk_reg(hdmi_dev, I2CM_OPERATION, m_I2CM_WR, v_I2CM_WR(1));
82 static void rockchip_hdmiv2_i2cm_read_request(struct hdmi_dev *hdmi_dev,
85 hdmi_writel(hdmi_dev, I2CM_ADDRESS, offset);
86 hdmi_msk_reg(hdmi_dev, I2CM_OPERATION, m_I2CM_RD, v_I2CM_RD(1));
89 static void rockchip_hdmiv2_i2cm_write_data(struct hdmi_dev *hdmi_dev,
96 while (trytime-- > 0) {
97 rockchip_hdmiv2_i2cm_write_request(hdmi_dev, offset, data);
99 usleep_range(900, 1000);
100 interrupt = hdmi_readl(hdmi_dev, IH_I2CM_STAT0);
102 hdmi_writel(hdmi_dev,
103 IH_I2CM_STAT0, interrupt);
105 if (interrupt & (m_SCDC_READREQ |
106 m_I2CM_DONE | m_I2CM_ERROR))
110 if (interrupt & m_I2CM_DONE) {
111 dev_dbg(hdmi_dev->hdmi->dev,
112 "[%s] write offset %02x data %02x success\n",
113 __func__, offset, data);
115 } else if ((interrupt & m_I2CM_ERROR) || (i == -1)) {
116 dev_err(hdmi_dev->hdmi->dev,
117 "[%s] write data error\n", __func__);
118 rockchip_hdmiv2_i2cm_reset(hdmi_dev);
123 static int rockchip_hdmiv2_i2cm_read_data(struct hdmi_dev *hdmi_dev, u8 offset)
129 while (trytime-- > 0) {
130 rockchip_hdmiv2_i2cm_read_request(hdmi_dev, offset);
132 usleep_range(900, 1000);
133 interrupt = hdmi_readl(hdmi_dev, IH_I2CM_STAT0);
135 hdmi_writel(hdmi_dev, IH_I2CM_STAT0, interrupt);
137 if (interrupt & (m_SCDC_READREQ |
138 m_I2CM_DONE | m_I2CM_ERROR))
142 if (interrupt & m_I2CM_DONE) {
143 val = hdmi_readl(hdmi_dev, I2CM_DATAI);
145 } else if ((interrupt & m_I2CM_ERROR) || (i == -1)) {
146 pr_err("[%s] read data error\n", __func__);
147 rockchip_hdmiv2_i2cm_reset(hdmi_dev);
153 static void rockchip_hdmiv2_i2cm_mask_int(struct hdmi_dev *hdmi_dev, int mask)
156 hdmi_msk_reg(hdmi_dev, I2CM_INT,
157 m_I2CM_DONE_MASK, v_I2CM_DONE_MASK(0));
158 hdmi_msk_reg(hdmi_dev, I2CM_CTLINT,
159 m_I2CM_NACK_MASK | m_I2CM_ARB_MASK,
160 v_I2CM_NACK_MASK(0) | v_I2CM_ARB_MASK(0));
162 hdmi_msk_reg(hdmi_dev, I2CM_INT,
163 m_I2CM_DONE_MASK, v_I2CM_DONE_MASK(1));
164 hdmi_msk_reg(hdmi_dev, I2CM_CTLINT,
165 m_I2CM_NACK_MASK | m_I2CM_ARB_MASK,
166 v_I2CM_NACK_MASK(1) | v_I2CM_ARB_MASK(1));
170 #define I2C_DIV_FACTOR 100000
171 static u16 i2c_count(u16 sfrclock, u16 sclmintime)
173 unsigned long tmp_scl_period = 0;
175 if (((sfrclock * sclmintime) % I2C_DIV_FACTOR) != 0)
176 tmp_scl_period = (unsigned long)((sfrclock * sclmintime) +
177 (I2C_DIV_FACTOR - ((sfrclock * sclmintime) %
178 I2C_DIV_FACTOR))) / I2C_DIV_FACTOR;
180 tmp_scl_period = (unsigned long)(sfrclock * sclmintime) /
183 return (u16)(tmp_scl_period);
186 #define EDID_I2C_MIN_SS_SCL_HIGH_TIME 50000
187 #define EDID_I2C_MIN_SS_SCL_LOW_TIME 50000
189 static void rockchip_hdmiv2_i2cm_clk_init(struct hdmi_dev *hdmi_dev)
191 /* Set DDC I2C CLK which devided from DDC_CLK. */
192 hdmi_writel(hdmi_dev, I2CM_SS_SCL_HCNT_0_ADDR,
193 i2c_count(24000, EDID_I2C_MIN_SS_SCL_HIGH_TIME));
194 hdmi_writel(hdmi_dev, I2CM_SS_SCL_LCNT_0_ADDR,
195 i2c_count(24000, EDID_I2C_MIN_SS_SCL_LOW_TIME));
196 hdmi_msk_reg(hdmi_dev, I2CM_DIV, m_I2CM_FAST_STD_MODE,
197 v_I2CM_FAST_STD_MODE(STANDARD_MODE));
200 static int rockchip_hdmiv2_scdc_get_sink_version(struct hdmi_dev *hdmi_dev)
202 return rockchip_hdmiv2_i2cm_read_data(hdmi_dev, SCDC_SINK_VER);
205 static void rockchip_hdmiv2_scdc_set_source_version(struct hdmi_dev *hdmi_dev,
208 rockchip_hdmiv2_i2cm_write_data(hdmi_dev, version, SCDC_SOURCE_VER);
212 static void rockchip_hdmiv2_scdc_read_request(struct hdmi_dev *hdmi_dev,
215 hdmi_msk_reg(hdmi_dev, I2CM_SCDC_READ_UPDATE,
216 m_I2CM_READ_REQ_EN, v_I2CM_READ_REQ_EN(enable));
217 rockchip_hdmiv2_i2cm_write_data(hdmi_dev, enable, SCDC_CONFIG_0);
221 static void rockchip_hdmiv2_scdc_update_read(struct hdmi_dev *hdmi_dev)
223 hdmi_msk_reg(hdmi_dev, I2CM_SCDC_READ_UPDATE,
224 m_I2CM_READ_UPDATE, v_I2CM_READ_UPDATE(1));
228 static int rockchip_hdmiv2_scdc_get_scambling_status(struct hdmi_dev *hdmi_dev)
232 val = rockchip_hdmiv2_i2cm_read_data(hdmi_dev, SCDC_SCRAMBLER_STAT);
236 static void rockchip_hdmiv2_scdc_enable_polling(struct hdmi_dev *hdmi_dev,
239 rockchip_hdmiv2_scdc_read_request(hdmi_dev, enable);
240 hdmi_msk_reg(hdmi_dev, I2CM_SCDC_READ_UPDATE,
241 m_I2CM_UPRD_VSYNC_EN, v_I2CM_UPRD_VSYNC_EN(enable));
244 static int rockchip_hdmiv2_scdc_get_status_reg0(struct hdmi_dev *hdmi_dev)
246 rockchip_hdmiv2_scdc_read_request(hdmi_dev, 1);
247 rockchip_hdmiv2_scdc_update_read(hdmi_dev);
248 return hdmi_readl(hdmi_dev, I2CM_SCDC_UPDATE0);
251 static int rockchip_hdmiv2_scdc_get_status_reg1(struct hdmi_dev *hdmi_dev)
253 rockchip_hdmiv2_scdc_read_request(hdmi_dev, 1);
254 rockchip_hdmiv2_scdc_update_read(hdmi_dev);
255 return hdmi_readl(hdmi_dev, I2CM_SCDC_UPDATE1);
259 static void rockchip_hdmiv2_scdc_init(struct hdmi_dev *hdmi_dev)
261 rockchip_hdmiv2_i2cm_reset(hdmi_dev);
262 rockchip_hdmiv2_i2cm_mask_int(hdmi_dev, 1);
263 rockchip_hdmiv2_i2cm_clk_init(hdmi_dev);
264 /* set scdc i2c addr */
265 hdmi_writel(hdmi_dev, I2CM_SLAVE, DDC_I2C_SCDC_ADDR);
266 rockchip_hdmiv2_i2cm_mask_int(hdmi_dev, 0);/*enable interrupt*/
270 static int rockchip_hdmiv2_scrambling_enable(struct hdmi_dev *hdmi_dev,
273 HDMIDBG("%s enable %d\n", __func__, enable);
275 /* Write on Rx the bit Scrambling_Enable, register 0x20 */
276 rockchip_hdmiv2_i2cm_write_data(hdmi_dev, 1, SCDC_TMDS_CONFIG);
277 /* TMDS software reset request */
278 hdmi_msk_reg(hdmi_dev, MC_SWRSTZREQ,
279 m_TMDS_SWRST, v_TMDS_SWRST(0));
280 /* Enable/Disable Scrambling */
281 hdmi_msk_reg(hdmi_dev, FC_SCRAMBLER_CTRL,
282 m_FC_SCRAMBLE_EN, v_FC_SCRAMBLE_EN(1));
284 /* Enable/Disable Scrambling */
285 hdmi_msk_reg(hdmi_dev, FC_SCRAMBLER_CTRL,
286 m_FC_SCRAMBLE_EN, v_FC_SCRAMBLE_EN(0));
287 /* TMDS software reset request */
288 hdmi_msk_reg(hdmi_dev, MC_SWRSTZREQ,
289 m_TMDS_SWRST, v_TMDS_SWRST(0));
290 /* Write on Rx the bit Scrambling_Enable, register 0x20 */
291 rockchip_hdmiv2_i2cm_write_data(hdmi_dev, 0, SCDC_TMDS_CONFIG);
298 static const struct phy_mpll_config_tab *get_phy_mpll_tab(
299 unsigned int pixclock, unsigned int tmdsclk,
300 char pixrepet, char colordepth)
306 HDMIDBG("%s pixClock %u pixRepet %d colorDepth %d\n",
307 __func__, pixclock, pixrepet, colordepth);
308 for (i = 0; i < ARRAY_SIZE(PHY_MPLL_TABLE); i++) {
309 if ((PHY_MPLL_TABLE[i].pix_clock == pixclock) &&
310 (PHY_MPLL_TABLE[i].tmdsclock == tmdsclk) &&
311 (PHY_MPLL_TABLE[i].pix_repet == pixrepet) &&
312 (PHY_MPLL_TABLE[i].color_depth == colordepth))
313 return &PHY_MPLL_TABLE[i];
318 static void rockchip_hdmiv2_powerdown(struct hdmi_dev *hdmi_dev)
320 hdmi_msk_reg(hdmi_dev, PHY_CONF0,
321 m_PDDQ_SIG | m_TXPWRON_SIG | m_ENHPD_RXSENSE_SIG,
322 v_PDDQ_SIG(1) | v_TXPWRON_SIG(0) |
323 v_ENHPD_RXSENSE_SIG(1));
324 hdmi_writel(hdmi_dev, MC_CLKDIS, 0x7f);
327 int rockchip_hdmiv2_write_phy(struct hdmi_dev *hdmi_dev,
328 int reg_addr, int val)
330 int trytime = 2, i = 0, op_status = 0;
333 hdmi_writel(hdmi_dev, PHY_I2CM_ADDRESS, reg_addr);
334 hdmi_writel(hdmi_dev, PHY_I2CM_DATAO_1, (val >> 8) & 0xff);
335 hdmi_writel(hdmi_dev, PHY_I2CM_DATAO_0, val & 0xff);
336 hdmi_writel(hdmi_dev, PHY_I2CM_OPERATION, m_PHY_I2CM_WRITE);
340 usleep_range(900, 1000);
341 op_status = hdmi_readl(hdmi_dev, IH_I2CMPHY_STAT0);
343 hdmi_writel(hdmi_dev,
347 if (op_status & (m_I2CMPHY_DONE | m_I2CMPHY_ERR))
351 if (op_status & m_I2CMPHY_DONE)
354 dev_err(hdmi_dev->hdmi->dev,
355 "[%s] operation error,trytime=%d\n",
363 int rockchip_hdmiv2_read_phy(struct hdmi_dev *hdmi_dev,
366 int trytime = 2, i = 0, op_status = 0;
370 hdmi_writel(hdmi_dev, PHY_I2CM_ADDRESS, reg_addr);
371 hdmi_writel(hdmi_dev, PHY_I2CM_DATAI_1, 0x00);
372 hdmi_writel(hdmi_dev, PHY_I2CM_DATAI_0, 0x00);
373 hdmi_writel(hdmi_dev, PHY_I2CM_OPERATION, m_PHY_I2CM_READ);
377 usleep_range(900, 1000);
378 op_status = hdmi_readl(hdmi_dev, IH_I2CMPHY_STAT0);
380 hdmi_writel(hdmi_dev, IH_I2CMPHY_STAT0,
383 if (op_status & (m_I2CMPHY_DONE | m_I2CMPHY_ERR))
387 if (op_status & m_I2CMPHY_DONE) {
388 val = hdmi_readl(hdmi_dev, PHY_I2CM_DATAI_1);
389 val = (val & 0xff) << 8;
390 val += (hdmi_readl(hdmi_dev, PHY_I2CM_DATAI_0) & 0xff);
391 pr_debug("phy_reg0x%02x: 0x%04x",
395 pr_err("[%s] operation error,trytime=%d\n",
404 static int rockchip_hdmiv2_config_phy(struct hdmi_dev *hdmi_dev)
407 const struct phy_mpll_config_tab *phy_mpll = NULL;
409 hdmi_msk_reg(hdmi_dev, PHY_I2CM_DIV,
410 m_PHY_I2CM_FAST_STD, v_PHY_I2CM_FAST_STD(0));
412 /* hdmi_writel(hdmi_dev, PHY_CONF0, 0x1e); */
413 hdmi_msk_reg(hdmi_dev, PHY_CONF0,
414 m_PDDQ_SIG | m_TXPWRON_SIG | m_SVSRET_SIG,
415 v_PDDQ_SIG(1) | v_TXPWRON_SIG(0) | v_SVSRET_SIG(1));
417 if (hdmi_dev->tmdsclk_ratio_change &&
418 hdmi_dev->hdmi->edid.scdc_present == 1) {
419 mutex_lock(&hdmi_dev->ddc_lock);
420 rockchip_hdmiv2_scdc_init(hdmi_dev);
421 stat = rockchip_hdmiv2_i2cm_read_data(hdmi_dev,
423 if (hdmi_dev->tmdsclk > 340000000)
427 rockchip_hdmiv2_i2cm_write_data(hdmi_dev,
428 stat, SCDC_TMDS_CONFIG);
429 mutex_unlock(&hdmi_dev->ddc_lock);
432 hdmi_writel(hdmi_dev, MC_PHYRSTZ, v_PHY_RSTZ(1));
433 usleep_range(1000, 2000);
434 hdmi_writel(hdmi_dev, MC_PHYRSTZ, v_PHY_RSTZ(0));
436 /* Set slave address as PHY GEN2 address */
437 hdmi_writel(hdmi_dev, PHY_I2CM_SLAVE, PHY_GEN2_ADDR);
439 /* config the required PHY I2C register */
440 phy_mpll = get_phy_mpll_tab(hdmi_dev->pixelclk,
442 hdmi_dev->pixelrepeat - 1,
443 hdmi_dev->colordepth);
445 rockchip_hdmiv2_write_phy(hdmi_dev, PHYTX_OPMODE_PLLCFG,
446 v_PREP_DIV(phy_mpll->prep_div) |
448 phy_mpll->tmdsmhl_cntrl) |
449 v_OPMODE(phy_mpll->opmode) |
451 phy_mpll->fbdiv2_cntrl) |
453 phy_mpll->fbdiv1_cntrl) |
454 v_REF_CNTRL(phy_mpll->ref_cntrl) |
455 v_MPLL_N_CNTRL(phy_mpll->n_cntrl));
456 rockchip_hdmiv2_write_phy(hdmi_dev, PHYTX_PLLCURRCTRL,
458 phy_mpll->prop_cntrl) |
460 phy_mpll->int_cntrl));
461 rockchip_hdmiv2_write_phy(hdmi_dev, PHYTX_PLLGMPCTRL,
463 phy_mpll->gmp_cntrl));
465 rockchip_hdmiv2_write_phy(hdmi_dev, PHYTX_TERM_RESIS,
466 v_TX_TERM(R50_OHMS));
467 rockchip_hdmiv2_write_phy(hdmi_dev, PHYTX_CLKSYMCTRL,
468 v_OVERRIDE(1) | v_SLOPEBOOST(0) |
469 v_TX_SYMON(1) | v_TX_TRAON(0) |
470 v_TX_TRBON(0) | v_CLK_SYMON(1));
471 if (hdmi_dev->tmdsclk > 340000000)
472 rockchip_hdmiv2_write_phy(hdmi_dev, PHYTX_VLEVCTRL,
473 v_SUP_TXLVL(9) | v_SUP_CLKLVL(17));
474 else if (hdmi_dev->tmdsclk > 165000000)
475 rockchip_hdmiv2_write_phy(hdmi_dev, PHYTX_VLEVCTRL,
476 v_SUP_TXLVL(14) | v_SUP_CLKLVL(17));
478 rockchip_hdmiv2_write_phy(hdmi_dev, PHYTX_VLEVCTRL,
479 v_SUP_TXLVL(18) | v_SUP_CLKLVL(17));
481 rockchip_hdmiv2_write_phy(hdmi_dev, 0x05, 0x8000);
482 if (hdmi_dev->tmdsclk_ratio_change)
485 hdmi_writel(hdmi_dev, PHY_CONF0, 0x2e);
487 hdmi_msk_reg(hdmi_dev, PHY_CONF0,
488 m_PDDQ_SIG | m_TXPWRON_SIG | m_ENHPD_RXSENSE_SIG,
489 v_PDDQ_SIG(0) | v_TXPWRON_SIG(1) |
490 v_ENHPD_RXSENSE_SIG(1));
492 /* check if the PHY PLL is locked */
493 #define PHY_TIMEOUT 10000
494 while (i++ < PHY_TIMEOUT) {
496 stat = hdmi_readl(hdmi_dev, PHY_STAT0);
497 if (stat & m_PHY_LOCK)
499 usleep_range(1000, 2000);
502 if ((stat & m_PHY_LOCK) == 0) {
503 stat = hdmi_readl(hdmi_dev, MC_LOCKONCLOCK);
504 dev_err(hdmi_dev->hdmi->dev,
505 "PHY PLL not locked: PCLK_ON=%d,TMDSCLK_ON=%d\n",
506 (stat & m_PCLK_ON) >> 6, (stat & m_TMDSCLK_ON) >> 5);
513 static int rockchip_hdmiv2_video_framecomposer(struct hdmi *hdmi_drv,
514 struct hdmi_video *vpara)
516 struct hdmi_dev *hdmi_dev = hdmi_drv->property->priv;
517 int value, vsync_pol, hsync_pol, de_pol;
518 struct hdmi_video_timing *timing = NULL;
519 struct fb_videomode *mode = NULL;
520 u32 sink_version, tmdsclk;
522 vsync_pol = hdmi_drv->lcdc->cur_screen->pin_vsync;
523 hsync_pol = hdmi_drv->lcdc->cur_screen->pin_hsync;
524 de_pol = (hdmi_drv->lcdc->cur_screen->pin_den == 0) ? 1 : 0;
526 hdmi_msk_reg(hdmi_dev, A_VIDPOLCFG,
527 m_DATAEN_POL | m_VSYNC_POL | m_HSYNC_POL,
528 v_DATAEN_POL(de_pol) |
529 v_VSYNC_POL(vsync_pol) |
530 v_HSYNC_POL(hsync_pol));
532 timing = (struct hdmi_video_timing *)hdmi_vic2timing(vpara->vic);
533 if (timing == NULL) {
534 dev_err(hdmi_drv->dev,
535 "[%s] not found vic %d\n", __func__, vpara->vic);
538 mode = &(timing->mode);
539 if (vpara->color_input == HDMI_COLOR_YCBCR420)
540 tmdsclk = mode->pixclock / 2;
542 tmdsclk = mode->pixclock;
543 switch (vpara->color_output_depth) {
545 tmdsclk += tmdsclk / 4;
548 tmdsclk += tmdsclk / 2;
558 if (tmdsclk > 594000000) {
559 vpara->color_output_depth = 8;
560 tmdsclk = mode->pixclock;
562 pr_info("pixel clk is %u tmds clk is %u\n", mode->pixclock, tmdsclk);
563 if ((tmdsclk > 340000000 && hdmi_dev->tmdsclk < 340000000) ||
564 (tmdsclk < 340000000 && hdmi_dev->tmdsclk > 340000000))
565 hdmi_dev->tmdsclk_ratio_change = true;
567 hdmi_dev->tmdsclk_ratio_change = false;
569 hdmi_dev->tmdsclk = tmdsclk;
570 hdmi_dev->pixelclk = mode->pixclock;
571 hdmi_dev->pixelrepeat = timing->pixelrepeat;
572 hdmi_dev->colordepth = vpara->color_output_depth;
574 /* Video Register has already been set in uboot,
575 so we no need to set again */
580 /* Start/stop HDCP keepout window generation */
581 hdmi_msk_reg(hdmi_dev, FC_INVIDCONF,
582 m_FC_HDCP_KEEPOUT, v_FC_HDCP_KEEPOUT(1));
583 if (hdmi_drv->edid.scdc_present == 1) {
584 if (tmdsclk > 340000000) {/* used for HDMI 2.0 TX */
585 mutex_lock(&hdmi_dev->ddc_lock);
586 rockchip_hdmiv2_scdc_init(hdmi_dev);
588 rockchip_hdmiv2_scdc_get_sink_version(hdmi_dev);
589 pr_info("sink scdc version is %d\n", sink_version);
590 sink_version = hdmi_drv->edid.hf_vsdb_version;
591 rockchip_hdmiv2_scdc_set_source_version(hdmi_dev,
593 if (hdmi_drv->edid.rr_capable == 1)
594 rockchip_hdmiv2_scdc_read_request(hdmi_dev, 1);
595 rockchip_hdmiv2_scrambling_enable(hdmi_dev, 1);
596 mutex_unlock(&hdmi_dev->ddc_lock);
598 mutex_lock(&hdmi_dev->ddc_lock);
599 rockchip_hdmiv2_scdc_init(hdmi_dev);
600 rockchip_hdmiv2_scrambling_enable(hdmi_dev, 0);
601 mutex_unlock(&hdmi_dev->ddc_lock);
605 hdmi_msk_reg(hdmi_dev, FC_INVIDCONF,
606 m_FC_VSYNC_POL | m_FC_HSYNC_POL | m_FC_DE_POL |
607 m_FC_HDMI_DVI | m_FC_INTERLACE_MODE,
608 v_FC_VSYNC_POL(vsync_pol) | v_FC_HSYNC_POL(hsync_pol) |
609 v_FC_DE_POL(de_pol) | v_FC_HDMI_DVI(vpara->sink_hdmi) |
610 v_FC_INTERLACE_MODE(mode->vmode));
611 if (mode->vmode == FB_VMODE_INTERLACED)
612 hdmi_msk_reg(hdmi_dev, FC_INVIDCONF,
613 m_FC_VBLANK, v_FC_VBLANK(1));
615 hdmi_msk_reg(hdmi_dev, FC_INVIDCONF,
616 m_FC_VBLANK, v_FC_VBLANK(0));
619 if (vpara->color_input == HDMI_COLOR_YCBCR420)
621 hdmi_writel(hdmi_dev, FC_INHACTIV1, v_FC_HACTIVE1(value >> 8));
622 hdmi_writel(hdmi_dev, FC_INHACTIV0, (value & 0xff));
625 hdmi_writel(hdmi_dev, FC_INVACTIV1, v_FC_VACTIVE1(value >> 8));
626 hdmi_writel(hdmi_dev, FC_INVACTIV0, (value & 0xff));
628 value = mode->hsync_len + mode->left_margin + mode->right_margin;
629 if (vpara->color_input == HDMI_COLOR_YCBCR420)
631 hdmi_writel(hdmi_dev, FC_INHBLANK1, v_FC_HBLANK1(value >> 8));
632 hdmi_writel(hdmi_dev, FC_INHBLANK0, (value & 0xff));
634 value = mode->vsync_len + mode->upper_margin + mode->lower_margin;
635 hdmi_writel(hdmi_dev, FC_INVBLANK, (value & 0xff));
637 value = mode->right_margin;
638 if (vpara->color_input == HDMI_COLOR_YCBCR420)
640 hdmi_writel(hdmi_dev, FC_HSYNCINDELAY1, v_FC_HSYNCINDEAY1(value >> 8));
641 hdmi_writel(hdmi_dev, FC_HSYNCINDELAY0, (value & 0xff));
643 value = mode->lower_margin;
644 hdmi_writel(hdmi_dev, FC_VSYNCINDELAY, (value & 0xff));
646 value = mode->hsync_len;
647 if (vpara->color_input == HDMI_COLOR_YCBCR420)
649 hdmi_writel(hdmi_dev, FC_HSYNCINWIDTH1, v_FC_HSYNCWIDTH1(value >> 8));
650 hdmi_writel(hdmi_dev, FC_HSYNCINWIDTH0, (value & 0xff));
652 value = mode->vsync_len;
653 hdmi_writel(hdmi_dev, FC_VSYNCINWIDTH, (value & 0xff));
655 /*Set the control period minimum duration
656 (min. of 12 pixel clock cycles, refer to HDMI 1.4b specification)*/
657 hdmi_writel(hdmi_dev, FC_CTRLDUR, 12);
658 hdmi_writel(hdmi_dev, FC_EXCTRLDUR, 32);
660 /* spacing < 256^2 * config / tmdsClock, spacing <= 50ms
661 * worst case: tmdsClock == 25MHz => config <= 19
663 hdmi_writel(hdmi_dev, FC_EXCTRLSPAC,
664 (hdmi_dev->tmdsclk/1000) * 50 / (256 * 512));
667 /*Set PreambleFilter*/
668 for (i = 0; i < 3; i++) {
669 value = (i + 1) * 11;
670 if (i == 0) /*channel 0*/
671 hdmi_writel(hdmi_dev, FC_CH0PREAM, value);
672 else if (i == 1) /*channel 1*/
673 hdmi_writel(hdmi_dev, FC_CH1PREAM, value & 0x3f);
674 else if (i == 2) /*channel 2*/
675 hdmi_writel(hdmi_dev, FC_CH2PREAM, value & 0x3f);
679 hdmi_writel(hdmi_dev, FC_PRCONF, v_FC_PR_FACTOR(timing->pixelrepeat));
684 static int rockchip_hdmiv2_video_packetizer(struct hdmi_dev *hdmi_dev,
685 struct hdmi_video *vpara)
687 unsigned char color_depth = 0;
688 unsigned char output_select = 0;
689 unsigned char remap_size = 0;
691 if (vpara->color_output == HDMI_COLOR_YCBCR422) {
692 switch (vpara->color_output_depth) {
694 remap_size = YCC422_16BIT;
697 remap_size = YCC422_20BIT;
700 remap_size = YCC422_24BIT;
703 remap_size = YCC422_16BIT;
707 output_select = OUT_FROM_YCC422_REMAP;
708 /*Config remap size for the different color Depth*/
709 hdmi_msk_reg(hdmi_dev, VP_REMAP,
710 m_YCC422_SIZE, v_YCC422_SIZE(remap_size));
712 switch (vpara->color_output_depth) {
714 color_depth = COLOR_DEPTH_30BIT;
715 output_select = OUT_FROM_PIXEL_PACKING;
718 color_depth = COLOR_DEPTH_36BIT;
719 output_select = OUT_FROM_PIXEL_PACKING;
722 color_depth = COLOR_DEPTH_48BIT;
723 output_select = OUT_FROM_PIXEL_PACKING;
727 color_depth = COLOR_DEPTH_24BIT_DEFAULT;
728 output_select = OUT_FROM_8BIT_BYPASS;
732 /*Config Color Depth*/
733 hdmi_msk_reg(hdmi_dev, VP_PR_CD,
734 m_COLOR_DEPTH, v_COLOR_DEPTH(color_depth));
737 /*Config pixel repettion*/
738 hdmi_msk_reg(hdmi_dev, VP_PR_CD, m_DESIRED_PR_FACTOR,
739 v_DESIRED_PR_FACTOR(hdmi_dev->pixelrepeat - 1));
740 if (hdmi_dev->pixelrepeat > 1)
741 hdmi_msk_reg(hdmi_dev, VP_CONF,
742 m_PIXEL_REPET_EN | m_BYPASS_SEL,
743 v_PIXEL_REPET_EN(1) | v_BYPASS_SEL(0));
745 hdmi_msk_reg(hdmi_dev, VP_CONF,
746 m_PIXEL_REPET_EN | m_BYPASS_SEL,
747 v_PIXEL_REPET_EN(0) | v_BYPASS_SEL(1));
749 /*config output select*/
750 if (output_select == OUT_FROM_PIXEL_PACKING) { /* pixel packing */
751 hdmi_msk_reg(hdmi_dev, VP_CONF,
752 m_BYPASS_EN | m_PIXEL_PACK_EN |
753 m_YCC422_EN | m_OUTPUT_SEL,
754 v_BYPASS_EN(0) | v_PIXEL_PACK_EN(1) |
755 v_YCC422_EN(0) | v_OUTPUT_SEL(output_select));
756 } else if (output_select == OUT_FROM_YCC422_REMAP) { /* YCC422 */
757 hdmi_msk_reg(hdmi_dev, VP_CONF,
758 m_BYPASS_EN | m_PIXEL_PACK_EN |
759 m_YCC422_EN | m_OUTPUT_SEL,
760 v_BYPASS_EN(0) | v_PIXEL_PACK_EN(0) |
761 v_YCC422_EN(1) | v_OUTPUT_SEL(output_select));
762 } else if (output_select == OUT_FROM_8BIT_BYPASS ||
763 output_select == 3) { /* bypass */
764 hdmi_msk_reg(hdmi_dev, VP_CONF,
765 m_BYPASS_EN | m_PIXEL_PACK_EN |
766 m_YCC422_EN | m_OUTPUT_SEL,
767 v_BYPASS_EN(1) | v_PIXEL_PACK_EN(0) |
768 v_YCC422_EN(0) | v_OUTPUT_SEL(output_select));
771 #if defined(HDMI_VIDEO_STUFFING)
772 /* YCC422 and pixel packing stuffing*/
773 hdmi_msk_reg(hdmi_dev, VP_STUFF, m_PR_STUFFING, v_PR_STUFFING(1));
774 hdmi_msk_reg(hdmi_dev, VP_STUFF,
775 m_YCC422_STUFFING | m_PP_STUFFING,
776 v_YCC422_STUFFING(1) | v_PP_STUFFING(1));
781 static int rockchip_hdmiv2_video_sampler(struct hdmi_dev *hdmi_dev,
782 struct hdmi_video *vpara)
786 if (vpara->color_input == HDMI_COLOR_YCBCR422) {
787 /* YCC422 mapping is discontinued - only map 1 is supported */
788 switch (vpara->color_output_depth) {
790 map_code = VIDEO_YCBCR422_8BIT;
793 map_code = VIDEO_YCBCR422_10BIT;
796 map_code = VIDEO_YCBCR422_12BIT;
799 map_code = VIDEO_YCBCR422_8BIT;
802 } else if (vpara->color_input == HDMI_COLOR_YCBCR420 ||
803 vpara->color_input == HDMI_COLOR_YCBCR444) {
804 switch (vpara->color_output_depth) {
806 map_code = VIDEO_YCBCR444_10BIT;
809 map_code = VIDEO_YCBCR444_12BIT;
812 map_code = VIDEO_YCBCR444_16BIT;
816 map_code = VIDEO_YCBCR444_8BIT;
820 switch (vpara->color_output_depth) {
822 map_code = VIDEO_RGB444_10BIT;
825 map_code = VIDEO_RGB444_12BIT;
828 map_code = VIDEO_RGB444_16BIT;
832 map_code = VIDEO_RGB444_8BIT;
835 map_code += (vpara->color_input == HDMI_COLOR_YCBCR444) ?
839 /* Set Data enable signal from external
840 and set video sample input mapping */
841 hdmi_msk_reg(hdmi_dev, TX_INVID0,
842 m_INTERNAL_DE_GEN | m_VIDEO_MAPPING,
843 v_INTERNAL_DE_GEN(0) | v_VIDEO_MAPPING(map_code));
845 #if defined(HDMI_VIDEO_STUFFING)
846 hdmi_writel(hdmi_dev, TX_GYDATA0, 0x00);
847 hdmi_writel(hdmi_dev, TX_GYDATA1, 0x00);
848 hdmi_msk_reg(hdmi_dev, TX_INSTUFFING,
849 m_GYDATA_STUFF, v_GYDATA_STUFF(1));
850 hdmi_writel(hdmi_dev, TX_RCRDATA0, 0x00);
851 hdmi_writel(hdmi_dev, TX_RCRDATA1, 0x00);
852 hdmi_msk_reg(hdmi_dev, TX_INSTUFFING,
853 m_RCRDATA_STUFF, v_RCRDATA_STUFF(1));
854 hdmi_writel(hdmi_dev, TX_BCBDATA0, 0x00);
855 hdmi_writel(hdmi_dev, TX_BCBDATA1, 0x00);
856 hdmi_msk_reg(hdmi_dev, TX_INSTUFFING,
857 m_BCBDATA_STUFF, v_BCBDATA_STUFF(1));
862 static const char coeff_csc[][24] = {
866 C1 | C2 | C3 | C4 | */
867 { /* CSC_RGB_0_255_TO_RGB_16_235_8BIT */
868 0x36, 0xf7, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, /*G*/
869 0x00, 0x00, 0x36, 0xf7, 0x00, 0x00, 0x00, 0x40, /*R*/
870 0x00, 0x00, 0x00, 0x00, 0x36, 0xf7, 0x00, 0x40, /*B*/
872 { /* CSC_RGB_0_255_TO_RGB_16_235_10BIT */
873 0x36, 0xf7, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, /*G*/
874 0x00, 0x00, 0x36, 0xf7, 0x00, 0x00, 0x01, 0x00, /*R*/
875 0x00, 0x00, 0x00, 0x00, 0x36, 0xf7, 0x01, 0x00, /*B*/
877 { /* CSC_RGB_0_255_TO_ITU601_16_235_8BIT */
878 0x20, 0x40, 0x10, 0x80, 0x06, 0x40, 0x00, 0x40, /*Y*/
879 0xe8, 0x80, 0x1c, 0x00, 0xfb, 0x80, 0x02, 0x00, /*Cr*/
880 0xed, 0x80, 0xf6, 0x80, 0x1c, 0x00, 0x02, 0x00, /*Cb*/
882 { /* CSC_RGB_0_255_TO_ITU601_16_235_10BIT */
883 0x20, 0x40, 0x10, 0x80, 0x06, 0x40, 0x01, 0x00, /*Y*/
884 0xe8, 0x80, 0x1c, 0x00, 0xfb, 0x80, 0x08, 0x00, /*Cr*/
885 0xed, 0x80, 0xf6, 0x80, 0x1c, 0x00, 0x08, 0x00, /*Cb*/
887 { /* CSC_RGB_0_255_TO_ITU709_16_235_8BIT */
888 0x27, 0x40, 0x0b, 0xc0, 0x04, 0x00, 0x00, 0x40, /*Y*/
889 0xe6, 0x80, 0x1c, 0x00, 0xfd, 0x80, 0x02, 0x00, /*Cr*/
890 0xea, 0x40, 0xf9, 0x80, 0x1c, 0x00, 0x02, 0x00, /*Cb*/
892 { /* CSC_RGB_0_255_TO_ITU709_16_235_10BIT */
893 0x27, 0x40, 0x0b, 0xc0, 0x04, 0x00, 0x01, 0x00, /*Y*/
894 0xe6, 0x80, 0x1c, 0x00, 0xfd, 0x80, 0x08, 0x00, /*Cr*/
895 0xea, 0x40, 0xf9, 0x80, 0x1c, 0x00, 0x08, 0x00, /*Cb*/
898 { /* CSC_ITU601_16_235_TO_RGB_0_255_8BIT */
899 0x20, 0x00, 0x69, 0x26, 0x74, 0xfd, 0x01, 0x0e, /*G*/
900 0x20, 0x00, 0x2c, 0xdd, 0x00, 0x00, 0x7e, 0x9a, /*R*/
901 0x20, 0x00, 0x00, 0x00, 0x38, 0xb4, 0x7e, 0x3b, /*B*/
903 { /* CSC_ITU709_16_235_TO_RGB_0_255_8BIT */
904 0x20, 0x00, 0x71, 0x06, 0x7a, 0x02, 0x00, 0xa7, /*G*/
905 0x20, 0x00, 0x32, 0x64, 0x00, 0x00, 0x7e, 0x6d, /*R*/
906 0x20, 0x00, 0x00, 0x00, 0x3b, 0x61, 0x7e, 0x25, /*B*/
910 static int rockchip_hdmiv2_video_csc(struct hdmi_dev *hdmi_dev,
911 struct hdmi_video *vpara)
913 int i, mode, interpolation, decimation, csc_scale;
914 const char *coeff = NULL;
915 unsigned char color_depth = 0;
917 if (vpara->color_input == vpara->color_output) {
918 hdmi_msk_reg(hdmi_dev, MC_FLOWCTRL,
919 m_FEED_THROUGH_OFF, v_FEED_THROUGH_OFF(0));
923 if (vpara->color_input == HDMI_COLOR_YCBCR422 &&
924 vpara->color_output != HDMI_COLOR_YCBCR422 &&
925 vpara->color_output != HDMI_COLOR_YCBCR420) {
927 hdmi_msk_reg(hdmi_dev, CSC_CFG,
928 m_CSC_INTPMODE, v_CSC_INTPMODE(interpolation));
931 if ((vpara->color_input == HDMI_COLOR_RGB_0_255 ||
932 vpara->color_input == HDMI_COLOR_YCBCR444) &&
933 vpara->color_output == HDMI_COLOR_YCBCR422) {
935 hdmi_msk_reg(hdmi_dev, CSC_CFG,
936 m_CSC_DECIMODE, v_CSC_DECIMODE(decimation));
939 switch (vpara->vic) {
940 case HDMI_720X480I_60HZ_4_3:
941 case HDMI_720X576I_50HZ_4_3:
942 case HDMI_720X480P_60HZ_4_3:
943 case HDMI_720X576P_50HZ_4_3:
944 case HDMI_720X480I_60HZ_16_9:
945 case HDMI_720X576I_50HZ_16_9:
946 case HDMI_720X480P_60HZ_16_9:
947 case HDMI_720X576P_50HZ_16_9:
948 if (vpara->color_input == HDMI_COLOR_RGB_0_255 &&
949 vpara->color_output >= HDMI_COLOR_YCBCR444) {
950 mode = CSC_RGB_0_255_TO_ITU601_16_235_8BIT;
952 } else if (vpara->color_input >= HDMI_COLOR_YCBCR444 &&
953 vpara->color_output == HDMI_COLOR_RGB_0_255) {
954 mode = CSC_ITU601_16_235_TO_RGB_0_255_8BIT;
959 if (vpara->color_input == HDMI_COLOR_RGB_0_255 &&
960 vpara->color_output >= HDMI_COLOR_YCBCR444) {
961 mode = CSC_RGB_0_255_TO_ITU709_16_235_8BIT;
963 } else if (vpara->color_input >= HDMI_COLOR_YCBCR444 &&
964 vpara->color_output == HDMI_COLOR_RGB_0_255) {
965 mode = CSC_ITU709_16_235_TO_RGB_0_255_8BIT;
971 if ((vpara->color_input == HDMI_COLOR_RGB_0_255) &&
972 (vpara->color_output == HDMI_COLOR_RGB_16_235)) {
973 mode = CSC_RGB_0_255_TO_RGB_16_235_8BIT;
977 switch (vpara->color_output_depth) {
979 color_depth = COLOR_DEPTH_30BIT;
983 color_depth = COLOR_DEPTH_36BIT;
987 color_depth = COLOR_DEPTH_48BIT;
992 color_depth = COLOR_DEPTH_24BIT;
996 coeff = coeff_csc[mode];
997 for (i = 0; i < 24; i++)
998 hdmi_writel(hdmi_dev, CSC_COEF_A1_MSB + i, coeff[i]);
1000 hdmi_msk_reg(hdmi_dev, CSC_SCALE,
1001 m_CSC_SCALE, v_CSC_SCALE(csc_scale));
1002 /*config CSC_COLOR_DEPTH*/
1003 hdmi_msk_reg(hdmi_dev, CSC_SCALE,
1004 m_CSC_COLOR_DEPTH, v_CSC_COLOR_DEPTH(color_depth));
1007 hdmi_msk_reg(hdmi_dev, MC_FLOWCTRL,
1008 m_FEED_THROUGH_OFF, v_FEED_THROUGH_OFF(1));
1014 static int hdmi_dev_detect_hotplug(struct hdmi *hdmi)
1016 struct hdmi_dev *hdmi_dev = hdmi->property->priv;
1017 u32 value = hdmi_readl(hdmi_dev, PHY_STAT0);
1019 HDMIDBG("[%s] reg%x value %02x\n", __func__, PHY_STAT0, value);
1021 if (value & m_PHY_HPD)
1022 return HDMI_HPD_ACTIVED;
1024 return HDMI_HPD_REMOVED;
1027 static int hdmi_dev_read_edid(struct hdmi *hdmi, int block, unsigned char *buff)
1029 struct hdmi_dev *hdmi_dev = hdmi->property->priv;
1030 int i = 0, n = 0, index = 0, ret = -1, trytime = 5;
1031 int offset = (block % 2) * 0x80;
1034 HDMIDBG("[%s] block %d\n", __func__, block);
1036 rockchip_hdmiv2_i2cm_reset(hdmi_dev);
1038 /* Set DDC I2C CLK which devided from DDC_CLK to 100KHz. */
1039 rockchip_hdmiv2_i2cm_clk_init(hdmi_dev);
1041 /* Enable I2C interrupt for reading edid */
1042 rockchip_hdmiv2_i2cm_mask_int(hdmi_dev, 0);
1044 hdmi_writel(hdmi_dev, I2CM_SLAVE, DDC_I2C_EDID_ADDR);
1045 hdmi_writel(hdmi_dev, I2CM_SEGADDR, DDC_I2C_SEG_ADDR);
1046 hdmi_writel(hdmi_dev, I2CM_SEGPTR, block / 2);
1047 for (n = 0; n < HDMI_EDID_BLOCK_SIZE / 8; n++) {
1048 for (trytime = 0; trytime < 5; trytime++) {
1049 hdmi_writel(hdmi_dev, I2CM_ADDRESS, offset + 8 * n);
1050 /* enable extend sequential read operation */
1052 hdmi_msk_reg(hdmi_dev, I2CM_OPERATION,
1053 m_I2CM_RD8, v_I2CM_RD8(1));
1055 hdmi_msk_reg(hdmi_dev, I2CM_OPERATION,
1061 usleep_range(900, 1000);
1062 interrupt = hdmi_readl(hdmi_dev,
1065 hdmi_writel(hdmi_dev,
1066 IH_I2CM_STAT0, interrupt);
1069 (m_SCDC_READREQ | m_I2CM_DONE |
1074 if (interrupt & m_I2CM_DONE) {
1075 for (index = 0; index < 8; index++)
1076 buff[8 * n + index] =
1077 hdmi_readl(hdmi_dev,
1081 if (n == HDMI_EDID_BLOCK_SIZE / 8 - 1) {
1086 } else if ((interrupt & m_I2CM_ERROR) || (i == -1)) {
1088 "[%s] edid read %d error\n",
1089 __func__, offset + 8 * n);
1094 "[%s] edid read error\n", __func__);
1100 /* Disable I2C interrupt */
1101 rockchip_hdmiv2_i2cm_mask_int(hdmi_dev, 1);
1105 static void hdmi_dev_config_avi(struct hdmi_dev *hdmi_dev,
1106 struct hdmi_video *vpara)
1108 unsigned char colorimetry, ext_colorimetry, aspect_ratio, y1y0;
1109 unsigned char rgb_quan_range = AVI_QUANTIZATION_RANGE_DEFAULT;
1111 /* Set AVI infoFrame Data byte1 */
1112 if (vpara->color_output == HDMI_COLOR_YCBCR444)
1113 y1y0 = AVI_COLOR_MODE_YCBCR444;
1114 else if (vpara->color_output == HDMI_COLOR_YCBCR422)
1115 y1y0 = AVI_COLOR_MODE_YCBCR422;
1116 else if (vpara->color_output == HDMI_COLOR_YCBCR420)
1117 y1y0 = AVI_COLOR_MODE_YCBCR420;
1119 y1y0 = AVI_COLOR_MODE_RGB;
1121 hdmi_msk_reg(hdmi_dev, FC_AVICONF0,
1122 m_FC_ACTIV_FORMAT | m_FC_RGC_YCC,
1123 v_FC_RGC_YCC(y1y0) | v_FC_ACTIV_FORMAT(1));
1125 /* Set AVI infoFrame Data byte2 */
1126 switch (vpara->vic) {
1127 case HDMI_720X480I_60HZ_4_3:
1128 case HDMI_720X576I_50HZ_4_3:
1129 case HDMI_720X480P_60HZ_4_3:
1130 case HDMI_720X576P_50HZ_4_3:
1131 aspect_ratio = AVI_CODED_FRAME_ASPECT_4_3;
1132 colorimetry = AVI_COLORIMETRY_SMPTE_170M;
1134 case HDMI_720X480I_60HZ_16_9:
1135 case HDMI_720X576I_50HZ_16_9:
1136 case HDMI_720X480P_60HZ_16_9:
1137 case HDMI_720X576P_50HZ_16_9:
1138 aspect_ratio = AVI_CODED_FRAME_ASPECT_16_9;
1139 colorimetry = AVI_COLORIMETRY_SMPTE_170M;
1142 aspect_ratio = AVI_CODED_FRAME_ASPECT_16_9;
1143 colorimetry = AVI_COLORIMETRY_ITU709;
1146 if (vpara->color_output_depth > 8) {
1147 colorimetry = AVI_COLORIMETRY_EXTENDED;
1148 ext_colorimetry = 6;
1149 } else if (vpara->color_output == HDMI_COLOR_RGB_16_235 ||
1150 vpara->color_output == HDMI_COLOR_RGB_0_255) {
1151 colorimetry = AVI_COLORIMETRY_NO_DATA;
1152 ext_colorimetry = 0;
1155 hdmi_writel(hdmi_dev, FC_AVICONF1,
1156 v_FC_COLORIMETRY(colorimetry) |
1157 v_FC_PIC_ASPEC_RATIO(aspect_ratio) |
1158 v_FC_ACT_ASPEC_RATIO(ACTIVE_ASPECT_RATE_DEFAULT));
1160 /* Set AVI infoFrame Data byte3 */
1161 hdmi_msk_reg(hdmi_dev, FC_AVICONF2,
1162 m_FC_EXT_COLORIMETRY | m_FC_QUAN_RANGE,
1163 v_FC_EXT_COLORIMETRY(ext_colorimetry) |
1164 v_FC_QUAN_RANGE(rgb_quan_range));
1166 /* Set AVI infoFrame Data byte4 */
1167 if ((vpara->vic > 92 && vpara->vic < 96) || (vpara->vic == 98))
1168 hdmi_writel(hdmi_dev, FC_AVIVID, 0);
1170 hdmi_writel(hdmi_dev, FC_AVIVID, vpara->vic & 0xff);
1171 /* Set AVI infoFrame Data byte5 */
1172 hdmi_msk_reg(hdmi_dev, FC_AVICONF3, m_FC_YQ | m_FC_CN,
1173 v_FC_YQ(YQ_LIMITED_RANGE) | v_FC_CN(CN_GRAPHICS));
1176 static int hdmi_dev_config_vsi(struct hdmi *hdmi,
1177 unsigned char vic_3d, unsigned char format)
1179 int i = 0, id = 0x000c03;
1180 unsigned char data[3] = {0};
1182 struct hdmi_dev *hdmi_dev = hdmi->property->priv;
1184 HDMIDBG("[%s] vic %d format %d.\n", __func__, vic_3d, format);
1186 hdmi_msk_reg(hdmi_dev, FC_DATAUTO0, m_VSD_AUTO, v_VSD_AUTO(0));
1187 hdmi_writel(hdmi_dev, FC_VSDIEEEID2, id & 0xff);
1188 hdmi_writel(hdmi_dev, FC_VSDIEEEID1, (id >> 8) & 0xff);
1189 hdmi_writel(hdmi_dev, FC_VSDIEEEID0, (id >> 16) & 0xff);
1191 data[0] = format << 5; /* PB4 --HDMI_Video_Format */
1193 case HDMI_VIDEO_FORMAT_4KX2K:
1194 data[1] = vic_3d; /* PB5--HDMI_VIC */
1197 case HDMI_VIDEO_FORMAT_3D:
1198 data[1] = vic_3d << 4; /* PB5--3D_Structure field */
1199 data[2] = 0; /* PB6--3D_Ext_Data field */
1207 for (i = 0; i < 3; i++)
1208 hdmi_writel(hdmi_dev, FC_VSDPAYLOAD0 + i, data[i]);
1209 hdmi_writel(hdmi_dev, FC_VSDSIZE, 0x6);
1210 /* if (auto_send) { */
1211 hdmi_writel(hdmi_dev, FC_DATAUTO1, 0);
1212 hdmi_writel(hdmi_dev, FC_DATAUTO2, 0x11);
1213 hdmi_msk_reg(hdmi_dev, FC_DATAUTO0, m_VSD_AUTO, v_VSD_AUTO(1));
1216 hdmi_msk_reg(hdmi_dev, FC_DATMAN, m_VSD_MAN, v_VSD_MAN(1));
1222 static int hdmi_dev_config_video(struct hdmi *hdmi, struct hdmi_video *vpara)
1224 struct hdmi_dev *hdmi_dev = hdmi->property->priv;
1226 HDMIDBG("%s vic %d 3dformat %d color mode %d color depth %d\n",
1227 __func__, vpara->vic, vpara->format_3d,
1228 vpara->color_output, vpara->color_output_depth);
1230 if (hdmi_dev->soctype == HDMI_SOC_RK3288)
1231 vpara->color_input = HDMI_COLOR_RGB_0_255;
1234 /* befor configure video, we power off phy */
1235 hdmi_msk_reg(hdmi_dev, PHY_CONF0,
1236 m_PDDQ_SIG | m_TXPWRON_SIG,
1237 v_PDDQ_SIG(1) | v_TXPWRON_SIG(0));
1239 /* force output blue */
1240 if (vpara->color_output == HDMI_COLOR_RGB_0_255) {
1241 hdmi_writel(hdmi_dev, FC_DBGTMDS2, 0x00); /*R*/
1242 hdmi_writel(hdmi_dev, FC_DBGTMDS1, 0x00); /*G*/
1243 hdmi_writel(hdmi_dev, FC_DBGTMDS0, 0x00); /*B*/
1244 } else if (vpara->color_output == HDMI_COLOR_RGB_16_235) {
1245 hdmi_writel(hdmi_dev, FC_DBGTMDS2, 0x10); /*R*/
1246 hdmi_writel(hdmi_dev, FC_DBGTMDS1, 0x10); /*G*/
1247 hdmi_writel(hdmi_dev, FC_DBGTMDS0, 0x10); /*B*/
1249 hdmi_writel(hdmi_dev, FC_DBGTMDS2, 0x80); /*R*/
1250 hdmi_writel(hdmi_dev, FC_DBGTMDS1, 0x10); /*G*/
1251 hdmi_writel(hdmi_dev, FC_DBGTMDS0, 0x80); /*B*/
1253 hdmi_msk_reg(hdmi_dev, FC_DBGFORCE,
1254 m_FC_FORCEVIDEO, v_FC_FORCEVIDEO(1));
1255 hdmi_writel(hdmi_dev, MC_CLKDIS, m_HDCPCLK_DISABLE);
1258 if (rockchip_hdmiv2_video_framecomposer(hdmi, vpara) < 0)
1261 if (rockchip_hdmiv2_video_packetizer(hdmi_dev, vpara) < 0)
1263 /* Color space convert */
1264 if (rockchip_hdmiv2_video_csc(hdmi_dev, vpara) < 0)
1266 if (rockchip_hdmiv2_video_sampler(hdmi_dev, vpara) < 0)
1269 if (vpara->sink_hdmi == OUTPUT_HDMI) {
1270 hdmi_dev_config_avi(hdmi_dev, vpara);
1271 if (vpara->format_3d != HDMI_3D_NONE) {
1272 hdmi_dev_config_vsi(hdmi,
1274 HDMI_VIDEO_FORMAT_3D);
1275 } else if ((vpara->vic > 92 && vpara->vic < 96) ||
1276 (vpara->vic == 98)) {
1277 vpara->vic = (vpara->vic == 98) ?
1278 4 : (96 - vpara->vic);
1279 hdmi_dev_config_vsi(hdmi,
1281 HDMI_VIDEO_FORMAT_4KX2K);
1283 hdmi_dev_config_vsi(hdmi,
1285 HDMI_VIDEO_FORMAT_NORMAL);
1287 dev_info(hdmi->dev, "[%s] sucess output HDMI.\n", __func__);
1289 dev_info(hdmi->dev, "[%s] sucess output DVI.\n", __func__);
1292 rockchip_hdmiv2_config_phy(hdmi_dev);
1296 static void hdmi_dev_config_aai(struct hdmi_dev *hdmi_dev,
1297 struct hdmi_audio *audio)
1299 /*Refer to CEA861-E Audio infoFrame*/
1300 /*Set both Audio Channel Count and Audio Coding
1301 Type Refer to Stream Head for HDMI*/
1302 hdmi_msk_reg(hdmi_dev, FC_AUDICONF0,
1303 m_FC_CHN_CNT | m_FC_CODING_TYEP,
1304 v_FC_CHN_CNT(audio->channel-1) | v_FC_CODING_TYEP(0));
1306 /*Set both Audio Sample Size and Sample Frequency
1307 Refer to Stream Head for HDMI*/
1308 hdmi_msk_reg(hdmi_dev, FC_AUDICONF1,
1309 m_FC_SAMPLE_SIZE | m_FC_SAMPLE_FREQ,
1310 v_FC_SAMPLE_SIZE(0) | v_FC_SAMPLE_FREQ(0));
1312 /*Set Channel Allocation*/
1313 hdmi_writel(hdmi_dev, FC_AUDICONF2, 0x00);
1315 /*Set LFEPBL¡¢DOWN-MIX INH and LSV*/
1316 hdmi_writel(hdmi_dev, FC_AUDICONF3, 0x00);
1319 static int hdmi_dev_config_audio(struct hdmi *hdmi, struct hdmi_audio *audio)
1321 struct hdmi_dev *hdmi_dev = hdmi->property->priv;
1322 int word_length = 0, channel = 0, mclk_fs;
1323 unsigned int N = 0, CTS = 0;
1326 HDMIDBG("%s\n", __func__);
1328 if (audio->channel < 3)
1329 channel = I2S_CHANNEL_1_2;
1330 else if (audio->channel < 5)
1331 channel = I2S_CHANNEL_3_4;
1332 else if (audio->channel < 7)
1333 channel = I2S_CHANNEL_5_6;
1335 channel = I2S_CHANNEL_7_8;
1337 switch (audio->rate) {
1338 case HDMI_AUDIO_FS_32000:
1341 if (hdmi_dev->tmdsclk >= 594000000)
1343 else if (hdmi_dev->tmdsclk >= 297000000)
1347 /*div a num to avoid the value is exceed 2^32(int)*/
1348 CTS = CALC_CTS(N, hdmi_dev->tmdsclk/1000, 32);
1350 case HDMI_AUDIO_FS_44100:
1353 if (hdmi_dev->tmdsclk >= 594000000)
1355 else if (hdmi_dev->tmdsclk >= 297000000)
1360 CTS = CALC_CTS(N, hdmi_dev->tmdsclk/100, 441);
1362 case HDMI_AUDIO_FS_48000:
1365 if (hdmi_dev->tmdsclk >= 594000000) /*FS_153.6*/
1367 else if (hdmi_dev->tmdsclk >= 297000000)
1372 CTS = CALC_CTS(N, hdmi_dev->tmdsclk/1000, 48);
1374 case HDMI_AUDIO_FS_88200:
1377 if (hdmi_dev->tmdsclk >= 594000000)
1379 else if (hdmi_dev->tmdsclk >= 297000000)
1384 CTS = CALC_CTS(N, hdmi_dev->tmdsclk/100, 882);
1386 case HDMI_AUDIO_FS_96000:
1389 if (hdmi_dev->tmdsclk >= 594000000) /*FS_153.6*/
1391 else if (hdmi_dev->tmdsclk >= 297000000)
1396 CTS = CALC_CTS(N, hdmi_dev->tmdsclk/1000, 96);
1398 case HDMI_AUDIO_FS_176400:
1401 if (hdmi_dev->tmdsclk >= 594000000)
1402 N = N_1764K_HIGHCLK;
1403 else if (hdmi_dev->tmdsclk >= 297000000)
1408 CTS = CALC_CTS(N, hdmi_dev->tmdsclk/100, 1764);
1410 case HDMI_AUDIO_FS_192000:
1413 if (hdmi_dev->tmdsclk >= 594000000) /*FS_153.6*/
1415 else if (hdmi_dev->tmdsclk >= 297000000)
1420 CTS = CALC_CTS(N, hdmi_dev->tmdsclk/1000, 192);
1423 dev_err(hdmi_dev->hdmi->dev,
1424 "[%s] not support such sample rate %d\n",
1425 __func__, audio->rate);
1429 switch (audio->word_length) {
1430 case HDMI_AUDIO_WORD_LENGTH_16bit:
1431 word_length = I2S_16BIT_SAMPLE;
1433 case HDMI_AUDIO_WORD_LENGTH_20bit:
1434 word_length = I2S_20BIT_SAMPLE;
1436 case HDMI_AUDIO_WORD_LENGTH_24bit:
1437 word_length = I2S_24BIT_SAMPLE;
1440 word_length = I2S_16BIT_SAMPLE;
1443 HDMIDBG("rate = %d, tmdsclk = %u, N = %d, CTS = %d\n",
1444 audio->rate, hdmi_dev->tmdsclk, N, CTS);
1445 /* more than 2 channels => layout 1 else layout 0 */
1446 hdmi_msk_reg(hdmi_dev, FC_AUDSCONF,
1448 v_AUD_PACK_LAYOUT((audio->channel > 2) ? 1 : 0));
1450 if (hdmi_dev->audiosrc == HDMI_AUDIO_SRC_SPDIF) {
1452 hdmi_msk_reg(hdmi_dev, AUD_CONF0,
1453 m_I2S_SEL, v_I2S_SEL(AUDIO_SPDIF_GPA));
1454 hdmi_msk_reg(hdmi_dev, AUD_SPDIF1,
1455 m_SET_NLPCM | m_SPDIF_WIDTH,
1456 v_SET_NLPCM(PCM_LINEAR) |
1457 v_SPDIF_WIDTH(word_length));
1458 /*Mask fifo empty and full int and reset fifo*/
1459 hdmi_msk_reg(hdmi_dev, AUD_SPDIFINT,
1460 m_FIFO_EMPTY_MASK | m_FIFO_FULL_MASK,
1461 v_FIFO_EMPTY_MASK(1) | v_FIFO_FULL_MASK(1));
1462 hdmi_msk_reg(hdmi_dev, AUD_SPDIF0,
1463 m_SW_SAUD_FIFO_RST, v_SW_SAUD_FIFO_RST(1));
1465 /*Mask fifo empty and full int and reset fifo*/
1466 hdmi_msk_reg(hdmi_dev, AUD_INT,
1467 m_FIFO_EMPTY_MASK | m_FIFO_FULL_MASK,
1468 v_FIFO_EMPTY_MASK(1) | v_FIFO_FULL_MASK(1));
1469 hdmi_msk_reg(hdmi_dev, AUD_CONF0,
1470 m_SW_AUD_FIFO_RST, v_SW_AUD_FIFO_RST(1));
1471 hdmi_writel(hdmi_dev, MC_SWRSTZREQ, 0xF7);
1472 hdmi_writel(hdmi_dev, AUD_CONF2, 0x0);
1473 usleep_range(90, 100);
1474 if (I2S_CHANNEL_7_8 == channel) {
1475 HDMIDBG("hbr mode.\n");
1476 hdmi_writel(hdmi_dev, AUD_CONF2, 0x1);
1477 word_length = I2S_24BIT_SAMPLE;
1478 } else if ((HDMI_AUDIO_FS_48000 == audio->rate) ||
1479 (HDMI_AUDIO_FS_192000 == audio->rate)) {
1480 HDMIDBG("nlpcm mode.\n");
1481 hdmi_writel(hdmi_dev, AUD_CONF2, 0x2);
1482 word_length = I2S_24BIT_SAMPLE;
1484 hdmi_writel(hdmi_dev, AUD_CONF2, 0x0);
1486 hdmi_msk_reg(hdmi_dev, AUD_CONF0,
1487 m_I2S_SEL | m_I2S_IN_EN,
1488 v_I2S_SEL(AUDIO_I2S) | v_I2S_IN_EN(channel));
1489 hdmi_writel(hdmi_dev, AUD_CONF1,
1490 v_I2S_MODE(I2S_STANDARD_MODE) |
1491 v_I2S_WIDTH(word_length));
1494 hdmi_msk_reg(hdmi_dev, AUD_INPUTCLKFS,
1495 m_LFS_FACTOR, v_LFS_FACTOR(mclk_fs));
1498 hdmi_msk_reg(hdmi_dev, AUD_N3, m_NCTS_ATOMIC_WR, v_NCTS_ATOMIC_WR(1));
1499 /*Set CTS by manual*/
1500 hdmi_msk_reg(hdmi_dev, AUD_CTS3,
1501 m_N_SHIFT | m_CTS_MANUAL | m_AUD_CTS3,
1502 v_N_SHIFT(N_SHIFT_1) |
1504 v_AUD_CTS3(CTS >> 16));
1505 hdmi_writel(hdmi_dev, AUD_CTS2, (CTS >> 8) & 0xff);
1506 hdmi_writel(hdmi_dev, AUD_CTS1, CTS & 0xff);
1508 hdmi_msk_reg(hdmi_dev, AUD_N3, m_AUD_N3, v_AUD_N3(N >> 16));
1509 hdmi_writel(hdmi_dev, AUD_N2, (N >> 8) & 0xff);
1510 hdmi_writel(hdmi_dev, AUD_N1, N & 0xff);
1512 /* set channel status register */
1513 hdmi_msk_reg(hdmi_dev, FC_AUDSCHNLS7,
1514 m_AUDIO_SAMPLE_RATE, v_AUDIO_SAMPLE_RATE(rate));
1515 hdmi_writel(hdmi_dev, FC_AUDSCHNLS8, ((~rate) << 4) | 0x2);
1517 hdmi_msk_reg(hdmi_dev, AUD_CONF0,
1518 m_SW_AUD_FIFO_RST, v_SW_AUD_FIFO_RST(1));
1520 hdmi_dev_config_aai(hdmi_dev, audio);
1525 static int hdmi_dev_control_output(struct hdmi *hdmi, int enable)
1527 struct hdmi_dev *hdmi_dev = hdmi->property->priv;
1528 struct hdmi_video vpara;
1530 HDMIDBG("[%s] %d\n", __func__, enable);
1531 if (enable == HDMI_AV_UNMUTE) {
1532 hdmi_writel(hdmi_dev, FC_DBGFORCE, 0x00);
1533 if (hdmi->edid.sink_hdmi == OUTPUT_HDMI)
1534 hdmi_msk_reg(hdmi_dev, FC_GCP,
1535 m_FC_SET_AVMUTE | m_FC_CLR_AVMUTE,
1536 v_FC_SET_AVMUTE(0) | v_FC_CLR_AVMUTE(1));
1538 if (enable & HDMI_VIDEO_MUTE) {
1539 hdmi_msk_reg(hdmi_dev, FC_DBGFORCE,
1540 m_FC_FORCEVIDEO, v_FC_FORCEVIDEO(1));
1541 if (hdmi->edid.sink_hdmi == OUTPUT_HDMI) {
1542 hdmi_msk_reg(hdmi_dev, FC_GCP,
1545 v_FC_SET_AVMUTE(1) |
1546 v_FC_CLR_AVMUTE(0));
1547 vpara.vic = hdmi->vic;
1548 vpara.color_output = HDMI_COLOR_RGB_0_255;
1549 hdmi_dev_config_avi(hdmi_dev, &vpara);
1552 /* if (enable & HDMI_AUDIO_MUTE) {
1553 hdmi_msk_reg(hdmi_dev, FC_AUDSCONF,
1555 v_AUD_PACK_SAMPFIT(0x0F));
1557 */ if (enable == (HDMI_VIDEO_MUTE | HDMI_AUDIO_MUTE)) {
1559 if (hdmi->ops->hdcp_power_off_cb)
1560 hdmi->ops->hdcp_power_off_cb(hdmi);
1561 rockchip_hdmiv2_powerdown(hdmi_dev);
1562 hdmi_dev->tmdsclk = 0;
1564 hdmi_msk_reg(hdmi_dev, PHY_CONF0,
1565 m_PDDQ_SIG | m_TXPWRON_SIG,
1566 v_PDDQ_SIG(1) | v_TXPWRON_SIG(0));
1567 hdmi_writel(hdmi_dev, MC_CLKDIS, 0x7f);
1573 static int hdmi_dev_insert(struct hdmi *hdmi)
1575 struct hdmi_dev *hdmi_dev = hdmi->property->priv;
1577 HDMIDBG("%s\n", __func__);
1579 hdmi_writel(hdmi_dev, MC_CLKDIS, m_HDCPCLK_DISABLE);
1580 return HDMI_ERROR_SUCESS;
1583 static int hdmi_dev_remove(struct hdmi *hdmi)
1585 struct hdmi_dev *hdmi_dev = hdmi->property->priv;
1587 HDMIDBG("%s\n", __func__);
1588 if (hdmi->ops->hdcp_power_off_cb)
1589 hdmi->ops->hdcp_power_off_cb(hdmi);
1590 rockchip_hdmiv2_powerdown(hdmi_dev);
1591 hdmi_dev->tmdsclk = 0;
1592 return HDMI_ERROR_SUCESS;
1595 static int hdmi_dev_enable(struct hdmi *hdmi)
1597 struct hdmi_dev *hdmi_dev = hdmi->property->priv;
1599 HDMIDBG("%s\n", __func__);
1600 if (!hdmi_dev->enable) {
1601 hdmi_writel(hdmi_dev, IH_MUTE, 0x00);
1602 hdmi_dev->enable = 1;
1604 hdmi_submit_work(hdmi, HDMI_HPD_CHANGE, 10, NULL);
1608 static int hdmi_dev_disable(struct hdmi *hdmi)
1610 struct hdmi_dev *hdmi_dev = hdmi->property->priv;
1612 HDMIDBG("%s\n", __func__);
1613 if (hdmi_dev->enable) {
1614 hdmi_dev->enable = 0;
1615 hdmi_writel(hdmi_dev, IH_MUTE, 0x1);
1620 void rockchip_hdmiv2_dev_init_ops(struct hdmi_ops *ops)
1623 ops->enable = hdmi_dev_enable;
1624 ops->disable = hdmi_dev_disable;
1625 ops->getstatus = hdmi_dev_detect_hotplug;
1626 ops->insert = hdmi_dev_insert;
1627 ops->remove = hdmi_dev_remove;
1628 ops->getedid = hdmi_dev_read_edid;
1629 ops->setvideo = hdmi_dev_config_video;
1630 ops->setaudio = hdmi_dev_config_audio;
1631 ops->setmute = hdmi_dev_control_output;
1632 ops->setvsi = hdmi_dev_config_vsi;
1636 void rockchip_hdmiv2_dev_initial(struct hdmi_dev *hdmi_dev)
1638 struct hdmi *hdmi = hdmi_dev->hdmi;
1642 if (hdmi_dev->soctype == HDMI_SOC_RK3288) {
1643 writel_relaxed((1 << 9) | (1 << 25),
1644 RK_CRU_VIRT + 0x01d4);
1646 writel_relaxed((0 << 9) | (1 << 25),
1647 RK_CRU_VIRT + 0x01d4);
1648 } else if (hdmi_dev->soctype == HDMI_SOC_RK3368) {
1649 pr_info("reset hdmi\n");
1650 regmap_write(hdmi_dev->grf_base, 0x031c,
1651 (1 << 9) | (1 << 25));
1653 regmap_write(hdmi_dev->grf_base, 0x031c,
1654 (0 << 9) | (1 << 25));
1656 rockchip_hdmiv2_powerdown(hdmi_dev);
1658 /*mute unnecessary interrrupt, only enable hpd*/
1659 hdmi_writel(hdmi_dev, IH_MUTE_FC_STAT0, 0xff);
1660 hdmi_writel(hdmi_dev, IH_MUTE_FC_STAT1, 0xff);
1661 hdmi_writel(hdmi_dev, IH_MUTE_FC_STAT2, 0xff);
1662 hdmi_writel(hdmi_dev, IH_MUTE_AS_STAT0, 0xff);
1663 hdmi_writel(hdmi_dev, IH_MUTE_PHY_STAT0, 0xfe);
1664 hdmi_writel(hdmi_dev, IH_MUTE_I2CM_STAT0, 0xff);
1665 hdmi_writel(hdmi_dev, IH_MUTE_CEC_STAT0, 0xff);
1666 hdmi_writel(hdmi_dev, IH_MUTE_VP_STAT0, 0xff);
1667 hdmi_writel(hdmi_dev, IH_MUTE_I2CMPHY_STAT0, 0xff);
1668 hdmi_writel(hdmi_dev, IH_MUTE_AHBDMAAUD_STAT0, 0xff);
1670 /* disable hdcp interrup */
1671 hdmi_writel(hdmi_dev, A_APIINTMSK, 0xff);
1672 hdmi_writel(hdmi_dev, PHY_MASK, 0xf1);
1674 if (hdmi->property->feature & SUPPORT_CEC)
1675 rockchip_hdmiv2_cec_init(hdmi);
1676 if (hdmi->property->feature & SUPPORT_HDCP)
1677 rockchip_hdmiv2_hdcp_init(hdmi);
1680 irqreturn_t rockchip_hdmiv2_dev_irq(int irq, void *priv)
1682 struct hdmi_dev *hdmi_dev = priv;
1683 struct hdmi *hdmi = hdmi_dev->hdmi;
1684 char phy_pol = hdmi_readl(hdmi_dev, PHY_POL0);
1685 char phy_status = hdmi_readl(hdmi_dev, PHY_STAT0);
1686 char phy_int0 = hdmi_readl(hdmi_dev, PHY_INI0);
1688 char fc_stat0 = hdmi_readl(hdmi_dev, IH_FC_STAT0);
1689 char fc_stat1 = hdmi_readl(hdmi_dev, IH_FC_STAT1);
1690 char fc_stat2 = hdmi_readl(hdmi_dev, IH_FC_STAT2);
1691 char aud_int = hdmi_readl(hdmi_dev, IH_AS_SATA0);
1692 char phy_int = hdmi_readl(hdmi_dev, IH_PHY_STAT0);
1693 char vp_stat0 = hdmi_readl(hdmi_dev, IH_VP_STAT0);
1694 char cec_int = hdmi_readl(hdmi_dev, IH_CEC_STAT0);
1695 char hdcp_int = hdmi_readl(hdmi_dev, A_APIINTSTAT);
1696 char hdcp2_int = hdmi_readl(hdmi_dev, HDCP2REG_STAT);
1699 hdmi_writel(hdmi_dev, IH_FC_STAT0, fc_stat0);
1700 hdmi_writel(hdmi_dev, IH_FC_STAT1, fc_stat1);
1701 hdmi_writel(hdmi_dev, IH_FC_STAT2, fc_stat2);
1702 hdmi_writel(hdmi_dev, IH_VP_STAT0, vp_stat0);
1704 if (phy_int0 || phy_int) {
1705 phy_pol = (phy_int0 & (~phy_status)) | ((~phy_int0) & phy_pol);
1706 hdmi_writel(hdmi_dev, PHY_POL0, phy_pol);
1707 hdmi_writel(hdmi_dev, IH_PHY_STAT0, phy_int);
1708 if ((phy_int & m_HPD) || ((phy_int & 0x3c) == 0x3c))
1709 hdmi_submit_work(hdmi, HDMI_HPD_CHANGE, 20, NULL);
1714 hdmi_writel(hdmi_dev, IH_AS_SATA0, aud_int);
1715 hdmi_msk_reg(hdmi_dev, AUD_CONF0,
1716 m_SW_AUD_FIFO_RST, v_SW_AUD_FIFO_RST(1));
1717 hdmi_writel(hdmi_dev, MC_SWRSTZREQ, 0xF7);
1721 hdmi_writel(hdmi_dev, IH_CEC_STAT0, cec_int);
1722 rockchip_hdmiv2_cec_isr(hdmi_dev, cec_int);
1726 hdmi_writel(hdmi_dev, A_APIINTCLR, hdcp_int);
1727 rockchip_hdmiv2_hdcp_isr(hdmi_dev, hdcp_int);
1732 hdmi_writel(hdmi_dev, HDCP2REG_STAT, hdcp2_int);
1733 pr_info("hdcp2_int is 0x%02x\n", hdcp2_int);
1734 if ((hdcp2_int & m_HDCP2_AUTH_FAIL ||
1735 hdcp2_int & m_HDCP2_AUTH_LOST) &&
1736 hdmi_dev->hdcp2_start) {
1737 pr_info("hdcp2 failed or lost\n");
1738 hdmi_dev->hdcp2_start();