drivers/video/rockchip/hdmi/rockchip-hdmiv2/rockchip_hdmiv2_hw.c

   1 #include <linux/clk.h>
   2 #include <linux/delay.h>
   3 #include <linux/interrupt.h>
   4 #include <linux/rockchip/cru.h>
   5 #include <linux/rockchip/grf.h>
   6 #include <linux/rockchip/iomap.h>
   7 #include "rockchip_hdmiv2.h"
   8 #include "rockchip_hdmiv2_hw.h"
   9 #include <linux/rockchip/grf.h>
  10
  11 #define HDMI_SEL_LCDC(x, bit)   ((((x) & 1) << bit) | (1 << (16 + bit)))
  12 #define grf_writel(v, offset)   writel_relaxed(v, RK_GRF_VIRT + offset)
  13 #define RK3399_GRF_SOC_CON20 0x6250
  14
  15 static const struct phy_mpll_config_tab PHY_MPLL_TABLE[] = {
  16 /*      tmdsclk = (pixclk / ref_cntrl ) * (fbdiv2 * fbdiv1) / nctrl / tmdsmhl
  17  *      opmode: 0:HDMI1.4       1:HDMI2.0
  18  *
  19  *      |pixclock|      tmdsclock|pixrepet|colordepth|prepdiv|tmdsmhl|opmode|
  20  *              fbdiv2|fbdiv1|ref_cntrl|nctrl|propctrl|intctrl|gmpctrl|
  21  */
  22         {27000000,      27000000,       0,      8,      0,      0,      0,
  23                 2,      3,      0,      3,      3,      0,      0},
  24         {27000000,      27000000,       1,      8,      0,      0,      0,
  25                 2,      3,      0,      3,      3,      0,      0},
  26         {27000000,      33750000,       0,      10,     1,      0,      0,
  27                 5,      1,      0,      3,      3,      0,      0},
  28         {27000000,      33750000,       1,      10,     1,      0,      0,
  29                 5,      1,      0,      3,      3,      0,      0},
  30         {27000000,      40500000,       0,      12,     2,      0,      0,
  31                 3,      3,      0,      3,      3,      0,      0},
  32         {27000000,      54000000,       0,      16,     3,      0,      0,
  33                 2,      3,      0,      2,      5,      0,      1},
  34         {59400000,      59400000,       0,      8,      0,      0,      0,
  35                 1,      3,      0,      2,      5,      0,      1},
  36         {59400000,      74250000,       0,      10,     1,      0,      0,
  37                 5,      0,      0,      2,      5,      0,      1},
  38         {59400000,      89100000,       0,      12,     2,      0,      0,
  39                 2,      2,      0,      2,      5,      0,      1},
  40         {59400000,      118800000,      0,      16,     3,      0,      0,
  41                 1,      3,      0,      1,      7,      0,      2},
  42         {65000000,      65000000,       0,      8,      0,      0,      0,
  43                 1,      3,      0,      2,      5,      0,      1},
  44         {74250000,      74250000,       0,      8,      0,      0,      0,
  45                 4,      3,      3,      2,      7,      0,      3},
  46         {74250000,      92812500,       0,      10,     1,      0,      0,
  47                 5,      0,      1,      1,      7,      0,      2},
  48         {74250000,      111375000,      0,      12,     2,      0,      0,
  49                 1,      2,      0,      1,      7,      0,      2},
  50         {74250000,      148500000,      0,      16,     3,      0,      0,
  51                 1,      3,      0,      1,      7,      0,      2},
  52         {83500000,      83500000,       0,      8,      0,      0,      0,
  53                 1,      3,      0,      2,      5,      0,      1},
  54         {85500000,      85500000,       0,      8,      0,      0,      0,
  55                 1,      3,      0,      2,      5,      0,      1},
  56         {106500000,     106500000,      0,      8,      0,      0,      0,
  57                 1,      1,      0,      1,      7,      0,      2},
  58         {108000000,     108000000,      0,      8,      0,      0,      0,
  59                 1,      1,      0,      1,      7,      0,      2},
  60         {146250000,     146250000,      0,      8,      0,      0,      0,
  61                 1,      1,      0,      1,      7,      0,      2},
  62         {148500000,     74250000,       0,      8,      0,      0,      0,
  63                 1,      1,      1,      1,      0,      0,      3},
  64         {148500000,     148500000,      0,      8,      0,      0,      0,
  65                 1,      1,      0,      1,      0,      0,      3},
  66         {148500000,     185625000,      0,      10,     1,      0,      0,
  67                 5,      0,      3,      0,      7,      0,      3},
  68         {148500000,     222750000,      0,      12,     2,      0,      0,
  69                 1,      2,      1,      0,      7,      0,      3},
  70         {148500000,     297000000,      0,      16,     3,      0,      0,
  71                 1,      1,      0,      0,      7,      0,      3},
  72         {148500000,     297000000,      0,      8,      0,      0,      0,
  73                 1,      1,      0,      0,      0,      0,      3},
  74         {148500000,     594000000,      0,      8,      0,      3,      1,
  75                 1,      3,      0,      0,      0,      0,      3},
  76         {269390000,     269390000,      0,      8,      0,      0,      0,
  77                 1,      0,      0,      0,      0,      0,      3},
  78         {297000000,     148500000,      0,      8,      0,      0,      0,
  79                 1,      0,      1,      0,      0,      0,      3},
  80         {297000000,     297000000,      0,      8,      0,      0,      0,
  81                 1,      0,      0,      0,      0,      0,      3},
  82         {297000000,     371250000,      0,      10,     1,      3,      1,
  83                 5,      1,      3,      1,      7,      0,      3},
  84         {297000000,     445500000,      0,      12,     2,      3,      1,
  85                 1,      2,      0,      1,      7,      0,      3},
  86         {297000000,     594000000,      0,      16,     3,      3,      1,
  87                 1,      3,      1,      0,      0,      0,      3},
  88         {403000000,     403000000,      0,      8,      0,      3,      1,
  89                 1,      3,      3,      0,      0,      0,      3},
  90         {594000000,     297000000,      0,      8,      0,      0,      0,
  91                 1,      0,      1,      0,      0,      0,      3},
  92         {594000000,     371250000,      0,      10,     1,      3,      1,
  93                 5,      0,      3,      0,      7,      0,      3},
  94         {594000000,     445500000,      0,      12,     2,      3,      1,
  95                 1,      2,      1,      1,      7,      0,      3},
  96         {594000000,     594000000,      0,      16,     3,      3,      1,
  97                 1,      3,      3,      0,      0,      0,      3},
  98         {594000000,     594000000,      0,      8,      0,      3,      1,
  99                 1,      3,      3,      0,      0,      0,      3},
 100 };
 101
 102 static const struct ext_pll_config_tab EXT_PLL_TABLE[] = {
 103         {27000000,      27000000,       8,      1,      90,     3,      2,
 104                 2,      10,     3,      3,      4,      0,      1,      40,
 105                 8},
 106         {27000000,      33750000,       10,     1,      90,     1,      3,
 107                 3,      10,     3,      3,      4,      0,      1,      40,
 108                 8},
 109         {59400000,      59400000,       8,      1,      99,     3,      2,
 110                 2,      1,      3,      3,      4,      0,      1,      40,
 111                 8},
 112         {59400000,      74250000,       10,     1,      99,     1,      2,
 113                 2,      1,      3,      3,      4,      0,      1,      40,
 114                 8},
 115         {74250000,      74250000,       8,      1,      99,     1,      2,
 116                 2,      1,      2,      3,      4,      0,      1,      40,
 117                 8},
 118         {74250000,      92812500,       10,     4,      495,    1,      2,
 119                 2,      1,      3,      3,      4,      0,      2,      40,
 120                 4},
 121         {148500000,     148500000,      8,      1,      99,     1,      1,
 122                 1,      1,      2,      2,      2,      0,      2,      40,
 123                 4},
 124         {148500000,     185625000,      10,     4,      495,    0,      2,
 125                 2,      1,      3,      2,      2,      0,      4,      40,
 126                 2},
 127         {297000000,     297000000,      8,      1,      99,     0,      1,
 128                 1,      1,      0,      2,      2,      0,      4,      40,
 129                 2},
 130         {297000000,     371250000,      10,     4,      495,    1,      2,
 131                 0,      1,      3,      1,      1,      0,      8,      40,
 132                 1},
 133         {594000000,     297000000,      8,      1,      99,     0,      1,
 134                 1,      1,      0,      2,      1,      0,      4,      40,
 135                 2},
 136         {594000000,     371250000,      10,     4,      495,    1,      2,
 137                 0,      1,      3,      1,      1,      1,      8,      40,
 138                 1},
 139         {594000000,     594000000,      8,      1,      99,     0,      2,
 140                 0,      1,      0,      1,      1,      0,      8,      40,
 141                 1},
 142 };
 143
 144 /* ddc i2c master reset */
 145 static void rockchip_hdmiv2_i2cm_reset(struct hdmi_dev *hdmi_dev)
 146 {
 147         hdmi_msk_reg(hdmi_dev, I2CM_SOFTRSTZ,
 148                      m_I2CM_SOFTRST, v_I2CM_SOFTRST(0));
 149         usleep_range(90, 100);
 150 }
 151
 152 /*set read/write offset,set read/write mode*/
 153 static void rockchip_hdmiv2_i2cm_write_request(struct hdmi_dev *hdmi_dev,
 154                                                u8 offset, u8 data)
 155 {
 156         hdmi_writel(hdmi_dev, I2CM_ADDRESS, offset);
 157         hdmi_writel(hdmi_dev, I2CM_DATAO, data);
 158         hdmi_msk_reg(hdmi_dev, I2CM_OPERATION, m_I2CM_WR, v_I2CM_WR(1));
 159 }
 160
 161 static void rockchip_hdmiv2_i2cm_read_request(struct hdmi_dev *hdmi_dev,
 162                                               u8 offset)
 163 {
 164         hdmi_writel(hdmi_dev, I2CM_ADDRESS, offset);
 165         hdmi_msk_reg(hdmi_dev, I2CM_OPERATION, m_I2CM_RD, v_I2CM_RD(1));
 166 }
 167
 168 static void rockchip_hdmiv2_i2cm_write_data(struct hdmi_dev *hdmi_dev,
 169                                             u8 data, u8 offset)
 170 {
 171         u8 interrupt = 0;
 172         int trytime = 2;
 173         int i = 20;
 174
 175         while (trytime-- > 0) {
 176                 rockchip_hdmiv2_i2cm_write_request(hdmi_dev, offset, data);
 177                 while (i--) {
 178                         usleep_range(900, 1000);
 179                         interrupt = hdmi_readl(hdmi_dev, IH_I2CM_STAT0);
 180                         if (interrupt)
 181                                 hdmi_writel(hdmi_dev,
 182                                             IH_I2CM_STAT0, interrupt);
 183
 184                         if (interrupt & (m_SCDC_READREQ |
 185                                          m_I2CM_DONE | m_I2CM_ERROR))
 186                                 break;
 187                 }
 188
 189                 if (interrupt & m_I2CM_DONE) {
 190                         dev_dbg(hdmi_dev->hdmi->dev,
 191                                 "[%s] write offset %02x data %02x success\n",
 192                                 __func__, offset, data);
 193                         trytime = 0;
 194                 } else if ((interrupt & m_I2CM_ERROR) || (i == -1)) {
 195                         dev_err(hdmi_dev->hdmi->dev,
 196                                 "[%s] write data error\n", __func__);
 197                         rockchip_hdmiv2_i2cm_reset(hdmi_dev);
 198                 }
 199         }
 200 }
 201
 202 static int rockchip_hdmiv2_i2cm_read_data(struct hdmi_dev *hdmi_dev, u8 offset)
 203 {
 204         u8 interrupt = 0, val;
 205         int trytime = 2;
 206         int i = 20;
 207
 208         while (trytime-- > 0) {
 209                 rockchip_hdmiv2_i2cm_read_request(hdmi_dev, offset);
 210                 while (i--) {
 211                         usleep_range(900, 1000);
 212                         interrupt = hdmi_readl(hdmi_dev, IH_I2CM_STAT0);
 213                         if (interrupt)
 214                                 hdmi_writel(hdmi_dev, IH_I2CM_STAT0, interrupt);
 215
 216                         if (interrupt & (m_SCDC_READREQ |
 217                                 m_I2CM_DONE | m_I2CM_ERROR))
 218                                 break;
 219                 }
 220
 221                 if (interrupt & m_I2CM_DONE) {
 222                         val = hdmi_readl(hdmi_dev, I2CM_DATAI);
 223                         trytime = 0;
 224                 } else if ((interrupt & m_I2CM_ERROR) || (i == -1)) {
 225                         pr_err("[%s] read data error\n", __func__);
 226                         rockchip_hdmiv2_i2cm_reset(hdmi_dev);
 227                 }
 228         }
 229         return val;
 230 }
 231
 232 static void rockchip_hdmiv2_i2cm_mask_int(struct hdmi_dev *hdmi_dev, int mask)
 233 {
 234         if (!mask) {
 235                 hdmi_msk_reg(hdmi_dev, I2CM_INT,
 236                              m_I2CM_DONE_MASK, v_I2CM_DONE_MASK(0));
 237                 hdmi_msk_reg(hdmi_dev, I2CM_CTLINT,
 238                              m_I2CM_NACK_MASK | m_I2CM_ARB_MASK,
 239                              v_I2CM_NACK_MASK(0) | v_I2CM_ARB_MASK(0));
 240         } else {
 241                 hdmi_msk_reg(hdmi_dev, I2CM_INT,
 242                              m_I2CM_DONE_MASK, v_I2CM_DONE_MASK(1));
 243                 hdmi_msk_reg(hdmi_dev, I2CM_CTLINT,
 244                              m_I2CM_NACK_MASK | m_I2CM_ARB_MASK,
 245                              v_I2CM_NACK_MASK(1) | v_I2CM_ARB_MASK(1));
 246         }
 247 }
 248
 249 #define I2C_DIV_FACTOR 1000000
 250 static u16 i2c_count(u16 sfrclock, u16 sclmintime)
 251 {
 252         unsigned long tmp_scl_period = 0;
 253
 254         if (((sfrclock * sclmintime) % I2C_DIV_FACTOR) != 0)
 255                 tmp_scl_period = (unsigned long)((sfrclock * sclmintime) +
 256                                 (I2C_DIV_FACTOR - ((sfrclock * sclmintime) %
 257                                 I2C_DIV_FACTOR))) / I2C_DIV_FACTOR;
 258         else
 259                 tmp_scl_period = (unsigned long)(sfrclock * sclmintime) /
 260                                 I2C_DIV_FACTOR;
 261
 262         return (u16)(tmp_scl_period);
 263 }
 264
 265 #define EDID_I2C_MIN_SS_SCL_HIGH_TIME   9625
 266 #define EDID_I2C_MIN_SS_SCL_LOW_TIME    10000
 267
 268 static void rockchip_hdmiv2_i2cm_clk_init(struct hdmi_dev *hdmi_dev)
 269 {
 270         int value;
 271
 272         /* Set DDC I2C CLK which divided from DDC_CLK. */
 273         value = i2c_count(24000, EDID_I2C_MIN_SS_SCL_HIGH_TIME);
 274         hdmi_writel(hdmi_dev, I2CM_SS_SCL_HCNT_0_ADDR,
 275                     value & 0xff);
 276         hdmi_writel(hdmi_dev, I2CM_SS_SCL_HCNT_1_ADDR,
 277                     (value >> 8) & 0xff);
 278         value = i2c_count(24000, EDID_I2C_MIN_SS_SCL_LOW_TIME);
 279         hdmi_writel(hdmi_dev, I2CM_SS_SCL_LCNT_0_ADDR,
 280                     value & 0xff);
 281         hdmi_writel(hdmi_dev, I2CM_SS_SCL_LCNT_1_ADDR,
 282                     (value >> 8) & 0xff);
 283         hdmi_msk_reg(hdmi_dev, I2CM_DIV, m_I2CM_FAST_STD_MODE,
 284                      v_I2CM_FAST_STD_MODE(STANDARD_MODE));
 285 }
 286
 287 static int rockchip_hdmiv2_scdc_get_sink_version(struct hdmi_dev *hdmi_dev)
 288 {
 289         return rockchip_hdmiv2_i2cm_read_data(hdmi_dev, SCDC_SINK_VER);
 290 }
 291
 292 static void rockchip_hdmiv2_scdc_set_source_version(struct hdmi_dev *hdmi_dev,
 293                                                     u8 version)
 294 {
 295         rockchip_hdmiv2_i2cm_write_data(hdmi_dev, version, SCDC_SOURCE_VER);
 296 }
 297
 298 static void rockchip_hdmiv2_scdc_read_request(struct hdmi_dev *hdmi_dev,
 299                                               int enable)
 300 {
 301         hdmi_msk_reg(hdmi_dev, I2CM_SCDC_READ_UPDATE,
 302                      m_I2CM_READ_REQ_EN, v_I2CM_READ_REQ_EN(enable));
 303         rockchip_hdmiv2_i2cm_write_data(hdmi_dev, enable, SCDC_CONFIG_0);
 304 }
 305
 306 #ifdef HDMI_20_SCDC
 307 static void rockchip_hdmiv2_scdc_update_read(struct hdmi_dev *hdmi_dev)
 308 {
 309         hdmi_msk_reg(hdmi_dev, I2CM_SCDC_READ_UPDATE,
 310                      m_I2CM_READ_UPDATE, v_I2CM_READ_UPDATE(1));
 311 }
 312
 313 static int rockchip_hdmiv2_scdc_get_scambling_status(struct hdmi_dev *hdmi_dev)
 314 {
 315         int val;
 316
 317         val = rockchip_hdmiv2_i2cm_read_data(hdmi_dev, SCDC_SCRAMBLER_STAT);
 318         return val;
 319 }
 320
 321 static void rockchip_hdmiv2_scdc_enable_polling(struct hdmi_dev *hdmi_dev,
 322                                                 int enable)
 323 {
 324         rockchip_hdmiv2_scdc_read_request(hdmi_dev, enable);
 325         hdmi_msk_reg(hdmi_dev, I2CM_SCDC_READ_UPDATE,
 326                      m_I2CM_UPRD_VSYNC_EN, v_I2CM_UPRD_VSYNC_EN(enable));
 327 }
 328
 329 static int rockchip_hdmiv2_scdc_get_status_reg0(struct hdmi_dev *hdmi_dev)
 330 {
 331         rockchip_hdmiv2_scdc_read_request(hdmi_dev, 1);
 332         rockchip_hdmiv2_scdc_update_read(hdmi_dev);
 333         return hdmi_readl(hdmi_dev, I2CM_SCDC_UPDATE0);
 334 }
 335
 336 static int rockchip_hdmiv2_scdc_get_status_reg1(struct hdmi_dev *hdmi_dev)
 337 {
 338         rockchip_hdmiv2_scdc_read_request(hdmi_dev, 1);
 339         rockchip_hdmiv2_scdc_update_read(hdmi_dev);
 340         return hdmi_readl(hdmi_dev, I2CM_SCDC_UPDATE1);
 341 }
 342 #endif
 343
 344 static void rockchip_hdmiv2_scdc_init(struct hdmi_dev *hdmi_dev)
 345 {
 346         rockchip_hdmiv2_i2cm_reset(hdmi_dev);
 347         rockchip_hdmiv2_i2cm_mask_int(hdmi_dev, 1);
 348         rockchip_hdmiv2_i2cm_clk_init(hdmi_dev);
 349         /* set scdc i2c addr */
 350         hdmi_writel(hdmi_dev, I2CM_SLAVE, DDC_I2C_SCDC_ADDR);
 351         rockchip_hdmiv2_i2cm_mask_int(hdmi_dev, 0);/*enable interrupt*/
 352 }
 353
 354 static void rockchip_hdmiv2_scdc_set_tmds_rate(struct hdmi_dev *hdmi_dev)
 355 {
 356         int stat;
 357
 358         mutex_lock(&hdmi_dev->ddc_lock);
 359         rockchip_hdmiv2_scdc_init(hdmi_dev);
 360         stat = rockchip_hdmiv2_i2cm_read_data(hdmi_dev,
 361                                               SCDC_TMDS_CONFIG);
 362         if (hdmi_dev->tmdsclk > 340000000)
 363                 stat |= 2;
 364         else
 365                 stat &= 0x1;
 366         rockchip_hdmiv2_i2cm_write_data(hdmi_dev,
 367                                         stat, SCDC_TMDS_CONFIG);
 368         mutex_unlock(&hdmi_dev->ddc_lock);
 369 }
 370
 371 static int rockchip_hdmiv2_scrambling_enable(struct hdmi_dev *hdmi_dev,
 372                                              int enable)
 373 {
 374         HDMIDBG("%s enable %d\n", __func__, enable);
 375         if (enable == 1) {
 376                 /* Write on Rx the bit Scrambling_Enable, register 0x20 */
 377                 rockchip_hdmiv2_i2cm_write_data(hdmi_dev, 1, SCDC_TMDS_CONFIG);
 378                 /* TMDS software reset request */
 379                 hdmi_msk_reg(hdmi_dev, MC_SWRSTZREQ,
 380                              m_TMDS_SWRST, v_TMDS_SWRST(0));
 381                 /* Enable/Disable Scrambling */
 382                 hdmi_msk_reg(hdmi_dev, FC_SCRAMBLER_CTRL,
 383                              m_FC_SCRAMBLE_EN, v_FC_SCRAMBLE_EN(1));
 384         } else {
 385                 /* Enable/Disable Scrambling */
 386                 hdmi_msk_reg(hdmi_dev, FC_SCRAMBLER_CTRL,
 387                              m_FC_SCRAMBLE_EN, v_FC_SCRAMBLE_EN(0));
 388                 /* TMDS software reset request */
 389                 hdmi_msk_reg(hdmi_dev, MC_SWRSTZREQ,
 390                              m_TMDS_SWRST, v_TMDS_SWRST(0));
 391                 /* Write on Rx the bit Scrambling_Enable, register 0x20 */
 392                 rockchip_hdmiv2_i2cm_write_data(hdmi_dev, 0, SCDC_TMDS_CONFIG);
 393         }
 394         return 0;
 395 }
 396
 397 static const struct ext_pll_config_tab *get_phy_ext_tab(
 398                 unsigned int pixclock, unsigned int tmdsclk,
 399                 char colordepth)
 400 {
 401         int i;
 402
 403         if (pixclock == 0)
 404                 return NULL;
 405         HDMIDBG("%s pixClock %u tmdsclk %u colorDepth %d\n",
 406                 __func__, pixclock, tmdsclk, colordepth);
 407         for (i = 0; i < ARRAY_SIZE(EXT_PLL_TABLE); i++) {
 408                 if ((EXT_PLL_TABLE[i].pix_clock == pixclock) &&
 409                     (EXT_PLL_TABLE[i].tmdsclock == tmdsclk) &&
 410                     (EXT_PLL_TABLE[i].color_depth == colordepth))
 411                         return &EXT_PLL_TABLE[i];
 412         }
 413         return NULL;
 414 }
 415
 416 static const struct phy_mpll_config_tab *get_phy_mpll_tab(
 417                 unsigned int pixclock, unsigned int tmdsclk,
 418                 char pixrepet, char colordepth)
 419 {
 420         int i;
 421
 422         if (pixclock == 0)
 423                 return NULL;
 424         HDMIDBG("%s pixClock %u tmdsclk %u pixRepet %d colorDepth %d\n",
 425                 __func__, pixclock, tmdsclk, pixrepet, colordepth);
 426         for (i = 0; i < ARRAY_SIZE(PHY_MPLL_TABLE); i++) {
 427                 if ((PHY_MPLL_TABLE[i].pix_clock == pixclock) &&
 428                     (PHY_MPLL_TABLE[i].tmdsclock == tmdsclk) &&
 429                     (PHY_MPLL_TABLE[i].pix_repet == pixrepet) &&
 430                     (PHY_MPLL_TABLE[i].color_depth == colordepth))
 431                         return &PHY_MPLL_TABLE[i];
 432         }
 433         return NULL;
 434 }
 435
 436 static void rockchip_hdmiv2_powerdown(struct hdmi_dev *hdmi_dev)
 437 {
 438         hdmi_msk_reg(hdmi_dev, PHY_MASK, m_PHY_LOCK, v_PHY_LOCK(1));
 439         if (hdmi_dev->soctype != HDMI_SOC_RK322X) {
 440                 hdmi_msk_reg(hdmi_dev, PHY_CONF0,
 441                              m_PDDQ_SIG | m_TXPWRON_SIG |
 442                              m_ENHPD_RXSENSE_SIG | m_SVSRET_SIG,
 443                              v_PDDQ_SIG(1) | v_TXPWRON_SIG(0) |
 444                              v_ENHPD_RXSENSE_SIG(1)) | v_SVSRET_SIG(0);
 445         } else {
 446                 hdmi_msk_reg(hdmi_dev, PHY_CONF0,
 447                              m_TXPWRON_SIG | m_ENHPD_RXSENSE_SIG,
 448                              v_TXPWRON_SIG(0) | v_ENHPD_RXSENSE_SIG(0));
 449                 regmap_write(hdmi_dev->grf_base,
 450                              RK322X_GRF_SOC_CON2,
 451                              RK322X_PLL_PDATA_DEN);
 452         }
 453         hdmi_writel(hdmi_dev, MC_CLKDIS, 0x7f);
 454 }
 455
 456 int rockchip_hdmiv2_write_phy(struct hdmi_dev *hdmi_dev,
 457                               int reg_addr, int val)
 458 {
 459         int trytime = 2, i = 0, op_status = 0;
 460
 461         if (hdmi_dev->phybase) {
 462                 writel_relaxed(val, hdmi_dev->phybase + (reg_addr) * 0x04);
 463                 return 0;
 464         }
 465         while (trytime--) {
 466                 hdmi_writel(hdmi_dev, PHY_I2CM_ADDRESS, reg_addr);
 467                 hdmi_writel(hdmi_dev, PHY_I2CM_DATAO_1, (val >> 8) & 0xff);
 468                 hdmi_writel(hdmi_dev, PHY_I2CM_DATAO_0, val & 0xff);
 469                 hdmi_writel(hdmi_dev, PHY_I2CM_OPERATION, m_PHY_I2CM_WRITE);
 470
 471                 i = 20;
 472                 while (i--) {
 473                         usleep_range(900, 1000);
 474                         op_status = hdmi_readl(hdmi_dev, IH_I2CMPHY_STAT0);
 475                         if (op_status)
 476                                 hdmi_writel(hdmi_dev,
 477                                             IH_I2CMPHY_STAT0,
 478                                             op_status);
 479
 480                         if (op_status & (m_I2CMPHY_DONE | m_I2CMPHY_ERR))
 481                                 break;
 482                 }
 483
 484                 if (!(op_status & m_I2CMPHY_DONE))
 485                         dev_err(hdmi_dev->hdmi->dev,
 486                                 "[%s] operation error,trytime=%d\n",
 487                                 __func__, trytime);
 488                 else
 489                         return 0;
 490                 msleep(100);
 491         }
 492
 493         return -1;
 494 }
 495
 496 int rockchip_hdmiv2_read_phy(struct hdmi_dev *hdmi_dev,
 497                              int reg_addr)
 498 {
 499         int trytime = 2, i = 0, op_status = 0;
 500         int val = 0;
 501
 502         if (hdmi_dev->phybase)
 503                 return readl_relaxed(hdmi_dev->phybase + (reg_addr) * 0x04);
 504
 505         while (trytime--) {
 506                 hdmi_writel(hdmi_dev, PHY_I2CM_ADDRESS, reg_addr);
 507                 hdmi_writel(hdmi_dev, PHY_I2CM_DATAI_1, 0x00);
 508                 hdmi_writel(hdmi_dev, PHY_I2CM_DATAI_0, 0x00);
 509                 hdmi_writel(hdmi_dev, PHY_I2CM_OPERATION, m_PHY_I2CM_READ);
 510
 511                 i = 20;
 512                 while (i--) {
 513                         usleep_range(900, 1000);
 514                         op_status = hdmi_readl(hdmi_dev, IH_I2CMPHY_STAT0);
 515                         if (op_status)
 516                                 hdmi_writel(hdmi_dev, IH_I2CMPHY_STAT0,
 517                                             op_status);
 518
 519                         if (op_status & (m_I2CMPHY_DONE | m_I2CMPHY_ERR))
 520                                 break;
 521                 }
 522
 523                 if (!(op_status & m_I2CMPHY_DONE)) {
 524                         pr_err("[%s] operation error,trytime=%d\n",
 525                                __func__, trytime);
 526                 } else {
 527                         val = hdmi_readl(hdmi_dev, PHY_I2CM_DATAI_1);
 528                         val = (val & 0xff) << 8;
 529                         val += (hdmi_readl(hdmi_dev, PHY_I2CM_DATAI_0) & 0xff);
 530                         pr_debug("phy_reg0x%02x: 0x%04x",
 531                                  reg_addr, val);
 532                         return val;
 533                 }
 534                 msleep(100);
 535         }
 536
 537         return -1;
 538 }
 539
 540 #define PHY_TIMEOUT     10000
 541
 542 static int ext_phy_config(struct hdmi_dev *hdmi_dev)
 543 {
 544         int stat = 0, i = 0, temp;
 545         const struct ext_pll_config_tab *phy_ext = NULL;
 546
 547         if (hdmi_dev->grf_base)
 548                 regmap_write(hdmi_dev->grf_base,
 549                              RK322X_GRF_SOC_CON2,
 550                              RK322X_PLL_POWER_DOWN |
 551                              RK322X_PLL_PDATA_DEN);
 552         if (hdmi_dev->tmdsclk_ratio_change &&
 553             hdmi_dev->hdmi->edid.scdc_present == 1)
 554                 rockchip_hdmiv2_scdc_set_tmds_rate(hdmi_dev);
 555
 556         /* config the required PHY I2C register */
 557         phy_ext = get_phy_ext_tab(hdmi_dev->pixelclk,
 558                                   hdmi_dev->tmdsclk,
 559                                   hdmi_dev->colordepth);
 560         if (phy_ext) {
 561                 stat = ((phy_ext->pll_nf >> 1) & EXT_PHY_PLL_FB_BIT8_MASK) |
 562                        ((phy_ext->vco_div_5 & 1) << 5) |
 563                        (phy_ext->pll_nd & EXT_PHY_PLL_PRE_DIVIDER_MASK);
 564                 rockchip_hdmiv2_write_phy(hdmi_dev,
 565                                           EXT_PHY_PLL_PRE_DIVIDER, stat);
 566                 stat = phy_ext->pll_nf & 0xff;
 567                 rockchip_hdmiv2_write_phy(hdmi_dev,
 568                                           EXT_PHY_PLL_FB_DIVIDER, stat);
 569                 stat = (phy_ext->pclk_divider_a & EXT_PHY_PCLK_DIVIDERA_MASK) |
 570                        ((phy_ext->pclk_divider_b & 3) << 5);
 571                 rockchip_hdmiv2_write_phy(hdmi_dev,
 572                                           EXT_PHY_PCLK_DIVIDER1, stat);
 573                 stat = (phy_ext->pclk_divider_d & EXT_PHY_PCLK_DIVIDERD_MASK) |
 574                        ((phy_ext->pclk_divider_c & 3) << 5);
 575                 rockchip_hdmiv2_write_phy(hdmi_dev,
 576                                           EXT_PHY_PCLK_DIVIDER2, stat);
 577                 stat = ((phy_ext->tmsd_divider_c & 3) << 4) |
 578                        ((phy_ext->tmsd_divider_a & 3) << 2) |
 579                        (phy_ext->tmsd_divider_b & 3);
 580                 rockchip_hdmiv2_write_phy(hdmi_dev,
 581                                           EXT_PHY_TMDSCLK_DIVIDER, stat);
 582                 rockchip_hdmiv2_write_phy(hdmi_dev,
 583                                           EXT_PHY_PPLL_FB_DIVIDER,
 584                                           phy_ext->ppll_nf);
 585
 586                 if (phy_ext->ppll_no == 1) {
 587                         rockchip_hdmiv2_write_phy(hdmi_dev,
 588                                                   EXT_PHY_PPLL_POST_DIVIDER,
 589                                                   0);
 590                         stat = 0x20 | phy_ext->ppll_nd;
 591                         rockchip_hdmiv2_write_phy(hdmi_dev,
 592                                                   EXT_PHY_PPLL_PRE_DIVIDER,
 593                                                   stat);
 594                 } else {
 595                         stat = ((phy_ext->ppll_no / 2) - 1) << 4;
 596                         rockchip_hdmiv2_write_phy(hdmi_dev,
 597                                                   EXT_PHY_PPLL_POST_DIVIDER,
 598                                                   stat);
 599                         stat = 0xe0 | phy_ext->ppll_nd;
 600                         rockchip_hdmiv2_write_phy(hdmi_dev,
 601                                                   EXT_PHY_PPLL_PRE_DIVIDER,
 602                                                   stat);
 603                 }
 604         } else {
 605                 pr_err("%s no supported phy configuration.\n", __func__);
 606                 return -1;
 607         }
 608
 609         if (hdmi_dev->phy_table) {
 610                 for (i = 0; i < hdmi_dev->phy_table_size; i++) {
 611                         temp = hdmi_dev->phy_table[i].maxfreq;
 612                         if (hdmi_dev->tmdsclk <= temp)
 613                                 break;
 614                 }
 615         }
 616
 617         if (i != hdmi_dev->phy_table_size) {
 618                 if (hdmi_dev->phy_table[i].slopeboost) {
 619                         rockchip_hdmiv2_write_phy(hdmi_dev,
 620                                                   EXT_PHY_SIGNAL_CTRL, 0xff);
 621                         temp = hdmi_dev->phy_table[i].slopeboost - 1;
 622                         stat = ((temp & 3) << 6) | ((temp & 3) << 4) |
 623                                ((temp & 3) << 2) | (temp & 3);
 624                         rockchip_hdmiv2_write_phy(hdmi_dev,
 625                                                   EXT_PHY_SLOPEBOOST, stat);
 626                 } else {
 627                         rockchip_hdmiv2_write_phy(hdmi_dev,
 628                                                   EXT_PHY_SIGNAL_CTRL, 0x0f);
 629                 }
 630                 stat = ((hdmi_dev->phy_table[i].pre_emphasis & 3) << 4) |
 631                        ((hdmi_dev->phy_table[i].pre_emphasis & 3) << 2) |
 632                        (hdmi_dev->phy_table[i].pre_emphasis & 3);
 633                 rockchip_hdmiv2_write_phy(hdmi_dev,
 634                                           EXT_PHY_PREEMPHASIS, stat);
 635                 stat = ((hdmi_dev->phy_table[i].clk_level & 0xf) << 4) |
 636                        (hdmi_dev->phy_table[i].data2_level & 0xf);
 637                 rockchip_hdmiv2_write_phy(hdmi_dev,
 638                                           EXT_PHY_LEVEL1, stat);
 639                 stat = ((hdmi_dev->phy_table[i].data1_level & 0xf) << 4) |
 640                        (hdmi_dev->phy_table[i].data0_level & 0xf);
 641                 rockchip_hdmiv2_write_phy(hdmi_dev,
 642                                           EXT_PHY_LEVEL2, stat);
 643         } else {
 644                 rockchip_hdmiv2_write_phy(hdmi_dev,
 645                                           EXT_PHY_SIGNAL_CTRL, 0x0f);
 646         }
 647         rockchip_hdmiv2_write_phy(hdmi_dev, 0xf3, 0x22);
 648
 649         stat = clk_get_rate(hdmi_dev->pclk_phy) / 100000;
 650         rockchip_hdmiv2_write_phy(hdmi_dev, EXT_PHY_TERM_CAL,
 651                                   ((stat >> 8) & 0xff) | 0x80);
 652         rockchip_hdmiv2_write_phy(hdmi_dev, EXT_PHY_TERM_CAL_DIV_L,
 653                                   stat & 0xff);
 654         if (hdmi_dev->tmdsclk > 340000000)
 655                 stat = EXT_PHY_AUTO_R100_OHMS;
 656         else if (hdmi_dev->tmdsclk > 200000000)
 657                 stat = EXT_PHY_AUTO_R50_OHMS;
 658         else
 659                 stat = EXT_PHY_AUTO_ROPEN_CIRCUIT;
 660         rockchip_hdmiv2_write_phy(hdmi_dev, EXT_PHY_TERM_RESIS_AUTO,
 661                                   stat | 0x20);
 662         rockchip_hdmiv2_write_phy(hdmi_dev, EXT_PHY_TERM_CAL,
 663                                   (stat >> 8) & 0xff);
 664         if (hdmi_dev->tmdsclk > 200000000)
 665                 stat = 0;
 666         else
 667                 stat = 0x11;
 668         rockchip_hdmiv2_write_phy(hdmi_dev, EXT_PHY_PLL_BW, stat);
 669         rockchip_hdmiv2_write_phy(hdmi_dev, EXT_PHY_PPLL_BW, 0x27);
 670         if (hdmi_dev->grf_base)
 671                 regmap_write(hdmi_dev->grf_base,
 672                              RK322X_GRF_SOC_CON2,
 673                              RK322X_PLL_POWER_UP);
 674         if (hdmi_dev->tmdsclk_ratio_change)
 675                 msleep(100);
 676         else
 677                 usleep_range(900, 1000);
 678         hdmi_msk_reg(hdmi_dev, PHY_CONF0,
 679                      m_TXPWRON_SIG, v_TXPWRON_SIG(1));
 680         i = 0;
 681         while (i++ < PHY_TIMEOUT) {
 682                 if ((i % 10) == 0) {
 683                         temp = EXT_PHY_PPLL_POST_DIVIDER;
 684                         stat = rockchip_hdmiv2_read_phy(hdmi_dev, temp);
 685                         if (stat & EXT_PHY_PPLL_LOCK_STATUS_MASK)
 686                                 break;
 687                         usleep_range(1000, 2000);
 688                 }
 689         }
 690         if ((stat & EXT_PHY_PPLL_LOCK_STATUS_MASK) == 0) {
 691                 stat = hdmi_readl(hdmi_dev, MC_LOCKONCLOCK);
 692                 dev_err(hdmi_dev->hdmi->dev,
 693                         "PHY PLL not locked: PCLK_ON=%ld,TMDSCLK_ON=%ld\n",
 694                         (stat & m_PCLK_ON) >> 6, (stat & m_TMDSCLK_ON) >> 5);
 695                 return -1;
 696         }
 697
 698         if (hdmi_dev->grf_base)
 699                 regmap_write(hdmi_dev->grf_base,
 700                              RK322X_GRF_SOC_CON2,
 701                              RK322X_PLL_PDATA_EN);
 702
 703         return 0;
 704 }
 705
 706 static int rockchip_hdmiv2_config_phy(struct hdmi_dev *hdmi_dev)
 707 {
 708         int stat = 0, i = 0;
 709         const struct phy_mpll_config_tab *phy_mpll = NULL;
 710
 711         if (hdmi_dev->soctype == HDMI_SOC_RK322X) {
 712                 return ext_phy_config(hdmi_dev);
 713         } else if (hdmi_dev->soctype == HDMI_SOC_RK3366) {
 714                 if (hdmi_dev->pixelclk > 148500000)
 715                         clk_set_rate(hdmi_dev->pclk_phy, 148500000);
 716                 else
 717                         clk_set_rate(hdmi_dev->pclk_phy, hdmi_dev->pixelclk);
 718         } else if (hdmi_dev->soctype == HDMI_SOC_RK3399) {
 719                 clk_set_rate(hdmi_dev->pclk_phy, hdmi_dev->pixelclk);
 720         }
 721
 722         hdmi_msk_reg(hdmi_dev, PHY_I2CM_DIV,
 723                      m_PHY_I2CM_FAST_STD, v_PHY_I2CM_FAST_STD(0));
 724         hdmi_msk_reg(hdmi_dev, PHY_MASK, m_PHY_LOCK, v_PHY_LOCK(1));
 725         /* power off PHY */
 726         hdmi_msk_reg(hdmi_dev, PHY_CONF0,
 727                      m_PDDQ_SIG | m_TXPWRON_SIG | m_SVSRET_SIG,
 728                      v_PDDQ_SIG(1) | v_TXPWRON_SIG(0) | v_SVSRET_SIG(1));
 729
 730         if (hdmi_dev->tmdsclk_ratio_change &&
 731             hdmi_dev->hdmi->edid.scdc_present == 1)
 732                 rockchip_hdmiv2_scdc_set_tmds_rate(hdmi_dev);
 733
 734         /* reset PHY */
 735         hdmi_writel(hdmi_dev, MC_PHYRSTZ, v_PHY_RSTZ(1));
 736         usleep_range(1000, 2000);
 737         hdmi_writel(hdmi_dev, MC_PHYRSTZ, v_PHY_RSTZ(0));
 738
 739         /* Set slave address as PHY GEN2 address */
 740         hdmi_writel(hdmi_dev, PHY_I2CM_SLAVE, PHY_GEN2_ADDR);
 741
 742         /* config the required PHY I2C register */
 743         if (hdmi_dev->soctype == HDMI_SOC_RK3366 &&
 744             hdmi_dev->pixelclk > 148500000)
 745                 phy_mpll = get_phy_mpll_tab(148500000,
 746                                             hdmi_dev->tmdsclk,
 747                                             hdmi_dev->pixelrepeat - 1,
 748                                             hdmi_dev->colordepth);
 749         else
 750                 phy_mpll = get_phy_mpll_tab(hdmi_dev->pixelclk,
 751                                             hdmi_dev->tmdsclk,
 752                                             hdmi_dev->pixelrepeat - 1,
 753                                             hdmi_dev->colordepth);
 754         if (phy_mpll) {
 755                 rockchip_hdmiv2_write_phy(hdmi_dev, PHYTX_OPMODE_PLLCFG,
 756                                           v_PREP_DIV(phy_mpll->prep_div) |
 757                                           v_TMDS_CNTRL(
 758                                           phy_mpll->tmdsmhl_cntrl) |
 759                                           v_OPMODE(phy_mpll->opmode) |
 760                                           v_FBDIV2_CNTRL(
 761                                           phy_mpll->fbdiv2_cntrl) |
 762                                           v_FBDIV1_CNTRL(
 763                                           phy_mpll->fbdiv1_cntrl) |
 764                                           v_REF_CNTRL(phy_mpll->ref_cntrl) |
 765                                           v_MPLL_N_CNTRL(phy_mpll->n_cntrl));
 766                 rockchip_hdmiv2_write_phy(hdmi_dev, PHYTX_PLLCURRCTRL,
 767                                           v_MPLL_PROP_CNTRL(
 768                                           phy_mpll->prop_cntrl) |
 769                                           v_MPLL_INT_CNTRL(
 770                                           phy_mpll->int_cntrl));
 771                 rockchip_hdmiv2_write_phy(hdmi_dev, PHYTX_PLLGMPCTRL,
 772                                           v_MPLL_GMP_CNTRL(
 773                                           phy_mpll->gmp_cntrl));
 774         }
 775
 776         if (hdmi_dev->phy_table) {
 777                 for (i = 0; i < hdmi_dev->phy_table_size; i++)
 778                         if (hdmi_dev->tmdsclk <= hdmi_dev->phy_table[i].maxfreq)
 779                                 break;
 780         }
 781         if (i == hdmi_dev->phy_table_size) {
 782                 pr_info("%s use default phy settings\n", __func__);
 783                 rockchip_hdmiv2_write_phy(hdmi_dev, PHYTX_CLKSYMCTRL,
 784                                           v_OVERRIDE(1) | v_SLOPEBOOST(0) |
 785                                           v_TX_SYMON(1) | v_CLK_SYMON(1) |
 786                                           v_PREEMPHASIS(0));
 787                 if (hdmi_dev->tmdsclk > 340000000)
 788                         rockchip_hdmiv2_write_phy(hdmi_dev, PHYTX_VLEVCTRL,
 789                                                   v_SUP_TXLVL(9) |
 790                                                   v_SUP_CLKLVL(17));
 791                 else if (hdmi_dev->tmdsclk > 165000000)
 792                         rockchip_hdmiv2_write_phy(hdmi_dev,
 793                                                   PHYTX_VLEVCTRL,
 794                                                   v_SUP_TXLVL(14) |
 795                                                   v_SUP_CLKLVL(17));
 796                 else
 797                         rockchip_hdmiv2_write_phy(hdmi_dev,
 798                                                   PHYTX_VLEVCTRL,
 799                                                   v_SUP_TXLVL(18) |
 800                                                   v_SUP_CLKLVL(17));
 801         } else {
 802                 stat = v_OVERRIDE(1) | v_TX_SYMON(1) | v_CLK_SYMON(1) |
 803                        v_PREEMPHASIS(hdmi_dev->phy_table[i].pre_emphasis) |
 804                        v_SLOPEBOOST(hdmi_dev->phy_table[i].slopeboost);
 805                 rockchip_hdmiv2_write_phy(hdmi_dev, PHYTX_CLKSYMCTRL, stat);
 806
 807                 stat = v_SUP_CLKLVL(hdmi_dev->phy_table[i].clk_level) |
 808                        v_SUP_TXLVL(hdmi_dev->phy_table[i].data0_level);
 809                 rockchip_hdmiv2_write_phy(hdmi_dev, PHYTX_VLEVCTRL, stat);
 810         }
 811
 812         if (hdmi_dev->tmdsclk > 340000000)
 813                 rockchip_hdmiv2_write_phy(hdmi_dev, PHYTX_TERM_RESIS,
 814                                           v_TX_TERM(R50_OHMS));
 815         else
 816                 rockchip_hdmiv2_write_phy(hdmi_dev, PHYTX_TERM_RESIS,
 817                                           v_TX_TERM(R100_OHMS));
 818         /* rockchip_hdmiv2_write_phy(hdmi_dev, 0x05, 0x8000); */
 819         if (hdmi_dev->tmdsclk_ratio_change)
 820                 msleep(100);
 821         /* power on PHY */
 822         hdmi_writel(hdmi_dev, PHY_CONF0, 0x2e);
 823
 824         /* check if the PHY PLL is locked */
 825
 826         i = 0;
 827         while (i++ < PHY_TIMEOUT) {
 828                 if ((i % 10) == 0) {
 829                         stat = hdmi_readl(hdmi_dev, PHY_STAT0);
 830                         if (stat & m_PHY_LOCK)
 831                                 break;
 832                         usleep_range(1000, 2000);
 833                 }
 834         }
 835         if ((stat & m_PHY_LOCK) == 0) {
 836                 stat = hdmi_readl(hdmi_dev, MC_LOCKONCLOCK);
 837                 dev_err(hdmi_dev->hdmi->dev,
 838                         "PHY PLL not locked: PCLK_ON=%ld,TMDSCLK_ON=%ld\n",
 839                         (stat & m_PCLK_ON) >> 6, (stat & m_TMDSCLK_ON) >> 5);
 840                 return -1;
 841         }
 842         hdmi_msk_reg(hdmi_dev, PHY_MASK, m_PHY_LOCK, v_PHY_LOCK(0));
 843         return 0;
 844 }
 845
 846 static int rockchip_hdmiv2_video_framecomposer(struct hdmi *hdmi_drv,
 847                                                struct hdmi_video *vpara)
 848 {
 849         struct hdmi_dev *hdmi_dev = hdmi_drv->property->priv;
 850         int value, vsync_pol, hsync_pol, de_pol;
 851         struct hdmi_video_timing *timing = NULL;
 852         struct fb_videomode *mode = NULL;
 853         u32 sink_version, tmdsclk;
 854
 855         vsync_pol = hdmi_drv->lcdc->cur_screen->pin_vsync;
 856         hsync_pol = hdmi_drv->lcdc->cur_screen->pin_hsync;
 857         de_pol = (hdmi_drv->lcdc->cur_screen->pin_den == 0) ? 1 : 0;
 858
 859         hdmi_msk_reg(hdmi_dev, A_VIDPOLCFG,
 860                      m_DATAEN_POL | m_VSYNC_POL | m_HSYNC_POL,
 861                      v_DATAEN_POL(de_pol) |
 862                      v_VSYNC_POL(vsync_pol) |
 863                      v_HSYNC_POL(hsync_pol));
 864
 865         timing = (struct hdmi_video_timing *)hdmi_vic2timing(vpara->vic);
 866         if (!timing) {
 867                 dev_err(hdmi_drv->dev,
 868                         "[%s] not found vic %d\n", __func__, vpara->vic);
 869                 return -ENOENT;
 870         }
 871         mode = &timing->mode;
 872         if (vpara->color_input == HDMI_COLOR_YCBCR420)
 873                 tmdsclk = mode->pixclock / 2;
 874         else if (vpara->format_3d == HDMI_3D_FRAME_PACKING)
 875                 tmdsclk = 2 * mode->pixclock;
 876         else
 877                 tmdsclk = mode->pixclock;
 878         if (vpara->color_output != HDMI_COLOR_YCBCR422) {
 879                 switch (vpara->color_output_depth) {
 880                 case 10:
 881                         tmdsclk += tmdsclk / 4;
 882                         break;
 883                 case 12:
 884                         tmdsclk += tmdsclk / 2;
 885                         break;
 886                 case 16:
 887                         tmdsclk += tmdsclk;
 888                         break;
 889                 case 8:
 890                 default:
 891                         break;
 892                 }
 893         } else if (vpara->color_output_depth > 12) {
 894                 /* YCbCr422 mode only support up to 12bit */
 895                 vpara->color_output_depth = 12;
 896         }
 897         if ((tmdsclk > 594000000) ||
 898             (tmdsclk > 340000000 &&
 899              tmdsclk > hdmi_drv->edid.maxtmdsclock)) {
 900                 pr_warn("out of max tmds clock, limit to 8bit\n");
 901                 vpara->color_output_depth = 8;
 902                 if (vpara->color_input == HDMI_COLOR_YCBCR420)
 903                         tmdsclk = mode->pixclock / 2;
 904                 else if (vpara->format_3d != HDMI_3D_FRAME_PACKING)
 905                         tmdsclk = mode->pixclock;
 906                 else
 907                         return -1;
 908         }
 909
 910         if ((tmdsclk > 340000000) ||
 911             (tmdsclk < 340000000 && hdmi_dev->tmdsclk > 340000000))
 912                 hdmi_dev->tmdsclk_ratio_change = true;
 913         else
 914                 hdmi_dev->tmdsclk_ratio_change = false;
 915
 916         hdmi_dev->tmdsclk = tmdsclk;
 917         if (vpara->format_3d == HDMI_3D_FRAME_PACKING)
 918                 hdmi_dev->pixelclk = 2 * mode->pixclock;
 919         else
 920                 hdmi_dev->pixelclk = mode->pixclock;
 921         hdmi_dev->pixelrepeat = timing->pixelrepeat;
 922         /* hdmi_dev->colordepth is used for find pll config.
 923          * For YCbCr422, tmdsclk is same on all color depth.
 924          */
 925         if (vpara->color_output == HDMI_COLOR_YCBCR422)
 926                 hdmi_dev->colordepth = 8;
 927         else
 928                 hdmi_dev->colordepth = vpara->color_output_depth;
 929         pr_info("pixel clk is %lu tmds clk is %u\n",
 930                 hdmi_dev->pixelclk, hdmi_dev->tmdsclk);
 931         /* Start/stop HDCP keepout window generation */
 932         hdmi_msk_reg(hdmi_dev, FC_INVIDCONF,
 933                      m_FC_HDCP_KEEPOUT, v_FC_HDCP_KEEPOUT(1));
 934         if (hdmi_drv->edid.scdc_present == 1 && !hdmi_drv->uboot) {
 935                 if (tmdsclk > 340000000 ||
 936                     hdmi_drv->edid.lte_340mcsc_scramble) {
 937                         /* used for HDMI 2.0 TX */
 938                         mutex_lock(&hdmi_dev->ddc_lock);
 939                         rockchip_hdmiv2_scdc_init(hdmi_dev);
 940                         sink_version =
 941                         rockchip_hdmiv2_scdc_get_sink_version(hdmi_dev);
 942                         pr_info("sink scdc version is %d\n", sink_version);
 943                         sink_version = hdmi_drv->edid.hf_vsdb_version;
 944                         rockchip_hdmiv2_scdc_set_source_version(hdmi_dev,
 945                                                                 sink_version);
 946                         if (hdmi_drv->edid.rr_capable == 1)
 947                                 rockchip_hdmiv2_scdc_read_request(hdmi_dev, 1);
 948                         rockchip_hdmiv2_scrambling_enable(hdmi_dev, 1);
 949                         mutex_unlock(&hdmi_dev->ddc_lock);
 950                 } else {
 951                         mutex_lock(&hdmi_dev->ddc_lock);
 952                         rockchip_hdmiv2_scdc_init(hdmi_dev);
 953                         rockchip_hdmiv2_scrambling_enable(hdmi_dev, 0);
 954                         mutex_unlock(&hdmi_dev->ddc_lock);
 955                 }
 956         } else {
 957                 hdmi_msk_reg(hdmi_dev, FC_SCRAMBLER_CTRL,
 958                              m_FC_SCRAMBLE_EN, v_FC_SCRAMBLE_EN(0));
 959         }
 960
 961         hdmi_msk_reg(hdmi_dev, FC_INVIDCONF,
 962                      m_FC_VSYNC_POL | m_FC_HSYNC_POL | m_FC_DE_POL |
 963                      m_FC_HDMI_DVI | m_FC_INTERLACE_MODE,
 964                      v_FC_VSYNC_POL(vsync_pol) | v_FC_HSYNC_POL(hsync_pol) |
 965                      v_FC_DE_POL(de_pol) | v_FC_HDMI_DVI(vpara->sink_hdmi) |
 966                      v_FC_INTERLACE_MODE(mode->vmode));
 967         if ((mode->vmode & FB_VMODE_INTERLACED) &&
 968             vpara->format_3d != HDMI_3D_FRAME_PACKING)
 969                 hdmi_msk_reg(hdmi_dev, FC_INVIDCONF,
 970                              m_FC_VBLANK, v_FC_VBLANK(1));
 971         else
 972                 hdmi_msk_reg(hdmi_dev, FC_INVIDCONF,
 973                              m_FC_VBLANK, v_FC_VBLANK(0));
 974
 975         value = mode->xres;
 976         if (vpara->color_input == HDMI_COLOR_YCBCR420)
 977                 value = value / 2;
 978         hdmi_writel(hdmi_dev, FC_INHACTIV1, v_FC_HACTIVE1(value >> 8));
 979         hdmi_writel(hdmi_dev, FC_INHACTIV0, (value & 0xff));
 980
 981         if (vpara->format_3d == HDMI_3D_FRAME_PACKING) {
 982                 if (mode->vmode == 0)
 983                         value = 2 * mode->yres +
 984                                 mode->upper_margin +
 985                                 mode->lower_margin +
 986                                 mode->vsync_len;
 987                 else
 988                         value = 2 * mode->yres +
 989                                 3 * (mode->upper_margin +
 990                                      mode->lower_margin +
 991                                      mode->vsync_len) + 2;
 992         } else {
 993                 value = mode->yres;
 994         }
 995         hdmi_writel(hdmi_dev, FC_INVACTIV1, v_FC_VACTIVE1(value >> 8));
 996         hdmi_writel(hdmi_dev, FC_INVACTIV0, (value & 0xff));
 997
 998         value = mode->hsync_len + mode->left_margin + mode->right_margin;
 999         if (vpara->color_input == HDMI_COLOR_YCBCR420)
1000                 value = value / 2;
1001         hdmi_writel(hdmi_dev, FC_INHBLANK1, v_FC_HBLANK1(value >> 8));
1002         hdmi_writel(hdmi_dev, FC_INHBLANK0, (value & 0xff));
1003
1004         value = mode->vsync_len + mode->upper_margin + mode->lower_margin;
1005         hdmi_writel(hdmi_dev, FC_INVBLANK, (value & 0xff));
1006
1007         value = mode->right_margin;
1008         if (vpara->color_input == HDMI_COLOR_YCBCR420)
1009                 value = value / 2;
1010         hdmi_writel(hdmi_dev, FC_HSYNCINDELAY1, v_FC_HSYNCINDEAY1(value >> 8));
1011         hdmi_writel(hdmi_dev, FC_HSYNCINDELAY0, (value & 0xff));
1012
1013         value = mode->lower_margin;
1014         hdmi_writel(hdmi_dev, FC_VSYNCINDELAY, (value & 0xff));
1015
1016         value = mode->hsync_len;
1017         if (vpara->color_input == HDMI_COLOR_YCBCR420)
1018                 value = value / 2;
1019         hdmi_writel(hdmi_dev, FC_HSYNCINWIDTH1, v_FC_HSYNCWIDTH1(value >> 8));
1020         hdmi_writel(hdmi_dev, FC_HSYNCINWIDTH0, (value & 0xff));
1021
1022         value = mode->vsync_len;
1023         hdmi_writel(hdmi_dev, FC_VSYNCINWIDTH, (value & 0xff));
1024
1025         /* Set the control period minimum duration (min. of 12 pixel
1026          * clock cycles, refer to HDMI 1.4b specification)
1027          */
1028         hdmi_writel(hdmi_dev, FC_CTRLDUR, 12);
1029         hdmi_writel(hdmi_dev, FC_EXCTRLDUR, 32);
1030
1031         /* spacing < 256^2 * config / tmdsClock, spacing <= 50ms
1032          * worst case: tmdsClock == 25MHz => config <= 19
1033          */
1034         hdmi_writel(hdmi_dev, FC_EXCTRLSPAC,
1035                     (hdmi_dev->tmdsclk / 1000) * 50 / (256 * 512));
1036
1037         hdmi_writel(hdmi_dev, FC_PRCONF,
1038                     v_FC_PR_FACTOR(timing->pixelrepeat) |
1039                     v_FC_PR_FACTOR_OUT(timing->pixelrepeat - 1));
1040
1041         return 0;
1042 }
1043
1044 static int rockchip_hdmiv2_video_packetizer(struct hdmi_dev *hdmi_dev,
1045                                             struct hdmi_video *vpara)
1046 {
1047         unsigned char color_depth = COLOR_DEPTH_24BIT_DEFAULT;
1048         unsigned char output_select = 0;
1049         unsigned char remap_size = 0;
1050
1051         if (vpara->color_output == HDMI_COLOR_YCBCR422) {
1052                 switch (vpara->color_output_depth) {
1053                 case 8:
1054                         remap_size = YCC422_16BIT;
1055                         break;
1056                 case 10:
1057                         remap_size = YCC422_20BIT;
1058                         break;
1059                 case 12:
1060                         remap_size = YCC422_24BIT;
1061                         break;
1062                 default:
1063                         remap_size = YCC422_16BIT;
1064                         break;
1065                 }
1066
1067                 output_select = OUT_FROM_YCC422_REMAP;
1068                 /*Config remap size for the different color Depth*/
1069                 hdmi_msk_reg(hdmi_dev, VP_REMAP,
1070                              m_YCC422_SIZE, v_YCC422_SIZE(remap_size));
1071         } else {
1072                 switch (vpara->color_output_depth) {
1073                 case 10:
1074                         color_depth = COLOR_DEPTH_30BIT;
1075                         output_select = OUT_FROM_PIXEL_PACKING;
1076                         break;
1077                 case 12:
1078                         color_depth = COLOR_DEPTH_36BIT;
1079                         output_select = OUT_FROM_PIXEL_PACKING;
1080                         break;
1081                 case 16:
1082                         color_depth = COLOR_DEPTH_48BIT;
1083                         output_select = OUT_FROM_PIXEL_PACKING;
1084                         break;
1085                 case 8:
1086                 default:
1087                         color_depth = COLOR_DEPTH_24BIT_DEFAULT;
1088                         output_select = OUT_FROM_8BIT_BYPASS;
1089                         break;
1090                 }
1091         }
1092         /*Config Color Depth*/
1093         hdmi_msk_reg(hdmi_dev, VP_PR_CD,
1094                      m_COLOR_DEPTH, v_COLOR_DEPTH(color_depth));
1095         /*Config pixel repettion*/
1096         hdmi_msk_reg(hdmi_dev, VP_PR_CD, m_DESIRED_PR_FACTOR,
1097                      v_DESIRED_PR_FACTOR(hdmi_dev->pixelrepeat - 1));
1098         if (hdmi_dev->pixelrepeat > 1)
1099                 hdmi_msk_reg(hdmi_dev, VP_CONF,
1100                              m_PIXEL_REPET_EN | m_BYPASS_SEL,
1101                              v_PIXEL_REPET_EN(1) | v_BYPASS_SEL(0));
1102         else
1103                 hdmi_msk_reg(hdmi_dev, VP_CONF,
1104                              m_PIXEL_REPET_EN | m_BYPASS_SEL,
1105                              v_PIXEL_REPET_EN(0) | v_BYPASS_SEL(1));
1106
1107         /*config output select*/
1108         if (output_select == OUT_FROM_PIXEL_PACKING) { /* pixel packing */
1109                 hdmi_msk_reg(hdmi_dev, VP_CONF,
1110                              m_BYPASS_EN | m_PIXEL_PACK_EN |
1111                              m_YCC422_EN | m_OUTPUT_SEL,
1112                              v_BYPASS_EN(0) | v_PIXEL_PACK_EN(1) |
1113                              v_YCC422_EN(0) | v_OUTPUT_SEL(output_select));
1114         } else if (output_select == OUT_FROM_YCC422_REMAP) { /* YCC422 */
1115                 hdmi_msk_reg(hdmi_dev, VP_CONF,
1116                              m_BYPASS_EN | m_PIXEL_PACK_EN |
1117                              m_YCC422_EN | m_OUTPUT_SEL,
1118                              v_BYPASS_EN(0) | v_PIXEL_PACK_EN(0) |
1119                              v_YCC422_EN(1) | v_OUTPUT_SEL(output_select));
1120         } else if (output_select == OUT_FROM_8BIT_BYPASS ||
1121                    output_select == 3) { /* bypass */
1122                 hdmi_msk_reg(hdmi_dev, VP_CONF,
1123                              m_BYPASS_EN | m_PIXEL_PACK_EN |
1124                              m_YCC422_EN | m_OUTPUT_SEL,
1125                              v_BYPASS_EN(1) | v_PIXEL_PACK_EN(0) |
1126                              v_YCC422_EN(0) | v_OUTPUT_SEL(output_select));
1127         }
1128
1129 #if defined(HDMI_VIDEO_STUFFING)
1130         /* YCC422 and pixel packing stuffing*/
1131         hdmi_msk_reg(hdmi_dev, VP_STUFF, m_PR_STUFFING, v_PR_STUFFING(1));
1132         hdmi_msk_reg(hdmi_dev, VP_STUFF,
1133                      m_YCC422_STUFFING | m_PP_STUFFING,
1134                      v_YCC422_STUFFING(1) | v_PP_STUFFING(1));
1135 #endif
1136         return 0;
1137 }
1138
1139 static int rockchip_hdmiv2_video_sampler(struct hdmi_dev *hdmi_dev,
1140                                          struct hdmi_video *vpara)
1141 {
1142         int map_code = 0;
1143
1144         if (vpara->color_input == HDMI_COLOR_YCBCR422) {
1145                 /* YCC422 mapping is discontinued - only map 1 is supported */
1146                 switch (vpara->color_output_depth) {
1147                 case 8:
1148                         map_code = VIDEO_YCBCR422_8BIT;
1149                         break;
1150                 case 10:
1151                         map_code = VIDEO_YCBCR422_10BIT;
1152                         break;
1153                 case 12:
1154                         map_code = VIDEO_YCBCR422_12BIT;
1155                         break;
1156                 default:
1157                         map_code = VIDEO_YCBCR422_8BIT;
1158                         break;
1159                 }
1160         } else if (vpara->color_input == HDMI_COLOR_YCBCR420 ||
1161                    vpara->color_input == HDMI_COLOR_YCBCR444) {
1162                 switch (vpara->color_output_depth) {
1163                 case 10:
1164                         map_code = VIDEO_YCBCR444_10BIT;
1165                         break;
1166                 case 12:
1167                         map_code = VIDEO_YCBCR444_12BIT;
1168                         break;
1169                 case 16:
1170                         map_code = VIDEO_YCBCR444_16BIT;
1171                         break;
1172                 case 8:
1173                 default:
1174                         map_code = VIDEO_YCBCR444_8BIT;
1175                         break;
1176                 }
1177         } else {
1178                 switch (vpara->color_output_depth) {
1179                 case 10:
1180                         map_code = VIDEO_RGB444_10BIT;
1181                         break;
1182                 case 12:
1183                         map_code = VIDEO_RGB444_12BIT;
1184                         break;
1185                 case 16:
1186                         map_code = VIDEO_RGB444_16BIT;
1187                         break;
1188                 case 8:
1189                 default:
1190                         map_code = VIDEO_RGB444_8BIT;
1191                         break;
1192                 }
1193                 map_code += (vpara->color_input == HDMI_COLOR_YCBCR444) ?
1194                             8 : 0;
1195         }
1196
1197         /* Set Data enable signal from external
1198          * and set video sample input mapping
1199          */
1200         hdmi_msk_reg(hdmi_dev, TX_INVID0,
1201                      m_INTERNAL_DE_GEN | m_VIDEO_MAPPING,
1202                      v_INTERNAL_DE_GEN(0) | v_VIDEO_MAPPING(map_code));
1203
1204 #if defined(HDMI_VIDEO_STUFFING)
1205         hdmi_writel(hdmi_dev, TX_GYDATA0, 0x00);
1206         hdmi_writel(hdmi_dev, TX_GYDATA1, 0x00);
1207         hdmi_msk_reg(hdmi_dev, TX_INSTUFFING,
1208                      m_GYDATA_STUFF, v_GYDATA_STUFF(1));
1209         hdmi_writel(hdmi_dev, TX_RCRDATA0, 0x00);
1210         hdmi_writel(hdmi_dev, TX_RCRDATA1, 0x00);
1211         hdmi_msk_reg(hdmi_dev, TX_INSTUFFING,
1212                      m_RCRDATA_STUFF, v_RCRDATA_STUFF(1));
1213         hdmi_writel(hdmi_dev, TX_BCBDATA0, 0x00);
1214         hdmi_writel(hdmi_dev, TX_BCBDATA1, 0x00);
1215         hdmi_msk_reg(hdmi_dev, TX_INSTUFFING,
1216                      m_BCBDATA_STUFF, v_BCBDATA_STUFF(1));
1217 #endif
1218         return 0;
1219 }
1220
1221 static const char coeff_csc[][24] = {
1222                 /*   G          R           B           Bias
1223                  *   A1    |    A2     |    A3     |    A4    |
1224                  *   B1    |    B2     |    B3     |    B4    |
1225                  *   C1    |    C2     |    C3     |    C4    |
1226                  */
1227         {       /* CSC_BYPASS */
1228                 0x10, 0x00, 0x10, 0x00, 0x10, 0x00, 0x00, 0x00,
1229                 0x10, 0x00, 0x10, 0x00, 0x10, 0x00, 0x00, 0x00,
1230                 0x10, 0x00, 0x10, 0x00, 0x10, 0x00, 0x00, 0x00,
1231         },
1232         {       /* CSC_RGB_0_255_TO_RGB_16_235_8BIT */
1233                 0x36, 0xf7, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40,         /*G*/
1234                 0x00, 0x00, 0x36, 0xf7, 0x00, 0x00, 0x00, 0x40,         /*R*/
1235                 0x00, 0x00, 0x00, 0x00, 0x36, 0xf7, 0x00, 0x40,         /*B*/
1236         },
1237         {       /* CSC_RGB_0_255_TO_RGB_16_235_10BIT */
1238                 0x36, 0xf7, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00,         /*G*/
1239                 0x00, 0x00, 0x36, 0xf7, 0x00, 0x00, 0x01, 0x00,         /*R*/
1240                 0x00, 0x00, 0x00, 0x00, 0x36, 0xf7, 0x01, 0x00,         /*B*/
1241         },
1242         {       /* CSC_RGB_0_255_TO_ITU601_16_235_8BIT */
1243                 0x20, 0x40, 0x10, 0x80, 0x06, 0x40, 0x00, 0x40,         /*Y*/
1244                 0xe8, 0x80, 0x1c, 0x00, 0xfb, 0x80, 0x02, 0x00,         /*Cr*/
1245                 0xed, 0x80, 0xf6, 0x80, 0x1c, 0x00, 0x02, 0x00,         /*Cb*/
1246         },
1247         {       /* CSC_RGB_0_255_TO_ITU601_16_235_10BIT */
1248                 0x20, 0x40, 0x10, 0x80, 0x06, 0x40, 0x01, 0x00,         /*Y*/
1249                 0xe8, 0x80, 0x1c, 0x00, 0xfb, 0x80, 0x08, 0x00,         /*Cr*/
1250                 0xed, 0x80, 0xf6, 0x80, 0x1c, 0x00, 0x08, 0x00,         /*Cb*/
1251         },
1252         {       /* CSC_RGB_0_255_TO_ITU709_16_235_8BIT */
1253                 0x27, 0x40, 0x0b, 0xc0, 0x04, 0x00, 0x00, 0x40,         /*Y*/
1254                 0xe6, 0x80, 0x1c, 0x00, 0xfd, 0x80, 0x02, 0x00,         /*Cr*/
1255                 0xea, 0x40, 0xf9, 0x80, 0x1c, 0x00, 0x02, 0x00,         /*Cb*/
1256         },
1257         {       /* CSC_RGB_0_255_TO_ITU709_16_235_10BIT */
1258                 0x27, 0x40, 0x0b, 0xc0, 0x04, 0x00, 0x01, 0x00,         /*Y*/
1259                 0xe6, 0x80, 0x1c, 0x00, 0xfd, 0x80, 0x08, 0x00,         /*Cr*/
1260                 0xea, 0x40, 0xf9, 0x80, 0x1c, 0x00, 0x08, 0x00,         /*Cb*/
1261         },
1262                 /* Y            Cr          Cb          Bias */
1263         {       /* CSC_ITU601_16_235_TO_RGB_0_255_8BIT */
1264                 0x20, 0x00, 0x69, 0x26, 0x74, 0xfd, 0x01, 0x0e,         /*G*/
1265                 0x20, 0x00, 0x2c, 0xdd, 0x00, 0x00, 0x7e, 0x9a,         /*R*/
1266                 0x20, 0x00, 0x00, 0x00, 0x38, 0xb4, 0x7e, 0x3b,         /*B*/
1267         },
1268         {       /* CSC_ITU709_16_235_TO_RGB_0_255_8BIT */
1269                 0x20, 0x00, 0x71, 0x06, 0x7a, 0x02, 0x00, 0xa7,         /*G*/
1270                 0x20, 0x00, 0x32, 0x64, 0x00, 0x00, 0x7e, 0x6d,         /*R*/
1271                 0x20, 0x00, 0x00, 0x00, 0x3b, 0x61, 0x7e, 0x25,         /*B*/
1272         },
1273 };
1274
1275 static int rockchip_hdmiv2_video_csc(struct hdmi_dev *hdmi_dev,
1276                                      struct hdmi_video *vpara)
1277 {
1278         int i, mode, interpolation, decimation, csc_scale = 0;
1279         const char *coeff = NULL;
1280         unsigned char color_depth = 0;
1281
1282         if (vpara->color_input == vpara->color_output) {
1283                 hdmi_msk_reg(hdmi_dev, MC_FLOWCTRL,
1284                              m_FEED_THROUGH_OFF, v_FEED_THROUGH_OFF(0));
1285                 return 0;
1286         }
1287
1288         if (vpara->color_input == HDMI_COLOR_YCBCR422 &&
1289             vpara->color_output != HDMI_COLOR_YCBCR422 &&
1290             vpara->color_output != HDMI_COLOR_YCBCR420) {
1291                 interpolation = 1;
1292                 hdmi_msk_reg(hdmi_dev, CSC_CFG,
1293                              m_CSC_INTPMODE, v_CSC_INTPMODE(interpolation));
1294         }
1295
1296         if ((vpara->color_input == HDMI_COLOR_RGB_0_255 ||
1297              vpara->color_input == HDMI_COLOR_YCBCR444) &&
1298              vpara->color_output == HDMI_COLOR_YCBCR422) {
1299                 decimation = 1;
1300                 hdmi_msk_reg(hdmi_dev, CSC_CFG,
1301                              m_CSC_DECIMODE, v_CSC_DECIMODE(decimation));
1302         }
1303
1304         mode = CSC_BYPASS;
1305         csc_scale = 0;
1306
1307         switch (vpara->vic) {
1308         case HDMI_720X480I_60HZ_4_3:
1309         case HDMI_720X576I_50HZ_4_3:
1310         case HDMI_720X480P_60HZ_4_3:
1311         case HDMI_720X576P_50HZ_4_3:
1312         case HDMI_720X480I_60HZ_16_9:
1313         case HDMI_720X576I_50HZ_16_9:
1314         case HDMI_720X480P_60HZ_16_9:
1315         case HDMI_720X576P_50HZ_16_9:
1316                 if (vpara->color_input == HDMI_COLOR_RGB_0_255 &&
1317                     vpara->color_output >= HDMI_COLOR_YCBCR444) {
1318                         mode = CSC_RGB_0_255_TO_ITU601_16_235_8BIT;
1319                         csc_scale = 0;
1320                 } else if (vpara->color_input >= HDMI_COLOR_YCBCR444 &&
1321                            vpara->color_output == HDMI_COLOR_RGB_0_255) {
1322                         mode = CSC_ITU601_16_235_TO_RGB_0_255_8BIT;
1323                         csc_scale = 1;
1324                 }
1325                 break;
1326         default:
1327                 if (vpara->color_input == HDMI_COLOR_RGB_0_255 &&
1328                     vpara->color_output >= HDMI_COLOR_YCBCR444) {
1329                         mode = CSC_RGB_0_255_TO_ITU709_16_235_8BIT;
1330                         csc_scale = 0;
1331                 } else if (vpara->color_input >= HDMI_COLOR_YCBCR444 &&
1332                            vpara->color_output == HDMI_COLOR_RGB_0_255) {
1333                         mode = CSC_ITU709_16_235_TO_RGB_0_255_8BIT;
1334                         csc_scale = 1;
1335                 }
1336                 break;
1337         }
1338
1339         if ((vpara->color_input == HDMI_COLOR_RGB_0_255) &&
1340             (vpara->color_output == HDMI_COLOR_RGB_16_235)) {
1341                 mode = CSC_RGB_0_255_TO_RGB_16_235_8BIT;
1342                 csc_scale = 0;
1343         }
1344
1345         switch (vpara->color_output_depth) {
1346         case 10:
1347                 color_depth = COLOR_DEPTH_30BIT;
1348                 mode += 1;
1349                 break;
1350         case 12:
1351                 color_depth = COLOR_DEPTH_36BIT;
1352                 mode += 2;
1353                 break;
1354         case 16:
1355                 color_depth = COLOR_DEPTH_48BIT;
1356                 mode += 3;
1357                 break;
1358         case 8:
1359         default:
1360                 color_depth = COLOR_DEPTH_24BIT;
1361                 break;
1362         }
1363
1364         coeff = coeff_csc[mode];
1365         for (i = 0; i < 24; i++)
1366                 hdmi_writel(hdmi_dev, CSC_COEF_A1_MSB + i, coeff[i]);
1367
1368         hdmi_msk_reg(hdmi_dev, CSC_SCALE,
1369                      m_CSC_SCALE, v_CSC_SCALE(csc_scale));
1370         /*config CSC_COLOR_DEPTH*/
1371         hdmi_msk_reg(hdmi_dev, CSC_SCALE,
1372                      m_CSC_COLOR_DEPTH, v_CSC_COLOR_DEPTH(color_depth));
1373
1374         /* enable CSC */
1375         hdmi_msk_reg(hdmi_dev, MC_FLOWCTRL,
1376                      m_FEED_THROUGH_OFF, v_FEED_THROUGH_OFF(1));
1377
1378         return 0;
1379 }
1380
1381 static int hdmi_dev_detect_hotplug(struct hdmi *hdmi)
1382 {
1383         struct hdmi_dev *hdmi_dev = hdmi->property->priv;
1384         u32 value;
1385
1386         value = hdmi_readl(hdmi_dev, PHY_STAT0);
1387         HDMIDBG("[%s] reg%x value %02x\n", __func__, PHY_STAT0, value);
1388         if (value & m_PHY_HPD)
1389                 return HDMI_HPD_ACTIVED;
1390
1391         return HDMI_HPD_REMOVED;
1392 }
1393
1394 static int hdmi_dev_read_edid(struct hdmi *hdmi, int block, unsigned char *buff)
1395 {
1396         struct hdmi_dev *hdmi_dev = hdmi->property->priv;
1397         int i = 0, n = 0, index = 0, ret = -1, trytime = 5;
1398         int offset = (block % 2) * 0x80;
1399         int interrupt = 0;
1400
1401         HDMIDBG("[%s] block %d\n", __func__, block);
1402
1403         rockchip_hdmiv2_i2cm_reset(hdmi_dev);
1404
1405         /* Set DDC I2C CLK which divided from DDC_CLK to 100KHz. */
1406         rockchip_hdmiv2_i2cm_clk_init(hdmi_dev);
1407
1408         /* Enable I2C interrupt for reading edid */
1409         rockchip_hdmiv2_i2cm_mask_int(hdmi_dev, 0);
1410
1411         hdmi_writel(hdmi_dev, I2CM_SLAVE, DDC_I2C_EDID_ADDR);
1412         hdmi_writel(hdmi_dev, I2CM_SEGADDR, DDC_I2C_SEG_ADDR);
1413         hdmi_writel(hdmi_dev, I2CM_SEGPTR, block / 2);
1414         for (n = 0; n < HDMI_EDID_BLOCK_SIZE / 8; n++) {
1415                 for (trytime = 0; trytime < 5; trytime++) {
1416                         hdmi_writel(hdmi_dev, I2CM_ADDRESS, offset + 8 * n);
1417                         /* enable extend sequential read operation */
1418                         if (block == 0)
1419                                 hdmi_msk_reg(hdmi_dev, I2CM_OPERATION,
1420                                              m_I2CM_RD8, v_I2CM_RD8(1));
1421                         else
1422                                 hdmi_msk_reg(hdmi_dev, I2CM_OPERATION,
1423                                              m_I2CM_RD8_EXT,
1424                                              v_I2CM_RD8_EXT(1));
1425
1426                         i = 20;
1427                         while (i--) {
1428                                 usleep_range(900, 1000);
1429                                 interrupt = hdmi_readl(hdmi_dev,
1430                                                        IH_I2CM_STAT0);
1431                                 if (interrupt)
1432                                         hdmi_writel(hdmi_dev,
1433                                                     IH_I2CM_STAT0, interrupt);
1434
1435                                 if (interrupt &
1436                                     (m_SCDC_READREQ | m_I2CM_DONE |
1437                                      m_I2CM_ERROR))
1438                                         break;
1439                         }
1440
1441                         if (interrupt & m_I2CM_DONE) {
1442                                 for (index = 0; index < 8; index++)
1443                                         buff[8 * n + index] =
1444                                                 hdmi_readl(hdmi_dev,
1445                                                            I2CM_READ_BUFF0 +
1446                                                            index);
1447
1448                                 if (n == HDMI_EDID_BLOCK_SIZE / 8 - 1) {
1449                                         ret = 0;
1450                                         goto exit;
1451                                 }
1452                                 break;
1453                         } else if ((interrupt & m_I2CM_ERROR) || (i == -1)) {
1454                                 dev_err(hdmi->dev,
1455                                         "[%s] edid read %d error\n",
1456                                         __func__, offset + 8 * n);
1457                         }
1458                 }
1459                 if (trytime == 5) {
1460                         dev_err(hdmi->dev,
1461                                 "[%s] edid read error\n", __func__);
1462                         break;
1463                 }
1464         }
1465
1466 exit:
1467         /* Disable I2C interrupt */
1468         rockchip_hdmiv2_i2cm_mask_int(hdmi_dev, 1);
1469         return ret;
1470 }
1471
1472 static void hdmi_dev_config_avi(struct hdmi_dev *hdmi_dev,
1473                                 struct hdmi_video *vpara)
1474 {
1475         unsigned char colorimetry, ext_colorimetry = 0, aspect_ratio, y1y0;
1476         unsigned char rgb_quan_range = AVI_QUANTIZATION_RANGE_DEFAULT;
1477
1478         hdmi_msk_reg(hdmi_dev, FC_DATAUTO3, m_AVI_AUTO, v_AVI_AUTO(0));
1479         hdmi_msk_reg(hdmi_dev, IH_FC_STAT1,
1480                      m_AVI_INFOFRAME, v_AVI_INFOFRAME(1));
1481         /* Set AVI infoFrame Data byte1 */
1482         if (vpara->color_output == HDMI_COLOR_YCBCR444)
1483                 y1y0 = AVI_COLOR_MODE_YCBCR444;
1484         else if (vpara->color_output == HDMI_COLOR_YCBCR422)
1485                 y1y0 = AVI_COLOR_MODE_YCBCR422;
1486         else if (vpara->color_output == HDMI_COLOR_YCBCR420)
1487                 y1y0 = AVI_COLOR_MODE_YCBCR420;
1488         else
1489                 y1y0 = AVI_COLOR_MODE_RGB;
1490
1491         hdmi_msk_reg(hdmi_dev, FC_AVICONF0,
1492                      m_FC_ACTIV_FORMAT | m_FC_RGC_YCC,
1493                      v_FC_RGC_YCC(y1y0) | v_FC_ACTIV_FORMAT(1));
1494
1495         /* Set AVI infoFrame Data byte2 */
1496         switch (vpara->vic) {
1497         case HDMI_720X480I_60HZ_4_3:
1498         case HDMI_720X576I_50HZ_4_3:
1499         case HDMI_720X480P_60HZ_4_3:
1500         case HDMI_720X576P_50HZ_4_3:
1501                 aspect_ratio = AVI_CODED_FRAME_ASPECT_4_3;
1502                 if (vpara->colorimetry == HDMI_COLORIMETRY_NO_DATA)
1503                         colorimetry = AVI_COLORIMETRY_SMPTE_170M;
1504                 break;
1505         case HDMI_720X480I_60HZ_16_9:
1506         case HDMI_720X576I_50HZ_16_9:
1507         case HDMI_720X480P_60HZ_16_9:
1508         case HDMI_720X576P_50HZ_16_9:
1509                 aspect_ratio = AVI_CODED_FRAME_ASPECT_16_9;
1510                 if (vpara->colorimetry == HDMI_COLORIMETRY_NO_DATA)
1511                         colorimetry = AVI_COLORIMETRY_SMPTE_170M;
1512                 break;
1513         default:
1514                 aspect_ratio = AVI_CODED_FRAME_ASPECT_16_9;
1515                 if (vpara->colorimetry == HDMI_COLORIMETRY_NO_DATA)
1516                         colorimetry = AVI_COLORIMETRY_ITU709;
1517         }
1518
1519         if (vpara->colorimetry > HDMI_COLORIMETRY_ITU709) {
1520                 colorimetry = AVI_COLORIMETRY_EXTENDED;
1521                 ext_colorimetry = vpara->colorimetry;
1522         } else if (vpara->color_output == HDMI_COLOR_RGB_16_235 ||
1523                  vpara->color_output == HDMI_COLOR_RGB_0_255) {
1524                 colorimetry = AVI_COLORIMETRY_NO_DATA;
1525         } else if (vpara->colorimetry != HDMI_COLORIMETRY_NO_DATA) {
1526                 colorimetry = vpara->colorimetry;
1527         }
1528
1529         hdmi_writel(hdmi_dev, FC_AVICONF1,
1530                     v_FC_COLORIMETRY(colorimetry) |
1531                     v_FC_PIC_ASPEC_RATIO(aspect_ratio) |
1532                     v_FC_ACT_ASPEC_RATIO(ACTIVE_ASPECT_RATE_DEFAULT));
1533
1534         /* Set AVI infoFrame Data byte3 */
1535         hdmi_msk_reg(hdmi_dev, FC_AVICONF2,
1536                      m_FC_EXT_COLORIMETRY | m_FC_QUAN_RANGE,
1537                      v_FC_EXT_COLORIMETRY(ext_colorimetry) |
1538                      v_FC_QUAN_RANGE(rgb_quan_range));
1539
1540         /* Set AVI infoFrame Data byte4 */
1541         if ((vpara->vic > 92 && vpara->vic < 96) ||
1542             (vpara->vic == 98) ||
1543             (vpara->vic & HDMI_VIDEO_DMT) ||
1544             (vpara->vic & HDMI_VIDEO_DISCRETE_VR))
1545                 hdmi_writel(hdmi_dev, FC_AVIVID, 0);
1546         else
1547                 hdmi_writel(hdmi_dev, FC_AVIVID, vpara->vic & 0xff);
1548         /* Set AVI infoFrame Data byte5 */
1549         hdmi_msk_reg(hdmi_dev, FC_AVICONF3, m_FC_YQ | m_FC_CN,
1550                      v_FC_YQ(YQ_LIMITED_RANGE) | v_FC_CN(CN_GRAPHICS));
1551         hdmi_msk_reg(hdmi_dev, FC_DATAUTO3, m_AVI_AUTO, v_AVI_AUTO(1));
1552 }
1553
1554 static int hdmi_dev_config_vsi(struct hdmi *hdmi,
1555                                unsigned char vic_3d, unsigned char format)
1556 {
1557         int i = 0, id = 0x000c03;
1558         unsigned char data[3] = {0};
1559
1560         struct hdmi_dev *hdmi_dev = hdmi->property->priv;
1561
1562         HDMIDBG("[%s] vic %d format %d.\n", __func__, vic_3d, format);
1563
1564         hdmi_msk_reg(hdmi_dev, FC_DATAUTO0, m_VSD_AUTO, v_VSD_AUTO(0));
1565         hdmi_writel(hdmi_dev, FC_VSDIEEEID2, id & 0xff);
1566         hdmi_writel(hdmi_dev, FC_VSDIEEEID1, (id >> 8) & 0xff);
1567         hdmi_writel(hdmi_dev, FC_VSDIEEEID0, (id >> 16) & 0xff);
1568
1569         data[0] = format << 5;  /* PB4 --HDMI_Video_Format */
1570         switch (format) {
1571         case HDMI_VIDEO_FORMAT_4KX2K:
1572                 data[1] = vic_3d;       /* PB5--HDMI_VIC */
1573                 data[2] = 0;
1574                 break;
1575         case HDMI_VIDEO_FORMAT_3D:
1576                 data[1] = vic_3d << 4;  /* PB5--3D_Structure field */
1577                 data[2] = 0;            /* PB6--3D_Ext_Data field */
1578                 break;
1579         default:
1580                 data[1] = 0;
1581                 data[2] = 0;
1582                 break;
1583         }
1584
1585         for (i = 0; i < 3; i++)
1586                 hdmi_writel(hdmi_dev, FC_VSDPAYLOAD0 + i, data[i]);
1587         hdmi_writel(hdmi_dev, FC_VSDSIZE, 0x6);
1588
1589         hdmi_writel(hdmi_dev, FC_DATAUTO1, 0);
1590         hdmi_writel(hdmi_dev, FC_DATAUTO2, 0x11);
1591         hdmi_msk_reg(hdmi_dev, FC_DATAUTO0, m_VSD_AUTO, v_VSD_AUTO(1));
1592         return 0;
1593 }
1594
1595 static int hdmi_dev_config_spd(struct hdmi *hdmi, const char *vendor,
1596                                const char *product, char deviceinfo)
1597 {
1598         struct hdmi_dev *hdmi_dev;
1599         int i, len;
1600
1601         if (!hdmi || !vendor || !product)
1602                 return -1;
1603         hdmi_dev = hdmi->property->priv;
1604
1605         hdmi_msk_reg(hdmi_dev, FC_DATAUTO0, m_SPD_AUTO, v_SPD_AUTO(0));
1606         len = strlen(vendor);
1607         for (i = 0; i < 8; i++) {
1608                 if (i < len)
1609                         hdmi_writel(hdmi_dev, FC_SPDVENDORNAME0 + i,
1610                                     vendor[i]);
1611                 else
1612                         hdmi_writel(hdmi_dev, FC_SPDVENDORNAME0 + i,
1613                                     0);
1614         }
1615         len = strlen(product);
1616         for (i = 0; i < 16; i++) {
1617                 if (i < len)
1618                         hdmi_writel(hdmi_dev, FC_SPDPRODUCTNAME0 + i,
1619                                     product[i]);
1620                 else
1621                         hdmi_writel(hdmi_dev, FC_SPDPRODUCTNAME0 + i,
1622                                     0);
1623         }
1624         hdmi_writel(hdmi_dev, FC_SPDDEVICEINF, deviceinfo);
1625         hdmi_msk_reg(hdmi_dev, FC_DATAUTO0, m_SPD_AUTO, v_SPD_AUTO(1));
1626         return 0;
1627 }
1628
1629 static int hdmi_dev_config_video(struct hdmi *hdmi, struct hdmi_video *vpara)
1630 {
1631         struct hdmi_dev *hdmi_dev = hdmi->property->priv;
1632
1633         HDMIDBG("%s vic %d 3dformat %d color mode %d color depth %d\n",
1634                 __func__, vpara->vic, vpara->format_3d,
1635                 vpara->color_output, vpara->color_output_depth);
1636
1637         if (hdmi_dev->soctype == HDMI_SOC_RK3288)
1638                 vpara->color_input = HDMI_COLOR_RGB_0_255;
1639
1640         if (!hdmi->uboot) {
1641                 /* before configure video, we power off phy */
1642                 if (hdmi_dev->soctype != HDMI_SOC_RK322X) {
1643                         hdmi_msk_reg(hdmi_dev, PHY_CONF0,
1644                                      m_PDDQ_SIG | m_TXPWRON_SIG,
1645                                      v_PDDQ_SIG(1) | v_TXPWRON_SIG(0));
1646                 } else {
1647                         hdmi_msk_reg(hdmi_dev, PHY_CONF0,
1648                                      m_ENHPD_RXSENSE_SIG,
1649                                      v_ENHPD_RXSENSE_SIG(1));
1650                         regmap_write(hdmi_dev->grf_base,
1651                                      RK322X_GRF_SOC_CON2,
1652                                      RK322X_PLL_POWER_DOWN);
1653                 }
1654                 /* force output blue */
1655                 if (vpara->color_output == HDMI_COLOR_RGB_0_255) {
1656                         hdmi_writel(hdmi_dev, FC_DBGTMDS2, 0x00);       /*R*/
1657                         hdmi_writel(hdmi_dev, FC_DBGTMDS1, 0x00);       /*G*/
1658                         hdmi_writel(hdmi_dev, FC_DBGTMDS0, 0x00);       /*B*/
1659                 } else if (vpara->color_output == HDMI_COLOR_RGB_16_235) {
1660                         hdmi_writel(hdmi_dev, FC_DBGTMDS2, 0x10);       /*R*/
1661                         hdmi_writel(hdmi_dev, FC_DBGTMDS1, 0x10);       /*G*/
1662                         hdmi_writel(hdmi_dev, FC_DBGTMDS0, 0x10);       /*B*/
1663                 } else {
1664                         hdmi_writel(hdmi_dev, FC_DBGTMDS2, 0x80);       /*Cr*/
1665                         hdmi_writel(hdmi_dev, FC_DBGTMDS1, 0x10);       /*Y*/
1666                         hdmi_writel(hdmi_dev, FC_DBGTMDS0, 0x80);       /*Cb*/
1667                 }
1668                 hdmi_msk_reg(hdmi_dev, FC_DBGFORCE,
1669                              m_FC_FORCEVIDEO, v_FC_FORCEVIDEO(1));
1670                 hdmi_writel(hdmi_dev, MC_CLKDIS, m_HDCPCLK_DISABLE);
1671         }
1672
1673         if (rockchip_hdmiv2_video_framecomposer(hdmi, vpara) < 0)
1674                 return -1;
1675
1676         if (rockchip_hdmiv2_video_packetizer(hdmi_dev, vpara) < 0)
1677                 return -1;
1678         /* Color space convert */
1679         if (rockchip_hdmiv2_video_csc(hdmi_dev, vpara) < 0)
1680                 return -1;
1681         if (rockchip_hdmiv2_video_sampler(hdmi_dev, vpara) < 0)
1682                 return -1;
1683
1684         if (vpara->sink_hdmi == OUTPUT_HDMI) {
1685                 hdmi_dev_config_avi(hdmi_dev, vpara);
1686                 hdmi_dev_config_spd(hdmi, hdmi_dev->vendor_name,
1687                                     hdmi_dev->product_name,
1688                                     hdmi_dev->deviceinfo);
1689                 if (vpara->format_3d != HDMI_3D_NONE) {
1690                         hdmi_dev_config_vsi(hdmi,
1691                                             vpara->format_3d,
1692                                             HDMI_VIDEO_FORMAT_3D);
1693                 } else if ((vpara->vic > 92 && vpara->vic < 96) ||
1694                          (vpara->vic == 98)) {
1695                         vpara->vic = (vpara->vic == 98) ?
1696                                      4 : (96 - vpara->vic);
1697                         hdmi_dev_config_vsi(hdmi,
1698                                             vpara->vic,
1699                                             HDMI_VIDEO_FORMAT_4KX2K);
1700                 } else {
1701                         hdmi_dev_config_vsi(hdmi,
1702                                             vpara->vic,
1703                                             HDMI_VIDEO_FORMAT_NORMAL);
1704                 }
1705                 dev_info(hdmi->dev, "[%s] success output HDMI.\n", __func__);
1706         } else {
1707                 dev_info(hdmi->dev, "[%s] success output DVI.\n", __func__);
1708         }
1709
1710         if (!hdmi->uboot)
1711                 rockchip_hdmiv2_config_phy(hdmi_dev);
1712         else
1713                 hdmi_msk_reg(hdmi_dev, PHY_MASK, m_PHY_LOCK, v_PHY_LOCK(0));
1714         return 0;
1715 }
1716
1717 static void hdmi_dev_config_aai(struct hdmi_dev *hdmi_dev,
1718                                 struct hdmi_audio *audio)
1719 {
1720         /* Refer to CEA861-E Audio infoFrame
1721          * Set both Audio Channel Count and Audio Coding
1722          * Type Refer to Stream Head for HDMI
1723          */
1724         hdmi_msk_reg(hdmi_dev, FC_AUDICONF0,
1725                      m_FC_CHN_CNT | m_FC_CODING_TYPE,
1726                      v_FC_CHN_CNT(audio->channel - 1) | v_FC_CODING_TYPE(0));
1727
1728         /* Set both Audio Sample Size and Sample Frequency
1729          * Refer to Stream Head for HDMI
1730          */
1731         hdmi_msk_reg(hdmi_dev, FC_AUDICONF1,
1732                      m_FC_SAMPLE_SIZE | m_FC_SAMPLE_FREQ,
1733                      v_FC_SAMPLE_SIZE(0) | v_FC_SAMPLE_FREQ(0));
1734
1735         /* Set Channel Allocation */
1736         hdmi_writel(hdmi_dev, FC_AUDICONF2, 0x00);
1737
1738         /* Set LFEPBLDOWN-MIX INH and LSV */
1739         hdmi_writel(hdmi_dev, FC_AUDICONF3, 0x00);
1740 }
1741
1742 static int hdmi_dev_config_audio(struct hdmi *hdmi, struct hdmi_audio *audio)
1743 {
1744         struct hdmi_dev *hdmi_dev = hdmi->property->priv;
1745         int word_length = 0, channel = 0, mclk_fs;
1746         unsigned int N = 0, CTS = 0;
1747         int rate = 0;
1748         char design_id;
1749
1750         HDMIDBG("%s\n", __func__);
1751
1752         if (audio->channel < 3)
1753                 channel = I2S_CHANNEL_1_2;
1754         else if (audio->channel < 5)
1755                 channel = I2S_CHANNEL_3_4;
1756         else if (audio->channel < 7)
1757                 channel = I2S_CHANNEL_5_6;
1758         else
1759                 channel = I2S_CHANNEL_7_8;
1760
1761         switch (audio->rate) {
1762         case HDMI_AUDIO_FS_32000:
1763                 mclk_fs = FS_128;
1764                 rate = AUDIO_32K;
1765                 if (hdmi_dev->tmdsclk >= 594000000)
1766                         N = N_32K_HIGHCLK;
1767                 else if (hdmi_dev->tmdsclk >= 297000000)
1768                         N = N_32K_MIDCLK;
1769                 else
1770                         N = N_32K_LOWCLK;
1771                 /*div a num to avoid the value is exceed 2^32(int)*/
1772                 CTS = CALC_CTS(N, hdmi_dev->tmdsclk / 1000, 32);
1773                 break;
1774         case HDMI_AUDIO_FS_44100:
1775                 mclk_fs = FS_128;
1776                 rate = AUDIO_441K;
1777                 if (hdmi_dev->tmdsclk >= 594000000)
1778                         N = N_441K_HIGHCLK;
1779                 else if (hdmi_dev->tmdsclk >= 297000000)
1780                         N = N_441K_MIDCLK;
1781                 else
1782                         N = N_441K_LOWCLK;
1783
1784                 CTS = CALC_CTS(N, hdmi_dev->tmdsclk / 100, 441);
1785                 break;
1786         case HDMI_AUDIO_FS_48000:
1787                 mclk_fs = FS_128;
1788                 rate = AUDIO_48K;
1789                 if (hdmi_dev->tmdsclk >= 594000000)     /*FS_153.6*/
1790                         N = N_48K_HIGHCLK;
1791                 else if (hdmi_dev->tmdsclk >= 297000000)
1792                         N = N_48K_MIDCLK;
1793                 else
1794                         N = N_48K_LOWCLK;
1795
1796                 CTS = CALC_CTS(N, hdmi_dev->tmdsclk / 1000, 48);
1797                 break;
1798         case HDMI_AUDIO_FS_88200:
1799                 mclk_fs = FS_128;
1800                 rate = AUDIO_882K;
1801                 if (hdmi_dev->tmdsclk >= 594000000)
1802                         N = N_882K_HIGHCLK;
1803                 else if (hdmi_dev->tmdsclk >= 297000000)
1804                         N = N_882K_MIDCLK;
1805                 else
1806                         N = N_882K_LOWCLK;
1807
1808                 CTS = CALC_CTS(N, hdmi_dev->tmdsclk / 100, 882);
1809                 break;
1810         case HDMI_AUDIO_FS_96000:
1811                 mclk_fs = FS_128;
1812                 rate = AUDIO_96K;
1813                 if (hdmi_dev->tmdsclk >= 594000000)     /*FS_153.6*/
1814                         N = N_96K_HIGHCLK;
1815                 else if (hdmi_dev->tmdsclk >= 297000000)
1816                         N = N_96K_MIDCLK;
1817                 else
1818                         N = N_96K_LOWCLK;
1819
1820                 CTS = CALC_CTS(N, hdmi_dev->tmdsclk / 1000, 96);
1821                 break;
1822         case HDMI_AUDIO_FS_176400:
1823                 mclk_fs = FS_128;
1824                 rate = AUDIO_1764K;
1825                 if (hdmi_dev->tmdsclk >= 594000000)
1826                         N = N_1764K_HIGHCLK;
1827                 else if (hdmi_dev->tmdsclk >= 297000000)
1828                         N = N_1764K_MIDCLK;
1829                 else
1830                         N = N_1764K_LOWCLK;
1831
1832                 CTS = CALC_CTS(N, hdmi_dev->tmdsclk / 100, 1764);
1833                 break;
1834         case HDMI_AUDIO_FS_192000:
1835                 mclk_fs = FS_128;
1836                 rate = AUDIO_192K;
1837                 if (hdmi_dev->tmdsclk >= 594000000)     /*FS_153.6*/
1838                         N = N_192K_HIGHCLK;
1839                 else if (hdmi_dev->tmdsclk >= 297000000)
1840                         N = N_192K_MIDCLK;
1841                 else
1842                         N = N_192K_LOWCLK;
1843
1844                 CTS = CALC_CTS(N, hdmi_dev->tmdsclk / 1000, 192);
1845                 break;
1846         default:
1847                 dev_err(hdmi_dev->hdmi->dev,
1848                         "[%s] not support such sample rate %d\n",
1849                         __func__, audio->rate);
1850                 return -ENOENT;
1851         }
1852
1853         switch (audio->word_length) {
1854         case HDMI_AUDIO_WORD_LENGTH_16bit:
1855                 word_length = I2S_16BIT_SAMPLE;
1856                 break;
1857         case HDMI_AUDIO_WORD_LENGTH_20bit:
1858                 word_length = I2S_20BIT_SAMPLE;
1859                 break;
1860         case HDMI_AUDIO_WORD_LENGTH_24bit:
1861                 word_length = I2S_24BIT_SAMPLE;
1862                 break;
1863         default:
1864                 word_length = I2S_16BIT_SAMPLE;
1865         }
1866
1867         HDMIDBG("rate = %d, tmdsclk = %u, N = %d, CTS = %d\n",
1868                 audio->rate, hdmi_dev->tmdsclk, N, CTS);
1869         /* more than 2 channels => layout 1 else layout 0 */
1870         hdmi_msk_reg(hdmi_dev, FC_AUDSCONF,
1871                      m_AUD_PACK_LAYOUT,
1872                      v_AUD_PACK_LAYOUT((audio->channel > 2) ? 1 : 0));
1873
1874         if (hdmi_dev->audiosrc == HDMI_AUDIO_SRC_SPDIF) {
1875                 mclk_fs = FS_128;
1876                 hdmi_msk_reg(hdmi_dev, AUD_CONF0,
1877                              m_I2S_SEL, v_I2S_SEL(AUDIO_SPDIF_GPA));
1878                 hdmi_msk_reg(hdmi_dev, AUD_SPDIF1,
1879                              m_SET_NLPCM | m_SPDIF_WIDTH,
1880                              v_SET_NLPCM(PCM_LINEAR) |
1881                              v_SPDIF_WIDTH(word_length));
1882                 /*Mask fifo empty and full int and reset fifo*/
1883                 hdmi_msk_reg(hdmi_dev, AUD_SPDIFINT,
1884                              m_FIFO_EMPTY_MASK | m_FIFO_FULL_MASK,
1885                              v_FIFO_EMPTY_MASK(1) | v_FIFO_FULL_MASK(1));
1886                 hdmi_msk_reg(hdmi_dev, AUD_SPDIF0,
1887                              m_SW_SAUD_FIFO_RST, v_SW_SAUD_FIFO_RST(1));
1888         } else {
1889                 /*Mask fifo empty and full int and reset fifo*/
1890                 hdmi_msk_reg(hdmi_dev, AUD_INT,
1891                              m_FIFO_EMPTY_MASK | m_FIFO_FULL_MASK,
1892                              v_FIFO_EMPTY_MASK(1) | v_FIFO_FULL_MASK(1));
1893                 hdmi_msk_reg(hdmi_dev, AUD_CONF0,
1894                              m_SW_AUD_FIFO_RST, v_SW_AUD_FIFO_RST(1));
1895                 hdmi_writel(hdmi_dev, MC_SWRSTZREQ, 0xF7);
1896                 design_id = hdmi_readl(hdmi_dev, DESIGN_ID);
1897                 if (design_id >= 0x21)
1898                         hdmi_writel(hdmi_dev, AUD_CONF2, 0x4);
1899                 else
1900                         hdmi_writel(hdmi_dev, AUD_CONF2, 0x0);
1901                 usleep_range(90, 100);
1902                 /*
1903                  * when we try to use hdmi nlpcm mode
1904                  * we should use set AUD_CONF2 to open this route and set
1905                  * word_length to 24bit for b.p.c.u.v with 16bit raw data
1906                  * when the bitstream data  up to 8 channel, we should use
1907                  * the hdmi hbr mode
1908                  * HBR Mode : Dolby TrueHD
1909                  *            Dolby Atmos
1910                  *            DTS-HDMA
1911                  * NLPCM Mode :
1912                  * FS_32000 FS_44100 FS_48000 : Dolby Digital &  DTS
1913                  * FS_176400 FS_192000        : Dolby Digital Plus
1914                  */
1915                 if (audio->type == HDMI_AUDIO_NLPCM) {
1916                         if (channel == I2S_CHANNEL_7_8) {
1917                                 HDMIDBG("hbr mode.\n");
1918                                 hdmi_writel(hdmi_dev, AUD_CONF2, 0x1);
1919                                 word_length = I2S_24BIT_SAMPLE;
1920                         } else if ((audio->rate == HDMI_AUDIO_FS_32000) ||
1921                                    (audio->rate == HDMI_AUDIO_FS_44100) ||
1922                                    (audio->rate == HDMI_AUDIO_FS_48000) ||
1923                                    (audio->rate == HDMI_AUDIO_FS_176400) ||
1924                                    (audio->rate == HDMI_AUDIO_FS_192000)) {
1925                                 HDMIDBG("nlpcm mode.\n");
1926                                 hdmi_writel(hdmi_dev, AUD_CONF2, 0x2);
1927                                 word_length = I2S_24BIT_SAMPLE;
1928                         } else {
1929                                 hdmi_writel(hdmi_dev, AUD_CONF2, 0x0);
1930                         }
1931                 } else {
1932                         if (design_id >= 0x21)
1933                                 hdmi_writel(hdmi_dev, AUD_CONF2, 0x4);
1934                         else
1935                                 hdmi_writel(hdmi_dev, AUD_CONF2, 0x0);
1936                 }
1937                 hdmi_msk_reg(hdmi_dev, AUD_CONF0,
1938                              m_I2S_SEL | m_I2S_IN_EN,
1939                              v_I2S_SEL(AUDIO_I2S) | v_I2S_IN_EN(channel));
1940                 hdmi_writel(hdmi_dev, AUD_CONF1,
1941                             v_I2S_MODE(I2S_STANDARD_MODE) |
1942                             v_I2S_WIDTH(word_length));
1943         }
1944
1945         hdmi_msk_reg(hdmi_dev, AUD_INPUTCLKFS,
1946                      m_LFS_FACTOR, v_LFS_FACTOR(mclk_fs));
1947
1948         /*Set N value*/
1949         hdmi_msk_reg(hdmi_dev, AUD_N3, m_NCTS_ATOMIC_WR, v_NCTS_ATOMIC_WR(1));
1950         /*Set CTS by manual*/
1951         hdmi_msk_reg(hdmi_dev, AUD_CTS3,
1952                      m_N_SHIFT | m_CTS_MANUAL | m_AUD_CTS3,
1953                      v_N_SHIFT(N_SHIFT_1) |
1954                      v_CTS_MANUAL(1) |
1955                      v_AUD_CTS3(CTS >> 16));
1956         hdmi_writel(hdmi_dev, AUD_CTS2, (CTS >> 8) & 0xff);
1957         hdmi_writel(hdmi_dev, AUD_CTS1, CTS & 0xff);
1958
1959         hdmi_msk_reg(hdmi_dev, AUD_N3, m_AUD_N3, v_AUD_N3(N >> 16));
1960         hdmi_writel(hdmi_dev, AUD_N2, (N >> 8) & 0xff);
1961         hdmi_writel(hdmi_dev, AUD_N1, N & 0xff);
1962
1963         /* set channel status register */
1964         hdmi_msk_reg(hdmi_dev, FC_AUDSCHNLS7,
1965                      m_AUDIO_SAMPLE_RATE, v_AUDIO_SAMPLE_RATE(rate));
1966         hdmi_writel(hdmi_dev, FC_AUDSCHNLS8, ((~rate) << 4) | 0x2);
1967
1968         hdmi_msk_reg(hdmi_dev, AUD_CONF0,
1969                      m_SW_AUD_FIFO_RST, v_SW_AUD_FIFO_RST(1));
1970
1971         hdmi_dev_config_aai(hdmi_dev, audio);
1972
1973         return 0;
1974 }
1975
1976 static int hdmi_dev_control_output(struct hdmi *hdmi, int enable)
1977 {
1978         struct hdmi_dev *hdmi_dev = hdmi->property->priv;
1979         struct hdmi_video vpara;
1980
1981         HDMIDBG("[%s] %d\n", __func__, enable);
1982         if (enable == HDMI_AV_UNMUTE) {
1983                 hdmi_writel(hdmi_dev, FC_DBGFORCE, 0x00);
1984                 if (hdmi->edid.sink_hdmi == OUTPUT_HDMI)
1985                         hdmi_msk_reg(hdmi_dev, FC_GCP,
1986                                      m_FC_SET_AVMUTE | m_FC_CLR_AVMUTE,
1987                                      v_FC_SET_AVMUTE(0) | v_FC_CLR_AVMUTE(1));
1988         } else {
1989                 if (enable & HDMI_VIDEO_MUTE) {
1990                         hdmi_msk_reg(hdmi_dev, FC_DBGFORCE,
1991                                      m_FC_FORCEVIDEO, v_FC_FORCEVIDEO(1));
1992                         if (hdmi->edid.sink_hdmi == OUTPUT_HDMI) {
1993                                 hdmi_msk_reg(hdmi_dev, FC_GCP,
1994                                              m_FC_SET_AVMUTE |
1995                                              m_FC_CLR_AVMUTE,
1996                                              v_FC_SET_AVMUTE(1) |
1997                                              v_FC_CLR_AVMUTE(0));
1998                                 vpara.vic = hdmi->vic;
1999                                 vpara.color_output = HDMI_COLOR_RGB_0_255;
2000                                 hdmi_dev_config_avi(hdmi_dev, &vpara);
2001                                 while ((!hdmi_readl(hdmi_dev, IH_FC_STAT1)) &
2002                                        m_AVI_INFOFRAME) {
2003                                         usleep_range(900, 1000);
2004                                 }
2005                         }
2006                 }
2007 /*              if (enable & HDMI_AUDIO_MUTE) {
2008  *                      hdmi_msk_reg(hdmi_dev, FC_AUDSCONF,
2009  *                                   m_AUD_PACK_SAMPFIT,
2010  *                                   v_AUD_PACK_SAMPFIT(0x0F));
2011  *              }
2012  */
2013                 if (enable == (HDMI_VIDEO_MUTE | HDMI_AUDIO_MUTE)) {
2014                         if (hdmi->ops->hdcp_power_off_cb)
2015                                 hdmi->ops->hdcp_power_off_cb(hdmi);
2016                         rockchip_hdmiv2_powerdown(hdmi_dev);
2017                 }
2018         }
2019         return 0;
2020 }
2021
2022 static int hdmi_dev_insert(struct hdmi *hdmi)
2023 {
2024         struct hdmi_dev *hdmi_dev = hdmi->property->priv;
2025
2026         HDMIDBG("%s\n", __func__);
2027         if (!hdmi->uboot)
2028                 hdmi_writel(hdmi_dev, MC_CLKDIS, m_HDCPCLK_DISABLE);
2029         return HDMI_ERROR_SUCCESS;
2030 }
2031
2032 static int hdmi_dev_remove(struct hdmi *hdmi)
2033 {
2034         struct hdmi_dev *hdmi_dev = hdmi->property->priv;
2035
2036         HDMIDBG("%s\n", __func__);
2037         if (hdmi->ops->hdcp_power_off_cb)
2038                 hdmi->ops->hdcp_power_off_cb(hdmi);
2039         rockchip_hdmiv2_powerdown(hdmi_dev);
2040         hdmi_dev->tmdsclk = 0;
2041         return HDMI_ERROR_SUCCESS;
2042 }
2043
2044 static int hdmi_dev_enable(struct hdmi *hdmi)
2045 {
2046         struct hdmi_dev *hdmi_dev = hdmi->property->priv;
2047
2048         HDMIDBG("%s\n", __func__);
2049         if (!hdmi_dev->enable) {
2050                 hdmi_writel(hdmi_dev, IH_MUTE, 0x00);
2051                 hdmi_dev->enable = 1;
2052         }
2053         hdmi_submit_work(hdmi, HDMI_HPD_CHANGE, 10, 0);
2054         return 0;
2055 }
2056
2057 static int hdmi_dev_disable(struct hdmi *hdmi)
2058 {
2059         struct hdmi_dev *hdmi_dev = hdmi->property->priv;
2060
2061         HDMIDBG("%s\n", __func__);
2062         if (hdmi_dev->enable) {
2063                 hdmi_dev->enable = 0;
2064                 hdmi_writel(hdmi_dev, IH_MUTE, 0x1);
2065         }
2066         return 0;
2067 }
2068
2069 void rockchip_hdmiv2_dev_init_ops(struct hdmi_ops *ops)
2070 {
2071         if (ops) {
2072                 ops->enable     = hdmi_dev_enable;
2073                 ops->disable    = hdmi_dev_disable;
2074                 ops->getstatus  = hdmi_dev_detect_hotplug;
2075                 ops->insert     = hdmi_dev_insert;
2076                 ops->remove     = hdmi_dev_remove;
2077                 ops->getedid    = hdmi_dev_read_edid;
2078                 ops->setvideo   = hdmi_dev_config_video;
2079                 ops->setaudio   = hdmi_dev_config_audio;
2080                 ops->setmute    = hdmi_dev_control_output;
2081                 ops->setvsi     = hdmi_dev_config_vsi;
2082         }
2083 }
2084
2085 void rockchip_hdmiv2_dev_initial(struct hdmi_dev *hdmi_dev)
2086 {
2087         struct hdmi *hdmi = hdmi_dev->hdmi;
2088
2089         /*lcdc source select*/
2090         if (hdmi_dev->soctype == HDMI_SOC_RK3288) {
2091                 grf_writel(HDMI_SEL_LCDC(hdmi->property->videosrc, 4),
2092                            RK3288_GRF_SOC_CON6);
2093                 /* select GPIO7_C0 as cec pin */
2094                 grf_writel(((1 << 12) | (1 << 28)), RK3288_GRF_SOC_CON8);
2095         } else if (hdmi_dev->soctype == HDMI_SOC_RK3399) {
2096                 regmap_write(hdmi_dev->grf_base,
2097                              RK3399_GRF_SOC_CON20,
2098                              HDMI_SEL_LCDC(hdmi->property->videosrc, 6));
2099         }
2100
2101         if (!hdmi->uboot) {
2102                 pr_info("reset hdmi\n");
2103                 if (hdmi_dev->soctype == HDMI_SOC_RK3288) {
2104                         rk3288_cru_set_soft_reset(RK3288_SOFT_RST_HDMI, true);
2105                         usleep_range(10, 20);
2106                         rk3288_cru_set_soft_reset(RK3288_SOFT_RST_HDMI, false);
2107                 } else {
2108                         if (hdmi_dev->soctype == HDMI_SOC_RK322X) {
2109                                 regmap_write(hdmi_dev->grf_base,
2110                                              RK322X_GRF_SOC_CON2,
2111                                              RK322X_DDC_MASK_EN);
2112                                 regmap_write(hdmi_dev->grf_base,
2113                                              RK322X_GRF_SOC_CON6,
2114                                              RK322X_IO_3V_DOMAIN);
2115                         }
2116                         reset_control_assert(hdmi_dev->reset);
2117                         usleep_range(10, 20);
2118                         reset_control_deassert(hdmi_dev->reset);
2119                 }
2120                 rockchip_hdmiv2_powerdown(hdmi_dev);
2121         } else {
2122                 hdmi->hotplug = hdmi_dev_detect_hotplug(hdmi);
2123                 if (hdmi->hotplug != HDMI_HPD_ACTIVED)
2124                         hdmi->uboot = 0;
2125         }
2126         /*mute unnecessary interrupt, only enable hpd*/
2127         hdmi_writel(hdmi_dev, IH_MUTE_FC_STAT0, 0xff);
2128         hdmi_writel(hdmi_dev, IH_MUTE_FC_STAT1, 0xff);
2129         hdmi_writel(hdmi_dev, IH_MUTE_FC_STAT2, 0xff);
2130         hdmi_writel(hdmi_dev, IH_MUTE_AS_STAT0, 0xff);
2131         hdmi_writel(hdmi_dev, IH_MUTE_PHY_STAT0, 0xfc);
2132         hdmi_writel(hdmi_dev, IH_MUTE_I2CM_STAT0, 0xff);
2133         hdmi_writel(hdmi_dev, IH_MUTE_CEC_STAT0, 0xff);
2134         hdmi_writel(hdmi_dev, IH_MUTE_VP_STAT0, 0xff);
2135         hdmi_writel(hdmi_dev, IH_MUTE_I2CMPHY_STAT0, 0xff);
2136         hdmi_writel(hdmi_dev, IH_MUTE_AHBDMAAUD_STAT0, 0xff);
2137
2138         /* disable hdcp interrupt */
2139         hdmi_writel(hdmi_dev, A_APIINTMSK, 0xff);
2140         hdmi_writel(hdmi_dev, PHY_MASK, 0xf1);
2141
2142         if (hdmi->property->feature & SUPPORT_CEC)
2143                 rockchip_hdmiv2_cec_init(hdmi);
2144         if (hdmi->property->feature & SUPPORT_HDCP)
2145                 rockchip_hdmiv2_hdcp_init(hdmi);
2146 }
2147
2148 irqreturn_t rockchip_hdmiv2_dev_irq(int irq, void *priv)
2149 {
2150         struct hdmi_dev *hdmi_dev = priv;
2151         struct hdmi *hdmi = hdmi_dev->hdmi;
2152         char phy_pol = hdmi_readl(hdmi_dev, PHY_POL0);
2153         char phy_status = hdmi_readl(hdmi_dev, PHY_STAT0);
2154         char phy_int0 = hdmi_readl(hdmi_dev, PHY_INI0);
2155         /*read interrupt*/
2156         char fc_stat0 = hdmi_readl(hdmi_dev, IH_FC_STAT0);
2157         char fc_stat1 = hdmi_readl(hdmi_dev, IH_FC_STAT1);
2158         char fc_stat2 = hdmi_readl(hdmi_dev, IH_FC_STAT2);
2159         char aud_int = hdmi_readl(hdmi_dev, IH_AS_SATA0);
2160         char phy_int = hdmi_readl(hdmi_dev, IH_PHY_STAT0);
2161         char vp_stat0 = hdmi_readl(hdmi_dev, IH_VP_STAT0);
2162         char cec_int = hdmi_readl(hdmi_dev, IH_CEC_STAT0);
2163         char hdcp_int = hdmi_readl(hdmi_dev, A_APIINTSTAT);
2164         char hdcp2_int = hdmi_readl(hdmi_dev, HDCP2REG_STAT);
2165
2166         /*clear interrupt*/
2167         hdmi_writel(hdmi_dev, IH_FC_STAT0, fc_stat0);
2168         hdmi_writel(hdmi_dev, IH_FC_STAT1, fc_stat1);
2169         hdmi_writel(hdmi_dev, IH_FC_STAT2, fc_stat2);
2170         hdmi_writel(hdmi_dev, IH_VP_STAT0, vp_stat0);
2171
2172         if (phy_int0 || phy_int) {
2173                 if ((phy_int0 & m_PHY_LOCK) &&
2174                     (phy_pol & m_PHY_LOCK) == 0) {
2175                         pr_info("hdmi phy pll unlock\n");
2176                         hdmi_submit_work(hdmi, HDMI_SET_VIDEO, 0, 0);
2177                 }
2178                 phy_pol = (phy_int0 & (~phy_status)) | ((~phy_int0) & phy_pol);
2179                 hdmi_writel(hdmi_dev, PHY_POL0, phy_pol);
2180                 hdmi_writel(hdmi_dev, IH_PHY_STAT0, phy_int);
2181                 if ((phy_int & m_HPD) || ((phy_int & 0x3c) == 0x3c))
2182                         hdmi_submit_work(hdmi, HDMI_HPD_CHANGE, 20, 0);
2183         }
2184
2185         /* Audio error */
2186         if (aud_int) {
2187                 hdmi_writel(hdmi_dev, IH_AS_SATA0, aud_int);
2188                 hdmi_msk_reg(hdmi_dev, AUD_CONF0,
2189                              m_SW_AUD_FIFO_RST, v_SW_AUD_FIFO_RST(1));
2190                 hdmi_writel(hdmi_dev, MC_SWRSTZREQ, 0xF7);
2191         }
2192         /* CEC */
2193         if (cec_int) {
2194                 hdmi_writel(hdmi_dev, IH_CEC_STAT0, cec_int);
2195                 if (hdmi_dev->hdmi->property->feature & SUPPORT_CEC)
2196                         rockchip_hdmiv2_cec_isr(hdmi_dev, cec_int);
2197         }
2198         /* HDCP */
2199         if (hdcp_int) {
2200                 hdmi_writel(hdmi_dev, A_APIINTCLR, hdcp_int);
2201                 rockchip_hdmiv2_hdcp_isr(hdmi_dev, hdcp_int);
2202         }
2203
2204         /* HDCP2 */
2205         if (hdcp2_int) {
2206                 hdmi_writel(hdmi_dev, HDCP2REG_STAT, hdcp2_int);
2207                 pr_info("hdcp2_int is 0x%02x\n", hdcp2_int);
2208                 if ((hdcp2_int & m_HDCP2_AUTH_FAIL ||
2209                      hdcp2_int & m_HDCP2_AUTH_LOST) &&
2210                     hdmi_dev->hdcp2_start) {
2211                         pr_info("hdcp2 failed or lost\n");
2212                         hdmi_dev->hdcp2_start();
2213                 }
2214         }
2215         return IRQ_HANDLED;
2216 }