1 /* ==========================================================================
2 * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_driver.c $
7 * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
8 * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
9 * otherwise expressly agreed to in writing between Synopsys and you.
11 * The Software IS NOT an item of Licensed Software or Licensed Product under
12 * any End User Software License Agreement or Agreement for Licensed Product
13 * with Synopsys or any supplement thereto. You are permitted to use and
14 * redistribute this Software in source and binary forms, with or without
15 * modification, provided that redistributions of source code must retain this
16 * notice. You may not view, use, disclose, copy or distribute this file or
17 * any information contained herein except pursuant to this license grant from
18 * Synopsys. If you do not agree with this notice, including the disclaimer
19 * below, then you are not authorized to use the Software.
21 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
25 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
26 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
27 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
28 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
32 * ========================================================================== */
35 * The dwc_otg_driver module provides the initialization and cleanup entry
36 * points for the DWC_otg driver. This module will be dynamically installed
37 * after Linux is booted using the insmod command. When the module is
38 * installed, the dwc_otg_driver_init function is called. When the module is
39 * removed (using rmmod), the dwc_otg_driver_cleanup function is called.
41 * This module also defines a data structure for the dwc_otg_driver, which is
42 * used in conjunction with the standard ARM lm_device structure. These
43 * structures allow the OTG driver to comply with the standard Linux driver
44 * model in which devices and drivers are registered with a bus driver. This
45 * has the benefit that Linux can expose attributes of the driver and device
46 * in its special sysfs file system. Users can then read or write files in
47 * this file system to perform diagnostics on the driver components or the
51 #include "dwc_otg_os_dep.h"
52 #include "common_port/dwc_os.h"
53 #include "dwc_otg_dbg.h"
54 #include "dwc_otg_driver.h"
55 #include "dwc_otg_attr.h"
56 #include "dwc_otg_core_if.h"
57 #include "dwc_otg_pcd_if.h"
58 #include "dwc_otg_hcd_if.h"
59 #include "dwc_otg_cil.h"
60 #include "dwc_otg_pcd.h"
62 #include "usbdev_rk.h"
64 #define DWC_DRIVER_VERSION "3.10a 21-DEC-2012"
65 #define DWC_DRIVER_DESC "HS OTG USB Controller driver"
67 static const char dwc_host20_driver_name[] = "usb20_host";
68 static const char dwc_otg20_driver_name[] = "usb20_otg";
70 dwc_otg_device_t *g_otgdev;
72 extern int pcd_init(struct platform_device *_dev);
73 extern int otg20_hcd_init(struct platform_device *_dev);
74 extern int host20_hcd_init(struct platform_device *_dev);
75 extern int pcd_remove(struct platform_device *_dev);
76 extern void hcd_remove(struct platform_device *_dev);
77 extern void dwc_otg_adp_start(dwc_otg_core_if_t *core_if, uint8_t is_host);
79 #ifdef CONFIG_USB20_OTG
80 static struct usb20otg_pdata_id usb20otg_pdata[] = {
82 .name = "rk3188-usb20otg",
83 .pdata = &usb20otg_pdata_rk3188,
86 .name = "rk3288-usb20otg",
87 .pdata = &usb20otg_pdata_rk3288,
90 .name = "rk3036-usb20otg",
91 .pdata = &usb20otg_pdata_rk3036,
94 .name = "rk3126-usb20otg",
95 .pdata = &usb20otg_pdata_rk3126,
101 #ifdef CONFIG_USB20_HOST
102 static struct usb20host_pdata_id usb20host_pdata[] = {
104 .name = "rk3188-usb20host",
105 .pdata = &usb20host_pdata_rk3188,
108 .name = "rk3288-usb20host",
109 .pdata = &usb20host_pdata_rk3288,
112 .name = "rk3036-usb20host",
113 .pdata = &usb20host_pdata_rk3036,
116 .name = "rk3126-usb20host",
117 .pdata = &usb20host_pdata_rk3126,
123 static u32 usb_to_uart_status;
124 /*-------------------------------------------------------------------------*/
125 /* Encapsulate the module parameter settings */
127 struct dwc_otg_driver_module_params {
131 int32_t dma_desc_enable;
132 int32_t dma_burst_size;
134 int32_t host_support_fs_ls_low_power;
135 int32_t host_ls_low_power_phy_clk;
136 int32_t enable_dynamic_fifo;
137 int32_t data_fifo_size;
138 int32_t dev_rx_fifo_size;
139 int32_t dev_nperio_tx_fifo_size;
140 uint32_t dev_perio_tx_fifo_size[MAX_PERIO_FIFOS];
141 int32_t host_rx_fifo_size;
142 int32_t host_nperio_tx_fifo_size;
143 int32_t host_perio_tx_fifo_size;
144 int32_t max_transfer_size;
145 int32_t max_packet_count;
146 int32_t host_channels;
147 int32_t dev_endpoints;
149 int32_t phy_utmi_width;
150 int32_t phy_ulpi_ddr;
151 int32_t phy_ulpi_ext_vbus;
155 int32_t en_multiple_tx_fifo;
156 uint32_t dev_tx_fifo_size[MAX_TX_FIFOS];
158 uint32_t tx_thr_length;
159 uint32_t rx_thr_length;
164 int32_t baseline_besl;
167 int32_t ahb_thr_ratio;
177 static struct dwc_otg_driver_module_params dwc_otg_module_params = {
179 .otg_cap = DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE,
181 .dma_desc_enable = 0,
182 .dma_burst_size = -1,
184 .host_support_fs_ls_low_power = -1,
185 .host_ls_low_power_phy_clk = -1,
186 .enable_dynamic_fifo = 1,
187 .data_fifo_size = -1,
188 .dev_rx_fifo_size = 0x120,
189 .dev_nperio_tx_fifo_size = 0x10,
190 .dev_perio_tx_fifo_size = {
191 /* dev_perio_tx_fifo_size_1 */
209 .host_rx_fifo_size = -1,
210 .host_nperio_tx_fifo_size = -1,
211 .host_perio_tx_fifo_size = -1,
212 .max_transfer_size = -1,
213 .max_packet_count = -1,
217 .phy_utmi_width = -1,
219 .phy_ulpi_ext_vbus = -1,
223 .en_multiple_tx_fifo = -1,
224 .dev_tx_fifo_size = {
225 /* dev_tx_fifo_size */
263 #ifdef CONFIG_USB20_HOST
264 static struct dwc_otg_driver_module_params dwc_host_module_params = {
266 .otg_cap = DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE,
268 .dma_desc_enable = 0,
269 .dma_burst_size = -1,
271 .host_support_fs_ls_low_power = -1,
272 .host_ls_low_power_phy_clk = -1,
273 .enable_dynamic_fifo = -1,
274 .data_fifo_size = -1,
275 .dev_rx_fifo_size = -1,
276 .dev_nperio_tx_fifo_size = -1,
277 .dev_perio_tx_fifo_size = {
278 /* dev_perio_tx_fifo_size_1 */
296 .host_rx_fifo_size = -1,
297 .host_nperio_tx_fifo_size = -1,
298 .host_perio_tx_fifo_size = -1,
299 .max_transfer_size = -1,
300 .max_packet_count = -1,
304 .phy_utmi_width = -1,
306 .phy_ulpi_ext_vbus = -1,
310 .en_multiple_tx_fifo = -1,
311 .dev_tx_fifo_size = {
312 /* dev_tx_fifo_size */
352 * This function shows the Driver Version.
354 static ssize_t version_show(struct device_driver *dev, char *buf)
356 return snprintf(buf, sizeof(DWC_DRIVER_VERSION) + 2, "%s\n",
360 static DRIVER_ATTR(version, S_IRUGO, version_show, NULL);
363 * Global Debug Level Mask.
365 uint32_t g_dbg_lvl = DBG_OFF; /* OFF */
368 * This function shows the driver Debug Level.
370 static ssize_t dbg_level_show(struct device_driver *drv, char *buf)
372 return sprintf(buf, "0x%0x\n", g_dbg_lvl);
376 * This function stores the driver Debug Level.
378 static ssize_t dbg_level_store(struct device_driver *drv, const char *buf,
381 g_dbg_lvl = simple_strtoul(buf, NULL, 16);
385 static DRIVER_ATTR(debuglevel, S_IRUGO | S_IWUSR, dbg_level_show,
388 extern void hcd_start(dwc_otg_core_if_t *core_if);
389 extern struct usb_hub *g_dwc_otg_root_hub20;
390 extern void dwc_otg_hub_disconnect_device(struct usb_hub *hub);
392 void dwc_otg_force_host(dwc_otg_core_if_t *core_if)
394 dwc_otg_device_t *otg_dev = core_if->otg_dev;
395 dctl_data_t dctl = {.d32 = 0 };
398 if (core_if->op_state == A_HOST) {
399 printk("dwc_otg_force_host,already in A_HOST mode,everest\n");
402 core_if->op_state = A_HOST;
404 cancel_delayed_work(&otg_dev->pcd->check_vbus_work);
405 dctl.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dctl);
406 dctl.b.sftdiscon = 1;
407 DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dctl, dctl.d32);
409 local_irq_save(flags);
410 cil_pcd_stop(core_if);
412 * Initialize the Core for Host mode.
415 dwc_otg_core_init(core_if);
416 dwc_otg_enable_global_interrupts(core_if);
417 cil_hcd_start(core_if);
418 local_irq_restore(flags);
421 void dwc_otg_force_device(dwc_otg_core_if_t *core_if)
423 dwc_otg_device_t *otg_dev = core_if->otg_dev;
426 local_irq_save(flags);
428 if (core_if->op_state == B_PERIPHERAL) {
430 ("dwc_otg_force_device,already in B_PERIPHERAL,everest\n");
433 core_if->op_state = B_PERIPHERAL;
434 cil_hcd_stop(core_if);
435 /* dwc_otg_hub_disconnect_device(g_dwc_otg_root_hub20); */
436 otg_dev->pcd->phy_suspend = 1;
437 otg_dev->pcd->vbus_status = 0;
438 dwc_otg_pcd_start_check_vbus_work(otg_dev->pcd);
440 /* Reset the Controller */
441 dwc_otg_core_reset(core_if);
443 dwc_otg_core_init(core_if);
444 dwc_otg_disable_global_interrupts(core_if);
445 cil_pcd_start(core_if);
447 local_irq_restore(flags);
450 static ssize_t force_usb_mode_show(struct device_driver *drv, char *buf)
452 dwc_otg_device_t *otg_dev = g_otgdev;
453 dwc_otg_core_if_t *core_if = otg_dev->core_if;
455 return sprintf(buf, "%d\n", core_if->usb_mode);
458 static ssize_t force_usb_mode_store(struct device_driver *drv, const char *buf,
461 int new_mode = simple_strtoul(buf, NULL, 16);
462 dwc_otg_device_t *otg_dev = g_otgdev;
463 dwc_otg_core_if_t *core_if;
464 struct dwc_otg_platform_data *pldata;
469 core_if = otg_dev->core_if;
470 pldata = otg_dev->pldata;
472 DWC_PRINTF("%s %d->%d\n", __func__, core_if->usb_mode, new_mode);
474 if (core_if->usb_mode == new_mode) {
478 if (pldata->phy_status == USB_PHY_SUSPEND) {
479 pldata->clock_enable(pldata, 1);
480 pldata->phy_suspend(pldata, USB_PHY_ENABLED);
484 case USB_MODE_FORCE_HOST:
485 if (USB_MODE_FORCE_DEVICE == core_if->usb_mode) {
487 core_if->usb_mode = new_mode;
488 dwc_otg_force_host(core_if);
489 } else if (USB_MODE_NORMAL == core_if->usb_mode) {
490 core_if->usb_mode = new_mode;
491 if (dwc_otg_is_host_mode(core_if))
492 dwc_otg_set_force_mode(core_if, new_mode);
494 dwc_otg_force_host(core_if);
498 case USB_MODE_FORCE_DEVICE:
499 if (USB_MODE_FORCE_HOST == core_if->usb_mode) {
500 core_if->usb_mode = new_mode;
501 dwc_otg_force_device(core_if);
502 } else if (USB_MODE_NORMAL == core_if->usb_mode) {
503 core_if->usb_mode = new_mode;
504 if (dwc_otg_is_device_mode(core_if))
505 dwc_otg_set_force_mode(core_if, new_mode);
507 dwc_otg_force_device(core_if);
511 case USB_MODE_NORMAL:
512 if (USB_MODE_FORCE_DEVICE == core_if->usb_mode) {
513 core_if->usb_mode = new_mode;
514 cancel_delayed_work(&otg_dev->pcd->check_vbus_work);
515 dwc_otg_set_force_mode(core_if, new_mode);
517 if (dwc_otg_is_host_mode(core_if)) {
518 dwc_otg_force_host(core_if);
520 dwc_otg_pcd_start_check_vbus_work(otg_dev->pcd);
522 } else if (USB_MODE_FORCE_HOST == core_if->usb_mode) {
523 core_if->usb_mode = new_mode;
524 dwc_otg_set_force_mode(core_if, new_mode);
526 if (dwc_otg_is_device_mode(core_if)) {
527 dwc_otg_force_device(core_if);
538 static DRIVER_ATTR(force_usb_mode, S_IRUGO | S_IWUSR, force_usb_mode_show,
539 force_usb_mode_store);
541 static ssize_t dwc_otg_conn_en_show(struct device_driver *_drv, char *_buf)
544 dwc_otg_device_t *otg_dev = g_otgdev;
545 dwc_otg_pcd_t *_pcd = otg_dev->pcd;
546 return sprintf(_buf, "%d\n", _pcd->conn_en);
550 static ssize_t dwc_otg_conn_en_store(struct device_driver *_drv,
551 const char *_buf, size_t _count)
553 int enable = simple_strtoul(_buf, NULL, 10);
554 dwc_otg_device_t *otg_dev = g_otgdev;
555 dwc_otg_pcd_t *_pcd = otg_dev->pcd;
556 DWC_PRINTF("%s %d->%d\n", __func__, _pcd->conn_en, enable);
558 _pcd->conn_en = enable;
562 static DRIVER_ATTR(dwc_otg_conn_en, S_IRUGO | S_IWUSR, dwc_otg_conn_en_show,
563 dwc_otg_conn_en_store);
565 /* used for product vbus power control, SDK not need.
566 * If dwc_otg is host mode, enable vbus power.
567 * If dwc_otg is device mode, disable vbus power.
568 * return 1 - host mode, 0 - device mode.
570 int dwc_otg_usb_state(void)
572 dwc_otg_device_t *otg_dev = g_otgdev;
575 /* op_state is A_HOST */
576 if (1 == otg_dev->core_if->op_state)
578 /* op_state is B_PERIPHERAL */
579 else if (4 == otg_dev->core_if->op_state)
584 DWC_WARN("g_otgdev is NULL, maybe otg probe is failed!\n");
588 EXPORT_SYMBOL(dwc_otg_usb_state);
590 static ssize_t dwc_otg_op_state_show(struct device_driver *_drv, char *_buf)
592 dwc_otg_device_t *otg_dev = g_otgdev;
595 return sprintf(_buf, "%d\n", otg_dev->core_if->op_state);
597 return sprintf(_buf, "%d\n", 0);
600 static DRIVER_ATTR(op_state, S_IRUGO, dwc_otg_op_state_show, NULL);
602 static ssize_t vbus_status_show(struct device_driver *_drv, char *_buf)
604 dwc_otg_device_t *otg_dev = g_otgdev;
605 dwc_otg_pcd_t *_pcd = otg_dev->pcd;
606 return sprintf(_buf, "%d\n", _pcd->vbus_status);
609 static DRIVER_ATTR(vbus_status, S_IRUGO, vbus_status_show, NULL);
612 * This function is called during module intialization
613 * to pass module parameters to the DWC_OTG CORE.
615 static int set_parameters(dwc_otg_core_if_t *core_if,
616 struct dwc_otg_driver_module_params module_params)
621 if (module_params.otg_cap != -1) {
623 dwc_otg_set_param_otg_cap(core_if, module_params.otg_cap);
625 if (module_params.dma_enable != -1) {
627 dwc_otg_set_param_dma_enable(core_if,
628 module_params.dma_enable);
630 if (module_params.dma_desc_enable != -1) {
632 dwc_otg_set_param_dma_desc_enable(core_if,
633 module_params.dma_desc_enable);
635 if (module_params.opt != -1) {
636 retval += dwc_otg_set_param_opt(core_if, module_params.opt);
638 if (module_params.dma_burst_size != -1) {
640 dwc_otg_set_param_dma_burst_size(core_if,
641 module_params.dma_burst_size);
643 if (module_params.host_support_fs_ls_low_power != -1) {
645 dwc_otg_set_param_host_support_fs_ls_low_power(core_if,
646 module_params.host_support_fs_ls_low_power);
648 if (module_params.enable_dynamic_fifo != -1) {
650 dwc_otg_set_param_enable_dynamic_fifo(core_if,
651 module_params.enable_dynamic_fifo);
653 if (module_params.data_fifo_size != -1) {
655 dwc_otg_set_param_data_fifo_size(core_if,
656 module_params.data_fifo_size);
658 if (module_params.dev_rx_fifo_size != -1) {
660 dwc_otg_set_param_dev_rx_fifo_size(core_if,
661 module_params.dev_rx_fifo_size);
663 if (module_params.dev_nperio_tx_fifo_size != -1) {
665 dwc_otg_set_param_dev_nperio_tx_fifo_size(core_if,
666 module_params.dev_nperio_tx_fifo_size);
668 if (module_params.host_rx_fifo_size != -1) {
670 dwc_otg_set_param_host_rx_fifo_size(core_if,
674 if (module_params.host_nperio_tx_fifo_size != -1) {
676 dwc_otg_set_param_host_nperio_tx_fifo_size(core_if,
677 module_params.host_nperio_tx_fifo_size);
679 if (module_params.host_perio_tx_fifo_size != -1) {
681 dwc_otg_set_param_host_perio_tx_fifo_size(core_if,
682 module_params.host_perio_tx_fifo_size);
684 if (module_params.max_transfer_size != -1) {
686 dwc_otg_set_param_max_transfer_size(core_if,
687 module_params.max_transfer_size);
689 if (module_params.max_packet_count != -1) {
691 dwc_otg_set_param_max_packet_count(core_if,
692 module_params.max_packet_count);
694 if (module_params.host_channels != -1) {
696 dwc_otg_set_param_host_channels(core_if,
697 module_params.host_channels);
699 if (module_params.dev_endpoints != -1) {
701 dwc_otg_set_param_dev_endpoints(core_if,
702 module_params.dev_endpoints);
704 if (module_params.phy_type != -1) {
706 dwc_otg_set_param_phy_type(core_if, module_params.phy_type);
708 if (module_params.speed != -1) {
709 retval += dwc_otg_set_param_speed(core_if, module_params.speed);
711 if (module_params.host_ls_low_power_phy_clk != -1) {
713 dwc_otg_set_param_host_ls_low_power_phy_clk(core_if,
714 module_params.host_ls_low_power_phy_clk);
716 if (module_params.phy_ulpi_ddr != -1) {
718 dwc_otg_set_param_phy_ulpi_ddr(core_if,
719 module_params.phy_ulpi_ddr);
721 if (module_params.phy_ulpi_ext_vbus != -1) {
723 dwc_otg_set_param_phy_ulpi_ext_vbus(core_if,
724 module_params.phy_ulpi_ext_vbus);
726 if (module_params.phy_utmi_width != -1) {
728 dwc_otg_set_param_phy_utmi_width(core_if,
729 module_params.phy_utmi_width);
731 if (module_params.ulpi_fs_ls != -1) {
733 dwc_otg_set_param_ulpi_fs_ls(core_if,
734 module_params.ulpi_fs_ls);
736 if (module_params.ts_dline != -1) {
738 dwc_otg_set_param_ts_dline(core_if, module_params.ts_dline);
740 if (module_params.i2c_enable != -1) {
742 dwc_otg_set_param_i2c_enable(core_if,
743 module_params.i2c_enable);
745 if (module_params.en_multiple_tx_fifo != -1) {
747 dwc_otg_set_param_en_multiple_tx_fifo(core_if,
748 module_params.en_multiple_tx_fifo);
750 for (i = 0; i < 15; i++) {
751 if (module_params.dev_perio_tx_fifo_size[i] != -1) {
753 dwc_otg_set_param_dev_perio_tx_fifo_size(core_if,
754 module_params.dev_perio_tx_fifo_size
759 for (i = 0; i < 15; i++) {
760 if (module_params.dev_tx_fifo_size[i] != -1) {
761 retval += dwc_otg_set_param_dev_tx_fifo_size(core_if,
762 module_params.dev_tx_fifo_size
766 if (module_params.thr_ctl != -1) {
768 dwc_otg_set_param_thr_ctl(core_if, module_params.thr_ctl);
770 if (module_params.mpi_enable != -1) {
772 dwc_otg_set_param_mpi_enable(core_if,
773 module_params.mpi_enable);
775 if (module_params.pti_enable != -1) {
777 dwc_otg_set_param_pti_enable(core_if,
778 module_params.pti_enable);
780 if (module_params.lpm_enable != -1) {
782 dwc_otg_set_param_lpm_enable(core_if,
783 module_params.lpm_enable);
785 if (module_params.besl_enable != -1) {
787 dwc_otg_set_param_besl_enable(core_if,
788 module_params.besl_enable);
790 if (module_params.baseline_besl != -1) {
792 dwc_otg_set_param_baseline_besl(core_if,
793 module_params.baseline_besl);
795 if (module_params.deep_besl != -1) {
797 dwc_otg_set_param_deep_besl(core_if,
798 module_params.deep_besl);
800 if (module_params.ic_usb_cap != -1) {
802 dwc_otg_set_param_ic_usb_cap(core_if,
803 module_params.ic_usb_cap);
805 if (module_params.tx_thr_length != -1) {
807 dwc_otg_set_param_tx_thr_length(core_if,
811 if (module_params.rx_thr_length != -1) {
813 dwc_otg_set_param_rx_thr_length(core_if,
814 module_params.rx_thr_length);
816 if (module_params.ahb_thr_ratio != -1) {
818 dwc_otg_set_param_ahb_thr_ratio(core_if,
822 if (module_params.power_down != -1) {
824 dwc_otg_set_param_power_down(core_if,
825 module_params.power_down);
827 if (module_params.reload_ctl != -1) {
829 dwc_otg_set_param_reload_ctl(core_if,
830 module_params.reload_ctl);
833 if (module_params.dev_out_nak != -1) {
835 dwc_otg_set_param_dev_out_nak(core_if,
836 module_params.dev_out_nak);
839 if (module_params.cont_on_bna != -1) {
841 dwc_otg_set_param_cont_on_bna(core_if,
842 module_params.cont_on_bna);
845 if (module_params.ahb_single != -1) {
847 dwc_otg_set_param_ahb_single(core_if,
848 module_params.ahb_single);
851 if (module_params.otg_ver != -1) {
853 dwc_otg_set_param_otg_ver(core_if, module_params.otg_ver);
855 if (module_params.adp_enable != -1) {
857 dwc_otg_set_param_adp_enable(core_if,
858 module_params.adp_enable);
864 * This function is the top level interrupt handler for the Common
865 * (Device and host modes) interrupts.
867 static irqreturn_t dwc_otg_common_irq(int irq, void *dev)
869 int32_t retval = IRQ_NONE;
871 retval = dwc_otg_handle_common_intr(dev);
873 /* S3C2410X_CLEAR_EINTPEND(); */
875 return IRQ_RETVAL(retval);
878 #ifdef CONFIG_USB20_HOST
880 * This function is called when a lm_device is unregistered with the
881 * dwc_otg_driver. This happens, for example, when the rmmod command is
882 * executed. The device may or may not be electrically present. If it is
883 * present, the driver stops device processing. Any resources used on behalf
884 * of this device are freed.
888 static int host20_driver_remove(struct platform_device *_dev)
891 dwc_otg_device_t *otg_dev = dwc_get_device_platform_data(_dev);
892 DWC_DEBUGPL(DBG_ANY, "%s(%p)\n", __func__, _dev);
895 /* Memory allocation for the dwc_otg_device failed. */
896 DWC_DEBUGPL(DBG_ANY, "%s: otg_dev NULL!\n", __func__);
899 #ifndef DWC_DEVICE_ONLY
903 DWC_DEBUGPL(DBG_ANY, "%s: otg_dev->hcd NULL!\n", __func__);
908 #ifndef DWC_HOST_ONLY
912 DWC_DEBUGPL(DBG_ANY, "%s: otg_dev->pcd NULL!\n", __func__);
920 if (otg_dev->common_irq_installed) {
921 /* free_irq(_dev->irq, otg_dev); */
922 free_irq(platform_get_irq(_dev, 0), otg_dev);
924 DWC_DEBUGPL(DBG_ANY, "%s: There is no installed irq!\n",
929 if (otg_dev->core_if) {
930 dwc_otg_cil_remove(otg_dev->core_if);
932 DWC_DEBUGPL(DBG_ANY, "%s: otg_dev->core_if NULL!\n", __func__);
937 * Remove the device attributes
939 dwc_otg_attr_remove(_dev);
944 if (otg_dev->os_dep.base) {
945 iounmap(otg_dev->os_dep.base);
950 * Clear the drvdata pointer.
953 dwc_set_device_platform_data(_dev, 0);
958 static const struct of_device_id usb20_host_of_match[] = {
960 .compatible = "rockchip,rk3188_usb20_host",
961 .data = &usb20host_pdata[RK3188_USB_CTLR],
964 .compatible = "rockchip,rk3288_usb20_host",
965 .data = &usb20host_pdata[RK3288_USB_CTLR],
968 .compatible = "rockchip,rk3036_usb20_host",
969 .data = &usb20host_pdata[RK3036_USB_CTLR],
972 .compatible = "rockchip,rk3126_usb20_host",
973 .data = &usb20host_pdata[RK3126_USB_CTLR],
978 MODULE_DEVICE_TABLE(of, usb20_host_of_match);
981 * This function is called when an lm_device is bound to a
982 * dwc_otg_driver. It creates the driver components required to
983 * control the device (CIL, HCD, and PCD) and it initializes the
984 * device. The driver components are stored in a dwc_otg_device
985 * structure. A reference to the dwc_otg_device is saved in the
986 * lm_device. This allows the driver to access the dwc_otg_device
987 * structure on subsequent calls to driver methods for this device.
989 * @param _dev Bus device
991 static int host20_driver_probe(struct platform_device *_dev)
995 struct resource *res_base;
996 dwc_otg_device_t *dwc_otg_device;
997 struct device *dev = &_dev->dev;
998 struct device_node *node = _dev->dev.of_node;
999 struct dwc_otg_platform_data *pldata;
1000 struct usb20host_pdata_id *p;
1001 const struct of_device_id *match =
1002 of_match_device(of_match_ptr(usb20_host_of_match), &_dev->dev);
1005 p = (struct usb20host_pdata_id *)match->data;
1007 dev_err(dev, "usb20host match failed\n");
1011 dev->platform_data = p->pdata;
1012 pldata = dev->platform_data;
1016 dev_err(dev, "device node not found\n");
1020 if (pldata->hw_init)
1023 if (pldata->clock_init) {
1024 pldata->clock_init(pldata);
1025 pldata->clock_enable(pldata, 1);
1028 if (pldata->phy_suspend)
1029 pldata->phy_suspend(pldata, USB_PHY_ENABLED);
1031 if (pldata->soft_reset)
1032 pldata->soft_reset(pldata, RST_POR);
1034 res_base = platform_get_resource(_dev, IORESOURCE_MEM, 0);
1036 dwc_otg_device = DWC_ALLOC(sizeof(dwc_otg_device_t));
1038 if (!dwc_otg_device) {
1039 dev_err(&_dev->dev, "kmalloc of dwc_otg_device failed\n");
1044 memset(dwc_otg_device, 0, sizeof(*dwc_otg_device));
1045 dwc_otg_device->os_dep.reg_offset = 0xFFFFFFFF;
1048 * Map the DWC_otg Core memory into virtual address space.
1051 dwc_otg_device->os_dep.base = devm_ioremap_resource(dev, res_base);
1053 if (!dwc_otg_device->os_dep.base) {
1054 dev_err(&_dev->dev, "ioremap() failed\n");
1055 DWC_FREE(dwc_otg_device);
1059 dev_dbg(&_dev->dev, "base=0x%08x\n",
1060 (unsigned)dwc_otg_device->os_dep.base);
1063 * Initialize driver data to point to the global DWC_otg
1067 dwc_set_device_platform_data(_dev, dwc_otg_device);
1068 pldata->privdata = dwc_otg_device;
1069 dwc_otg_device->pldata = (void *)pldata;
1071 dev_dbg(&_dev->dev, "dwc_otg_device=0x%p\n", dwc_otg_device);
1073 dwc_otg_device->core_if = dwc_otg_cil_init(dwc_otg_device->os_dep.base);
1075 if (!dwc_otg_device->core_if) {
1076 dev_err(&_dev->dev, "CIL initialization failed!\n");
1081 dwc_otg_device->core_if->otg_dev = dwc_otg_device;
1084 * Attempt to ensure this device is really a DWC_otg Controller.
1085 * Read and verify the SNPSID register contents. The value should be
1086 * 0x45F42XXX or 0x45F42XXX, which corresponds to either "OT2" or "OTG3",
1087 * as in "OTG version 2.XX" or "OTG version 3.XX".
1090 if (((dwc_otg_get_gsnpsid(dwc_otg_device->core_if) & 0xFFFFF000) !=
1092 && ((dwc_otg_get_gsnpsid(dwc_otg_device->core_if) & 0xFFFFF000) !=
1094 dev_err(&_dev->dev, "Bad value for SNPSID: 0x%08x\n",
1095 dwc_otg_get_gsnpsid(dwc_otg_device->core_if));
1101 * Validate parameter values.
1103 if (set_parameters(dwc_otg_device->core_if, dwc_host_module_params)) {
1109 * Create Device Attributes in sysfs
1111 dwc_otg_attr_create(_dev);
1114 * Disable the global interrupt until all the interrupt
1115 * handlers are installed.
1117 dwc_otg_disable_global_interrupts(dwc_otg_device->core_if);
1120 * Install the interrupt handler for the common interrupts before
1121 * enabling common interrupts in core_init below.
1123 irq = platform_get_irq(_dev, 0);
1124 DWC_DEBUGPL(DBG_CIL, "registering (common) handler for irq%d\n", irq);
1125 retval = request_irq(irq, dwc_otg_common_irq,
1126 IRQF_SHARED, "dwc_otg", dwc_otg_device);
1128 DWC_ERROR("request of irq%d failed\n", irq);
1132 dwc_otg_device->common_irq_installed = 1;
1136 * Initialize the DWC_otg core.
1137 * In order to reduce the time of initialization,
1138 * we do core soft reset after connection detected.
1140 dwc_otg_core_init_no_reset(dwc_otg_device->core_if);
1143 * Initialize the HCD
1145 retval = host20_hcd_init(_dev);
1147 DWC_ERROR("hcd_init failed\n");
1148 dwc_otg_device->hcd = NULL;
1152 clk_set_rate(pldata->phyclk_480m, 480000000);
1154 * Enable the global interrupt after all the interrupt
1155 * handlers are installed if there is no ADP support else
1156 * perform initial actions required for Internal ADP logic.
1158 if (!dwc_otg_get_param_adp_enable(dwc_otg_device->core_if)) {
1159 if (pldata->phy_status == USB_PHY_ENABLED) {
1160 pldata->phy_suspend(pldata, USB_PHY_SUSPEND);
1162 pldata->clock_enable(pldata, 0);
1164 /* dwc_otg_enable_global_interrupts(dwc_otg_device->core_if); */
1166 dwc_otg_adp_start(dwc_otg_device->core_if,
1167 dwc_otg_is_host_mode(dwc_otg_device->
1173 host20_driver_remove(_dev);
1175 if (pldata->clock_enable)
1176 pldata->clock_enable(pldata, 0);
1182 static int dwc_otg_driver_suspend(struct platform_device *_dev,
1188 static int dwc_otg_driver_resume(struct platform_device *_dev)
1193 static void dwc_otg_driver_shutdown(struct platform_device *_dev)
1195 struct device *dev = &_dev->dev;
1196 struct dwc_otg_platform_data *pldata = dev->platform_data;
1197 dwc_otg_device_t *otg_dev = dev->platform_data;
1198 dwc_otg_core_if_t *core_if = otg_dev->core_if;
1199 dctl_data_t dctl = {.d32 = 0 };
1201 DWC_PRINTF("%s: disconnect USB %s mode\n", __func__,
1202 dwc_otg_is_host_mode(core_if) ? "host" : "device");
1204 if( pldata->dwc_otg_uart_mode != NULL)
1205 pldata->dwc_otg_uart_mode( pldata, PHY_USB_MODE);
1206 if(pldata->phy_suspend != NULL)
1207 pldata->phy_suspend(pldata, USB_PHY_ENABLED);
1208 if (dwc_otg_is_host_mode(core_if)) {
1209 if (core_if->hcd_cb && core_if->hcd_cb->stop)
1210 core_if->hcd_cb->stop(core_if->hcd_cb_p);
1212 /* soft disconnect */
1214 DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dctl);
1215 dctl.b.sftdiscon = 1;
1216 DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dctl,
1219 /* Clear any pending interrupts */
1220 DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, 0xFFFFFFFF);
1225 * This structure defines the methods to be called by a bus driver
1226 * during the lifecycle of a device on that bus. Both drivers and
1227 * devices are registered with a bus driver. The bus driver matches
1228 * devices to drivers based on information in the device and driver
1231 * The probe function is called when the bus driver matches a device
1232 * to this driver. The remove function is called when a device is
1233 * unregistered with the bus driver.
1235 #ifdef CONFIG_USB20_HOST
1236 static struct platform_driver dwc_host_driver = {
1238 .name = (char *)dwc_host20_driver_name,
1239 .of_match_table = of_match_ptr(usb20_host_of_match),
1241 .probe = host20_driver_probe,
1242 .remove = host20_driver_remove,
1243 .suspend = dwc_otg_driver_suspend,
1244 .resume = dwc_otg_driver_resume,
1248 #ifdef CONFIG_USB20_OTG
1250 * This function is called when a lm_device is unregistered with the
1251 * dwc_otg_driver. This happens, for example, when the rmmod command is
1252 * executed. The device may or may not be electrically present. If it is
1253 * present, the driver stops device processing. Any resources used on behalf
1254 * of this device are freed.
1258 static int otg20_driver_remove(struct platform_device *_dev)
1261 dwc_otg_device_t *otg_dev = dwc_get_device_platform_data(_dev);
1262 DWC_DEBUGPL(DBG_ANY, "%s(%p)\n", __func__, _dev);
1265 /* Memory allocation for the dwc_otg_device failed. */
1266 DWC_DEBUGPL(DBG_ANY, "%s: otg_dev NULL!\n", __func__);
1269 #ifndef DWC_DEVICE_ONLY
1273 DWC_DEBUGPL(DBG_ANY, "%s: otg_dev->hcd NULL!\n", __func__);
1278 #ifndef DWC_HOST_ONLY
1282 DWC_DEBUGPL(DBG_ANY, "%s: otg_dev->pcd NULL!\n", __func__);
1289 if (otg_dev->common_irq_installed) {
1290 /* free_irq(_dev->irq, otg_dev); */
1291 free_irq(platform_get_irq(_dev, 0), otg_dev);
1293 DWC_DEBUGPL(DBG_ANY, "%s: There is no installed irq!\n",
1298 if (otg_dev->core_if) {
1299 dwc_otg_cil_remove(otg_dev->core_if);
1301 DWC_DEBUGPL(DBG_ANY, "%s: otg_dev->core_if NULL!\n", __func__);
1306 * Remove the device attributes
1308 dwc_otg_attr_remove(_dev);
1311 * Return the memory.
1313 if (otg_dev->os_dep.base)
1314 iounmap(otg_dev->os_dep.base);
1318 * Clear the drvdata pointer.
1321 dwc_set_device_platform_data(_dev, 0);
1326 static const struct of_device_id usb20_otg_of_match[] = {
1328 .compatible = "rockchip,rk3188_usb20_otg",
1329 .data = &usb20otg_pdata[RK3188_USB_CTLR],
1332 .compatible = "rockchip,rk3288_usb20_otg",
1333 .data = &usb20otg_pdata[RK3288_USB_CTLR],
1336 .compatible = "rockchip,rk3036_usb20_otg",
1337 .data = &usb20otg_pdata[RK3036_USB_CTLR],
1340 .compatible = "rockchip,rk3126_usb20_otg",
1341 .data = &usb20otg_pdata[RK3126_USB_CTLR],
1347 MODULE_DEVICE_TABLE(of, usb20_otg_of_match);
1350 * This function is called when an lm_device is bound to a
1351 * dwc_otg_driver. It creates the driver components required to
1352 * control the device (CIL, HCD, and PCD) and it initializes the
1353 * device. The driver components are stored in a dwc_otg_device
1354 * structure. A reference to the dwc_otg_device is saved in the
1355 * lm_device. This allows the driver to access the dwc_otg_device
1356 * structure on subsequent calls to driver methods for this device.
1358 * @param _dev Bus device
1360 static int otg20_driver_probe(struct platform_device *_dev)
1365 struct resource *res_base;
1366 dwc_otg_device_t *dwc_otg_device;
1367 struct device *dev = &_dev->dev;
1368 struct device_node *node = _dev->dev.of_node;
1369 struct dwc_otg_platform_data *pldata;
1370 struct usb20otg_pdata_id *p;
1371 const struct of_device_id *match =
1372 of_match_device(of_match_ptr(usb20_otg_of_match), &_dev->dev);
1375 p = (struct usb20otg_pdata_id *)match->data;
1377 dev_err(dev, "usb20otg match failed\n");
1381 dev->platform_data = p->pdata;
1382 /* dev->platform_data = &usb20otg_pdata; */
1383 pldata = dev->platform_data;
1387 dev_err(dev, "device node not found\n");
1390 /*todo : move to usbdev_rk-XX.c */
1391 if (pldata->hw_init)
1394 if (pldata->clock_init) {
1395 pldata->clock_init(pldata);
1396 pldata->clock_enable(pldata, 1);
1399 if (pldata->phy_suspend)
1400 pldata->phy_suspend(pldata, USB_PHY_ENABLED);
1402 if (pldata->dwc_otg_uart_mode)
1403 pldata->dwc_otg_uart_mode(pldata, PHY_USB_MODE);
1405 /* do reset later, because reset need about
1406 * 100ms to ensure otg id state change.
1409 if(pldata->soft_reset)
1410 pldata->soft_reset();
1414 res_base = platform_get_resource(_dev, IORESOURCE_MEM, 0);
1416 dwc_otg_device = DWC_ALLOC(sizeof(dwc_otg_device_t));
1418 if (!dwc_otg_device) {
1419 dev_err(&_dev->dev, "kmalloc of dwc_otg_device failed\n");
1424 memset(dwc_otg_device, 0, sizeof(*dwc_otg_device));
1425 dwc_otg_device->os_dep.reg_offset = 0xFFFFFFFF;
1428 * Map the DWC_otg Core memory into virtual address space.
1431 dwc_otg_device->os_dep.base = devm_ioremap_resource(dev, res_base);
1433 if (!dwc_otg_device->os_dep.base) {
1434 dev_err(&_dev->dev, "ioremap() failed\n");
1435 DWC_FREE(dwc_otg_device);
1439 dev_dbg(&_dev->dev, "base=0x%08x\n",
1440 (unsigned)dwc_otg_device->os_dep.base);
1443 * Initialize driver data to point to the global DWC_otg
1447 g_otgdev = dwc_otg_device;
1448 pldata->privdata = dwc_otg_device;
1449 dwc_otg_device->pldata = pldata;
1451 dwc_set_device_platform_data(_dev, dwc_otg_device);
1453 dev_dbg(&_dev->dev, "dwc_otg_device=0x%p\n", dwc_otg_device);
1455 dwc_otg_device->core_if = dwc_otg_cil_init(dwc_otg_device->os_dep.base);
1456 if (!dwc_otg_device->core_if) {
1457 dev_err(&_dev->dev, "CIL initialization failed!\n");
1462 dwc_otg_device->core_if->otg_dev = dwc_otg_device;
1464 * Attempt to ensure this device is really a DWC_otg Controller.
1465 * Read and verify the SNPSID register contents. The value should be
1466 * 0x45F42XXX or 0x45F42XXX, which corresponds to either "OT2" or "OTG3",
1467 * as in "OTG version 2.XX" or "OTG version 3.XX".
1470 if (((dwc_otg_get_gsnpsid(dwc_otg_device->core_if) & 0xFFFFF000) !=
1472 && ((dwc_otg_get_gsnpsid(dwc_otg_device->core_if) & 0xFFFFF000) !=
1474 dev_err(&_dev->dev, "Bad value for SNPSID: 0x%08x\n",
1475 dwc_otg_get_gsnpsid(dwc_otg_device->core_if));
1481 * Validate parameter values.
1483 if (set_parameters(dwc_otg_device->core_if, dwc_otg_module_params)) {
1489 * Create Device Attributes in sysfs
1491 dwc_otg_attr_create(_dev);
1494 * Disable the global interrupt until all the interrupt
1495 * handlers are installed.
1497 dwc_otg_disable_global_interrupts(dwc_otg_device->core_if);
1500 * Install the interrupt handler for the common interrupts before
1501 * enabling common interrupts in core_init below.
1503 irq = platform_get_irq(_dev, 0);
1504 DWC_DEBUGPL(DBG_CIL, "registering (common) handler for irq%d\n", irq);
1505 retval = request_irq(irq, dwc_otg_common_irq,
1506 IRQF_SHARED, "dwc_otg", dwc_otg_device);
1508 DWC_ERROR("request of irq%d failed\n", irq);
1512 dwc_otg_device->common_irq_installed = 1;
1516 * Initialize the DWC_otg core.
1517 * In order to reduce the time of initialization,
1518 * we do core soft reset after connection detected.
1520 dwc_otg_core_init_no_reset(dwc_otg_device->core_if);
1523 * 0 - USB_MODE_NORMAL
1524 * 1 - USB_MODE_FORCE_HOST
1525 * 2 - USB_MODE_FORCE_DEVICE
1527 of_property_read_u32(node, "rockchip,usb-mode", &val);
1528 dwc_otg_device->core_if->usb_mode = val;
1530 #ifndef DWC_HOST_ONLY
1532 * Initialize the PCD
1534 retval = pcd_init(_dev);
1536 DWC_ERROR("pcd_init failed\n");
1537 dwc_otg_device->pcd = NULL;
1541 #ifndef DWC_DEVICE_ONLY
1543 * Initialize the HCD
1545 retval = otg20_hcd_init(_dev);
1547 DWC_ERROR("hcd_init failed\n");
1548 dwc_otg_device->hcd = NULL;
1553 * Enable the global interrupt after all the interrupt
1554 * handlers are installed if there is no ADP support else
1555 * perform initial actions required for Internal ADP logic.
1557 if (!dwc_otg_get_param_adp_enable(dwc_otg_device->core_if)) {
1558 if (pldata->phy_status == USB_PHY_ENABLED) {
1559 pldata->phy_suspend(pldata, USB_PHY_SUSPEND);
1561 pldata->clock_enable(pldata, 0);
1563 /* dwc_otg_enable_global_interrupts(dwc_otg_device->core_if); */
1565 dwc_otg_adp_start(dwc_otg_device->core_if,
1566 dwc_otg_is_host_mode(dwc_otg_device->
1572 otg20_driver_remove(_dev);
1575 if (pldata->clock_enable)
1576 pldata->clock_enable(pldata, 0);
1581 static struct platform_driver dwc_otg_driver = {
1583 .name = (char *)dwc_otg20_driver_name,
1584 .of_match_table = of_match_ptr(usb20_otg_of_match),
1586 .probe = otg20_driver_probe,
1587 .remove = otg20_driver_remove,
1588 .suspend = dwc_otg_driver_suspend,
1589 .resume = dwc_otg_driver_resume,
1590 .shutdown = dwc_otg_driver_shutdown,
1594 void rk_usb_power_up(void)
1596 struct dwc_otg_platform_data *pldata_otg;
1597 struct dwc_otg_platform_data *pldata_host;
1598 struct rkehci_platform_data *pldata_ehci;
1599 if (cpu_is_rk312x()) {
1600 pldata_otg = &usb20otg_pdata_rk3126;
1601 if (usb_to_uart_status)
1602 pldata_otg->dwc_otg_uart_mode(pldata_otg, PHY_UART_MODE);
1604 if (cpu_is_rk3288()) {
1605 #ifdef CONFIG_RK_USB_UART
1606 /* enable USB bypass UART function */
1607 writel_relaxed(0x00c00000 | usb_to_uart_status,
1608 RK_GRF_VIRT + RK3288_GRF_UOC0_CON3);
1611 /* unset siddq,the analog blocks are powered up */
1612 #ifdef CONFIG_USB20_OTG
1613 pldata_otg = &usb20otg_pdata_rk3288;
1615 if (pldata_otg->phy_status == USB_PHY_SUSPEND)
1616 writel_relaxed((0x01 << 13) << 16,
1618 RK3288_GRF_UOC0_CON0);
1621 #ifdef CONFIG_USB20_HOST
1622 pldata_host = &usb20host_pdata_rk3288;
1624 if (pldata_host->phy_status == USB_PHY_SUSPEND)
1625 writel_relaxed((0x01 << 13) << 16,
1627 RK3288_GRF_UOC2_CON0);
1630 #ifdef CONFIG_USB_EHCI_RK
1631 pldata_ehci = &rkehci_pdata_rk3288;
1633 if (pldata_ehci->phy_status == USB_PHY_SUSPEND)
1634 writel_relaxed((0x01 << 13) << 16,
1636 RK3288_GRF_UOC1_CON0);
1643 void rk_usb_power_down(void)
1645 struct dwc_otg_platform_data *pldata_otg;
1646 struct dwc_otg_platform_data *pldata_host;
1647 struct rkehci_platform_data *pldata_ehci;
1649 if (cpu_is_rk312x()) {
1650 pldata_otg = &usb20otg_pdata_rk3126;
1651 usb_to_uart_status = pldata_otg->get_status(USB_STATUS_UARTMODE);
1652 pldata_otg->dwc_otg_uart_mode(pldata_otg, PHY_USB_MODE);
1654 if (cpu_is_rk3288()) {
1655 #ifdef CONFIG_RK_USB_UART
1656 /* disable USB bypass UART function */
1657 usb_to_uart_status =
1658 readl_relaxed(RK_GRF_VIRT + RK3288_GRF_UOC0_CON3);
1659 writel_relaxed(0x00c00000, RK_GRF_VIRT + RK3288_GRF_UOC0_CON3);
1661 /* set siddq,the analog blocks are powered down
1663 * 1. Before asserting SIDDQ, ensure that VDATSRCENB0,
1664 * VDATDETENB0, DCDENB0, BYPASSSEL0, ADPPRBENB0,
1665 * and TESTBURNIN are set to 1'b0.
1666 * 2. Before asserting SIDDQ, ensure that phy enter suspend.*/
1667 #ifdef CONFIG_USB20_OTG
1668 pldata_otg = &usb20otg_pdata_rk3288;
1670 if (pldata_otg->phy_status == USB_PHY_SUSPEND)
1671 writel_relaxed((0x01 << 13) |
1672 ((0x01 << 13) << 16),
1674 RK3288_GRF_UOC0_CON0);
1677 #ifdef CONFIG_USB20_HOST
1678 pldata_host = &usb20host_pdata_rk3288;
1680 if (pldata_host->phy_status == USB_PHY_SUSPEND)
1681 writel_relaxed((0x01 << 13) |
1682 ((0x01 << 13) << 16),
1684 RK3288_GRF_UOC2_CON0);
1687 #ifdef CONFIG_USB_EHCI_RK
1688 pldata_ehci = &rkehci_pdata_rk3288;
1690 if (pldata_ehci->phy_status == USB_PHY_SUSPEND)
1691 writel_relaxed((0x01 << 13) |
1692 ((0x01 << 13) << 16),
1694 RK3288_GRF_UOC1_CON0);
1700 EXPORT_SYMBOL(rk_usb_power_up);
1701 EXPORT_SYMBOL(rk_usb_power_down);
1703 * This function is called when the dwc_otg_driver is installed with the
1704 * insmod command. It registers the dwc_otg_driver structure with the
1705 * appropriate bus driver. This will cause the dwc_otg_driver_probe function
1706 * to be called. In addition, the bus driver will automatically expose
1707 * attributes defined for the device and driver in the special sysfs file
1712 static int __init dwc_otg_driver_init(void)
1717 #ifdef CONFIG_USB20_OTG
1718 /* register otg20 */
1719 printk(KERN_INFO "%s: version %s\n", dwc_otg20_driver_name,
1720 DWC_DRIVER_VERSION);
1722 retval = platform_driver_register(&dwc_otg_driver);
1724 printk(KERN_ERR "%s retval=%d\n", __func__, retval);
1729 driver_create_file(&dwc_otg_driver.driver, &driver_attr_version);
1731 driver_create_file(&dwc_otg_driver.driver, &driver_attr_debuglevel);
1733 driver_create_file(&dwc_otg_driver.driver,
1734 &driver_attr_dwc_otg_conn_en);
1736 driver_create_file(&dwc_otg_driver.driver,
1737 &driver_attr_vbus_status);
1739 driver_create_file(&dwc_otg_driver.driver,
1740 &driver_attr_force_usb_mode);
1742 driver_create_file(&dwc_otg_driver.driver,
1743 &driver_attr_op_state);
1747 /* register host20 */
1748 #ifdef CONFIG_USB20_HOST
1749 printk(KERN_INFO "%s: version %s\n", dwc_host20_driver_name,
1750 DWC_DRIVER_VERSION);
1752 retval = platform_driver_register(&dwc_host_driver);
1754 printk(KERN_ERR "%s retval=%d\n", __func__, retval);
1759 driver_create_file(&dwc_host_driver.driver, &driver_attr_version);
1761 driver_create_file(&dwc_host_driver.driver,
1762 &driver_attr_debuglevel);
1767 module_init(dwc_otg_driver_init);
1770 * This function is called when the driver is removed from the kernel
1771 * with the rmmod command. The driver unregisters itself with its bus
1775 static void __exit dwc_otg_driver_cleanup(void)
1777 printk(KERN_DEBUG "dwc_otg_driver_cleanup()\n");
1779 #ifdef CONFIG_USB20_HOST
1781 driver_remove_file(&dwc_host_driver.driver, &driver_attr_debuglevel);
1782 driver_remove_file(&dwc_host_driver.driver, &driver_attr_version);
1783 platform_driver_unregister(&dwc_host_driver);
1784 printk(KERN_INFO "%s module removed\n", dwc_host20_driver_name);
1787 #ifdef CONFIG_USB20_OTG
1789 driver_remove_file(&dwc_otg_driver.driver,
1790 &driver_attr_dwc_otg_conn_en);
1791 driver_remove_file(&dwc_otg_driver.driver, &driver_attr_debuglevel);
1792 driver_remove_file(&dwc_otg_driver.driver, &driver_attr_version);
1793 driver_remove_file(&dwc_otg_driver.driver, &driver_attr_vbus_status);
1794 driver_remove_file(&dwc_otg_driver.driver, &driver_attr_force_usb_mode);
1795 driver_remove_file(&dwc_otg_driver.driver, &driver_attr_op_state);
1796 platform_driver_unregister(&dwc_otg_driver);
1797 printk(KERN_INFO "%s module removed\n", dwc_otg20_driver_name);
1801 module_exit(dwc_otg_driver_cleanup);
1803 MODULE_DESCRIPTION(DWC_DRIVER_DESC);
1804 MODULE_AUTHOR("Synopsys Inc.");
1805 MODULE_LICENSE("GPL");
1807 module_param_named(otg_cap, dwc_otg_module_params.otg_cap, int, 0444);
1808 MODULE_PARM_DESC(otg_cap, "OTG Capabilities 0=HNP&SRP 1=SRP Only 2=None");
1809 module_param_named(opt, dwc_otg_module_params.opt, int, 0444);
1810 MODULE_PARM_DESC(opt, "OPT Mode");
1811 module_param_named(dma_enable, dwc_otg_module_params.dma_enable, int, 0444);
1812 MODULE_PARM_DESC(dma_enable, "DMA Mode 0=Slave 1=DMA enabled");
1814 module_param_named(dma_desc_enable, dwc_otg_module_params.dma_desc_enable, int,
1816 MODULE_PARM_DESC(dma_desc_enable,
1817 "DMA Desc Mode 0=Address DMA 1=DMA Descriptor enabled");
1819 module_param_named(dma_burst_size, dwc_otg_module_params.dma_burst_size, int,
1821 MODULE_PARM_DESC(dma_burst_size,
1822 "DMA Burst Size 1, 4, 8, 16, 32, 64, 128, 256");
1823 module_param_named(speed, dwc_otg_module_params.speed, int, 0444);
1824 MODULE_PARM_DESC(speed, "Speed 0=High Speed 1=Full Speed");
1825 module_param_named(host_support_fs_ls_low_power,
1826 dwc_otg_module_params.host_support_fs_ls_low_power, int,
1828 MODULE_PARM_DESC(host_support_fs_ls_low_power,
1829 "Support Low Power w/FS or LS 0=Support 1=Don't Support");
1830 module_param_named(host_ls_low_power_phy_clk,
1831 dwc_otg_module_params.host_ls_low_power_phy_clk, int, 0444);
1832 MODULE_PARM_DESC(host_ls_low_power_phy_clk,
1833 "Low Speed Low Power Clock 0=48Mhz 1=6Mhz");
1834 module_param_named(enable_dynamic_fifo,
1835 dwc_otg_module_params.enable_dynamic_fifo, int, 0444);
1836 MODULE_PARM_DESC(enable_dynamic_fifo, "0=cC Setting 1=Allow Dynamic Sizing");
1837 module_param_named(data_fifo_size, dwc_otg_module_params.data_fifo_size, int,
1839 MODULE_PARM_DESC(data_fifo_size,
1840 "Total number of words in the data FIFO memory 32-32768");
1841 module_param_named(dev_rx_fifo_size, dwc_otg_module_params.dev_rx_fifo_size,
1843 MODULE_PARM_DESC(dev_rx_fifo_size, "Number of words in the Rx FIFO 16-32768");
1844 module_param_named(dev_nperio_tx_fifo_size,
1845 dwc_otg_module_params.dev_nperio_tx_fifo_size, int, 0444);
1846 MODULE_PARM_DESC(dev_nperio_tx_fifo_size,
1847 "Number of words in the non-periodic Tx FIFO 16-32768");
1848 module_param_named(dev_perio_tx_fifo_size_1,
1849 dwc_otg_module_params.dev_perio_tx_fifo_size[0], int, 0444);
1850 MODULE_PARM_DESC(dev_perio_tx_fifo_size_1,
1851 "Number of words in the periodic Tx FIFO 4-768");
1852 module_param_named(dev_perio_tx_fifo_size_2,
1853 dwc_otg_module_params.dev_perio_tx_fifo_size[1], int, 0444);
1854 MODULE_PARM_DESC(dev_perio_tx_fifo_size_2,
1855 "Number of words in the periodic Tx FIFO 4-768");
1856 module_param_named(dev_perio_tx_fifo_size_3,
1857 dwc_otg_module_params.dev_perio_tx_fifo_size[2], int, 0444);
1858 MODULE_PARM_DESC(dev_perio_tx_fifo_size_3,
1859 "Number of words in the periodic Tx FIFO 4-768");
1860 module_param_named(dev_perio_tx_fifo_size_4,
1861 dwc_otg_module_params.dev_perio_tx_fifo_size[3], int, 0444);
1862 MODULE_PARM_DESC(dev_perio_tx_fifo_size_4,
1863 "Number of words in the periodic Tx FIFO 4-768");
1864 module_param_named(dev_perio_tx_fifo_size_5,
1865 dwc_otg_module_params.dev_perio_tx_fifo_size[4], int, 0444);
1866 MODULE_PARM_DESC(dev_perio_tx_fifo_size_5,
1867 "Number of words in the periodic Tx FIFO 4-768");
1868 module_param_named(dev_perio_tx_fifo_size_6,
1869 dwc_otg_module_params.dev_perio_tx_fifo_size[5], int, 0444);
1870 MODULE_PARM_DESC(dev_perio_tx_fifo_size_6,
1871 "Number of words in the periodic Tx FIFO 4-768");
1872 module_param_named(dev_perio_tx_fifo_size_7,
1873 dwc_otg_module_params.dev_perio_tx_fifo_size[6], int, 0444);
1874 MODULE_PARM_DESC(dev_perio_tx_fifo_size_7,
1875 "Number of words in the periodic Tx FIFO 4-768");
1876 module_param_named(dev_perio_tx_fifo_size_8,
1877 dwc_otg_module_params.dev_perio_tx_fifo_size[7], int, 0444);
1878 MODULE_PARM_DESC(dev_perio_tx_fifo_size_8,
1879 "Number of words in the periodic Tx FIFO 4-768");
1880 module_param_named(dev_perio_tx_fifo_size_9,
1881 dwc_otg_module_params.dev_perio_tx_fifo_size[8], int, 0444);
1882 MODULE_PARM_DESC(dev_perio_tx_fifo_size_9,
1883 "Number of words in the periodic Tx FIFO 4-768");
1884 module_param_named(dev_perio_tx_fifo_size_10,
1885 dwc_otg_module_params.dev_perio_tx_fifo_size[9], int, 0444);
1886 MODULE_PARM_DESC(dev_perio_tx_fifo_size_10,
1887 "Number of words in the periodic Tx FIFO 4-768");
1888 module_param_named(dev_perio_tx_fifo_size_11,
1889 dwc_otg_module_params.dev_perio_tx_fifo_size[10], int, 0444);
1890 MODULE_PARM_DESC(dev_perio_tx_fifo_size_11,
1891 "Number of words in the periodic Tx FIFO 4-768");
1892 module_param_named(dev_perio_tx_fifo_size_12,
1893 dwc_otg_module_params.dev_perio_tx_fifo_size[11], int, 0444);
1894 MODULE_PARM_DESC(dev_perio_tx_fifo_size_12,
1895 "Number of words in the periodic Tx FIFO 4-768");
1896 module_param_named(dev_perio_tx_fifo_size_13,
1897 dwc_otg_module_params.dev_perio_tx_fifo_size[12], int, 0444);
1898 MODULE_PARM_DESC(dev_perio_tx_fifo_size_13,
1899 "Number of words in the periodic Tx FIFO 4-768");
1900 module_param_named(dev_perio_tx_fifo_size_14,
1901 dwc_otg_module_params.dev_perio_tx_fifo_size[13], int, 0444);
1902 MODULE_PARM_DESC(dev_perio_tx_fifo_size_14,
1903 "Number of words in the periodic Tx FIFO 4-768");
1904 module_param_named(dev_perio_tx_fifo_size_15,
1905 dwc_otg_module_params.dev_perio_tx_fifo_size[14], int, 0444);
1906 MODULE_PARM_DESC(dev_perio_tx_fifo_size_15,
1907 "Number of words in the periodic Tx FIFO 4-768");
1908 module_param_named(host_rx_fifo_size, dwc_otg_module_params.host_rx_fifo_size,
1910 MODULE_PARM_DESC(host_rx_fifo_size, "Number of words in the Rx FIFO 16-32768");
1911 module_param_named(host_nperio_tx_fifo_size,
1912 dwc_otg_module_params.host_nperio_tx_fifo_size, int, 0444);
1913 MODULE_PARM_DESC(host_nperio_tx_fifo_size,
1914 "Number of words in the non-periodic Tx FIFO 16-32768");
1915 module_param_named(host_perio_tx_fifo_size,
1916 dwc_otg_module_params.host_perio_tx_fifo_size, int, 0444);
1917 MODULE_PARM_DESC(host_perio_tx_fifo_size,
1918 "Number of words in the host periodic Tx FIFO 16-32768");
1919 module_param_named(max_transfer_size, dwc_otg_module_params.max_transfer_size,
1921 /** @todo Set the max to 512K, modify checks */
1922 MODULE_PARM_DESC(max_transfer_size,
1923 "The maximum transfer size supported in bytes 2047-65535");
1924 module_param_named(max_packet_count, dwc_otg_module_params.max_packet_count,
1926 MODULE_PARM_DESC(max_packet_count,
1927 "The maximum number of packets in a transfer 15-511");
1928 module_param_named(host_channels, dwc_otg_module_params.host_channels, int,
1930 MODULE_PARM_DESC(host_channels,
1931 "The number of host channel registers to use 1-16");
1932 module_param_named(dev_endpoints, dwc_otg_module_params.dev_endpoints, int,
1934 MODULE_PARM_DESC(dev_endpoints,
1935 "The number of endpoints in addition to EP0 available for device mode 1-15");
1936 module_param_named(phy_type, dwc_otg_module_params.phy_type, int, 0444);
1937 MODULE_PARM_DESC(phy_type, "0=Reserved 1=UTMI+ 2=ULPI");
1938 module_param_named(phy_utmi_width, dwc_otg_module_params.phy_utmi_width, int,
1940 MODULE_PARM_DESC(phy_utmi_width, "Specifies the UTMI+ Data Width 8 or 16 bits");
1941 module_param_named(phy_ulpi_ddr, dwc_otg_module_params.phy_ulpi_ddr, int, 0444);
1942 MODULE_PARM_DESC(phy_ulpi_ddr,
1943 "ULPI at double or single data rate 0=Single 1=Double");
1944 module_param_named(phy_ulpi_ext_vbus, dwc_otg_module_params.phy_ulpi_ext_vbus,
1946 MODULE_PARM_DESC(phy_ulpi_ext_vbus,
1947 "ULPI PHY using internal or external vbus 0=Internal");
1948 module_param_named(i2c_enable, dwc_otg_module_params.i2c_enable, int, 0444);
1949 MODULE_PARM_DESC(i2c_enable, "FS PHY Interface");
1950 module_param_named(ulpi_fs_ls, dwc_otg_module_params.ulpi_fs_ls, int, 0444);
1951 MODULE_PARM_DESC(ulpi_fs_ls, "ULPI PHY FS/LS mode only");
1952 module_param_named(ts_dline, dwc_otg_module_params.ts_dline, int, 0444);
1953 MODULE_PARM_DESC(ts_dline, "Term select Dline pulsing for all PHYs");
1954 module_param_named(debug, g_dbg_lvl, int, 0444);
1955 MODULE_PARM_DESC(debug, "");
1957 module_param_named(en_multiple_tx_fifo,
1958 dwc_otg_module_params.en_multiple_tx_fifo, int, 0444);
1959 MODULE_PARM_DESC(en_multiple_tx_fifo,
1960 "Dedicated Non Periodic Tx FIFOs 0=disabled 1=enabled");
1961 module_param_named(dev_tx_fifo_size_1,
1962 dwc_otg_module_params.dev_tx_fifo_size[0], int, 0444);
1963 MODULE_PARM_DESC(dev_tx_fifo_size_1, "Number of words in the Tx FIFO 4-768");
1964 module_param_named(dev_tx_fifo_size_2,
1965 dwc_otg_module_params.dev_tx_fifo_size[1], int, 0444);
1966 MODULE_PARM_DESC(dev_tx_fifo_size_2, "Number of words in the Tx FIFO 4-768");
1967 module_param_named(dev_tx_fifo_size_3,
1968 dwc_otg_module_params.dev_tx_fifo_size[2], int, 0444);
1969 MODULE_PARM_DESC(dev_tx_fifo_size_3, "Number of words in the Tx FIFO 4-768");
1970 module_param_named(dev_tx_fifo_size_4,
1971 dwc_otg_module_params.dev_tx_fifo_size[3], int, 0444);
1972 MODULE_PARM_DESC(dev_tx_fifo_size_4, "Number of words in the Tx FIFO 4-768");
1973 module_param_named(dev_tx_fifo_size_5,
1974 dwc_otg_module_params.dev_tx_fifo_size[4], int, 0444);
1975 MODULE_PARM_DESC(dev_tx_fifo_size_5, "Number of words in the Tx FIFO 4-768");
1976 module_param_named(dev_tx_fifo_size_6,
1977 dwc_otg_module_params.dev_tx_fifo_size[5], int, 0444);
1978 MODULE_PARM_DESC(dev_tx_fifo_size_6, "Number of words in the Tx FIFO 4-768");
1979 module_param_named(dev_tx_fifo_size_7,
1980 dwc_otg_module_params.dev_tx_fifo_size[6], int, 0444);
1981 MODULE_PARM_DESC(dev_tx_fifo_size_7, "Number of words in the Tx FIFO 4-768");
1982 module_param_named(dev_tx_fifo_size_8,
1983 dwc_otg_module_params.dev_tx_fifo_size[7], int, 0444);
1984 MODULE_PARM_DESC(dev_tx_fifo_size_8, "Number of words in the Tx FIFO 4-768");
1985 module_param_named(dev_tx_fifo_size_9,
1986 dwc_otg_module_params.dev_tx_fifo_size[8], int, 0444);
1987 MODULE_PARM_DESC(dev_tx_fifo_size_9, "Number of words in the Tx FIFO 4-768");
1988 module_param_named(dev_tx_fifo_size_10,
1989 dwc_otg_module_params.dev_tx_fifo_size[9], int, 0444);
1990 MODULE_PARM_DESC(dev_tx_fifo_size_10, "Number of words in the Tx FIFO 4-768");
1991 module_param_named(dev_tx_fifo_size_11,
1992 dwc_otg_module_params.dev_tx_fifo_size[10], int, 0444);
1993 MODULE_PARM_DESC(dev_tx_fifo_size_11, "Number of words in the Tx FIFO 4-768");
1994 module_param_named(dev_tx_fifo_size_12,
1995 dwc_otg_module_params.dev_tx_fifo_size[11], int, 0444);
1996 MODULE_PARM_DESC(dev_tx_fifo_size_12, "Number of words in the Tx FIFO 4-768");
1997 module_param_named(dev_tx_fifo_size_13,
1998 dwc_otg_module_params.dev_tx_fifo_size[12], int, 0444);
1999 MODULE_PARM_DESC(dev_tx_fifo_size_13, "Number of words in the Tx FIFO 4-768");
2000 module_param_named(dev_tx_fifo_size_14,
2001 dwc_otg_module_params.dev_tx_fifo_size[13], int, 0444);
2002 MODULE_PARM_DESC(dev_tx_fifo_size_14, "Number of words in the Tx FIFO 4-768");
2003 module_param_named(dev_tx_fifo_size_15,
2004 dwc_otg_module_params.dev_tx_fifo_size[14], int, 0444);
2005 MODULE_PARM_DESC(dev_tx_fifo_size_15, "Number of words in the Tx FIFO 4-768");
2007 module_param_named(thr_ctl, dwc_otg_module_params.thr_ctl, int, 0444);
2008 MODULE_PARM_DESC(thr_ctl,
2009 "Thresholding enable flag bit 0 - non ISO Tx thr., 1 - ISO Tx thr., 2 - Rx thr.- bit 0=disabled 1=enabled");
2010 module_param_named(tx_thr_length, dwc_otg_module_params.tx_thr_length, int,
2012 MODULE_PARM_DESC(tx_thr_length, "Tx Threshold length in 32 bit DWORDs");
2013 module_param_named(rx_thr_length, dwc_otg_module_params.rx_thr_length, int,
2015 MODULE_PARM_DESC(rx_thr_length, "Rx Threshold length in 32 bit DWORDs");
2017 module_param_named(pti_enable, dwc_otg_module_params.pti_enable, int, 0444);
2018 module_param_named(mpi_enable, dwc_otg_module_params.mpi_enable, int, 0444);
2019 module_param_named(lpm_enable, dwc_otg_module_params.lpm_enable, int, 0444);
2020 MODULE_PARM_DESC(lpm_enable, "LPM Enable 0=LPM Disabled 1=LPM Enabled");
2022 module_param_named(besl_enable, dwc_otg_module_params.besl_enable, int, 0444);
2023 MODULE_PARM_DESC(besl_enable, "BESL Enable 0=BESL Disabled 1=BESL Enabled");
2024 module_param_named(baseline_besl, dwc_otg_module_params.baseline_besl, int,
2026 MODULE_PARM_DESC(baseline_besl, "Set the baseline besl value");
2027 module_param_named(deep_besl, dwc_otg_module_params.deep_besl, int, 0444);
2028 MODULE_PARM_DESC(deep_besl, "Set the deep besl value");
2030 module_param_named(ic_usb_cap, dwc_otg_module_params.ic_usb_cap, int, 0444);
2031 MODULE_PARM_DESC(ic_usb_cap,
2032 "IC_USB Capability 0=IC_USB Disabled 1=IC_USB Enabled");
2033 module_param_named(ahb_thr_ratio, dwc_otg_module_params.ahb_thr_ratio, int,
2035 MODULE_PARM_DESC(ahb_thr_ratio, "AHB Threshold Ratio");
2036 module_param_named(power_down, dwc_otg_module_params.power_down, int, 0444);
2037 MODULE_PARM_DESC(power_down, "Power Down Mode");
2038 module_param_named(reload_ctl, dwc_otg_module_params.reload_ctl, int, 0444);
2039 MODULE_PARM_DESC(reload_ctl, "HFIR Reload Control");
2040 module_param_named(dev_out_nak, dwc_otg_module_params.dev_out_nak, int, 0444);
2041 MODULE_PARM_DESC(dev_out_nak, "Enable Device OUT NAK");
2042 module_param_named(cont_on_bna, dwc_otg_module_params.cont_on_bna, int, 0444);
2043 MODULE_PARM_DESC(cont_on_bna, "Enable Enable Continue on BNA");
2044 module_param_named(ahb_single, dwc_otg_module_params.ahb_single, int, 0444);
2045 MODULE_PARM_DESC(ahb_single, "Enable AHB Single Support");
2046 module_param_named(adp_enable, dwc_otg_module_params.adp_enable, int, 0444);
2047 MODULE_PARM_DESC(adp_enable, "ADP Enable 0=ADP Disabled 1=ADP Enabled");
2048 module_param_named(otg_ver, dwc_otg_module_params.otg_ver, int, 0444);
2049 MODULE_PARM_DESC(otg_ver, "OTG revision supported 0=OTG 1.3 1=OTG 2.0");
2051 /** @page "Module Parameters"
2053 * The following parameters may be specified when starting the module.
2054 * These parameters define how the DWC_otg controller should be
2055 * configured. Parameter values are passed to the CIL initialization
2056 * function dwc_otg_cil_init
2058 * Example: <code>modprobe dwc_otg speed=1 otg_cap=1</code>
2062 <tr><td>Parameter Name</td><td>Meaning</td></tr>
2066 <td>Specifies the OTG capabilities. The driver will automatically detect the
2067 value for this parameter if none is specified.
2068 - 0: HNP and SRP capable (default, if available)
2069 - 1: SRP Only capable
2070 - 2: No HNP/SRP capable
2075 <td>Specifies whether to use slave or DMA mode for accessing the data FIFOs.
2076 The driver will automatically detect the value for this parameter if none is
2079 - 1: DMA (default, if available)
2083 <td>dma_burst_size</td>
2084 <td>The DMA Burst size (applicable only for External DMA Mode).
2085 - Values: 1, 4, 8 16, 32, 64, 128, 256 (default 32)
2090 <td>Specifies the maximum speed of operation in host and device mode. The
2091 actual speed depends on the speed of the attached device and the value of
2093 - 0: High Speed (default)
2098 <td>host_support_fs_ls_low_power</td>
2099 <td>Specifies whether low power mode is supported when attached to a Full
2100 Speed or Low Speed device in host mode.
2101 - 0: Don't support low power mode (default)
2102 - 1: Support low power mode
2106 <td>host_ls_low_power_phy_clk</td>
2107 <td>Specifies the PHY clock rate in low power mode when connected to a Low
2108 Speed device in host mode. This parameter is applicable only if
2109 HOST_SUPPORT_FS_LS_LOW_POWER is enabled.
2110 - 0: 48 MHz (default)
2115 <td>enable_dynamic_fifo</td>
2116 <td> Specifies whether FIFOs may be resized by the driver software.
2117 - 0: Use cC FIFO size parameters
2118 - 1: Allow dynamic FIFO sizing (default)
2122 <td>data_fifo_size</td>
2123 <td>Total number of 4-byte words in the data FIFO memory. This memory
2124 includes the Rx FIFO, non-periodic Tx FIFO, and periodic Tx FIFOs.
2125 - Values: 32 to 32768 (default 8192)
2127 Note: The total FIFO memory depth in the FPGA configuration is 8192.
2131 <td>dev_rx_fifo_size</td>
2132 <td>Number of 4-byte words in the Rx FIFO in device mode when dynamic
2133 FIFO sizing is enabled.
2134 - Values: 16 to 32768 (default 1064)
2138 <td>dev_nperio_tx_fifo_size</td>
2139 <td>Number of 4-byte words in the non-periodic Tx FIFO in device mode when
2140 dynamic FIFO sizing is enabled.
2141 - Values: 16 to 32768 (default 1024)
2145 <td>dev_perio_tx_fifo_size_n (n = 1 to 15)</td>
2146 <td>Number of 4-byte words in each of the periodic Tx FIFOs in device mode
2147 when dynamic FIFO sizing is enabled.
2148 - Values: 4 to 768 (default 256)
2152 <td>host_rx_fifo_size</td>
2153 <td>Number of 4-byte words in the Rx FIFO in host mode when dynamic FIFO
2155 - Values: 16 to 32768 (default 1024)
2159 <td>host_nperio_tx_fifo_size</td>
2160 <td>Number of 4-byte words in the non-periodic Tx FIFO in host mode when
2161 dynamic FIFO sizing is enabled in the core.
2162 - Values: 16 to 32768 (default 1024)
2166 <td>host_perio_tx_fifo_size</td>
2167 <td>Number of 4-byte words in the host periodic Tx FIFO when dynamic FIFO
2169 - Values: 16 to 32768 (default 1024)
2173 <td>max_transfer_size</td>
2174 <td>The maximum transfer size supported in bytes.
2175 - Values: 2047 to 65,535 (default 65,535)
2179 <td>max_packet_count</td>
2180 <td>The maximum number of packets in a transfer.
2181 - Values: 15 to 511 (default 511)
2185 <td>host_channels</td>
2186 <td>The number of host channel registers to use.
2187 - Values: 1 to 16 (default 12)
2189 Note: The FPGA configuration supports a maximum of 12 host channels.
2193 <td>dev_endpoints</td>
2194 <td>The number of endpoints in addition to EP0 available for device mode
2196 - Values: 1 to 15 (default 6 IN and OUT)
2198 Note: The FPGA configuration supports a maximum of 6 IN and OUT endpoints in
2204 <td>Specifies the type of PHY interface to use. By default, the driver will
2205 automatically detect the phy_type.
2207 - 1: UTMI+ (default, if available)
2212 <td>phy_utmi_width</td>
2213 <td>Specifies the UTMI+ Data Width. This parameter is applicable for a
2214 phy_type of UTMI+. Also, this parameter is applicable only if the
2215 OTG_HSPHY_WIDTH cC parameter was set to "8 and 16 bits", meaning that the
2216 core has been configured to work at either data path width.
2217 - Values: 8 or 16 bits (default 16)
2221 <td>phy_ulpi_ddr</td>
2222 <td>Specifies whether the ULPI operates at double or single data rate. This
2223 parameter is only applicable if phy_type is ULPI.
2224 - 0: single data rate ULPI interface with 8 bit wide data bus (default)
2225 - 1: double data rate ULPI interface with 4 bit wide data bus
2230 <td>Specifies whether to use the I2C interface for full speed PHY. This
2231 parameter is only applicable if PHY_TYPE is FS.
2232 - 0: Disabled (default)
2238 <td>Specifies whether to use ULPI FS/LS mode only.
2239 - 0: Disabled (default)
2245 <td>Specifies whether term select D-Line pulsing for all PHYs is enabled.
2246 - 0: Disabled (default)
2251 <td>en_multiple_tx_fifo</td>
2252 <td>Specifies whether dedicatedto tx fifos are enabled for non periodic IN EPs.
2253 The driver will automatically detect the value for this parameter if none is
2256 - 1: Enabled (default, if available)
2260 <td>dev_tx_fifo_size_n (n = 1 to 15)</td>
2261 <td>Number of 4-byte words in each of the Tx FIFOs in device mode
2262 when dynamic FIFO sizing is enabled.
2263 - Values: 4 to 768 (default 256)
2267 <td>tx_thr_length</td>
2268 <td>Transmit Threshold length in 32 bit double words
2269 - Values: 8 to 128 (default 64)
2273 <td>rx_thr_length</td>
2274 <td>Receive Threshold length in 32 bit double words
2275 - Values: 8 to 128 (default 64)
2280 <td>Specifies whether to enable Thresholding for Device mode. Bits 0, 1, 2 of
2281 this parmater specifies if thresholding is enabled for non-Iso Tx, Iso Tx and
2282 Rx transfers accordingly.
2283 The driver will automatically detect the value for this parameter if none is
2285 - Values: 0 to 7 (default 0)
2286 Bit values indicate:
2287 - 0: Thresholding disabled
2288 - 1: Thresholding enabled
2292 <td>dma_desc_enable</td>
2293 <td>Specifies whether to enable Descriptor DMA mode.
2294 The driver will automatically detect the value for this parameter if none is
2296 - 0: Descriptor DMA disabled
2297 - 1: Descriptor DMA (default, if available)
2302 <td>Specifies whether to enable MPI enhancement mode.
2303 The driver will automatically detect the value for this parameter if none is
2305 - 0: MPI disabled (default)
2311 <td>Specifies whether to enable PTI enhancement support.
2312 The driver will automatically detect the value for this parameter if none is
2314 - 0: PTI disabled (default)
2320 <td>Specifies whether to enable LPM support.
2321 The driver will automatically detect the value for this parameter if none is
2324 - 1: LPM enable (default, if available)
2328 <td>besl_enable</td>
2329 <td>Specifies whether to enable LPM Errata support.
2330 The driver will automatically detect the value for this parameter if none is
2332 - 0: LPM Errata disabled (default)
2333 - 1: LPM Errata enable
2337 <td>baseline_besl</td>
2338 <td>Specifies the baseline besl value.
2339 - Values: 0 to 15 (default 0)
2344 <td>Specifies the deep besl value.
2345 - Values: 0 to 15 (default 15)
2350 <td>Specifies whether to enable IC_USB capability.
2351 The driver will automatically detect the value for this parameter if none is
2353 - 0: IC_USB disabled (default, if available)
2358 <td>ahb_thr_ratio</td>
2359 <td>Specifies AHB Threshold ratio.
2360 - Values: 0 to 3 (default 0)
2365 <td>Specifies Power Down(Hibernation) Mode.
2366 The driver will automatically detect the value for this parameter if none is
2368 - 0: Power Down disabled (default)
2369 - 2: Power Down enabled
2374 <td>Specifies whether dynamic reloading of the HFIR register is allowed during
2375 run time. The driver will automatically detect the value for this parameter if
2376 none is specified. In case the HFIR value is reloaded when HFIR.RldCtrl == 1'b0
2377 the core might misbehave.
2378 - 0: Reload Control disabled (default)
2379 - 1: Reload Control enabled
2383 <td>dev_out_nak</td>
2384 <td>Specifies whether Device OUT NAK enhancement enabled or no.
2385 The driver will automatically detect the value for this parameter if
2386 none is specified. This parameter is valid only when OTG_EN_DESC_DMA == 1
\92b1.
2387 - 0: The core does not set NAK after Bulk OUT transfer complete (default)
2388 - 1: The core sets NAK after Bulk OUT transfer complete
2392 <td>cont_on_bna</td>
2393 <td>Specifies whether Enable Continue on BNA enabled or no.
2394 After receiving BNA interrupt the core disables the endpoint,when the
2395 endpoint is re-enabled by the application the
2396 - 0: Core starts processing from the DOEPDMA descriptor (default)
2397 - 1: Core starts processing from the descriptor which received the BNA.
2398 This parameter is valid only when OTG_EN_DESC_DMA == 1
\92b1.
2403 <td>This bit when programmed supports SINGLE transfers for remainder data
2404 in a transfer for DMA mode of operation.
2405 - 0: The remainder data will be sent using INCR burst size (default)
2406 - 1: The remainder data will be sent using SINGLE burst size.
2411 <td>Specifies whether ADP feature is enabled.
2412 The driver will automatically detect the value for this parameter if none is
2414 - 0: ADP feature disabled (default)
2415 - 1: ADP feature enabled
2420 <td>Specifies whether OTG is performing as USB OTG Revision 2.0 or Revision 1.3
2422 - 0: OTG 2.0 support disabled (default)
2423 - 1: OTG 2.0 support enabled