1 /* ==========================================================================
2 * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_driver.c $
7 * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
8 * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
9 * otherwise expressly agreed to in writing between Synopsys and you.
11 * The Software IS NOT an item of Licensed Software or Licensed Product under
12 * any End User Software License Agreement or Agreement for Licensed Product
13 * with Synopsys or any supplement thereto. You are permitted to use and
14 * redistribute this Software in source and binary forms, with or without
15 * modification, provided that redistributions of source code must retain this
16 * notice. You may not view, use, disclose, copy or distribute this file or
17 * any information contained herein except pursuant to this license grant from
18 * Synopsys. If you do not agree with this notice, including the disclaimer
19 * below, then you are not authorized to use the Software.
21 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
25 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
26 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
27 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
28 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
32 * ========================================================================== */
35 * The dwc_otg_driver module provides the initialization and cleanup entry
36 * points for the DWC_otg driver. This module will be dynamically installed
37 * after Linux is booted using the insmod command. When the module is
38 * installed, the dwc_otg_driver_init function is called. When the module is
39 * removed (using rmmod), the dwc_otg_driver_cleanup function is called.
41 * This module also defines a data structure for the dwc_otg_driver, which is
42 * used in conjunction with the standard ARM lm_device structure. These
43 * structures allow the OTG driver to comply with the standard Linux driver
44 * model in which devices and drivers are registered with a bus driver. This
45 * has the benefit that Linux can expose attributes of the driver and device
46 * in its special sysfs file system. Users can then read or write files in
47 * this file system to perform diagnostics on the driver components or the
51 #include "dwc_otg_os_dep.h"
52 #include "common_port/dwc_os.h"
53 #include "dwc_otg_dbg.h"
54 #include "dwc_otg_driver.h"
55 #include "dwc_otg_attr.h"
56 #include "dwc_otg_core_if.h"
57 #include "dwc_otg_pcd_if.h"
58 #include "dwc_otg_hcd_if.h"
59 #include "dwc_otg_cil.h"
60 #include "dwc_otg_pcd.h"
62 #include "usbdev_rk.h"
64 #define DWC_DRIVER_VERSION "3.10a 21-DEC-2012"
65 #define DWC_DRIVER_DESC "HS OTG USB Controller driver"
67 static const char dwc_host20_driver_name[] = "usb20_host";
68 static const char dwc_otg20_driver_name[] = "usb20_otg";
70 dwc_otg_device_t *g_otgdev;
72 extern int pcd_init(struct platform_device *_dev);
73 extern int otg20_hcd_init(struct platform_device *_dev);
74 extern int host20_hcd_init(struct platform_device *_dev);
75 extern int pcd_remove(struct platform_device *_dev);
76 extern void hcd_remove(struct platform_device *_dev);
77 extern void dwc_otg_adp_start(dwc_otg_core_if_t *core_if, uint8_t is_host);
80 #ifdef CONFIG_RK_USB_UART
81 static u32 usb_to_uart_status;
83 /*-------------------------------------------------------------------------*/
84 /* Encapsulate the module parameter settings */
86 struct dwc_otg_driver_module_params {
90 int32_t dma_desc_enable;
91 int32_t dma_burst_size;
93 int32_t host_support_fs_ls_low_power;
94 int32_t host_ls_low_power_phy_clk;
95 int32_t enable_dynamic_fifo;
96 int32_t data_fifo_size;
97 int32_t dev_rx_fifo_size;
98 int32_t dev_nperio_tx_fifo_size;
99 uint32_t dev_perio_tx_fifo_size[MAX_PERIO_FIFOS];
100 int32_t host_rx_fifo_size;
101 int32_t host_nperio_tx_fifo_size;
102 int32_t host_perio_tx_fifo_size;
103 int32_t max_transfer_size;
104 int32_t max_packet_count;
105 int32_t host_channels;
106 int32_t dev_endpoints;
108 int32_t phy_utmi_width;
109 int32_t phy_ulpi_ddr;
110 int32_t phy_ulpi_ext_vbus;
114 int32_t en_multiple_tx_fifo;
115 uint32_t dev_tx_fifo_size[MAX_TX_FIFOS];
117 uint32_t tx_thr_length;
118 uint32_t rx_thr_length;
123 int32_t baseline_besl;
126 int32_t ahb_thr_ratio;
136 static struct dwc_otg_driver_module_params dwc_otg_module_params = {
138 .otg_cap = DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE,
140 .dma_desc_enable = 0,
141 .dma_burst_size = -1,
143 .host_support_fs_ls_low_power = -1,
144 .host_ls_low_power_phy_clk = -1,
145 .enable_dynamic_fifo = 1,
146 .data_fifo_size = -1,
147 .dev_rx_fifo_size = 0x120,
148 .dev_nperio_tx_fifo_size = 0x10,
149 .dev_perio_tx_fifo_size = {
150 /* dev_perio_tx_fifo_size_1 */
168 .host_rx_fifo_size = -1,
169 .host_nperio_tx_fifo_size = -1,
170 .host_perio_tx_fifo_size = -1,
171 .max_transfer_size = -1,
172 .max_packet_count = -1,
176 .phy_utmi_width = -1,
178 .phy_ulpi_ext_vbus = -1,
182 .en_multiple_tx_fifo = -1,
183 .dev_tx_fifo_size = {
184 /* dev_tx_fifo_size */
222 #ifdef CONFIG_USB20_HOST
223 static struct dwc_otg_driver_module_params dwc_host_module_params = {
225 .otg_cap = DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE,
227 .dma_desc_enable = 0,
228 .dma_burst_size = -1,
230 .host_support_fs_ls_low_power = -1,
231 .host_ls_low_power_phy_clk = -1,
232 .enable_dynamic_fifo = -1,
233 .data_fifo_size = -1,
234 .dev_rx_fifo_size = -1,
235 .dev_nperio_tx_fifo_size = -1,
236 .dev_perio_tx_fifo_size = {
237 /* dev_perio_tx_fifo_size_1 */
255 .host_rx_fifo_size = -1,
256 .host_nperio_tx_fifo_size = -1,
257 .host_perio_tx_fifo_size = -1,
258 .max_transfer_size = -1,
259 .max_packet_count = -1,
263 .phy_utmi_width = -1,
265 .phy_ulpi_ext_vbus = -1,
269 .en_multiple_tx_fifo = -1,
270 .dev_tx_fifo_size = {
271 /* dev_tx_fifo_size */
311 * This function shows the Driver Version.
313 static ssize_t version_show(struct device_driver *dev, char *buf)
315 return snprintf(buf, sizeof(DWC_DRIVER_VERSION) + 2, "%s\n",
319 static DRIVER_ATTR(version, S_IRUGO, version_show, NULL);
322 * Global Debug Level Mask.
324 uint32_t g_dbg_lvl = DBG_OFF; /* OFF */
327 * This function shows the driver Debug Level.
329 static ssize_t dbg_level_show(struct device_driver *drv, char *buf)
331 return sprintf(buf, "0x%0x\n", g_dbg_lvl);
335 * This function stores the driver Debug Level.
337 static ssize_t dbg_level_store(struct device_driver *drv, const char *buf,
340 g_dbg_lvl = simple_strtoul(buf, NULL, 16);
344 static DRIVER_ATTR(debuglevel, S_IRUGO | S_IWUSR, dbg_level_show,
347 extern void hcd_start(dwc_otg_core_if_t *core_if);
348 extern struct usb_hub *g_dwc_otg_root_hub20;
349 extern void dwc_otg_hub_disconnect_device(struct usb_hub *hub);
351 void dwc_otg_force_host(dwc_otg_core_if_t *core_if)
353 dwc_otg_device_t *otg_dev = core_if->otg_dev;
354 dctl_data_t dctl = {.d32 = 0 };
357 if (core_if->op_state == A_HOST) {
358 printk("dwc_otg_force_host,already in A_HOST mode,everest\n");
361 core_if->op_state = A_HOST;
363 cancel_delayed_work(&otg_dev->pcd->check_vbus_work);
364 dctl.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dctl);
365 dctl.b.sftdiscon = 1;
366 DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dctl, dctl.d32);
368 local_irq_save(flags);
369 cil_pcd_stop(core_if);
371 * Initialize the Core for Host mode.
374 dwc_otg_core_init(core_if);
375 dwc_otg_enable_global_interrupts(core_if);
376 cil_hcd_start(core_if);
377 local_irq_restore(flags);
380 void dwc_otg_force_device(dwc_otg_core_if_t *core_if)
382 dwc_otg_device_t *otg_dev = core_if->otg_dev;
385 local_irq_save(flags);
387 if (core_if->op_state == B_PERIPHERAL) {
389 ("dwc_otg_force_device,already in B_PERIPHERAL,everest\n");
392 core_if->op_state = B_PERIPHERAL;
393 cil_hcd_stop(core_if);
394 /* dwc_otg_hub_disconnect_device(g_dwc_otg_root_hub20); */
395 otg_dev->pcd->phy_suspend = 1;
396 otg_dev->pcd->vbus_status = 0;
397 dwc_otg_pcd_start_check_vbus_work(otg_dev->pcd);
399 /* Reset the Controller */
400 dwc_otg_core_reset(core_if);
402 dwc_otg_core_init(core_if);
403 dwc_otg_disable_global_interrupts(core_if);
404 cil_pcd_start(core_if);
406 local_irq_restore(flags);
409 static ssize_t force_usb_mode_show(struct device_driver *drv, char *buf)
411 dwc_otg_device_t *otg_dev = g_otgdev;
412 dwc_otg_core_if_t *core_if = otg_dev->core_if;
414 return sprintf(buf, "%d\n", core_if->usb_mode);
417 static ssize_t force_usb_mode_store(struct device_driver *drv, const char *buf,
420 int new_mode = simple_strtoul(buf, NULL, 16);
421 dwc_otg_device_t *otg_dev = g_otgdev;
422 dwc_otg_core_if_t *core_if;
423 struct dwc_otg_platform_data *pldata;
428 core_if = otg_dev->core_if;
429 pldata = otg_dev->pldata;
431 DWC_PRINTF("%s %d->%d\n", __func__, core_if->usb_mode, new_mode);
433 if (core_if->usb_mode == new_mode) {
437 if (pldata->phy_status == USB_PHY_SUSPEND) {
438 pldata->clock_enable(pldata, 1);
439 pldata->phy_suspend(pldata, USB_PHY_ENABLED);
443 case USB_MODE_FORCE_HOST:
444 if (USB_MODE_FORCE_DEVICE == core_if->usb_mode) {
446 core_if->usb_mode = new_mode;
447 dwc_otg_force_host(core_if);
448 } else if (USB_MODE_NORMAL == core_if->usb_mode) {
449 core_if->usb_mode = new_mode;
450 if (dwc_otg_is_host_mode(core_if))
451 dwc_otg_set_force_mode(core_if, new_mode);
453 dwc_otg_force_host(core_if);
457 case USB_MODE_FORCE_DEVICE:
458 if (USB_MODE_FORCE_HOST == core_if->usb_mode) {
459 core_if->usb_mode = new_mode;
460 dwc_otg_force_device(core_if);
461 } else if (USB_MODE_NORMAL == core_if->usb_mode) {
462 core_if->usb_mode = new_mode;
463 if (dwc_otg_is_device_mode(core_if))
464 dwc_otg_set_force_mode(core_if, new_mode);
466 dwc_otg_force_device(core_if);
470 case USB_MODE_NORMAL:
471 if (USB_MODE_FORCE_DEVICE == core_if->usb_mode) {
472 core_if->usb_mode = new_mode;
473 cancel_delayed_work(&otg_dev->pcd->check_vbus_work);
474 dwc_otg_set_force_mode(core_if, new_mode);
476 if (dwc_otg_is_host_mode(core_if)) {
477 dwc_otg_force_host(core_if);
479 dwc_otg_pcd_start_check_vbus_work(otg_dev->pcd);
481 } else if (USB_MODE_FORCE_HOST == core_if->usb_mode) {
482 core_if->usb_mode = new_mode;
483 dwc_otg_set_force_mode(core_if, new_mode);
485 if (dwc_otg_is_device_mode(core_if)) {
486 dwc_otg_force_device(core_if);
497 static DRIVER_ATTR(force_usb_mode, S_IRUGO | S_IWUSR, force_usb_mode_show,
498 force_usb_mode_store);
500 static ssize_t dwc_otg_conn_en_show(struct device_driver *_drv, char *_buf)
503 dwc_otg_device_t *otg_dev = g_otgdev;
504 dwc_otg_pcd_t *_pcd = otg_dev->pcd;
505 return sprintf(_buf, "%d\n", _pcd->conn_en);
509 static ssize_t dwc_otg_conn_en_store(struct device_driver *_drv,
510 const char *_buf, size_t _count)
512 int enable = simple_strtoul(_buf, NULL, 10);
513 dwc_otg_device_t *otg_dev = g_otgdev;
514 dwc_otg_pcd_t *_pcd = otg_dev->pcd;
515 DWC_PRINTF("%s %d->%d\n", __func__, _pcd->conn_en, enable);
517 _pcd->conn_en = enable;
521 static DRIVER_ATTR(dwc_otg_conn_en, S_IRUGO | S_IWUSR, dwc_otg_conn_en_show,
522 dwc_otg_conn_en_store);
524 /* used for product vbus power control, SDK not need.
525 * If dwc_otg is host mode, enable vbus power.
526 * If dwc_otg is device mode, disable vbus power.
527 * return 1 - host mode, 0 - device mode.
529 int dwc_otg_usb_state(void)
531 dwc_otg_device_t *otg_dev = g_otgdev;
534 /* op_state is A_HOST */
535 if (1 == otg_dev->core_if->op_state)
537 /* op_state is B_PERIPHERAL */
538 else if (4 == otg_dev->core_if->op_state)
543 DWC_WARN("g_otgdev is NULL, maybe otg probe is failed!\n");
547 EXPORT_SYMBOL(dwc_otg_usb_state);
549 static ssize_t dwc_otg_op_state_show(struct device_driver *_drv, char *_buf)
551 dwc_otg_device_t *otg_dev = g_otgdev;
554 return sprintf(_buf, "%d\n", otg_dev->core_if->op_state);
556 return sprintf(_buf, "%d\n", 0);
559 static DRIVER_ATTR(op_state, S_IRUGO, dwc_otg_op_state_show, NULL);
561 static ssize_t vbus_status_show(struct device_driver *_drv, char *_buf)
563 dwc_otg_device_t *otg_dev = g_otgdev;
564 dwc_otg_pcd_t *_pcd = otg_dev->pcd;
565 return sprintf(_buf, "%d\n", _pcd->vbus_status);
568 static DRIVER_ATTR(vbus_status, S_IRUGO, vbus_status_show, NULL);
571 * This function is called during module intialization
572 * to pass module parameters to the DWC_OTG CORE.
574 static int set_parameters(dwc_otg_core_if_t *core_if,
575 struct dwc_otg_driver_module_params module_params)
580 if (module_params.otg_cap != -1) {
582 dwc_otg_set_param_otg_cap(core_if, module_params.otg_cap);
584 if (module_params.dma_enable != -1) {
586 dwc_otg_set_param_dma_enable(core_if,
587 module_params.dma_enable);
589 if (module_params.dma_desc_enable != -1) {
591 dwc_otg_set_param_dma_desc_enable(core_if,
592 module_params.dma_desc_enable);
594 if (module_params.opt != -1) {
595 retval += dwc_otg_set_param_opt(core_if, module_params.opt);
597 if (module_params.dma_burst_size != -1) {
599 dwc_otg_set_param_dma_burst_size(core_if,
600 module_params.dma_burst_size);
602 if (module_params.host_support_fs_ls_low_power != -1) {
604 dwc_otg_set_param_host_support_fs_ls_low_power(core_if,
605 module_params.host_support_fs_ls_low_power);
607 if (module_params.enable_dynamic_fifo != -1) {
609 dwc_otg_set_param_enable_dynamic_fifo(core_if,
610 module_params.enable_dynamic_fifo);
612 if (module_params.data_fifo_size != -1) {
614 dwc_otg_set_param_data_fifo_size(core_if,
615 module_params.data_fifo_size);
617 if (module_params.dev_rx_fifo_size != -1) {
619 dwc_otg_set_param_dev_rx_fifo_size(core_if,
620 module_params.dev_rx_fifo_size);
622 if (module_params.dev_nperio_tx_fifo_size != -1) {
624 dwc_otg_set_param_dev_nperio_tx_fifo_size(core_if,
625 module_params.dev_nperio_tx_fifo_size);
627 if (module_params.host_rx_fifo_size != -1) {
629 dwc_otg_set_param_host_rx_fifo_size(core_if,
633 if (module_params.host_nperio_tx_fifo_size != -1) {
635 dwc_otg_set_param_host_nperio_tx_fifo_size(core_if,
636 module_params.host_nperio_tx_fifo_size);
638 if (module_params.host_perio_tx_fifo_size != -1) {
640 dwc_otg_set_param_host_perio_tx_fifo_size(core_if,
641 module_params.host_perio_tx_fifo_size);
643 if (module_params.max_transfer_size != -1) {
645 dwc_otg_set_param_max_transfer_size(core_if,
646 module_params.max_transfer_size);
648 if (module_params.max_packet_count != -1) {
650 dwc_otg_set_param_max_packet_count(core_if,
651 module_params.max_packet_count);
653 if (module_params.host_channels != -1) {
655 dwc_otg_set_param_host_channels(core_if,
656 module_params.host_channels);
658 if (module_params.dev_endpoints != -1) {
660 dwc_otg_set_param_dev_endpoints(core_if,
661 module_params.dev_endpoints);
663 if (module_params.phy_type != -1) {
665 dwc_otg_set_param_phy_type(core_if, module_params.phy_type);
667 if (module_params.speed != -1) {
668 retval += dwc_otg_set_param_speed(core_if, module_params.speed);
670 if (module_params.host_ls_low_power_phy_clk != -1) {
672 dwc_otg_set_param_host_ls_low_power_phy_clk(core_if,
673 module_params.host_ls_low_power_phy_clk);
675 if (module_params.phy_ulpi_ddr != -1) {
677 dwc_otg_set_param_phy_ulpi_ddr(core_if,
678 module_params.phy_ulpi_ddr);
680 if (module_params.phy_ulpi_ext_vbus != -1) {
682 dwc_otg_set_param_phy_ulpi_ext_vbus(core_if,
683 module_params.phy_ulpi_ext_vbus);
685 if (module_params.phy_utmi_width != -1) {
687 dwc_otg_set_param_phy_utmi_width(core_if,
688 module_params.phy_utmi_width);
690 if (module_params.ulpi_fs_ls != -1) {
692 dwc_otg_set_param_ulpi_fs_ls(core_if,
693 module_params.ulpi_fs_ls);
695 if (module_params.ts_dline != -1) {
697 dwc_otg_set_param_ts_dline(core_if, module_params.ts_dline);
699 if (module_params.i2c_enable != -1) {
701 dwc_otg_set_param_i2c_enable(core_if,
702 module_params.i2c_enable);
704 if (module_params.en_multiple_tx_fifo != -1) {
706 dwc_otg_set_param_en_multiple_tx_fifo(core_if,
707 module_params.en_multiple_tx_fifo);
709 for (i = 0; i < 15; i++) {
710 if (module_params.dev_perio_tx_fifo_size[i] != -1) {
712 dwc_otg_set_param_dev_perio_tx_fifo_size(core_if,
713 module_params.dev_perio_tx_fifo_size
718 for (i = 0; i < 15; i++) {
719 if (module_params.dev_tx_fifo_size[i] != -1) {
720 retval += dwc_otg_set_param_dev_tx_fifo_size(core_if,
721 module_params.dev_tx_fifo_size
725 if (module_params.thr_ctl != -1) {
727 dwc_otg_set_param_thr_ctl(core_if, module_params.thr_ctl);
729 if (module_params.mpi_enable != -1) {
731 dwc_otg_set_param_mpi_enable(core_if,
732 module_params.mpi_enable);
734 if (module_params.pti_enable != -1) {
736 dwc_otg_set_param_pti_enable(core_if,
737 module_params.pti_enable);
739 if (module_params.lpm_enable != -1) {
741 dwc_otg_set_param_lpm_enable(core_if,
742 module_params.lpm_enable);
744 if (module_params.besl_enable != -1) {
746 dwc_otg_set_param_besl_enable(core_if,
747 module_params.besl_enable);
749 if (module_params.baseline_besl != -1) {
751 dwc_otg_set_param_baseline_besl(core_if,
752 module_params.baseline_besl);
754 if (module_params.deep_besl != -1) {
756 dwc_otg_set_param_deep_besl(core_if,
757 module_params.deep_besl);
759 if (module_params.ic_usb_cap != -1) {
761 dwc_otg_set_param_ic_usb_cap(core_if,
762 module_params.ic_usb_cap);
764 if (module_params.tx_thr_length != -1) {
766 dwc_otg_set_param_tx_thr_length(core_if,
770 if (module_params.rx_thr_length != -1) {
772 dwc_otg_set_param_rx_thr_length(core_if,
773 module_params.rx_thr_length);
775 if (module_params.ahb_thr_ratio != -1) {
777 dwc_otg_set_param_ahb_thr_ratio(core_if,
781 if (module_params.power_down != -1) {
783 dwc_otg_set_param_power_down(core_if,
784 module_params.power_down);
786 if (module_params.reload_ctl != -1) {
788 dwc_otg_set_param_reload_ctl(core_if,
789 module_params.reload_ctl);
792 if (module_params.dev_out_nak != -1) {
794 dwc_otg_set_param_dev_out_nak(core_if,
795 module_params.dev_out_nak);
798 if (module_params.cont_on_bna != -1) {
800 dwc_otg_set_param_cont_on_bna(core_if,
801 module_params.cont_on_bna);
804 if (module_params.ahb_single != -1) {
806 dwc_otg_set_param_ahb_single(core_if,
807 module_params.ahb_single);
810 if (module_params.otg_ver != -1) {
812 dwc_otg_set_param_otg_ver(core_if, module_params.otg_ver);
814 if (module_params.adp_enable != -1) {
816 dwc_otg_set_param_adp_enable(core_if,
817 module_params.adp_enable);
823 * This function is the top level interrupt handler for the Common
824 * (Device and host modes) interrupts.
826 static irqreturn_t dwc_otg_common_irq(int irq, void *dev)
828 int32_t retval = IRQ_NONE;
830 retval = dwc_otg_handle_common_intr(dev);
832 /* S3C2410X_CLEAR_EINTPEND(); */
834 return IRQ_RETVAL(retval);
837 #ifdef CONFIG_USB20_HOST
839 * This function is called when a lm_device is unregistered with the
840 * dwc_otg_driver. This happens, for example, when the rmmod command is
841 * executed. The device may or may not be electrically present. If it is
842 * present, the driver stops device processing. Any resources used on behalf
843 * of this device are freed.
847 static int host20_driver_remove(struct platform_device *_dev)
850 dwc_otg_device_t *otg_dev = dwc_get_device_platform_data(_dev);
851 DWC_DEBUGPL(DBG_ANY, "%s(%p)\n", __func__, _dev);
854 /* Memory allocation for the dwc_otg_device failed. */
855 DWC_DEBUGPL(DBG_ANY, "%s: otg_dev NULL!\n", __func__);
858 #ifndef DWC_DEVICE_ONLY
862 DWC_DEBUGPL(DBG_ANY, "%s: otg_dev->hcd NULL!\n", __func__);
867 #ifndef DWC_HOST_ONLY
871 DWC_DEBUGPL(DBG_ANY, "%s: otg_dev->pcd NULL!\n", __func__);
879 if (otg_dev->common_irq_installed) {
880 /* free_irq(_dev->irq, otg_dev); */
881 free_irq(platform_get_irq(_dev, 0), otg_dev);
883 DWC_DEBUGPL(DBG_ANY, "%s: There is no installed irq!\n",
888 if (otg_dev->core_if) {
889 dwc_otg_cil_remove(otg_dev->core_if);
891 DWC_DEBUGPL(DBG_ANY, "%s: otg_dev->core_if NULL!\n", __func__);
896 * Remove the device attributes
898 dwc_otg_attr_remove(_dev);
903 if (otg_dev->os_dep.base) {
904 iounmap(otg_dev->os_dep.base);
909 * Clear the drvdata pointer.
912 dwc_set_device_platform_data(_dev, 0);
917 static const struct of_device_id usb20_host_of_match[] = {
920 .compatible = "rockchip,rk3188_usb20_host",
921 .data = &usb20host_pdata_rk3188,
924 .compatible = "rockchip,rk3288_usb20_host",
925 .data = &usb20host_pdata_rk3288,
928 .compatible = "rockchip,rk3036_usb20_host",
929 .data = &usb20host_pdata_rk3036,
932 .compatible = "rockchip,rk3126_usb20_host",
933 .data = &usb20host_pdata_rk3126,
939 MODULE_DEVICE_TABLE(of, usb20_host_of_match);
942 * This function is called when an lm_device is bound to a
943 * dwc_otg_driver. It creates the driver components required to
944 * control the device (CIL, HCD, and PCD) and it initializes the
945 * device. The driver components are stored in a dwc_otg_device
946 * structure. A reference to the dwc_otg_device is saved in the
947 * lm_device. This allows the driver to access the dwc_otg_device
948 * structure on subsequent calls to driver methods for this device.
950 * @param _dev Bus device
952 static int host20_driver_probe(struct platform_device *_dev)
956 struct resource *res_base;
957 dwc_otg_device_t *dwc_otg_device;
958 struct device *dev = &_dev->dev;
959 struct device_node *node = _dev->dev.of_node;
960 struct dwc_otg_platform_data *pldata;
961 const struct of_device_id *match =
962 of_match_device(of_match_ptr(usb20_host_of_match), &_dev->dev);
964 if (match && match->data) {
965 pldata = (void *)match->data;
968 dev_err(dev, "usb20otg match failed\n");
973 dev_err(dev, "device node not found\n");
980 if (pldata->clock_init) {
981 pldata->clock_init(pldata);
982 pldata->clock_enable(pldata, 1);
985 if (pldata->phy_suspend)
986 pldata->phy_suspend(pldata, USB_PHY_ENABLED);
988 if (pldata->soft_reset)
989 pldata->soft_reset(pldata, RST_POR);
991 res_base = platform_get_resource(_dev, IORESOURCE_MEM, 0);
993 dwc_otg_device = DWC_ALLOC(sizeof(dwc_otg_device_t));
995 if (!dwc_otg_device) {
996 dev_err(&_dev->dev, "kmalloc of dwc_otg_device failed\n");
1001 memset(dwc_otg_device, 0, sizeof(*dwc_otg_device));
1002 dwc_otg_device->os_dep.reg_offset = 0xFFFFFFFF;
1005 * Map the DWC_otg Core memory into virtual address space.
1008 dwc_otg_device->os_dep.base = devm_ioremap_resource(dev, res_base);
1010 if (!dwc_otg_device->os_dep.base) {
1011 dev_err(&_dev->dev, "ioremap() failed\n");
1012 DWC_FREE(dwc_otg_device);
1016 dev_dbg(&_dev->dev, "base=0x%p\n", dwc_otg_device->os_dep.base);
1018 /* Set device flags indicating whether the HCD supports DMA. */
1019 if (!_dev->dev.dma_mask)
1020 _dev->dev.dma_mask = &_dev->dev.coherent_dma_mask;
1021 retval = dma_set_coherent_mask(&_dev->dev, DMA_BIT_MASK(32));
1026 * Initialize driver data to point to the global DWC_otg
1030 dwc_set_device_platform_data(_dev, dwc_otg_device);
1031 pldata->privdata = dwc_otg_device;
1032 dwc_otg_device->pldata = (void *)pldata;
1034 dev_dbg(&_dev->dev, "dwc_otg_device=0x%p\n", dwc_otg_device);
1036 dwc_otg_device->core_if = dwc_otg_cil_init(dwc_otg_device->os_dep.base);
1038 if (!dwc_otg_device->core_if) {
1039 dev_err(&_dev->dev, "CIL initialization failed!\n");
1044 dwc_otg_device->core_if->otg_dev = dwc_otg_device;
1047 * Attempt to ensure this device is really a DWC_otg Controller.
1048 * Read and verify the SNPSID register contents. The value should be
1049 * 0x45F42XXX or 0x45F42XXX, which corresponds to either "OT2" or "OTG3",
1050 * as in "OTG version 2.XX" or "OTG version 3.XX".
1053 if (((dwc_otg_get_gsnpsid(dwc_otg_device->core_if) & 0xFFFFF000) !=
1055 && ((dwc_otg_get_gsnpsid(dwc_otg_device->core_if) & 0xFFFFF000) !=
1057 dev_err(&_dev->dev, "Bad value for SNPSID: 0x%08x\n",
1058 dwc_otg_get_gsnpsid(dwc_otg_device->core_if));
1064 * Validate parameter values.
1066 if (set_parameters(dwc_otg_device->core_if, dwc_host_module_params)) {
1072 * Create Device Attributes in sysfs
1074 dwc_otg_attr_create(_dev);
1077 * Disable the global interrupt until all the interrupt
1078 * handlers are installed.
1080 dwc_otg_disable_global_interrupts(dwc_otg_device->core_if);
1083 * Install the interrupt handler for the common interrupts before
1084 * enabling common interrupts in core_init below.
1086 irq = platform_get_irq(_dev, 0);
1087 DWC_DEBUGPL(DBG_CIL, "registering (common) handler for irq%d\n", irq);
1088 retval = request_irq(irq, dwc_otg_common_irq,
1089 IRQF_SHARED, "dwc_otg", dwc_otg_device);
1091 DWC_ERROR("request of irq%d failed\n", irq);
1095 dwc_otg_device->common_irq_installed = 1;
1099 * Initialize the DWC_otg core.
1100 * In order to reduce the time of initialization,
1101 * we do core soft reset after connection detected.
1103 dwc_otg_core_init_no_reset(dwc_otg_device->core_if);
1106 * Initialize the HCD
1108 retval = host20_hcd_init(_dev);
1110 DWC_ERROR("hcd_init failed\n");
1111 dwc_otg_device->hcd = NULL;
1115 clk_set_rate(pldata->phyclk_480m, 480000000);
1117 * Enable the global interrupt after all the interrupt
1118 * handlers are installed if there is no ADP support else
1119 * perform initial actions required for Internal ADP logic.
1121 if (!dwc_otg_get_param_adp_enable(dwc_otg_device->core_if)) {
1122 if (pldata->phy_status == USB_PHY_ENABLED) {
1123 pldata->phy_suspend(pldata, USB_PHY_SUSPEND);
1125 pldata->clock_enable(pldata, 0);
1127 /* dwc_otg_enable_global_interrupts(dwc_otg_device->core_if); */
1129 dwc_otg_adp_start(dwc_otg_device->core_if,
1130 dwc_otg_is_host_mode(dwc_otg_device->
1136 host20_driver_remove(_dev);
1138 if (pldata->clock_enable)
1139 pldata->clock_enable(pldata, 0);
1145 static int dwc_otg_driver_suspend(struct platform_device *_dev,
1151 static int dwc_otg_driver_resume(struct platform_device *_dev)
1156 static void dwc_otg_driver_shutdown(struct platform_device *_dev)
1158 struct device *dev = &_dev->dev;
1159 dwc_otg_device_t *otg_dev = dev->platform_data;
1160 dwc_otg_core_if_t *core_if = otg_dev->core_if;
1161 struct dwc_otg_platform_data *pldata = otg_dev->pldata;
1162 dctl_data_t dctl = {.d32 = 0 };
1163 dwc_otg_pcd_t *pcd = core_if->otg_dev->pcd;
1165 DWC_PRINTF("%s: disconnect USB %s mode\n", __func__,
1166 dwc_otg_is_host_mode(core_if) ? "host" : "device");
1168 if (dwc_otg_is_host_mode(core_if)) {
1169 if (core_if->hcd_cb && core_if->hcd_cb->stop)
1170 core_if->hcd_cb->stop(core_if->hcd_cb_p);
1172 cancel_delayed_work_sync(&pcd->check_vbus_work);
1173 /* soft disconnect */
1175 DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dctl);
1176 dctl.b.sftdiscon = 1;
1177 DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dctl,
1180 /* Clear any pending interrupts */
1181 DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, 0xFFFFFFFF);
1183 if (pldata->dwc_otg_uart_mode != NULL)
1184 pldata->dwc_otg_uart_mode(pldata, PHY_USB_MODE);
1185 if (pldata->phy_suspend != NULL)
1186 pldata->phy_suspend(pldata, USB_PHY_ENABLED);
1191 * This structure defines the methods to be called by a bus driver
1192 * during the lifecycle of a device on that bus. Both drivers and
1193 * devices are registered with a bus driver. The bus driver matches
1194 * devices to drivers based on information in the device and driver
1197 * The probe function is called when the bus driver matches a device
1198 * to this driver. The remove function is called when a device is
1199 * unregistered with the bus driver.
1201 #ifdef CONFIG_USB20_HOST
1202 static struct platform_driver dwc_host_driver = {
1204 .name = (char *)dwc_host20_driver_name,
1205 .of_match_table = of_match_ptr(usb20_host_of_match),
1207 .probe = host20_driver_probe,
1208 .remove = host20_driver_remove,
1209 .suspend = dwc_otg_driver_suspend,
1210 .resume = dwc_otg_driver_resume,
1214 #ifdef CONFIG_USB20_OTG
1216 * This function is called when a lm_device is unregistered with the
1217 * dwc_otg_driver. This happens, for example, when the rmmod command is
1218 * executed. The device may or may not be electrically present. If it is
1219 * present, the driver stops device processing. Any resources used on behalf
1220 * of this device are freed.
1224 static int otg20_driver_remove(struct platform_device *_dev)
1227 dwc_otg_device_t *otg_dev = dwc_get_device_platform_data(_dev);
1228 DWC_DEBUGPL(DBG_ANY, "%s(%p)\n", __func__, _dev);
1231 /* Memory allocation for the dwc_otg_device failed. */
1232 DWC_DEBUGPL(DBG_ANY, "%s: otg_dev NULL!\n", __func__);
1235 #ifndef DWC_DEVICE_ONLY
1239 DWC_DEBUGPL(DBG_ANY, "%s: otg_dev->hcd NULL!\n", __func__);
1244 #ifndef DWC_HOST_ONLY
1248 DWC_DEBUGPL(DBG_ANY, "%s: otg_dev->pcd NULL!\n", __func__);
1255 if (otg_dev->common_irq_installed) {
1256 /* free_irq(_dev->irq, otg_dev); */
1257 free_irq(platform_get_irq(_dev, 0), otg_dev);
1259 DWC_DEBUGPL(DBG_ANY, "%s: There is no installed irq!\n",
1264 if (otg_dev->core_if) {
1265 dwc_otg_cil_remove(otg_dev->core_if);
1267 DWC_DEBUGPL(DBG_ANY, "%s: otg_dev->core_if NULL!\n", __func__);
1272 * Remove the device attributes
1274 dwc_otg_attr_remove(_dev);
1277 * Return the memory.
1279 if (otg_dev->os_dep.base)
1280 iounmap(otg_dev->os_dep.base);
1284 * Clear the drvdata pointer.
1287 dwc_set_device_platform_data(_dev, 0);
1292 static const struct of_device_id usb20_otg_of_match[] = {
1295 .compatible = "rockchip,rk3188_usb20_otg",
1296 .data = &usb20otg_pdata_rk3188,
1299 .compatible = "rockchip,rk3288_usb20_otg",
1300 .data = &usb20otg_pdata_rk3288,
1303 .compatible = "rockchip,rk3036_usb20_otg",
1304 .data = &usb20otg_pdata_rk3036,
1307 .compatible = "rockchip,rk3126_usb20_otg",
1308 .data = &usb20otg_pdata_rk3126,
1313 .compatible = "rockchip,rk3368_usb20_otg",
1314 .data = &usb20otg_pdata_rk3368,
1320 MODULE_DEVICE_TABLE(of, usb20_otg_of_match);
1323 * This function is called when an lm_device is bound to a
1324 * dwc_otg_driver. It creates the driver components required to
1325 * control the device (CIL, HCD, and PCD) and it initializes the
1326 * device. The driver components are stored in a dwc_otg_device
1327 * structure. A reference to the dwc_otg_device is saved in the
1328 * lm_device. This allows the driver to access the dwc_otg_device
1329 * structure on subsequent calls to driver methods for this device.
1331 * @param _dev Bus device
1333 static int otg20_driver_probe(struct platform_device *_dev)
1338 struct resource *res_base;
1339 dwc_otg_device_t *dwc_otg_device;
1340 struct device *dev = &_dev->dev;
1341 struct device_node *node = _dev->dev.of_node;
1342 struct dwc_otg_platform_data *pldata;
1343 const struct of_device_id *match =
1344 of_match_device(of_match_ptr(usb20_otg_of_match), &_dev->dev);
1346 if (match && match->data) {
1347 pldata = (void *)match->data;
1350 dev_err(dev, "usb20otg match failed\n");
1355 dev_err(dev, "device node not found\n");
1359 if (pldata->hw_init)
1362 if (pldata->clock_init) {
1363 pldata->clock_init(pldata);
1364 pldata->clock_enable(pldata, 1);
1367 if (pldata->phy_suspend)
1368 pldata->phy_suspend(pldata, USB_PHY_ENABLED);
1370 if (pldata->dwc_otg_uart_mode)
1371 pldata->dwc_otg_uart_mode(pldata, PHY_USB_MODE);
1373 /* do reset later, because reset need about
1374 * 100ms to ensure otg id state change.
1377 if(pldata->soft_reset)
1378 pldata->soft_reset();
1382 res_base = platform_get_resource(_dev, IORESOURCE_MEM, 0);
1384 dwc_otg_device = DWC_ALLOC(sizeof(dwc_otg_device_t));
1386 if (!dwc_otg_device) {
1387 dev_err(&_dev->dev, "kmalloc of dwc_otg_device failed\n");
1392 memset(dwc_otg_device, 0, sizeof(*dwc_otg_device));
1393 dwc_otg_device->os_dep.reg_offset = 0xFFFFFFFF;
1396 * Map the DWC_otg Core memory into virtual address space.
1399 dwc_otg_device->os_dep.base = devm_ioremap_resource(dev, res_base);
1401 if (!dwc_otg_device->os_dep.base) {
1402 dev_err(&_dev->dev, "ioremap() failed\n");
1403 DWC_FREE(dwc_otg_device);
1407 dev_dbg(&_dev->dev, "base=0x%p\n", dwc_otg_device->os_dep.base);
1409 /* Set device flags indicating whether the HCD supports DMA. */
1410 if (!_dev->dev.dma_mask)
1411 _dev->dev.dma_mask = &_dev->dev.coherent_dma_mask;
1412 retval = dma_set_coherent_mask(&_dev->dev, DMA_BIT_MASK(32));
1417 * Initialize driver data to point to the global DWC_otg
1421 g_otgdev = dwc_otg_device;
1422 pldata->privdata = dwc_otg_device;
1423 dwc_otg_device->pldata = pldata;
1425 dwc_set_device_platform_data(_dev, dwc_otg_device);
1427 dev_dbg(&_dev->dev, "dwc_otg_device=0x%p\n", dwc_otg_device);
1429 dwc_otg_device->core_if = dwc_otg_cil_init(dwc_otg_device->os_dep.base);
1430 if (!dwc_otg_device->core_if) {
1431 dev_err(&_dev->dev, "CIL initialization failed!\n");
1436 dwc_otg_device->core_if->otg_dev = dwc_otg_device;
1438 * Attempt to ensure this device is really a DWC_otg Controller.
1439 * Read and verify the SNPSID register contents. The value should be
1440 * 0x45F42XXX or 0x45F42XXX, which corresponds to either "OT2" or "OTG3",
1441 * as in "OTG version 2.XX" or "OTG version 3.XX".
1444 if (((dwc_otg_get_gsnpsid(dwc_otg_device->core_if) & 0xFFFFF000) !=
1446 && ((dwc_otg_get_gsnpsid(dwc_otg_device->core_if) & 0xFFFFF000) !=
1448 dev_err(&_dev->dev, "Bad value for SNPSID: 0x%08x\n",
1449 dwc_otg_get_gsnpsid(dwc_otg_device->core_if));
1455 * Validate parameter values.
1457 if (set_parameters(dwc_otg_device->core_if, dwc_otg_module_params)) {
1463 * Create Device Attributes in sysfs
1465 dwc_otg_attr_create(_dev);
1468 * Disable the global interrupt until all the interrupt
1469 * handlers are installed.
1471 dwc_otg_disable_global_interrupts(dwc_otg_device->core_if);
1474 * Install the interrupt handler for the common interrupts before
1475 * enabling common interrupts in core_init below.
1477 irq = platform_get_irq(_dev, 0);
1478 DWC_DEBUGPL(DBG_CIL, "registering (common) handler for irq%d\n", irq);
1479 retval = request_irq(irq, dwc_otg_common_irq,
1480 IRQF_SHARED, "dwc_otg", dwc_otg_device);
1482 DWC_ERROR("request of irq%d failed\n", irq);
1486 dwc_otg_device->common_irq_installed = 1;
1490 * Initialize the DWC_otg core.
1491 * In order to reduce the time of initialization,
1492 * we do core soft reset after connection detected.
1494 dwc_otg_core_init_no_reset(dwc_otg_device->core_if);
1497 * 0 - USB_MODE_NORMAL
1498 * 1 - USB_MODE_FORCE_HOST
1499 * 2 - USB_MODE_FORCE_DEVICE
1501 of_property_read_u32(node, "rockchip,usb-mode", &val);
1502 dwc_otg_device->core_if->usb_mode = val;
1504 #ifndef DWC_HOST_ONLY
1506 * Initialize the PCD
1508 retval = pcd_init(_dev);
1510 DWC_ERROR("pcd_init failed\n");
1511 dwc_otg_device->pcd = NULL;
1515 #ifndef DWC_DEVICE_ONLY
1517 * Initialize the HCD
1519 retval = otg20_hcd_init(_dev);
1521 DWC_ERROR("hcd_init failed\n");
1522 dwc_otg_device->hcd = NULL;
1527 * Enable the global interrupt after all the interrupt
1528 * handlers are installed if there is no ADP support else
1529 * perform initial actions required for Internal ADP logic.
1531 if (!dwc_otg_get_param_adp_enable(dwc_otg_device->core_if)) {
1532 if (dwc_otg_device->core_if->usb_mode == USB_MODE_NORMAL &&
1533 pldata->phy_status == USB_PHY_ENABLED) {
1534 pldata->phy_suspend(pldata, USB_PHY_SUSPEND);
1536 pldata->clock_enable(pldata, 0);
1538 /* dwc_otg_enable_global_interrupts(dwc_otg_device->core_if); */
1540 dwc_otg_adp_start(dwc_otg_device->core_if,
1541 dwc_otg_is_host_mode(dwc_otg_device->
1547 otg20_driver_remove(_dev);
1550 if (pldata->clock_enable)
1551 pldata->clock_enable(pldata, 0);
1557 static int dwc_otg_pm_suspend(struct device *dev)
1559 dwc_otg_device_t *dwc_otg_device;
1560 struct dwc_otg_platform_data *pdata_otg;
1562 dwc_otg_device = dev_get_platdata(dev);
1564 dev_dbg(dev, "dwc_otg PM suspend\n");
1566 if (dwc_otg_device->core_if->op_state == B_PERIPHERAL)
1569 pdata_otg = dwc_otg_device->pldata;
1570 pdata_otg->phy_suspend(pdata_otg, USB_PHY_SUSPEND);
1575 static int dwc_otg_pm_resume(struct device *dev)
1577 dwc_otg_device_t *dwc_otg_device;
1578 struct dwc_otg_platform_data *pdata_otg;
1580 dwc_otg_device = dev_get_platdata(dev);
1582 dev_dbg(dev, "dwc_otg PM resume\n");
1584 if (dwc_otg_device->core_if->op_state == B_PERIPHERAL)
1587 pdata_otg = dwc_otg_device->pldata;
1588 pdata_otg->phy_suspend(pdata_otg, USB_PHY_ENABLED);
1593 #define dwc_otg_pm_suspend NULL
1594 #define dwc_otg_pm_resume NULL
1597 static const struct dev_pm_ops dwc_otg_dev_pm_ops = {
1598 .suspend = dwc_otg_pm_suspend,
1599 .resume = dwc_otg_pm_resume,
1602 static struct platform_driver dwc_otg_driver = {
1604 .name = (char *)dwc_otg20_driver_name,
1605 .of_match_table = of_match_ptr(usb20_otg_of_match),
1607 .pm = &dwc_otg_dev_pm_ops,
1610 .probe = otg20_driver_probe,
1611 .remove = otg20_driver_remove,
1612 .suspend = dwc_otg_driver_suspend,
1613 .resume = dwc_otg_driver_resume,
1614 .shutdown = dwc_otg_driver_shutdown,
1618 void rk_usb_power_up(void)
1620 struct dwc_otg_platform_data *pldata_otg;
1621 struct dwc_otg_platform_data *pldata_host;
1622 struct rkehci_platform_data *pldata_ehci;
1624 if (cpu_is_rk3288()) {
1625 #ifdef CONFIG_RK_USB_UART
1626 /* enable USB bypass UART function */
1627 writel_relaxed(0x00c00000 | usb_to_uart_status,
1628 RK_GRF_VIRT + RK3288_GRF_UOC0_CON3);
1631 /* unset siddq,the analog blocks are powered up */
1632 #ifdef CONFIG_USB20_OTG
1633 pldata_otg = &usb20otg_pdata_rk3288;
1635 if (pldata_otg->phy_status == USB_PHY_SUSPEND)
1636 writel_relaxed((0x01 << 13) << 16,
1638 RK3288_GRF_UOC0_CON0);
1641 #ifdef CONFIG_USB20_HOST
1642 pldata_host = &usb20host_pdata_rk3288;
1644 if (pldata_host->phy_status == USB_PHY_SUSPEND)
1645 writel_relaxed((0x01 << 13) << 16,
1647 RK3288_GRF_UOC2_CON0);
1650 #ifdef CONFIG_USB_EHCI_RK
1651 pldata_ehci = &rkehci_pdata_rk3288;
1653 if (pldata_ehci->phy_status == USB_PHY_SUSPEND)
1654 writel_relaxed((0x01 << 13) << 16,
1656 RK3288_GRF_UOC1_CON0);
1661 dwc_otg_device_t *otg_dev = g_otgdev;
1666 pldata_otg = otg_dev->pldata;
1667 if (pldata_otg && pldata_otg->phy_power_down)
1668 pldata_otg->phy_power_down(PHY_POWER_UP);
1672 void rk_usb_power_down(void)
1674 struct dwc_otg_platform_data *pldata_otg;
1675 struct dwc_otg_platform_data *pldata_host;
1676 struct rkehci_platform_data *pldata_ehci;
1678 if (cpu_is_rk3288()) {
1679 #ifdef CONFIG_RK_USB_UART
1680 /* disable USB bypass UART function */
1681 usb_to_uart_status =
1682 readl_relaxed(RK_GRF_VIRT + RK3288_GRF_UOC0_CON3);
1683 writel_relaxed(0x00c00000, RK_GRF_VIRT + RK3288_GRF_UOC0_CON3);
1685 /* set siddq,the analog blocks are powered down
1687 * 1. Before asserting SIDDQ, ensure that VDATSRCENB0,
1688 * VDATDETENB0, DCDENB0, BYPASSSEL0, ADPPRBENB0,
1689 * and TESTBURNIN are set to 1'b0.
1690 * 2. Before asserting SIDDQ, ensure that phy enter suspend.*/
1691 #ifdef CONFIG_USB20_OTG
1692 pldata_otg = &usb20otg_pdata_rk3288;
1694 if (pldata_otg->phy_status == USB_PHY_SUSPEND)
1695 writel_relaxed((0x01 << 13) |
1696 ((0x01 << 13) << 16),
1698 RK3288_GRF_UOC0_CON0);
1701 #ifdef CONFIG_USB20_HOST
1702 pldata_host = &usb20host_pdata_rk3288;
1704 if (pldata_host->phy_status == USB_PHY_SUSPEND)
1705 writel_relaxed((0x01 << 13) |
1706 ((0x01 << 13) << 16),
1708 RK3288_GRF_UOC2_CON0);
1711 #ifdef CONFIG_USB_EHCI_RK
1712 pldata_ehci = &rkehci_pdata_rk3288;
1714 if (pldata_ehci->phy_status == USB_PHY_SUSPEND)
1715 writel_relaxed((0x01 << 13) |
1716 ((0x01 << 13) << 16),
1718 RK3288_GRF_UOC1_CON0);
1722 dwc_otg_device_t *otg_dev = g_otgdev;
1727 pldata_otg = otg_dev->pldata;
1728 if (pldata_otg && pldata_otg->phy_power_down)
1729 pldata_otg->phy_power_down(PHY_POWER_DOWN);
1733 EXPORT_SYMBOL(rk_usb_power_up);
1734 EXPORT_SYMBOL(rk_usb_power_down);
1736 * This function is called when the dwc_otg_driver is installed with the
1737 * insmod command. It registers the dwc_otg_driver structure with the
1738 * appropriate bus driver. This will cause the dwc_otg_driver_probe function
1739 * to be called. In addition, the bus driver will automatically expose
1740 * attributes defined for the device and driver in the special sysfs file
1745 static int __init dwc_otg_driver_init(void)
1750 #ifdef CONFIG_USB20_OTG
1751 /* register otg20 */
1752 printk(KERN_INFO "%s: version %s\n", dwc_otg20_driver_name,
1753 DWC_DRIVER_VERSION);
1755 retval = platform_driver_register(&dwc_otg_driver);
1757 printk(KERN_ERR "%s retval=%d\n", __func__, retval);
1762 driver_create_file(&dwc_otg_driver.driver, &driver_attr_version);
1764 driver_create_file(&dwc_otg_driver.driver, &driver_attr_debuglevel);
1766 driver_create_file(&dwc_otg_driver.driver,
1767 &driver_attr_dwc_otg_conn_en);
1769 driver_create_file(&dwc_otg_driver.driver,
1770 &driver_attr_vbus_status);
1772 driver_create_file(&dwc_otg_driver.driver,
1773 &driver_attr_force_usb_mode);
1775 driver_create_file(&dwc_otg_driver.driver,
1776 &driver_attr_op_state);
1780 /* register host20 */
1781 #ifdef CONFIG_USB20_HOST
1782 printk(KERN_INFO "%s: version %s\n", dwc_host20_driver_name,
1783 DWC_DRIVER_VERSION);
1785 retval = platform_driver_register(&dwc_host_driver);
1787 printk(KERN_ERR "%s retval=%d\n", __func__, retval);
1792 driver_create_file(&dwc_host_driver.driver, &driver_attr_version);
1794 driver_create_file(&dwc_host_driver.driver,
1795 &driver_attr_debuglevel);
1800 module_init(dwc_otg_driver_init);
1803 * This function is called when the driver is removed from the kernel
1804 * with the rmmod command. The driver unregisters itself with its bus
1808 static void __exit dwc_otg_driver_cleanup(void)
1810 printk(KERN_DEBUG "dwc_otg_driver_cleanup()\n");
1812 #ifdef CONFIG_USB20_HOST
1814 driver_remove_file(&dwc_host_driver.driver, &driver_attr_debuglevel);
1815 driver_remove_file(&dwc_host_driver.driver, &driver_attr_version);
1816 platform_driver_unregister(&dwc_host_driver);
1817 printk(KERN_INFO "%s module removed\n", dwc_host20_driver_name);
1820 #ifdef CONFIG_USB20_OTG
1822 driver_remove_file(&dwc_otg_driver.driver,
1823 &driver_attr_dwc_otg_conn_en);
1824 driver_remove_file(&dwc_otg_driver.driver, &driver_attr_debuglevel);
1825 driver_remove_file(&dwc_otg_driver.driver, &driver_attr_version);
1826 driver_remove_file(&dwc_otg_driver.driver, &driver_attr_vbus_status);
1827 driver_remove_file(&dwc_otg_driver.driver, &driver_attr_force_usb_mode);
1828 driver_remove_file(&dwc_otg_driver.driver, &driver_attr_op_state);
1829 platform_driver_unregister(&dwc_otg_driver);
1830 printk(KERN_INFO "%s module removed\n", dwc_otg20_driver_name);
1834 module_exit(dwc_otg_driver_cleanup);
1836 MODULE_DESCRIPTION(DWC_DRIVER_DESC);
1837 MODULE_AUTHOR("Synopsys Inc.");
1838 MODULE_LICENSE("GPL");
1840 module_param_named(otg_cap, dwc_otg_module_params.otg_cap, int, 0444);
1841 MODULE_PARM_DESC(otg_cap, "OTG Capabilities 0=HNP&SRP 1=SRP Only 2=None");
1842 module_param_named(opt, dwc_otg_module_params.opt, int, 0444);
1843 MODULE_PARM_DESC(opt, "OPT Mode");
1844 module_param_named(dma_enable, dwc_otg_module_params.dma_enable, int, 0444);
1845 MODULE_PARM_DESC(dma_enable, "DMA Mode 0=Slave 1=DMA enabled");
1847 module_param_named(dma_desc_enable, dwc_otg_module_params.dma_desc_enable, int,
1849 MODULE_PARM_DESC(dma_desc_enable,
1850 "DMA Desc Mode 0=Address DMA 1=DMA Descriptor enabled");
1852 module_param_named(dma_burst_size, dwc_otg_module_params.dma_burst_size, int,
1854 MODULE_PARM_DESC(dma_burst_size,
1855 "DMA Burst Size 1, 4, 8, 16, 32, 64, 128, 256");
1856 module_param_named(speed, dwc_otg_module_params.speed, int, 0444);
1857 MODULE_PARM_DESC(speed, "Speed 0=High Speed 1=Full Speed");
1858 module_param_named(host_support_fs_ls_low_power,
1859 dwc_otg_module_params.host_support_fs_ls_low_power, int,
1861 MODULE_PARM_DESC(host_support_fs_ls_low_power,
1862 "Support Low Power w/FS or LS 0=Support 1=Don't Support");
1863 module_param_named(host_ls_low_power_phy_clk,
1864 dwc_otg_module_params.host_ls_low_power_phy_clk, int, 0444);
1865 MODULE_PARM_DESC(host_ls_low_power_phy_clk,
1866 "Low Speed Low Power Clock 0=48Mhz 1=6Mhz");
1867 module_param_named(enable_dynamic_fifo,
1868 dwc_otg_module_params.enable_dynamic_fifo, int, 0444);
1869 MODULE_PARM_DESC(enable_dynamic_fifo, "0=cC Setting 1=Allow Dynamic Sizing");
1870 module_param_named(data_fifo_size, dwc_otg_module_params.data_fifo_size, int,
1872 MODULE_PARM_DESC(data_fifo_size,
1873 "Total number of words in the data FIFO memory 32-32768");
1874 module_param_named(dev_rx_fifo_size, dwc_otg_module_params.dev_rx_fifo_size,
1876 MODULE_PARM_DESC(dev_rx_fifo_size, "Number of words in the Rx FIFO 16-32768");
1877 module_param_named(dev_nperio_tx_fifo_size,
1878 dwc_otg_module_params.dev_nperio_tx_fifo_size, int, 0444);
1879 MODULE_PARM_DESC(dev_nperio_tx_fifo_size,
1880 "Number of words in the non-periodic Tx FIFO 16-32768");
1881 module_param_named(dev_perio_tx_fifo_size_1,
1882 dwc_otg_module_params.dev_perio_tx_fifo_size[0], int, 0444);
1883 MODULE_PARM_DESC(dev_perio_tx_fifo_size_1,
1884 "Number of words in the periodic Tx FIFO 4-768");
1885 module_param_named(dev_perio_tx_fifo_size_2,
1886 dwc_otg_module_params.dev_perio_tx_fifo_size[1], int, 0444);
1887 MODULE_PARM_DESC(dev_perio_tx_fifo_size_2,
1888 "Number of words in the periodic Tx FIFO 4-768");
1889 module_param_named(dev_perio_tx_fifo_size_3,
1890 dwc_otg_module_params.dev_perio_tx_fifo_size[2], int, 0444);
1891 MODULE_PARM_DESC(dev_perio_tx_fifo_size_3,
1892 "Number of words in the periodic Tx FIFO 4-768");
1893 module_param_named(dev_perio_tx_fifo_size_4,
1894 dwc_otg_module_params.dev_perio_tx_fifo_size[3], int, 0444);
1895 MODULE_PARM_DESC(dev_perio_tx_fifo_size_4,
1896 "Number of words in the periodic Tx FIFO 4-768");
1897 module_param_named(dev_perio_tx_fifo_size_5,
1898 dwc_otg_module_params.dev_perio_tx_fifo_size[4], int, 0444);
1899 MODULE_PARM_DESC(dev_perio_tx_fifo_size_5,
1900 "Number of words in the periodic Tx FIFO 4-768");
1901 module_param_named(dev_perio_tx_fifo_size_6,
1902 dwc_otg_module_params.dev_perio_tx_fifo_size[5], int, 0444);
1903 MODULE_PARM_DESC(dev_perio_tx_fifo_size_6,
1904 "Number of words in the periodic Tx FIFO 4-768");
1905 module_param_named(dev_perio_tx_fifo_size_7,
1906 dwc_otg_module_params.dev_perio_tx_fifo_size[6], int, 0444);
1907 MODULE_PARM_DESC(dev_perio_tx_fifo_size_7,
1908 "Number of words in the periodic Tx FIFO 4-768");
1909 module_param_named(dev_perio_tx_fifo_size_8,
1910 dwc_otg_module_params.dev_perio_tx_fifo_size[7], int, 0444);
1911 MODULE_PARM_DESC(dev_perio_tx_fifo_size_8,
1912 "Number of words in the periodic Tx FIFO 4-768");
1913 module_param_named(dev_perio_tx_fifo_size_9,
1914 dwc_otg_module_params.dev_perio_tx_fifo_size[8], int, 0444);
1915 MODULE_PARM_DESC(dev_perio_tx_fifo_size_9,
1916 "Number of words in the periodic Tx FIFO 4-768");
1917 module_param_named(dev_perio_tx_fifo_size_10,
1918 dwc_otg_module_params.dev_perio_tx_fifo_size[9], int, 0444);
1919 MODULE_PARM_DESC(dev_perio_tx_fifo_size_10,
1920 "Number of words in the periodic Tx FIFO 4-768");
1921 module_param_named(dev_perio_tx_fifo_size_11,
1922 dwc_otg_module_params.dev_perio_tx_fifo_size[10], int, 0444);
1923 MODULE_PARM_DESC(dev_perio_tx_fifo_size_11,
1924 "Number of words in the periodic Tx FIFO 4-768");
1925 module_param_named(dev_perio_tx_fifo_size_12,
1926 dwc_otg_module_params.dev_perio_tx_fifo_size[11], int, 0444);
1927 MODULE_PARM_DESC(dev_perio_tx_fifo_size_12,
1928 "Number of words in the periodic Tx FIFO 4-768");
1929 module_param_named(dev_perio_tx_fifo_size_13,
1930 dwc_otg_module_params.dev_perio_tx_fifo_size[12], int, 0444);
1931 MODULE_PARM_DESC(dev_perio_tx_fifo_size_13,
1932 "Number of words in the periodic Tx FIFO 4-768");
1933 module_param_named(dev_perio_tx_fifo_size_14,
1934 dwc_otg_module_params.dev_perio_tx_fifo_size[13], int, 0444);
1935 MODULE_PARM_DESC(dev_perio_tx_fifo_size_14,
1936 "Number of words in the periodic Tx FIFO 4-768");
1937 module_param_named(dev_perio_tx_fifo_size_15,
1938 dwc_otg_module_params.dev_perio_tx_fifo_size[14], int, 0444);
1939 MODULE_PARM_DESC(dev_perio_tx_fifo_size_15,
1940 "Number of words in the periodic Tx FIFO 4-768");
1941 module_param_named(host_rx_fifo_size, dwc_otg_module_params.host_rx_fifo_size,
1943 MODULE_PARM_DESC(host_rx_fifo_size, "Number of words in the Rx FIFO 16-32768");
1944 module_param_named(host_nperio_tx_fifo_size,
1945 dwc_otg_module_params.host_nperio_tx_fifo_size, int, 0444);
1946 MODULE_PARM_DESC(host_nperio_tx_fifo_size,
1947 "Number of words in the non-periodic Tx FIFO 16-32768");
1948 module_param_named(host_perio_tx_fifo_size,
1949 dwc_otg_module_params.host_perio_tx_fifo_size, int, 0444);
1950 MODULE_PARM_DESC(host_perio_tx_fifo_size,
1951 "Number of words in the host periodic Tx FIFO 16-32768");
1952 module_param_named(max_transfer_size, dwc_otg_module_params.max_transfer_size,
1954 /** @todo Set the max to 512K, modify checks */
1955 MODULE_PARM_DESC(max_transfer_size,
1956 "The maximum transfer size supported in bytes 2047-65535");
1957 module_param_named(max_packet_count, dwc_otg_module_params.max_packet_count,
1959 MODULE_PARM_DESC(max_packet_count,
1960 "The maximum number of packets in a transfer 15-511");
1961 module_param_named(host_channels, dwc_otg_module_params.host_channels, int,
1963 MODULE_PARM_DESC(host_channels,
1964 "The number of host channel registers to use 1-16");
1965 module_param_named(dev_endpoints, dwc_otg_module_params.dev_endpoints, int,
1967 MODULE_PARM_DESC(dev_endpoints,
1968 "The number of endpoints in addition to EP0 available for device mode 1-15");
1969 module_param_named(phy_type, dwc_otg_module_params.phy_type, int, 0444);
1970 MODULE_PARM_DESC(phy_type, "0=Reserved 1=UTMI+ 2=ULPI");
1971 module_param_named(phy_utmi_width, dwc_otg_module_params.phy_utmi_width, int,
1973 MODULE_PARM_DESC(phy_utmi_width, "Specifies the UTMI+ Data Width 8 or 16 bits");
1974 module_param_named(phy_ulpi_ddr, dwc_otg_module_params.phy_ulpi_ddr, int, 0444);
1975 MODULE_PARM_DESC(phy_ulpi_ddr,
1976 "ULPI at double or single data rate 0=Single 1=Double");
1977 module_param_named(phy_ulpi_ext_vbus, dwc_otg_module_params.phy_ulpi_ext_vbus,
1979 MODULE_PARM_DESC(phy_ulpi_ext_vbus,
1980 "ULPI PHY using internal or external vbus 0=Internal");
1981 module_param_named(i2c_enable, dwc_otg_module_params.i2c_enable, int, 0444);
1982 MODULE_PARM_DESC(i2c_enable, "FS PHY Interface");
1983 module_param_named(ulpi_fs_ls, dwc_otg_module_params.ulpi_fs_ls, int, 0444);
1984 MODULE_PARM_DESC(ulpi_fs_ls, "ULPI PHY FS/LS mode only");
1985 module_param_named(ts_dline, dwc_otg_module_params.ts_dline, int, 0444);
1986 MODULE_PARM_DESC(ts_dline, "Term select Dline pulsing for all PHYs");
1987 module_param_named(debug, g_dbg_lvl, int, 0444);
1988 MODULE_PARM_DESC(debug, "");
1990 module_param_named(en_multiple_tx_fifo,
1991 dwc_otg_module_params.en_multiple_tx_fifo, int, 0444);
1992 MODULE_PARM_DESC(en_multiple_tx_fifo,
1993 "Dedicated Non Periodic Tx FIFOs 0=disabled 1=enabled");
1994 module_param_named(dev_tx_fifo_size_1,
1995 dwc_otg_module_params.dev_tx_fifo_size[0], int, 0444);
1996 MODULE_PARM_DESC(dev_tx_fifo_size_1, "Number of words in the Tx FIFO 4-768");
1997 module_param_named(dev_tx_fifo_size_2,
1998 dwc_otg_module_params.dev_tx_fifo_size[1], int, 0444);
1999 MODULE_PARM_DESC(dev_tx_fifo_size_2, "Number of words in the Tx FIFO 4-768");
2000 module_param_named(dev_tx_fifo_size_3,
2001 dwc_otg_module_params.dev_tx_fifo_size[2], int, 0444);
2002 MODULE_PARM_DESC(dev_tx_fifo_size_3, "Number of words in the Tx FIFO 4-768");
2003 module_param_named(dev_tx_fifo_size_4,
2004 dwc_otg_module_params.dev_tx_fifo_size[3], int, 0444);
2005 MODULE_PARM_DESC(dev_tx_fifo_size_4, "Number of words in the Tx FIFO 4-768");
2006 module_param_named(dev_tx_fifo_size_5,
2007 dwc_otg_module_params.dev_tx_fifo_size[4], int, 0444);
2008 MODULE_PARM_DESC(dev_tx_fifo_size_5, "Number of words in the Tx FIFO 4-768");
2009 module_param_named(dev_tx_fifo_size_6,
2010 dwc_otg_module_params.dev_tx_fifo_size[5], int, 0444);
2011 MODULE_PARM_DESC(dev_tx_fifo_size_6, "Number of words in the Tx FIFO 4-768");
2012 module_param_named(dev_tx_fifo_size_7,
2013 dwc_otg_module_params.dev_tx_fifo_size[6], int, 0444);
2014 MODULE_PARM_DESC(dev_tx_fifo_size_7, "Number of words in the Tx FIFO 4-768");
2015 module_param_named(dev_tx_fifo_size_8,
2016 dwc_otg_module_params.dev_tx_fifo_size[7], int, 0444);
2017 MODULE_PARM_DESC(dev_tx_fifo_size_8, "Number of words in the Tx FIFO 4-768");
2018 module_param_named(dev_tx_fifo_size_9,
2019 dwc_otg_module_params.dev_tx_fifo_size[8], int, 0444);
2020 MODULE_PARM_DESC(dev_tx_fifo_size_9, "Number of words in the Tx FIFO 4-768");
2021 module_param_named(dev_tx_fifo_size_10,
2022 dwc_otg_module_params.dev_tx_fifo_size[9], int, 0444);
2023 MODULE_PARM_DESC(dev_tx_fifo_size_10, "Number of words in the Tx FIFO 4-768");
2024 module_param_named(dev_tx_fifo_size_11,
2025 dwc_otg_module_params.dev_tx_fifo_size[10], int, 0444);
2026 MODULE_PARM_DESC(dev_tx_fifo_size_11, "Number of words in the Tx FIFO 4-768");
2027 module_param_named(dev_tx_fifo_size_12,
2028 dwc_otg_module_params.dev_tx_fifo_size[11], int, 0444);
2029 MODULE_PARM_DESC(dev_tx_fifo_size_12, "Number of words in the Tx FIFO 4-768");
2030 module_param_named(dev_tx_fifo_size_13,
2031 dwc_otg_module_params.dev_tx_fifo_size[12], int, 0444);
2032 MODULE_PARM_DESC(dev_tx_fifo_size_13, "Number of words in the Tx FIFO 4-768");
2033 module_param_named(dev_tx_fifo_size_14,
2034 dwc_otg_module_params.dev_tx_fifo_size[13], int, 0444);
2035 MODULE_PARM_DESC(dev_tx_fifo_size_14, "Number of words in the Tx FIFO 4-768");
2036 module_param_named(dev_tx_fifo_size_15,
2037 dwc_otg_module_params.dev_tx_fifo_size[14], int, 0444);
2038 MODULE_PARM_DESC(dev_tx_fifo_size_15, "Number of words in the Tx FIFO 4-768");
2040 module_param_named(thr_ctl, dwc_otg_module_params.thr_ctl, int, 0444);
2041 MODULE_PARM_DESC(thr_ctl,
2042 "Thresholding enable flag bit 0 - non ISO Tx thr., 1 - ISO Tx thr., 2 - Rx thr.- bit 0=disabled 1=enabled");
2043 module_param_named(tx_thr_length, dwc_otg_module_params.tx_thr_length, int,
2045 MODULE_PARM_DESC(tx_thr_length, "Tx Threshold length in 32 bit DWORDs");
2046 module_param_named(rx_thr_length, dwc_otg_module_params.rx_thr_length, int,
2048 MODULE_PARM_DESC(rx_thr_length, "Rx Threshold length in 32 bit DWORDs");
2050 module_param_named(pti_enable, dwc_otg_module_params.pti_enable, int, 0444);
2051 module_param_named(mpi_enable, dwc_otg_module_params.mpi_enable, int, 0444);
2052 module_param_named(lpm_enable, dwc_otg_module_params.lpm_enable, int, 0444);
2053 MODULE_PARM_DESC(lpm_enable, "LPM Enable 0=LPM Disabled 1=LPM Enabled");
2055 module_param_named(besl_enable, dwc_otg_module_params.besl_enable, int, 0444);
2056 MODULE_PARM_DESC(besl_enable, "BESL Enable 0=BESL Disabled 1=BESL Enabled");
2057 module_param_named(baseline_besl, dwc_otg_module_params.baseline_besl, int,
2059 MODULE_PARM_DESC(baseline_besl, "Set the baseline besl value");
2060 module_param_named(deep_besl, dwc_otg_module_params.deep_besl, int, 0444);
2061 MODULE_PARM_DESC(deep_besl, "Set the deep besl value");
2063 module_param_named(ic_usb_cap, dwc_otg_module_params.ic_usb_cap, int, 0444);
2064 MODULE_PARM_DESC(ic_usb_cap,
2065 "IC_USB Capability 0=IC_USB Disabled 1=IC_USB Enabled");
2066 module_param_named(ahb_thr_ratio, dwc_otg_module_params.ahb_thr_ratio, int,
2068 MODULE_PARM_DESC(ahb_thr_ratio, "AHB Threshold Ratio");
2069 module_param_named(power_down, dwc_otg_module_params.power_down, int, 0444);
2070 MODULE_PARM_DESC(power_down, "Power Down Mode");
2071 module_param_named(reload_ctl, dwc_otg_module_params.reload_ctl, int, 0444);
2072 MODULE_PARM_DESC(reload_ctl, "HFIR Reload Control");
2073 module_param_named(dev_out_nak, dwc_otg_module_params.dev_out_nak, int, 0444);
2074 MODULE_PARM_DESC(dev_out_nak, "Enable Device OUT NAK");
2075 module_param_named(cont_on_bna, dwc_otg_module_params.cont_on_bna, int, 0444);
2076 MODULE_PARM_DESC(cont_on_bna, "Enable Enable Continue on BNA");
2077 module_param_named(ahb_single, dwc_otg_module_params.ahb_single, int, 0444);
2078 MODULE_PARM_DESC(ahb_single, "Enable AHB Single Support");
2079 module_param_named(adp_enable, dwc_otg_module_params.adp_enable, int, 0444);
2080 MODULE_PARM_DESC(adp_enable, "ADP Enable 0=ADP Disabled 1=ADP Enabled");
2081 module_param_named(otg_ver, dwc_otg_module_params.otg_ver, int, 0444);
2082 MODULE_PARM_DESC(otg_ver, "OTG revision supported 0=OTG 1.3 1=OTG 2.0");
2084 /** @page "Module Parameters"
2086 * The following parameters may be specified when starting the module.
2087 * These parameters define how the DWC_otg controller should be
2088 * configured. Parameter values are passed to the CIL initialization
2089 * function dwc_otg_cil_init
2091 * Example: <code>modprobe dwc_otg speed=1 otg_cap=1</code>
2095 <tr><td>Parameter Name</td><td>Meaning</td></tr>
2099 <td>Specifies the OTG capabilities. The driver will automatically detect the
2100 value for this parameter if none is specified.
2101 - 0: HNP and SRP capable (default, if available)
2102 - 1: SRP Only capable
2103 - 2: No HNP/SRP capable
2108 <td>Specifies whether to use slave or DMA mode for accessing the data FIFOs.
2109 The driver will automatically detect the value for this parameter if none is
2112 - 1: DMA (default, if available)
2116 <td>dma_burst_size</td>
2117 <td>The DMA Burst size (applicable only for External DMA Mode).
2118 - Values: 1, 4, 8 16, 32, 64, 128, 256 (default 32)
2123 <td>Specifies the maximum speed of operation in host and device mode. The
2124 actual speed depends on the speed of the attached device and the value of
2126 - 0: High Speed (default)
2131 <td>host_support_fs_ls_low_power</td>
2132 <td>Specifies whether low power mode is supported when attached to a Full
2133 Speed or Low Speed device in host mode.
2134 - 0: Don't support low power mode (default)
2135 - 1: Support low power mode
2139 <td>host_ls_low_power_phy_clk</td>
2140 <td>Specifies the PHY clock rate in low power mode when connected to a Low
2141 Speed device in host mode. This parameter is applicable only if
2142 HOST_SUPPORT_FS_LS_LOW_POWER is enabled.
2143 - 0: 48 MHz (default)
2148 <td>enable_dynamic_fifo</td>
2149 <td> Specifies whether FIFOs may be resized by the driver software.
2150 - 0: Use cC FIFO size parameters
2151 - 1: Allow dynamic FIFO sizing (default)
2155 <td>data_fifo_size</td>
2156 <td>Total number of 4-byte words in the data FIFO memory. This memory
2157 includes the Rx FIFO, non-periodic Tx FIFO, and periodic Tx FIFOs.
2158 - Values: 32 to 32768 (default 8192)
2160 Note: The total FIFO memory depth in the FPGA configuration is 8192.
2164 <td>dev_rx_fifo_size</td>
2165 <td>Number of 4-byte words in the Rx FIFO in device mode when dynamic
2166 FIFO sizing is enabled.
2167 - Values: 16 to 32768 (default 1064)
2171 <td>dev_nperio_tx_fifo_size</td>
2172 <td>Number of 4-byte words in the non-periodic Tx FIFO in device mode when
2173 dynamic FIFO sizing is enabled.
2174 - Values: 16 to 32768 (default 1024)
2178 <td>dev_perio_tx_fifo_size_n (n = 1 to 15)</td>
2179 <td>Number of 4-byte words in each of the periodic Tx FIFOs in device mode
2180 when dynamic FIFO sizing is enabled.
2181 - Values: 4 to 768 (default 256)
2185 <td>host_rx_fifo_size</td>
2186 <td>Number of 4-byte words in the Rx FIFO in host mode when dynamic FIFO
2188 - Values: 16 to 32768 (default 1024)
2192 <td>host_nperio_tx_fifo_size</td>
2193 <td>Number of 4-byte words in the non-periodic Tx FIFO in host mode when
2194 dynamic FIFO sizing is enabled in the core.
2195 - Values: 16 to 32768 (default 1024)
2199 <td>host_perio_tx_fifo_size</td>
2200 <td>Number of 4-byte words in the host periodic Tx FIFO when dynamic FIFO
2202 - Values: 16 to 32768 (default 1024)
2206 <td>max_transfer_size</td>
2207 <td>The maximum transfer size supported in bytes.
2208 - Values: 2047 to 65,535 (default 65,535)
2212 <td>max_packet_count</td>
2213 <td>The maximum number of packets in a transfer.
2214 - Values: 15 to 511 (default 511)
2218 <td>host_channels</td>
2219 <td>The number of host channel registers to use.
2220 - Values: 1 to 16 (default 12)
2222 Note: The FPGA configuration supports a maximum of 12 host channels.
2226 <td>dev_endpoints</td>
2227 <td>The number of endpoints in addition to EP0 available for device mode
2229 - Values: 1 to 15 (default 6 IN and OUT)
2231 Note: The FPGA configuration supports a maximum of 6 IN and OUT endpoints in
2237 <td>Specifies the type of PHY interface to use. By default, the driver will
2238 automatically detect the phy_type.
2240 - 1: UTMI+ (default, if available)
2245 <td>phy_utmi_width</td>
2246 <td>Specifies the UTMI+ Data Width. This parameter is applicable for a
2247 phy_type of UTMI+. Also, this parameter is applicable only if the
2248 OTG_HSPHY_WIDTH cC parameter was set to "8 and 16 bits", meaning that the
2249 core has been configured to work at either data path width.
2250 - Values: 8 or 16 bits (default 16)
2254 <td>phy_ulpi_ddr</td>
2255 <td>Specifies whether the ULPI operates at double or single data rate. This
2256 parameter is only applicable if phy_type is ULPI.
2257 - 0: single data rate ULPI interface with 8 bit wide data bus (default)
2258 - 1: double data rate ULPI interface with 4 bit wide data bus
2263 <td>Specifies whether to use the I2C interface for full speed PHY. This
2264 parameter is only applicable if PHY_TYPE is FS.
2265 - 0: Disabled (default)
2271 <td>Specifies whether to use ULPI FS/LS mode only.
2272 - 0: Disabled (default)
2278 <td>Specifies whether term select D-Line pulsing for all PHYs is enabled.
2279 - 0: Disabled (default)
2284 <td>en_multiple_tx_fifo</td>
2285 <td>Specifies whether dedicatedto tx fifos are enabled for non periodic IN EPs.
2286 The driver will automatically detect the value for this parameter if none is
2289 - 1: Enabled (default, if available)
2293 <td>dev_tx_fifo_size_n (n = 1 to 15)</td>
2294 <td>Number of 4-byte words in each of the Tx FIFOs in device mode
2295 when dynamic FIFO sizing is enabled.
2296 - Values: 4 to 768 (default 256)
2300 <td>tx_thr_length</td>
2301 <td>Transmit Threshold length in 32 bit double words
2302 - Values: 8 to 128 (default 64)
2306 <td>rx_thr_length</td>
2307 <td>Receive Threshold length in 32 bit double words
2308 - Values: 8 to 128 (default 64)
2313 <td>Specifies whether to enable Thresholding for Device mode. Bits 0, 1, 2 of
2314 this parmater specifies if thresholding is enabled for non-Iso Tx, Iso Tx and
2315 Rx transfers accordingly.
2316 The driver will automatically detect the value for this parameter if none is
2318 - Values: 0 to 7 (default 0)
2319 Bit values indicate:
2320 - 0: Thresholding disabled
2321 - 1: Thresholding enabled
2325 <td>dma_desc_enable</td>
2326 <td>Specifies whether to enable Descriptor DMA mode.
2327 The driver will automatically detect the value for this parameter if none is
2329 - 0: Descriptor DMA disabled
2330 - 1: Descriptor DMA (default, if available)
2335 <td>Specifies whether to enable MPI enhancement mode.
2336 The driver will automatically detect the value for this parameter if none is
2338 - 0: MPI disabled (default)
2344 <td>Specifies whether to enable PTI enhancement support.
2345 The driver will automatically detect the value for this parameter if none is
2347 - 0: PTI disabled (default)
2353 <td>Specifies whether to enable LPM support.
2354 The driver will automatically detect the value for this parameter if none is
2357 - 1: LPM enable (default, if available)
2361 <td>besl_enable</td>
2362 <td>Specifies whether to enable LPM Errata support.
2363 The driver will automatically detect the value for this parameter if none is
2365 - 0: LPM Errata disabled (default)
2366 - 1: LPM Errata enable
2370 <td>baseline_besl</td>
2371 <td>Specifies the baseline besl value.
2372 - Values: 0 to 15 (default 0)
2377 <td>Specifies the deep besl value.
2378 - Values: 0 to 15 (default 15)
2383 <td>Specifies whether to enable IC_USB capability.
2384 The driver will automatically detect the value for this parameter if none is
2386 - 0: IC_USB disabled (default, if available)
2391 <td>ahb_thr_ratio</td>
2392 <td>Specifies AHB Threshold ratio.
2393 - Values: 0 to 3 (default 0)
2398 <td>Specifies Power Down(Hibernation) Mode.
2399 The driver will automatically detect the value for this parameter if none is
2401 - 0: Power Down disabled (default)
2402 - 2: Power Down enabled
2407 <td>Specifies whether dynamic reloading of the HFIR register is allowed during
2408 run time. The driver will automatically detect the value for this parameter if
2409 none is specified. In case the HFIR value is reloaded when HFIR.RldCtrl == 1'b0
2410 the core might misbehave.
2411 - 0: Reload Control disabled (default)
2412 - 1: Reload Control enabled
2416 <td>dev_out_nak</td>
2417 <td>Specifies whether Device OUT NAK enhancement enabled or no.
2418 The driver will automatically detect the value for this parameter if
2419 none is specified. This parameter is valid only when OTG_EN_DESC_DMA == 1
\92b1.
2420 - 0: The core does not set NAK after Bulk OUT transfer complete (default)
2421 - 1: The core sets NAK after Bulk OUT transfer complete
2425 <td>cont_on_bna</td>
2426 <td>Specifies whether Enable Continue on BNA enabled or no.
2427 After receiving BNA interrupt the core disables the endpoint,when the
2428 endpoint is re-enabled by the application the
2429 - 0: Core starts processing from the DOEPDMA descriptor (default)
2430 - 1: Core starts processing from the descriptor which received the BNA.
2431 This parameter is valid only when OTG_EN_DESC_DMA == 1
\92b1.
2436 <td>This bit when programmed supports SINGLE transfers for remainder data
2437 in a transfer for DMA mode of operation.
2438 - 0: The remainder data will be sent using INCR burst size (default)
2439 - 1: The remainder data will be sent using SINGLE burst size.
2444 <td>Specifies whether ADP feature is enabled.
2445 The driver will automatically detect the value for this parameter if none is
2447 - 0: ADP feature disabled (default)
2448 - 1: ADP feature enabled
2453 <td>Specifies whether OTG is performing as USB OTG Revision 2.0 or Revision 1.3
2455 - 0: OTG 2.0 support disabled (default)
2456 - 1: OTG 2.0 support enabled