1 /* ==========================================================================
2 * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_driver.c $
7 * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
8 * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
9 * otherwise expressly agreed to in writing between Synopsys and you.
11 * The Software IS NOT an item of Licensed Software or Licensed Product under
12 * any End User Software License Agreement or Agreement for Licensed Product
13 * with Synopsys or any supplement thereto. You are permitted to use and
14 * redistribute this Software in source and binary forms, with or without
15 * modification, provided that redistributions of source code must retain this
16 * notice. You may not view, use, disclose, copy or distribute this file or
17 * any information contained herein except pursuant to this license grant from
18 * Synopsys. If you do not agree with this notice, including the disclaimer
19 * below, then you are not authorized to use the Software.
21 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
25 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
26 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
27 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
28 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
32 * ========================================================================== */
35 * The dwc_otg_driver module provides the initialization and cleanup entry
36 * points for the DWC_otg driver. This module will be dynamically installed
37 * after Linux is booted using the insmod command. When the module is
38 * installed, the dwc_otg_driver_init function is called. When the module is
39 * removed (using rmmod), the dwc_otg_driver_cleanup function is called.
41 * This module also defines a data structure for the dwc_otg_driver, which is
42 * used in conjunction with the standard ARM lm_device structure. These
43 * structures allow the OTG driver to comply with the standard Linux driver
44 * model in which devices and drivers are registered with a bus driver. This
45 * has the benefit that Linux can expose attributes of the driver and device
46 * in its special sysfs file system. Users can then read or write files in
47 * this file system to perform diagnostics on the driver components or the
51 #include "dwc_otg_os_dep.h"
52 #include "common_port/dwc_os.h"
53 #include "dwc_otg_dbg.h"
54 #include "dwc_otg_driver.h"
55 #include "dwc_otg_attr.h"
56 #include "dwc_otg_core_if.h"
57 #include "dwc_otg_pcd_if.h"
58 #include "dwc_otg_hcd_if.h"
59 #include "dwc_otg_cil.h"
60 #include "dwc_otg_pcd.h"
62 #include "usbdev_rk.h"
64 #define DWC_DRIVER_VERSION "3.10a 21-DEC-2012"
65 #define DWC_DRIVER_DESC "HS OTG USB Controller driver"
67 static const char dwc_host20_driver_name[] = "usb20_host";
68 static const char dwc_otg20_driver_name[] = "usb20_otg";
70 dwc_otg_device_t *g_otgdev;
72 extern int pcd_init(struct platform_device *_dev);
73 extern int otg20_hcd_init(struct platform_device *_dev);
74 extern int host20_hcd_init(struct platform_device *_dev);
75 extern int pcd_remove(struct platform_device *_dev);
76 extern void hcd_remove(struct platform_device *_dev);
77 extern void dwc_otg_adp_start(dwc_otg_core_if_t *core_if, uint8_t is_host);
80 #ifdef CONFIG_RK_USB_UART
81 static u32 usb_to_uart_status;
83 /*-------------------------------------------------------------------------*/
84 /* Encapsulate the module parameter settings */
86 struct dwc_otg_driver_module_params {
90 int32_t dma_desc_enable;
91 int32_t dma_burst_size;
93 int32_t host_support_fs_ls_low_power;
94 int32_t host_ls_low_power_phy_clk;
95 int32_t enable_dynamic_fifo;
96 int32_t data_fifo_size;
97 int32_t dev_rx_fifo_size;
98 int32_t dev_nperio_tx_fifo_size;
99 uint32_t dev_perio_tx_fifo_size[MAX_PERIO_FIFOS];
100 int32_t host_rx_fifo_size;
101 int32_t host_nperio_tx_fifo_size;
102 int32_t host_perio_tx_fifo_size;
103 int32_t max_transfer_size;
104 int32_t max_packet_count;
105 int32_t host_channels;
106 int32_t dev_endpoints;
108 int32_t phy_utmi_width;
109 int32_t phy_ulpi_ddr;
110 int32_t phy_ulpi_ext_vbus;
114 int32_t en_multiple_tx_fifo;
115 uint32_t dev_tx_fifo_size[MAX_TX_FIFOS];
117 uint32_t tx_thr_length;
118 uint32_t rx_thr_length;
123 int32_t baseline_besl;
126 int32_t ahb_thr_ratio;
136 static struct dwc_otg_driver_module_params dwc_otg_module_params = {
138 .otg_cap = DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE,
140 .dma_desc_enable = 0,
141 .dma_burst_size = -1,
143 .host_support_fs_ls_low_power = -1,
144 .host_ls_low_power_phy_clk = -1,
145 .enable_dynamic_fifo = 1,
146 .data_fifo_size = -1,
147 .dev_rx_fifo_size = 0x120,
148 .dev_nperio_tx_fifo_size = 0x10,
149 .dev_perio_tx_fifo_size = {
150 /* dev_perio_tx_fifo_size_1 */
168 .host_rx_fifo_size = -1,
169 .host_nperio_tx_fifo_size = -1,
170 .host_perio_tx_fifo_size = -1,
171 .max_transfer_size = -1,
172 .max_packet_count = -1,
176 .phy_utmi_width = -1,
178 .phy_ulpi_ext_vbus = -1,
182 .en_multiple_tx_fifo = -1,
183 .dev_tx_fifo_size = {
184 /* dev_tx_fifo_size */
222 #ifdef CONFIG_USB20_HOST
223 static struct dwc_otg_driver_module_params dwc_host_module_params = {
225 .otg_cap = DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE,
227 .dma_desc_enable = 0,
228 .dma_burst_size = -1,
230 .host_support_fs_ls_low_power = -1,
231 .host_ls_low_power_phy_clk = -1,
232 .enable_dynamic_fifo = -1,
233 .data_fifo_size = -1,
234 .dev_rx_fifo_size = -1,
235 .dev_nperio_tx_fifo_size = -1,
236 .dev_perio_tx_fifo_size = {
237 /* dev_perio_tx_fifo_size_1 */
255 .host_rx_fifo_size = -1,
256 .host_nperio_tx_fifo_size = -1,
257 .host_perio_tx_fifo_size = -1,
258 .max_transfer_size = -1,
259 .max_packet_count = -1,
263 .phy_utmi_width = -1,
265 .phy_ulpi_ext_vbus = -1,
269 .en_multiple_tx_fifo = -1,
270 .dev_tx_fifo_size = {
271 /* dev_tx_fifo_size */
311 * This function shows the Driver Version.
313 static ssize_t version_show(struct device_driver *dev, char *buf)
315 return snprintf(buf, sizeof(DWC_DRIVER_VERSION) + 2, "%s\n",
319 static DRIVER_ATTR(version, S_IRUGO, version_show, NULL);
322 * Global Debug Level Mask.
324 uint32_t g_dbg_lvl = DBG_OFF; /* OFF */
327 * This function shows the driver Debug Level.
329 static ssize_t dbg_level_show(struct device_driver *drv, char *buf)
331 return sprintf(buf, "0x%0x\n", g_dbg_lvl);
335 * This function stores the driver Debug Level.
337 static ssize_t dbg_level_store(struct device_driver *drv, const char *buf,
340 g_dbg_lvl = simple_strtoul(buf, NULL, 16);
344 static DRIVER_ATTR(debuglevel, S_IRUGO | S_IWUSR, dbg_level_show,
347 extern void hcd_start(dwc_otg_core_if_t *core_if);
348 extern struct usb_hub *g_dwc_otg_root_hub20;
349 extern void dwc_otg_hub_disconnect_device(struct usb_hub *hub);
351 void dwc_otg_force_host(dwc_otg_core_if_t *core_if)
353 dwc_otg_device_t *otg_dev = core_if->otg_dev;
354 dctl_data_t dctl = {.d32 = 0 };
357 if (core_if->op_state == A_HOST) {
358 printk("dwc_otg_force_host,already in A_HOST mode,everest\n");
361 core_if->op_state = A_HOST;
363 cancel_delayed_work(&otg_dev->pcd->check_vbus_work);
364 dctl.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dctl);
365 dctl.b.sftdiscon = 1;
366 DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dctl, dctl.d32);
368 local_irq_save(flags);
369 cil_pcd_stop(core_if);
371 * Initialize the Core for Host mode.
374 dwc_otg_core_init(core_if);
375 dwc_otg_enable_global_interrupts(core_if);
376 cil_hcd_start(core_if);
377 local_irq_restore(flags);
380 void dwc_otg_force_device(dwc_otg_core_if_t *core_if)
382 dwc_otg_device_t *otg_dev = core_if->otg_dev;
385 local_irq_save(flags);
387 if (core_if->op_state == B_PERIPHERAL) {
389 ("dwc_otg_force_device,already in B_PERIPHERAL,everest\n");
392 core_if->op_state = B_PERIPHERAL;
393 cil_hcd_stop(core_if);
394 /* dwc_otg_hub_disconnect_device(g_dwc_otg_root_hub20); */
395 otg_dev->pcd->phy_suspend = 1;
396 otg_dev->pcd->vbus_status = 0;
397 dwc_otg_pcd_start_check_vbus_work(otg_dev->pcd);
399 /* Reset the Controller */
400 dwc_otg_core_reset(core_if);
402 dwc_otg_core_init(core_if);
403 dwc_otg_disable_global_interrupts(core_if);
404 cil_pcd_start(core_if);
406 local_irq_restore(flags);
409 static ssize_t force_usb_mode_show(struct device_driver *drv, char *buf)
411 dwc_otg_device_t *otg_dev = g_otgdev;
412 dwc_otg_core_if_t *core_if = otg_dev->core_if;
414 return sprintf(buf, "%d\n", core_if->usb_mode);
417 static ssize_t force_usb_mode_store(struct device_driver *drv, const char *buf,
420 int new_mode = simple_strtoul(buf, NULL, 16);
421 dwc_otg_device_t *otg_dev = g_otgdev;
422 dwc_otg_core_if_t *core_if;
423 struct dwc_otg_platform_data *pldata;
428 core_if = otg_dev->core_if;
429 pldata = otg_dev->pldata;
431 DWC_PRINTF("%s %d->%d\n", __func__, core_if->usb_mode, new_mode);
433 if (core_if->usb_mode == new_mode) {
437 if (pldata->phy_status == USB_PHY_SUSPEND) {
438 pldata->clock_enable(pldata, 1);
439 pldata->phy_suspend(pldata, USB_PHY_ENABLED);
443 case USB_MODE_FORCE_HOST:
444 if (USB_MODE_FORCE_DEVICE == core_if->usb_mode) {
446 core_if->usb_mode = new_mode;
447 dwc_otg_force_host(core_if);
448 } else if (USB_MODE_NORMAL == core_if->usb_mode) {
449 core_if->usb_mode = new_mode;
450 if (dwc_otg_is_host_mode(core_if))
451 dwc_otg_set_force_mode(core_if, new_mode);
453 dwc_otg_force_host(core_if);
457 case USB_MODE_FORCE_DEVICE:
458 if (USB_MODE_FORCE_HOST == core_if->usb_mode) {
459 core_if->usb_mode = new_mode;
460 dwc_otg_force_device(core_if);
461 } else if (USB_MODE_NORMAL == core_if->usb_mode) {
462 core_if->usb_mode = new_mode;
463 if (dwc_otg_is_device_mode(core_if))
464 dwc_otg_set_force_mode(core_if, new_mode);
466 dwc_otg_force_device(core_if);
470 case USB_MODE_NORMAL:
471 if (USB_MODE_FORCE_DEVICE == core_if->usb_mode) {
472 core_if->usb_mode = new_mode;
473 cancel_delayed_work(&otg_dev->pcd->check_vbus_work);
474 dwc_otg_set_force_mode(core_if, new_mode);
476 if (dwc_otg_is_host_mode(core_if)) {
477 dwc_otg_force_host(core_if);
479 dwc_otg_pcd_start_check_vbus_work(otg_dev->pcd);
481 } else if (USB_MODE_FORCE_HOST == core_if->usb_mode) {
482 core_if->usb_mode = new_mode;
483 dwc_otg_set_force_mode(core_if, new_mode);
485 if (dwc_otg_is_device_mode(core_if)) {
486 dwc_otg_force_device(core_if);
497 static DRIVER_ATTR(force_usb_mode, S_IRUGO | S_IWUSR, force_usb_mode_show,
498 force_usb_mode_store);
500 static ssize_t dwc_otg_conn_en_show(struct device_driver *_drv, char *_buf)
503 dwc_otg_device_t *otg_dev = g_otgdev;
504 dwc_otg_pcd_t *_pcd = otg_dev->pcd;
505 return sprintf(_buf, "%d\n", _pcd->conn_en);
509 static ssize_t dwc_otg_conn_en_store(struct device_driver *_drv,
510 const char *_buf, size_t _count)
512 int enable = simple_strtoul(_buf, NULL, 10);
513 dwc_otg_device_t *otg_dev = g_otgdev;
514 dwc_otg_pcd_t *_pcd = otg_dev->pcd;
515 DWC_PRINTF("%s %d->%d\n", __func__, _pcd->conn_en, enable);
517 _pcd->conn_en = enable;
521 static DRIVER_ATTR(dwc_otg_conn_en, S_IRUGO | S_IWUSR, dwc_otg_conn_en_show,
522 dwc_otg_conn_en_store);
524 /* used for product vbus power control, SDK not need.
525 * If dwc_otg is host mode, enable vbus power.
526 * If dwc_otg is device mode, disable vbus power.
527 * return 1 - host mode, 0 - device mode.
529 int dwc_otg_usb_state(void)
531 dwc_otg_device_t *otg_dev = g_otgdev;
534 /* op_state is A_HOST */
535 if (1 == otg_dev->core_if->op_state)
537 /* op_state is B_PERIPHERAL */
538 else if (4 == otg_dev->core_if->op_state)
543 DWC_WARN("g_otgdev is NULL, maybe otg probe is failed!\n");
547 EXPORT_SYMBOL(dwc_otg_usb_state);
549 static ssize_t dwc_otg_op_state_show(struct device_driver *_drv, char *_buf)
551 dwc_otg_device_t *otg_dev = g_otgdev;
554 return sprintf(_buf, "%d\n", otg_dev->core_if->op_state);
556 return sprintf(_buf, "%d\n", 0);
559 static DRIVER_ATTR(op_state, S_IRUGO, dwc_otg_op_state_show, NULL);
561 static ssize_t vbus_status_show(struct device_driver *_drv, char *_buf)
563 dwc_otg_device_t *otg_dev = g_otgdev;
564 dwc_otg_pcd_t *_pcd = otg_dev->pcd;
565 return sprintf(_buf, "%d\n", _pcd->vbus_status);
568 static DRIVER_ATTR(vbus_status, S_IRUGO, vbus_status_show, NULL);
571 * This function is called during module intialization
572 * to pass module parameters to the DWC_OTG CORE.
574 static int set_parameters(dwc_otg_core_if_t *core_if,
575 struct dwc_otg_driver_module_params module_params)
580 if (module_params.otg_cap != -1) {
582 dwc_otg_set_param_otg_cap(core_if, module_params.otg_cap);
584 if (module_params.dma_enable != -1) {
586 dwc_otg_set_param_dma_enable(core_if,
587 module_params.dma_enable);
589 if (module_params.dma_desc_enable != -1) {
591 dwc_otg_set_param_dma_desc_enable(core_if,
592 module_params.dma_desc_enable);
594 if (module_params.opt != -1) {
595 retval += dwc_otg_set_param_opt(core_if, module_params.opt);
597 if (module_params.dma_burst_size != -1) {
599 dwc_otg_set_param_dma_burst_size(core_if,
600 module_params.dma_burst_size);
602 if (module_params.host_support_fs_ls_low_power != -1) {
604 dwc_otg_set_param_host_support_fs_ls_low_power(core_if,
605 module_params.host_support_fs_ls_low_power);
607 if (module_params.enable_dynamic_fifo != -1) {
609 dwc_otg_set_param_enable_dynamic_fifo(core_if,
610 module_params.enable_dynamic_fifo);
612 if (module_params.data_fifo_size != -1) {
614 dwc_otg_set_param_data_fifo_size(core_if,
615 module_params.data_fifo_size);
617 if (module_params.dev_rx_fifo_size != -1) {
619 dwc_otg_set_param_dev_rx_fifo_size(core_if,
620 module_params.dev_rx_fifo_size);
622 if (module_params.dev_nperio_tx_fifo_size != -1) {
624 dwc_otg_set_param_dev_nperio_tx_fifo_size(core_if,
625 module_params.dev_nperio_tx_fifo_size);
627 if (module_params.host_rx_fifo_size != -1) {
629 dwc_otg_set_param_host_rx_fifo_size(core_if,
633 if (module_params.host_nperio_tx_fifo_size != -1) {
635 dwc_otg_set_param_host_nperio_tx_fifo_size(core_if,
636 module_params.host_nperio_tx_fifo_size);
638 if (module_params.host_perio_tx_fifo_size != -1) {
640 dwc_otg_set_param_host_perio_tx_fifo_size(core_if,
641 module_params.host_perio_tx_fifo_size);
643 if (module_params.max_transfer_size != -1) {
645 dwc_otg_set_param_max_transfer_size(core_if,
646 module_params.max_transfer_size);
648 if (module_params.max_packet_count != -1) {
650 dwc_otg_set_param_max_packet_count(core_if,
651 module_params.max_packet_count);
653 if (module_params.host_channels != -1) {
655 dwc_otg_set_param_host_channels(core_if,
656 module_params.host_channels);
658 if (module_params.dev_endpoints != -1) {
660 dwc_otg_set_param_dev_endpoints(core_if,
661 module_params.dev_endpoints);
663 if (module_params.phy_type != -1) {
665 dwc_otg_set_param_phy_type(core_if, module_params.phy_type);
667 if (module_params.speed != -1) {
668 retval += dwc_otg_set_param_speed(core_if, module_params.speed);
670 if (module_params.host_ls_low_power_phy_clk != -1) {
672 dwc_otg_set_param_host_ls_low_power_phy_clk(core_if,
673 module_params.host_ls_low_power_phy_clk);
675 if (module_params.phy_ulpi_ddr != -1) {
677 dwc_otg_set_param_phy_ulpi_ddr(core_if,
678 module_params.phy_ulpi_ddr);
680 if (module_params.phy_ulpi_ext_vbus != -1) {
682 dwc_otg_set_param_phy_ulpi_ext_vbus(core_if,
683 module_params.phy_ulpi_ext_vbus);
685 if (module_params.phy_utmi_width != -1) {
687 dwc_otg_set_param_phy_utmi_width(core_if,
688 module_params.phy_utmi_width);
690 if (module_params.ulpi_fs_ls != -1) {
692 dwc_otg_set_param_ulpi_fs_ls(core_if,
693 module_params.ulpi_fs_ls);
695 if (module_params.ts_dline != -1) {
697 dwc_otg_set_param_ts_dline(core_if, module_params.ts_dline);
699 if (module_params.i2c_enable != -1) {
701 dwc_otg_set_param_i2c_enable(core_if,
702 module_params.i2c_enable);
704 if (module_params.en_multiple_tx_fifo != -1) {
706 dwc_otg_set_param_en_multiple_tx_fifo(core_if,
707 module_params.en_multiple_tx_fifo);
709 for (i = 0; i < 15; i++) {
710 if (module_params.dev_perio_tx_fifo_size[i] != -1) {
712 dwc_otg_set_param_dev_perio_tx_fifo_size(core_if,
713 module_params.dev_perio_tx_fifo_size
718 for (i = 0; i < 15; i++) {
719 if (module_params.dev_tx_fifo_size[i] != -1) {
720 retval += dwc_otg_set_param_dev_tx_fifo_size(core_if,
721 module_params.dev_tx_fifo_size
725 if (module_params.thr_ctl != -1) {
727 dwc_otg_set_param_thr_ctl(core_if, module_params.thr_ctl);
729 if (module_params.mpi_enable != -1) {
731 dwc_otg_set_param_mpi_enable(core_if,
732 module_params.mpi_enable);
734 if (module_params.pti_enable != -1) {
736 dwc_otg_set_param_pti_enable(core_if,
737 module_params.pti_enable);
739 if (module_params.lpm_enable != -1) {
741 dwc_otg_set_param_lpm_enable(core_if,
742 module_params.lpm_enable);
744 if (module_params.besl_enable != -1) {
746 dwc_otg_set_param_besl_enable(core_if,
747 module_params.besl_enable);
749 if (module_params.baseline_besl != -1) {
751 dwc_otg_set_param_baseline_besl(core_if,
752 module_params.baseline_besl);
754 if (module_params.deep_besl != -1) {
756 dwc_otg_set_param_deep_besl(core_if,
757 module_params.deep_besl);
759 if (module_params.ic_usb_cap != -1) {
761 dwc_otg_set_param_ic_usb_cap(core_if,
762 module_params.ic_usb_cap);
764 if (module_params.tx_thr_length != -1) {
766 dwc_otg_set_param_tx_thr_length(core_if,
770 if (module_params.rx_thr_length != -1) {
772 dwc_otg_set_param_rx_thr_length(core_if,
773 module_params.rx_thr_length);
775 if (module_params.ahb_thr_ratio != -1) {
777 dwc_otg_set_param_ahb_thr_ratio(core_if,
781 if (module_params.power_down != -1) {
783 dwc_otg_set_param_power_down(core_if,
784 module_params.power_down);
786 if (module_params.reload_ctl != -1) {
788 dwc_otg_set_param_reload_ctl(core_if,
789 module_params.reload_ctl);
792 if (module_params.dev_out_nak != -1) {
794 dwc_otg_set_param_dev_out_nak(core_if,
795 module_params.dev_out_nak);
798 if (module_params.cont_on_bna != -1) {
800 dwc_otg_set_param_cont_on_bna(core_if,
801 module_params.cont_on_bna);
804 if (module_params.ahb_single != -1) {
806 dwc_otg_set_param_ahb_single(core_if,
807 module_params.ahb_single);
810 if (module_params.otg_ver != -1) {
812 dwc_otg_set_param_otg_ver(core_if, module_params.otg_ver);
814 if (module_params.adp_enable != -1) {
816 dwc_otg_set_param_adp_enable(core_if,
817 module_params.adp_enable);
823 * This function is the top level interrupt handler for the Common
824 * (Device and host modes) interrupts.
826 static irqreturn_t dwc_otg_common_irq(int irq, void *dev)
828 int32_t retval = IRQ_NONE;
830 retval = dwc_otg_handle_common_intr(dev);
832 /* S3C2410X_CLEAR_EINTPEND(); */
834 return IRQ_RETVAL(retval);
837 #ifdef CONFIG_USB20_HOST
839 * This function is called when a lm_device is unregistered with the
840 * dwc_otg_driver. This happens, for example, when the rmmod command is
841 * executed. The device may or may not be electrically present. If it is
842 * present, the driver stops device processing. Any resources used on behalf
843 * of this device are freed.
847 static int host20_driver_remove(struct platform_device *_dev)
850 dwc_otg_device_t *otg_dev = dwc_get_device_platform_data(_dev);
851 DWC_DEBUGPL(DBG_ANY, "%s(%p)\n", __func__, _dev);
854 /* Memory allocation for the dwc_otg_device failed. */
855 DWC_DEBUGPL(DBG_ANY, "%s: otg_dev NULL!\n", __func__);
858 #ifndef DWC_DEVICE_ONLY
862 DWC_DEBUGPL(DBG_ANY, "%s: otg_dev->hcd NULL!\n", __func__);
867 #ifndef DWC_HOST_ONLY
871 DWC_DEBUGPL(DBG_ANY, "%s: otg_dev->pcd NULL!\n", __func__);
879 if (otg_dev->common_irq_installed) {
880 /* free_irq(_dev->irq, otg_dev); */
881 free_irq(platform_get_irq(_dev, 0), otg_dev);
883 DWC_DEBUGPL(DBG_ANY, "%s: There is no installed irq!\n",
888 if (otg_dev->core_if) {
889 dwc_otg_cil_remove(otg_dev->core_if);
891 DWC_DEBUGPL(DBG_ANY, "%s: otg_dev->core_if NULL!\n", __func__);
896 * Remove the device attributes
898 dwc_otg_attr_remove(_dev);
903 if (otg_dev->os_dep.base) {
904 iounmap(otg_dev->os_dep.base);
909 * Clear the drvdata pointer.
912 dwc_set_device_platform_data(_dev, 0);
917 static const struct of_device_id usb20_host_of_match[] = {
919 .compatible = "rockchip,rk3188_usb20_host",
920 .data = &usb20host_pdata_rk3188,
923 .compatible = "rockchip,rk3288_usb20_host",
924 .data = &usb20host_pdata_rk3288,
927 .compatible = "rockchip,rk3036_usb20_host",
928 .data = &usb20host_pdata_rk3036,
931 .compatible = "rockchip,rk3126_usb20_host",
932 .data = &usb20host_pdata_rk3126,
937 MODULE_DEVICE_TABLE(of, usb20_host_of_match);
940 * This function is called when an lm_device is bound to a
941 * dwc_otg_driver. It creates the driver components required to
942 * control the device (CIL, HCD, and PCD) and it initializes the
943 * device. The driver components are stored in a dwc_otg_device
944 * structure. A reference to the dwc_otg_device is saved in the
945 * lm_device. This allows the driver to access the dwc_otg_device
946 * structure on subsequent calls to driver methods for this device.
948 * @param _dev Bus device
950 static int host20_driver_probe(struct platform_device *_dev)
954 struct resource *res_base;
955 dwc_otg_device_t *dwc_otg_device;
956 struct device *dev = &_dev->dev;
957 struct device_node *node = _dev->dev.of_node;
958 struct dwc_otg_platform_data *pldata;
959 const struct of_device_id *match =
960 of_match_device(of_match_ptr(usb20_host_of_match), &_dev->dev);
962 if (match && match->data) {
963 pldata = (void *)match->data;
966 dev_err(dev, "usb20otg match failed\n");
971 dev_err(dev, "device node not found\n");
978 if (pldata->clock_init) {
979 pldata->clock_init(pldata);
980 pldata->clock_enable(pldata, 1);
983 if (pldata->phy_suspend)
984 pldata->phy_suspend(pldata, USB_PHY_ENABLED);
986 if (pldata->soft_reset)
987 pldata->soft_reset(pldata, RST_POR);
989 res_base = platform_get_resource(_dev, IORESOURCE_MEM, 0);
991 dwc_otg_device = DWC_ALLOC(sizeof(dwc_otg_device_t));
993 if (!dwc_otg_device) {
994 dev_err(&_dev->dev, "kmalloc of dwc_otg_device failed\n");
999 memset(dwc_otg_device, 0, sizeof(*dwc_otg_device));
1000 dwc_otg_device->os_dep.reg_offset = 0xFFFFFFFF;
1003 * Map the DWC_otg Core memory into virtual address space.
1006 dwc_otg_device->os_dep.base = devm_ioremap_resource(dev, res_base);
1008 if (!dwc_otg_device->os_dep.base) {
1009 dev_err(&_dev->dev, "ioremap() failed\n");
1010 DWC_FREE(dwc_otg_device);
1014 dev_dbg(&_dev->dev, "base=0x%p\n", dwc_otg_device->os_dep.base);
1016 /* Set device flags indicating whether the HCD supports DMA. */
1017 if (!_dev->dev.dma_mask)
1018 _dev->dev.dma_mask = &_dev->dev.coherent_dma_mask;
1019 retval = dma_set_coherent_mask(&_dev->dev, DMA_BIT_MASK(32));
1024 * Initialize driver data to point to the global DWC_otg
1028 dwc_set_device_platform_data(_dev, dwc_otg_device);
1029 pldata->privdata = dwc_otg_device;
1030 dwc_otg_device->pldata = (void *)pldata;
1032 dev_dbg(&_dev->dev, "dwc_otg_device=0x%p\n", dwc_otg_device);
1034 dwc_otg_device->core_if = dwc_otg_cil_init(dwc_otg_device->os_dep.base);
1036 if (!dwc_otg_device->core_if) {
1037 dev_err(&_dev->dev, "CIL initialization failed!\n");
1042 dwc_otg_device->core_if->otg_dev = dwc_otg_device;
1045 * Attempt to ensure this device is really a DWC_otg Controller.
1046 * Read and verify the SNPSID register contents. The value should be
1047 * 0x45F42XXX or 0x45F42XXX, which corresponds to either "OT2" or "OTG3",
1048 * as in "OTG version 2.XX" or "OTG version 3.XX".
1051 if (((dwc_otg_get_gsnpsid(dwc_otg_device->core_if) & 0xFFFFF000) !=
1053 && ((dwc_otg_get_gsnpsid(dwc_otg_device->core_if) & 0xFFFFF000) !=
1055 dev_err(&_dev->dev, "Bad value for SNPSID: 0x%08x\n",
1056 dwc_otg_get_gsnpsid(dwc_otg_device->core_if));
1062 * Validate parameter values.
1064 if (set_parameters(dwc_otg_device->core_if, dwc_host_module_params)) {
1070 * Create Device Attributes in sysfs
1072 dwc_otg_attr_create(_dev);
1075 * Disable the global interrupt until all the interrupt
1076 * handlers are installed.
1078 dwc_otg_disable_global_interrupts(dwc_otg_device->core_if);
1081 * Install the interrupt handler for the common interrupts before
1082 * enabling common interrupts in core_init below.
1084 irq = platform_get_irq(_dev, 0);
1085 DWC_DEBUGPL(DBG_CIL, "registering (common) handler for irq%d\n", irq);
1086 retval = request_irq(irq, dwc_otg_common_irq,
1087 IRQF_SHARED, "dwc_otg", dwc_otg_device);
1089 DWC_ERROR("request of irq%d failed\n", irq);
1093 dwc_otg_device->common_irq_installed = 1;
1097 * Initialize the DWC_otg core.
1098 * In order to reduce the time of initialization,
1099 * we do core soft reset after connection detected.
1101 dwc_otg_core_init_no_reset(dwc_otg_device->core_if);
1104 * Initialize the HCD
1106 retval = host20_hcd_init(_dev);
1108 DWC_ERROR("hcd_init failed\n");
1109 dwc_otg_device->hcd = NULL;
1113 clk_set_rate(pldata->phyclk_480m, 480000000);
1115 * Enable the global interrupt after all the interrupt
1116 * handlers are installed if there is no ADP support else
1117 * perform initial actions required for Internal ADP logic.
1119 if (!dwc_otg_get_param_adp_enable(dwc_otg_device->core_if)) {
1120 if (pldata->phy_status == USB_PHY_ENABLED) {
1121 pldata->phy_suspend(pldata, USB_PHY_SUSPEND);
1123 pldata->clock_enable(pldata, 0);
1125 /* dwc_otg_enable_global_interrupts(dwc_otg_device->core_if); */
1127 dwc_otg_adp_start(dwc_otg_device->core_if,
1128 dwc_otg_is_host_mode(dwc_otg_device->
1134 host20_driver_remove(_dev);
1136 if (pldata->clock_enable)
1137 pldata->clock_enable(pldata, 0);
1143 static int dwc_otg_driver_suspend(struct platform_device *_dev,
1149 static int dwc_otg_driver_resume(struct platform_device *_dev)
1154 static void dwc_otg_driver_shutdown(struct platform_device *_dev)
1156 struct device *dev = &_dev->dev;
1157 dwc_otg_device_t *otg_dev = dev->platform_data;
1158 dwc_otg_core_if_t *core_if = otg_dev->core_if;
1159 struct dwc_otg_platform_data *pldata = otg_dev->pldata;
1160 dctl_data_t dctl = {.d32 = 0 };
1162 DWC_PRINTF("%s: disconnect USB %s mode\n", __func__,
1163 dwc_otg_is_host_mode(core_if) ? "host" : "device");
1165 if (pldata->dwc_otg_uart_mode != NULL)
1166 pldata->dwc_otg_uart_mode(pldata, PHY_USB_MODE);
1167 if (pldata->phy_suspend != NULL)
1168 pldata->phy_suspend(pldata, USB_PHY_ENABLED);
1169 if (dwc_otg_is_host_mode(core_if)) {
1170 if (core_if->hcd_cb && core_if->hcd_cb->stop)
1171 core_if->hcd_cb->stop(core_if->hcd_cb_p);
1173 /* soft disconnect */
1175 DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dctl);
1176 dctl.b.sftdiscon = 1;
1177 DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dctl,
1180 /* Clear any pending interrupts */
1181 DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, 0xFFFFFFFF);
1186 * This structure defines the methods to be called by a bus driver
1187 * during the lifecycle of a device on that bus. Both drivers and
1188 * devices are registered with a bus driver. The bus driver matches
1189 * devices to drivers based on information in the device and driver
1192 * The probe function is called when the bus driver matches a device
1193 * to this driver. The remove function is called when a device is
1194 * unregistered with the bus driver.
1196 #ifdef CONFIG_USB20_HOST
1197 static struct platform_driver dwc_host_driver = {
1199 .name = (char *)dwc_host20_driver_name,
1200 .of_match_table = of_match_ptr(usb20_host_of_match),
1202 .probe = host20_driver_probe,
1203 .remove = host20_driver_remove,
1204 .suspend = dwc_otg_driver_suspend,
1205 .resume = dwc_otg_driver_resume,
1209 #ifdef CONFIG_USB20_OTG
1211 * This function is called when a lm_device is unregistered with the
1212 * dwc_otg_driver. This happens, for example, when the rmmod command is
1213 * executed. The device may or may not be electrically present. If it is
1214 * present, the driver stops device processing. Any resources used on behalf
1215 * of this device are freed.
1219 static int otg20_driver_remove(struct platform_device *_dev)
1222 dwc_otg_device_t *otg_dev = dwc_get_device_platform_data(_dev);
1223 DWC_DEBUGPL(DBG_ANY, "%s(%p)\n", __func__, _dev);
1226 /* Memory allocation for the dwc_otg_device failed. */
1227 DWC_DEBUGPL(DBG_ANY, "%s: otg_dev NULL!\n", __func__);
1230 #ifndef DWC_DEVICE_ONLY
1234 DWC_DEBUGPL(DBG_ANY, "%s: otg_dev->hcd NULL!\n", __func__);
1239 #ifndef DWC_HOST_ONLY
1243 DWC_DEBUGPL(DBG_ANY, "%s: otg_dev->pcd NULL!\n", __func__);
1250 if (otg_dev->common_irq_installed) {
1251 /* free_irq(_dev->irq, otg_dev); */
1252 free_irq(platform_get_irq(_dev, 0), otg_dev);
1254 DWC_DEBUGPL(DBG_ANY, "%s: There is no installed irq!\n",
1259 if (otg_dev->core_if) {
1260 dwc_otg_cil_remove(otg_dev->core_if);
1262 DWC_DEBUGPL(DBG_ANY, "%s: otg_dev->core_if NULL!\n", __func__);
1267 * Remove the device attributes
1269 dwc_otg_attr_remove(_dev);
1272 * Return the memory.
1274 if (otg_dev->os_dep.base)
1275 iounmap(otg_dev->os_dep.base);
1279 * Clear the drvdata pointer.
1282 dwc_set_device_platform_data(_dev, 0);
1287 static const struct of_device_id usb20_otg_of_match[] = {
1289 .compatible = "rockchip,rk3188_usb20_otg",
1290 .data = &usb20otg_pdata_rk3188,
1293 .compatible = "rockchip,rk3288_usb20_otg",
1294 .data = &usb20otg_pdata_rk3288,
1297 .compatible = "rockchip,rk3036_usb20_otg",
1298 .data = &usb20otg_pdata_rk3036,
1301 .compatible = "rockchip,rk3126_usb20_otg",
1302 .data = &usb20otg_pdata_rk3126,
1305 .compatible = "rockchip,rk3368_usb20_otg",
1306 .data = &usb20otg_pdata_rk3368,
1311 MODULE_DEVICE_TABLE(of, usb20_otg_of_match);
1314 * This function is called when an lm_device is bound to a
1315 * dwc_otg_driver. It creates the driver components required to
1316 * control the device (CIL, HCD, and PCD) and it initializes the
1317 * device. The driver components are stored in a dwc_otg_device
1318 * structure. A reference to the dwc_otg_device is saved in the
1319 * lm_device. This allows the driver to access the dwc_otg_device
1320 * structure on subsequent calls to driver methods for this device.
1322 * @param _dev Bus device
1324 static int otg20_driver_probe(struct platform_device *_dev)
1329 struct resource *res_base;
1330 dwc_otg_device_t *dwc_otg_device;
1331 struct device *dev = &_dev->dev;
1332 struct device_node *node = _dev->dev.of_node;
1333 struct dwc_otg_platform_data *pldata;
1334 const struct of_device_id *match =
1335 of_match_device(of_match_ptr(usb20_otg_of_match), &_dev->dev);
1337 if (match && match->data) {
1338 pldata = (void *)match->data;
1341 dev_err(dev, "usb20otg match failed\n");
1346 dev_err(dev, "device node not found\n");
1350 if (pldata->hw_init)
1353 if (pldata->clock_init) {
1354 pldata->clock_init(pldata);
1355 pldata->clock_enable(pldata, 1);
1358 if (pldata->phy_suspend)
1359 pldata->phy_suspend(pldata, USB_PHY_ENABLED);
1361 if (pldata->dwc_otg_uart_mode)
1362 pldata->dwc_otg_uart_mode(pldata, PHY_USB_MODE);
1364 /* do reset later, because reset need about
1365 * 100ms to ensure otg id state change.
1368 if(pldata->soft_reset)
1369 pldata->soft_reset();
1373 res_base = platform_get_resource(_dev, IORESOURCE_MEM, 0);
1375 dwc_otg_device = DWC_ALLOC(sizeof(dwc_otg_device_t));
1377 if (!dwc_otg_device) {
1378 dev_err(&_dev->dev, "kmalloc of dwc_otg_device failed\n");
1383 memset(dwc_otg_device, 0, sizeof(*dwc_otg_device));
1384 dwc_otg_device->os_dep.reg_offset = 0xFFFFFFFF;
1387 * Map the DWC_otg Core memory into virtual address space.
1390 dwc_otg_device->os_dep.base = devm_ioremap_resource(dev, res_base);
1392 if (!dwc_otg_device->os_dep.base) {
1393 dev_err(&_dev->dev, "ioremap() failed\n");
1394 DWC_FREE(dwc_otg_device);
1398 dev_dbg(&_dev->dev, "base=0x%p\n", dwc_otg_device->os_dep.base);
1400 /* Set device flags indicating whether the HCD supports DMA. */
1401 if (!_dev->dev.dma_mask)
1402 _dev->dev.dma_mask = &_dev->dev.coherent_dma_mask;
1403 retval = dma_set_coherent_mask(&_dev->dev, DMA_BIT_MASK(32));
1408 * Initialize driver data to point to the global DWC_otg
1412 g_otgdev = dwc_otg_device;
1413 pldata->privdata = dwc_otg_device;
1414 dwc_otg_device->pldata = pldata;
1416 dwc_set_device_platform_data(_dev, dwc_otg_device);
1418 dev_dbg(&_dev->dev, "dwc_otg_device=0x%p\n", dwc_otg_device);
1420 dwc_otg_device->core_if = dwc_otg_cil_init(dwc_otg_device->os_dep.base);
1421 if (!dwc_otg_device->core_if) {
1422 dev_err(&_dev->dev, "CIL initialization failed!\n");
1427 dwc_otg_device->core_if->otg_dev = dwc_otg_device;
1429 * Attempt to ensure this device is really a DWC_otg Controller.
1430 * Read and verify the SNPSID register contents. The value should be
1431 * 0x45F42XXX or 0x45F42XXX, which corresponds to either "OT2" or "OTG3",
1432 * as in "OTG version 2.XX" or "OTG version 3.XX".
1435 if (((dwc_otg_get_gsnpsid(dwc_otg_device->core_if) & 0xFFFFF000) !=
1437 && ((dwc_otg_get_gsnpsid(dwc_otg_device->core_if) & 0xFFFFF000) !=
1439 dev_err(&_dev->dev, "Bad value for SNPSID: 0x%08x\n",
1440 dwc_otg_get_gsnpsid(dwc_otg_device->core_if));
1446 * Validate parameter values.
1448 if (set_parameters(dwc_otg_device->core_if, dwc_otg_module_params)) {
1454 * Create Device Attributes in sysfs
1456 dwc_otg_attr_create(_dev);
1459 * Disable the global interrupt until all the interrupt
1460 * handlers are installed.
1462 dwc_otg_disable_global_interrupts(dwc_otg_device->core_if);
1465 * Install the interrupt handler for the common interrupts before
1466 * enabling common interrupts in core_init below.
1468 irq = platform_get_irq(_dev, 0);
1469 DWC_DEBUGPL(DBG_CIL, "registering (common) handler for irq%d\n", irq);
1470 retval = request_irq(irq, dwc_otg_common_irq,
1471 IRQF_SHARED, "dwc_otg", dwc_otg_device);
1473 DWC_ERROR("request of irq%d failed\n", irq);
1477 dwc_otg_device->common_irq_installed = 1;
1481 * Initialize the DWC_otg core.
1482 * In order to reduce the time of initialization,
1483 * we do core soft reset after connection detected.
1485 dwc_otg_core_init_no_reset(dwc_otg_device->core_if);
1488 * 0 - USB_MODE_NORMAL
1489 * 1 - USB_MODE_FORCE_HOST
1490 * 2 - USB_MODE_FORCE_DEVICE
1492 of_property_read_u32(node, "rockchip,usb-mode", &val);
1493 dwc_otg_device->core_if->usb_mode = val;
1495 #ifndef DWC_HOST_ONLY
1497 * Initialize the PCD
1499 retval = pcd_init(_dev);
1501 DWC_ERROR("pcd_init failed\n");
1502 dwc_otg_device->pcd = NULL;
1506 #ifndef DWC_DEVICE_ONLY
1508 * Initialize the HCD
1510 retval = otg20_hcd_init(_dev);
1512 DWC_ERROR("hcd_init failed\n");
1513 dwc_otg_device->hcd = NULL;
1518 * Enable the global interrupt after all the interrupt
1519 * handlers are installed if there is no ADP support else
1520 * perform initial actions required for Internal ADP logic.
1522 if (!dwc_otg_get_param_adp_enable(dwc_otg_device->core_if)) {
1523 if (dwc_otg_device->core_if->usb_mode == USB_MODE_NORMAL &&
1524 pldata->phy_status == USB_PHY_ENABLED) {
1525 pldata->phy_suspend(pldata, USB_PHY_SUSPEND);
1527 pldata->clock_enable(pldata, 0);
1529 /* dwc_otg_enable_global_interrupts(dwc_otg_device->core_if); */
1531 dwc_otg_adp_start(dwc_otg_device->core_if,
1532 dwc_otg_is_host_mode(dwc_otg_device->
1538 otg20_driver_remove(_dev);
1541 if (pldata->clock_enable)
1542 pldata->clock_enable(pldata, 0);
1548 static int dwc_otg_pm_suspend(struct device *dev)
1550 dwc_otg_device_t *dwc_otg_device;
1551 struct dwc_otg_platform_data *pdata_otg;
1553 dwc_otg_device = dev_get_platdata(dev);
1555 dev_dbg(dev, "dwc_otg PM suspend\n");
1557 if (dwc_otg_device->core_if->op_state == B_PERIPHERAL)
1560 pdata_otg = dwc_otg_device->pldata;
1561 pdata_otg->phy_suspend(pdata_otg, USB_PHY_SUSPEND);
1566 static int dwc_otg_pm_resume(struct device *dev)
1568 dwc_otg_device_t *dwc_otg_device;
1569 struct dwc_otg_platform_data *pdata_otg;
1571 dwc_otg_device = dev_get_platdata(dev);
1573 dev_dbg(dev, "dwc_otg PM resume\n");
1575 if (dwc_otg_device->core_if->op_state == B_PERIPHERAL)
1578 pdata_otg = dwc_otg_device->pldata;
1579 pdata_otg->phy_suspend(pdata_otg, USB_PHY_ENABLED);
1584 #define dwc_otg_pm_suspend NULL
1585 #define dwc_otg_pm_resume NULL
1588 static const struct dev_pm_ops dwc_otg_dev_pm_ops = {
1589 .suspend = dwc_otg_pm_suspend,
1590 .resume = dwc_otg_pm_resume,
1593 static struct platform_driver dwc_otg_driver = {
1595 .name = (char *)dwc_otg20_driver_name,
1596 .of_match_table = of_match_ptr(usb20_otg_of_match),
1598 .pm = &dwc_otg_dev_pm_ops,
1601 .probe = otg20_driver_probe,
1602 .remove = otg20_driver_remove,
1603 .suspend = dwc_otg_driver_suspend,
1604 .resume = dwc_otg_driver_resume,
1605 .shutdown = dwc_otg_driver_shutdown,
1609 void rk_usb_power_up(void)
1611 struct dwc_otg_platform_data *pldata_otg;
1612 struct dwc_otg_platform_data *pldata_host;
1613 struct rkehci_platform_data *pldata_ehci;
1615 if (cpu_is_rk3288()) {
1616 #ifdef CONFIG_RK_USB_UART
1617 /* enable USB bypass UART function */
1618 writel_relaxed(0x00c00000 | usb_to_uart_status,
1619 RK_GRF_VIRT + RK3288_GRF_UOC0_CON3);
1622 /* unset siddq,the analog blocks are powered up */
1623 #ifdef CONFIG_USB20_OTG
1624 pldata_otg = &usb20otg_pdata_rk3288;
1626 if (pldata_otg->phy_status == USB_PHY_SUSPEND)
1627 writel_relaxed((0x01 << 13) << 16,
1629 RK3288_GRF_UOC0_CON0);
1632 #ifdef CONFIG_USB20_HOST
1633 pldata_host = &usb20host_pdata_rk3288;
1635 if (pldata_host->phy_status == USB_PHY_SUSPEND)
1636 writel_relaxed((0x01 << 13) << 16,
1638 RK3288_GRF_UOC2_CON0);
1641 #ifdef CONFIG_USB_EHCI_RK
1642 pldata_ehci = &rkehci_pdata_rk3288;
1644 if (pldata_ehci->phy_status == USB_PHY_SUSPEND)
1645 writel_relaxed((0x01 << 13) << 16,
1647 RK3288_GRF_UOC1_CON0);
1652 dwc_otg_device_t *otg_dev = g_otgdev;
1657 pldata_otg = otg_dev->pldata;
1658 if (pldata_otg && pldata_otg->phy_power_down)
1659 pldata_otg->phy_power_down(PHY_POWER_UP);
1663 void rk_usb_power_down(void)
1665 struct dwc_otg_platform_data *pldata_otg;
1666 struct dwc_otg_platform_data *pldata_host;
1667 struct rkehci_platform_data *pldata_ehci;
1669 if (cpu_is_rk3288()) {
1670 #ifdef CONFIG_RK_USB_UART
1671 /* disable USB bypass UART function */
1672 usb_to_uart_status =
1673 readl_relaxed(RK_GRF_VIRT + RK3288_GRF_UOC0_CON3);
1674 writel_relaxed(0x00c00000, RK_GRF_VIRT + RK3288_GRF_UOC0_CON3);
1676 /* set siddq,the analog blocks are powered down
1678 * 1. Before asserting SIDDQ, ensure that VDATSRCENB0,
1679 * VDATDETENB0, DCDENB0, BYPASSSEL0, ADPPRBENB0,
1680 * and TESTBURNIN are set to 1'b0.
1681 * 2. Before asserting SIDDQ, ensure that phy enter suspend.*/
1682 #ifdef CONFIG_USB20_OTG
1683 pldata_otg = &usb20otg_pdata_rk3288;
1685 if (pldata_otg->phy_status == USB_PHY_SUSPEND)
1686 writel_relaxed((0x01 << 13) |
1687 ((0x01 << 13) << 16),
1689 RK3288_GRF_UOC0_CON0);
1692 #ifdef CONFIG_USB20_HOST
1693 pldata_host = &usb20host_pdata_rk3288;
1695 if (pldata_host->phy_status == USB_PHY_SUSPEND)
1696 writel_relaxed((0x01 << 13) |
1697 ((0x01 << 13) << 16),
1699 RK3288_GRF_UOC2_CON0);
1702 #ifdef CONFIG_USB_EHCI_RK
1703 pldata_ehci = &rkehci_pdata_rk3288;
1705 if (pldata_ehci->phy_status == USB_PHY_SUSPEND)
1706 writel_relaxed((0x01 << 13) |
1707 ((0x01 << 13) << 16),
1709 RK3288_GRF_UOC1_CON0);
1713 dwc_otg_device_t *otg_dev = g_otgdev;
1718 pldata_otg = otg_dev->pldata;
1719 if (pldata_otg && pldata_otg->phy_power_down)
1720 pldata_otg->phy_power_down(PHY_POWER_DOWN);
1724 EXPORT_SYMBOL(rk_usb_power_up);
1725 EXPORT_SYMBOL(rk_usb_power_down);
1727 * This function is called when the dwc_otg_driver is installed with the
1728 * insmod command. It registers the dwc_otg_driver structure with the
1729 * appropriate bus driver. This will cause the dwc_otg_driver_probe function
1730 * to be called. In addition, the bus driver will automatically expose
1731 * attributes defined for the device and driver in the special sysfs file
1736 static int __init dwc_otg_driver_init(void)
1741 #ifdef CONFIG_USB20_OTG
1742 /* register otg20 */
1743 printk(KERN_INFO "%s: version %s\n", dwc_otg20_driver_name,
1744 DWC_DRIVER_VERSION);
1746 retval = platform_driver_register(&dwc_otg_driver);
1748 printk(KERN_ERR "%s retval=%d\n", __func__, retval);
1753 driver_create_file(&dwc_otg_driver.driver, &driver_attr_version);
1755 driver_create_file(&dwc_otg_driver.driver, &driver_attr_debuglevel);
1757 driver_create_file(&dwc_otg_driver.driver,
1758 &driver_attr_dwc_otg_conn_en);
1760 driver_create_file(&dwc_otg_driver.driver,
1761 &driver_attr_vbus_status);
1763 driver_create_file(&dwc_otg_driver.driver,
1764 &driver_attr_force_usb_mode);
1766 driver_create_file(&dwc_otg_driver.driver,
1767 &driver_attr_op_state);
1771 /* register host20 */
1772 #ifdef CONFIG_USB20_HOST
1773 printk(KERN_INFO "%s: version %s\n", dwc_host20_driver_name,
1774 DWC_DRIVER_VERSION);
1776 retval = platform_driver_register(&dwc_host_driver);
1778 printk(KERN_ERR "%s retval=%d\n", __func__, retval);
1783 driver_create_file(&dwc_host_driver.driver, &driver_attr_version);
1785 driver_create_file(&dwc_host_driver.driver,
1786 &driver_attr_debuglevel);
1791 module_init(dwc_otg_driver_init);
1794 * This function is called when the driver is removed from the kernel
1795 * with the rmmod command. The driver unregisters itself with its bus
1799 static void __exit dwc_otg_driver_cleanup(void)
1801 printk(KERN_DEBUG "dwc_otg_driver_cleanup()\n");
1803 #ifdef CONFIG_USB20_HOST
1805 driver_remove_file(&dwc_host_driver.driver, &driver_attr_debuglevel);
1806 driver_remove_file(&dwc_host_driver.driver, &driver_attr_version);
1807 platform_driver_unregister(&dwc_host_driver);
1808 printk(KERN_INFO "%s module removed\n", dwc_host20_driver_name);
1811 #ifdef CONFIG_USB20_OTG
1813 driver_remove_file(&dwc_otg_driver.driver,
1814 &driver_attr_dwc_otg_conn_en);
1815 driver_remove_file(&dwc_otg_driver.driver, &driver_attr_debuglevel);
1816 driver_remove_file(&dwc_otg_driver.driver, &driver_attr_version);
1817 driver_remove_file(&dwc_otg_driver.driver, &driver_attr_vbus_status);
1818 driver_remove_file(&dwc_otg_driver.driver, &driver_attr_force_usb_mode);
1819 driver_remove_file(&dwc_otg_driver.driver, &driver_attr_op_state);
1820 platform_driver_unregister(&dwc_otg_driver);
1821 printk(KERN_INFO "%s module removed\n", dwc_otg20_driver_name);
1825 module_exit(dwc_otg_driver_cleanup);
1827 MODULE_DESCRIPTION(DWC_DRIVER_DESC);
1828 MODULE_AUTHOR("Synopsys Inc.");
1829 MODULE_LICENSE("GPL");
1831 module_param_named(otg_cap, dwc_otg_module_params.otg_cap, int, 0444);
1832 MODULE_PARM_DESC(otg_cap, "OTG Capabilities 0=HNP&SRP 1=SRP Only 2=None");
1833 module_param_named(opt, dwc_otg_module_params.opt, int, 0444);
1834 MODULE_PARM_DESC(opt, "OPT Mode");
1835 module_param_named(dma_enable, dwc_otg_module_params.dma_enable, int, 0444);
1836 MODULE_PARM_DESC(dma_enable, "DMA Mode 0=Slave 1=DMA enabled");
1838 module_param_named(dma_desc_enable, dwc_otg_module_params.dma_desc_enable, int,
1840 MODULE_PARM_DESC(dma_desc_enable,
1841 "DMA Desc Mode 0=Address DMA 1=DMA Descriptor enabled");
1843 module_param_named(dma_burst_size, dwc_otg_module_params.dma_burst_size, int,
1845 MODULE_PARM_DESC(dma_burst_size,
1846 "DMA Burst Size 1, 4, 8, 16, 32, 64, 128, 256");
1847 module_param_named(speed, dwc_otg_module_params.speed, int, 0444);
1848 MODULE_PARM_DESC(speed, "Speed 0=High Speed 1=Full Speed");
1849 module_param_named(host_support_fs_ls_low_power,
1850 dwc_otg_module_params.host_support_fs_ls_low_power, int,
1852 MODULE_PARM_DESC(host_support_fs_ls_low_power,
1853 "Support Low Power w/FS or LS 0=Support 1=Don't Support");
1854 module_param_named(host_ls_low_power_phy_clk,
1855 dwc_otg_module_params.host_ls_low_power_phy_clk, int, 0444);
1856 MODULE_PARM_DESC(host_ls_low_power_phy_clk,
1857 "Low Speed Low Power Clock 0=48Mhz 1=6Mhz");
1858 module_param_named(enable_dynamic_fifo,
1859 dwc_otg_module_params.enable_dynamic_fifo, int, 0444);
1860 MODULE_PARM_DESC(enable_dynamic_fifo, "0=cC Setting 1=Allow Dynamic Sizing");
1861 module_param_named(data_fifo_size, dwc_otg_module_params.data_fifo_size, int,
1863 MODULE_PARM_DESC(data_fifo_size,
1864 "Total number of words in the data FIFO memory 32-32768");
1865 module_param_named(dev_rx_fifo_size, dwc_otg_module_params.dev_rx_fifo_size,
1867 MODULE_PARM_DESC(dev_rx_fifo_size, "Number of words in the Rx FIFO 16-32768");
1868 module_param_named(dev_nperio_tx_fifo_size,
1869 dwc_otg_module_params.dev_nperio_tx_fifo_size, int, 0444);
1870 MODULE_PARM_DESC(dev_nperio_tx_fifo_size,
1871 "Number of words in the non-periodic Tx FIFO 16-32768");
1872 module_param_named(dev_perio_tx_fifo_size_1,
1873 dwc_otg_module_params.dev_perio_tx_fifo_size[0], int, 0444);
1874 MODULE_PARM_DESC(dev_perio_tx_fifo_size_1,
1875 "Number of words in the periodic Tx FIFO 4-768");
1876 module_param_named(dev_perio_tx_fifo_size_2,
1877 dwc_otg_module_params.dev_perio_tx_fifo_size[1], int, 0444);
1878 MODULE_PARM_DESC(dev_perio_tx_fifo_size_2,
1879 "Number of words in the periodic Tx FIFO 4-768");
1880 module_param_named(dev_perio_tx_fifo_size_3,
1881 dwc_otg_module_params.dev_perio_tx_fifo_size[2], int, 0444);
1882 MODULE_PARM_DESC(dev_perio_tx_fifo_size_3,
1883 "Number of words in the periodic Tx FIFO 4-768");
1884 module_param_named(dev_perio_tx_fifo_size_4,
1885 dwc_otg_module_params.dev_perio_tx_fifo_size[3], int, 0444);
1886 MODULE_PARM_DESC(dev_perio_tx_fifo_size_4,
1887 "Number of words in the periodic Tx FIFO 4-768");
1888 module_param_named(dev_perio_tx_fifo_size_5,
1889 dwc_otg_module_params.dev_perio_tx_fifo_size[4], int, 0444);
1890 MODULE_PARM_DESC(dev_perio_tx_fifo_size_5,
1891 "Number of words in the periodic Tx FIFO 4-768");
1892 module_param_named(dev_perio_tx_fifo_size_6,
1893 dwc_otg_module_params.dev_perio_tx_fifo_size[5], int, 0444);
1894 MODULE_PARM_DESC(dev_perio_tx_fifo_size_6,
1895 "Number of words in the periodic Tx FIFO 4-768");
1896 module_param_named(dev_perio_tx_fifo_size_7,
1897 dwc_otg_module_params.dev_perio_tx_fifo_size[6], int, 0444);
1898 MODULE_PARM_DESC(dev_perio_tx_fifo_size_7,
1899 "Number of words in the periodic Tx FIFO 4-768");
1900 module_param_named(dev_perio_tx_fifo_size_8,
1901 dwc_otg_module_params.dev_perio_tx_fifo_size[7], int, 0444);
1902 MODULE_PARM_DESC(dev_perio_tx_fifo_size_8,
1903 "Number of words in the periodic Tx FIFO 4-768");
1904 module_param_named(dev_perio_tx_fifo_size_9,
1905 dwc_otg_module_params.dev_perio_tx_fifo_size[8], int, 0444);
1906 MODULE_PARM_DESC(dev_perio_tx_fifo_size_9,
1907 "Number of words in the periodic Tx FIFO 4-768");
1908 module_param_named(dev_perio_tx_fifo_size_10,
1909 dwc_otg_module_params.dev_perio_tx_fifo_size[9], int, 0444);
1910 MODULE_PARM_DESC(dev_perio_tx_fifo_size_10,
1911 "Number of words in the periodic Tx FIFO 4-768");
1912 module_param_named(dev_perio_tx_fifo_size_11,
1913 dwc_otg_module_params.dev_perio_tx_fifo_size[10], int, 0444);
1914 MODULE_PARM_DESC(dev_perio_tx_fifo_size_11,
1915 "Number of words in the periodic Tx FIFO 4-768");
1916 module_param_named(dev_perio_tx_fifo_size_12,
1917 dwc_otg_module_params.dev_perio_tx_fifo_size[11], int, 0444);
1918 MODULE_PARM_DESC(dev_perio_tx_fifo_size_12,
1919 "Number of words in the periodic Tx FIFO 4-768");
1920 module_param_named(dev_perio_tx_fifo_size_13,
1921 dwc_otg_module_params.dev_perio_tx_fifo_size[12], int, 0444);
1922 MODULE_PARM_DESC(dev_perio_tx_fifo_size_13,
1923 "Number of words in the periodic Tx FIFO 4-768");
1924 module_param_named(dev_perio_tx_fifo_size_14,
1925 dwc_otg_module_params.dev_perio_tx_fifo_size[13], int, 0444);
1926 MODULE_PARM_DESC(dev_perio_tx_fifo_size_14,
1927 "Number of words in the periodic Tx FIFO 4-768");
1928 module_param_named(dev_perio_tx_fifo_size_15,
1929 dwc_otg_module_params.dev_perio_tx_fifo_size[14], int, 0444);
1930 MODULE_PARM_DESC(dev_perio_tx_fifo_size_15,
1931 "Number of words in the periodic Tx FIFO 4-768");
1932 module_param_named(host_rx_fifo_size, dwc_otg_module_params.host_rx_fifo_size,
1934 MODULE_PARM_DESC(host_rx_fifo_size, "Number of words in the Rx FIFO 16-32768");
1935 module_param_named(host_nperio_tx_fifo_size,
1936 dwc_otg_module_params.host_nperio_tx_fifo_size, int, 0444);
1937 MODULE_PARM_DESC(host_nperio_tx_fifo_size,
1938 "Number of words in the non-periodic Tx FIFO 16-32768");
1939 module_param_named(host_perio_tx_fifo_size,
1940 dwc_otg_module_params.host_perio_tx_fifo_size, int, 0444);
1941 MODULE_PARM_DESC(host_perio_tx_fifo_size,
1942 "Number of words in the host periodic Tx FIFO 16-32768");
1943 module_param_named(max_transfer_size, dwc_otg_module_params.max_transfer_size,
1945 /** @todo Set the max to 512K, modify checks */
1946 MODULE_PARM_DESC(max_transfer_size,
1947 "The maximum transfer size supported in bytes 2047-65535");
1948 module_param_named(max_packet_count, dwc_otg_module_params.max_packet_count,
1950 MODULE_PARM_DESC(max_packet_count,
1951 "The maximum number of packets in a transfer 15-511");
1952 module_param_named(host_channels, dwc_otg_module_params.host_channels, int,
1954 MODULE_PARM_DESC(host_channels,
1955 "The number of host channel registers to use 1-16");
1956 module_param_named(dev_endpoints, dwc_otg_module_params.dev_endpoints, int,
1958 MODULE_PARM_DESC(dev_endpoints,
1959 "The number of endpoints in addition to EP0 available for device mode 1-15");
1960 module_param_named(phy_type, dwc_otg_module_params.phy_type, int, 0444);
1961 MODULE_PARM_DESC(phy_type, "0=Reserved 1=UTMI+ 2=ULPI");
1962 module_param_named(phy_utmi_width, dwc_otg_module_params.phy_utmi_width, int,
1964 MODULE_PARM_DESC(phy_utmi_width, "Specifies the UTMI+ Data Width 8 or 16 bits");
1965 module_param_named(phy_ulpi_ddr, dwc_otg_module_params.phy_ulpi_ddr, int, 0444);
1966 MODULE_PARM_DESC(phy_ulpi_ddr,
1967 "ULPI at double or single data rate 0=Single 1=Double");
1968 module_param_named(phy_ulpi_ext_vbus, dwc_otg_module_params.phy_ulpi_ext_vbus,
1970 MODULE_PARM_DESC(phy_ulpi_ext_vbus,
1971 "ULPI PHY using internal or external vbus 0=Internal");
1972 module_param_named(i2c_enable, dwc_otg_module_params.i2c_enable, int, 0444);
1973 MODULE_PARM_DESC(i2c_enable, "FS PHY Interface");
1974 module_param_named(ulpi_fs_ls, dwc_otg_module_params.ulpi_fs_ls, int, 0444);
1975 MODULE_PARM_DESC(ulpi_fs_ls, "ULPI PHY FS/LS mode only");
1976 module_param_named(ts_dline, dwc_otg_module_params.ts_dline, int, 0444);
1977 MODULE_PARM_DESC(ts_dline, "Term select Dline pulsing for all PHYs");
1978 module_param_named(debug, g_dbg_lvl, int, 0444);
1979 MODULE_PARM_DESC(debug, "");
1981 module_param_named(en_multiple_tx_fifo,
1982 dwc_otg_module_params.en_multiple_tx_fifo, int, 0444);
1983 MODULE_PARM_DESC(en_multiple_tx_fifo,
1984 "Dedicated Non Periodic Tx FIFOs 0=disabled 1=enabled");
1985 module_param_named(dev_tx_fifo_size_1,
1986 dwc_otg_module_params.dev_tx_fifo_size[0], int, 0444);
1987 MODULE_PARM_DESC(dev_tx_fifo_size_1, "Number of words in the Tx FIFO 4-768");
1988 module_param_named(dev_tx_fifo_size_2,
1989 dwc_otg_module_params.dev_tx_fifo_size[1], int, 0444);
1990 MODULE_PARM_DESC(dev_tx_fifo_size_2, "Number of words in the Tx FIFO 4-768");
1991 module_param_named(dev_tx_fifo_size_3,
1992 dwc_otg_module_params.dev_tx_fifo_size[2], int, 0444);
1993 MODULE_PARM_DESC(dev_tx_fifo_size_3, "Number of words in the Tx FIFO 4-768");
1994 module_param_named(dev_tx_fifo_size_4,
1995 dwc_otg_module_params.dev_tx_fifo_size[3], int, 0444);
1996 MODULE_PARM_DESC(dev_tx_fifo_size_4, "Number of words in the Tx FIFO 4-768");
1997 module_param_named(dev_tx_fifo_size_5,
1998 dwc_otg_module_params.dev_tx_fifo_size[4], int, 0444);
1999 MODULE_PARM_DESC(dev_tx_fifo_size_5, "Number of words in the Tx FIFO 4-768");
2000 module_param_named(dev_tx_fifo_size_6,
2001 dwc_otg_module_params.dev_tx_fifo_size[5], int, 0444);
2002 MODULE_PARM_DESC(dev_tx_fifo_size_6, "Number of words in the Tx FIFO 4-768");
2003 module_param_named(dev_tx_fifo_size_7,
2004 dwc_otg_module_params.dev_tx_fifo_size[6], int, 0444);
2005 MODULE_PARM_DESC(dev_tx_fifo_size_7, "Number of words in the Tx FIFO 4-768");
2006 module_param_named(dev_tx_fifo_size_8,
2007 dwc_otg_module_params.dev_tx_fifo_size[7], int, 0444);
2008 MODULE_PARM_DESC(dev_tx_fifo_size_8, "Number of words in the Tx FIFO 4-768");
2009 module_param_named(dev_tx_fifo_size_9,
2010 dwc_otg_module_params.dev_tx_fifo_size[8], int, 0444);
2011 MODULE_PARM_DESC(dev_tx_fifo_size_9, "Number of words in the Tx FIFO 4-768");
2012 module_param_named(dev_tx_fifo_size_10,
2013 dwc_otg_module_params.dev_tx_fifo_size[9], int, 0444);
2014 MODULE_PARM_DESC(dev_tx_fifo_size_10, "Number of words in the Tx FIFO 4-768");
2015 module_param_named(dev_tx_fifo_size_11,
2016 dwc_otg_module_params.dev_tx_fifo_size[10], int, 0444);
2017 MODULE_PARM_DESC(dev_tx_fifo_size_11, "Number of words in the Tx FIFO 4-768");
2018 module_param_named(dev_tx_fifo_size_12,
2019 dwc_otg_module_params.dev_tx_fifo_size[11], int, 0444);
2020 MODULE_PARM_DESC(dev_tx_fifo_size_12, "Number of words in the Tx FIFO 4-768");
2021 module_param_named(dev_tx_fifo_size_13,
2022 dwc_otg_module_params.dev_tx_fifo_size[12], int, 0444);
2023 MODULE_PARM_DESC(dev_tx_fifo_size_13, "Number of words in the Tx FIFO 4-768");
2024 module_param_named(dev_tx_fifo_size_14,
2025 dwc_otg_module_params.dev_tx_fifo_size[13], int, 0444);
2026 MODULE_PARM_DESC(dev_tx_fifo_size_14, "Number of words in the Tx FIFO 4-768");
2027 module_param_named(dev_tx_fifo_size_15,
2028 dwc_otg_module_params.dev_tx_fifo_size[14], int, 0444);
2029 MODULE_PARM_DESC(dev_tx_fifo_size_15, "Number of words in the Tx FIFO 4-768");
2031 module_param_named(thr_ctl, dwc_otg_module_params.thr_ctl, int, 0444);
2032 MODULE_PARM_DESC(thr_ctl,
2033 "Thresholding enable flag bit 0 - non ISO Tx thr., 1 - ISO Tx thr., 2 - Rx thr.- bit 0=disabled 1=enabled");
2034 module_param_named(tx_thr_length, dwc_otg_module_params.tx_thr_length, int,
2036 MODULE_PARM_DESC(tx_thr_length, "Tx Threshold length in 32 bit DWORDs");
2037 module_param_named(rx_thr_length, dwc_otg_module_params.rx_thr_length, int,
2039 MODULE_PARM_DESC(rx_thr_length, "Rx Threshold length in 32 bit DWORDs");
2041 module_param_named(pti_enable, dwc_otg_module_params.pti_enable, int, 0444);
2042 module_param_named(mpi_enable, dwc_otg_module_params.mpi_enable, int, 0444);
2043 module_param_named(lpm_enable, dwc_otg_module_params.lpm_enable, int, 0444);
2044 MODULE_PARM_DESC(lpm_enable, "LPM Enable 0=LPM Disabled 1=LPM Enabled");
2046 module_param_named(besl_enable, dwc_otg_module_params.besl_enable, int, 0444);
2047 MODULE_PARM_DESC(besl_enable, "BESL Enable 0=BESL Disabled 1=BESL Enabled");
2048 module_param_named(baseline_besl, dwc_otg_module_params.baseline_besl, int,
2050 MODULE_PARM_DESC(baseline_besl, "Set the baseline besl value");
2051 module_param_named(deep_besl, dwc_otg_module_params.deep_besl, int, 0444);
2052 MODULE_PARM_DESC(deep_besl, "Set the deep besl value");
2054 module_param_named(ic_usb_cap, dwc_otg_module_params.ic_usb_cap, int, 0444);
2055 MODULE_PARM_DESC(ic_usb_cap,
2056 "IC_USB Capability 0=IC_USB Disabled 1=IC_USB Enabled");
2057 module_param_named(ahb_thr_ratio, dwc_otg_module_params.ahb_thr_ratio, int,
2059 MODULE_PARM_DESC(ahb_thr_ratio, "AHB Threshold Ratio");
2060 module_param_named(power_down, dwc_otg_module_params.power_down, int, 0444);
2061 MODULE_PARM_DESC(power_down, "Power Down Mode");
2062 module_param_named(reload_ctl, dwc_otg_module_params.reload_ctl, int, 0444);
2063 MODULE_PARM_DESC(reload_ctl, "HFIR Reload Control");
2064 module_param_named(dev_out_nak, dwc_otg_module_params.dev_out_nak, int, 0444);
2065 MODULE_PARM_DESC(dev_out_nak, "Enable Device OUT NAK");
2066 module_param_named(cont_on_bna, dwc_otg_module_params.cont_on_bna, int, 0444);
2067 MODULE_PARM_DESC(cont_on_bna, "Enable Enable Continue on BNA");
2068 module_param_named(ahb_single, dwc_otg_module_params.ahb_single, int, 0444);
2069 MODULE_PARM_DESC(ahb_single, "Enable AHB Single Support");
2070 module_param_named(adp_enable, dwc_otg_module_params.adp_enable, int, 0444);
2071 MODULE_PARM_DESC(adp_enable, "ADP Enable 0=ADP Disabled 1=ADP Enabled");
2072 module_param_named(otg_ver, dwc_otg_module_params.otg_ver, int, 0444);
2073 MODULE_PARM_DESC(otg_ver, "OTG revision supported 0=OTG 1.3 1=OTG 2.0");
2075 /** @page "Module Parameters"
2077 * The following parameters may be specified when starting the module.
2078 * These parameters define how the DWC_otg controller should be
2079 * configured. Parameter values are passed to the CIL initialization
2080 * function dwc_otg_cil_init
2082 * Example: <code>modprobe dwc_otg speed=1 otg_cap=1</code>
2086 <tr><td>Parameter Name</td><td>Meaning</td></tr>
2090 <td>Specifies the OTG capabilities. The driver will automatically detect the
2091 value for this parameter if none is specified.
2092 - 0: HNP and SRP capable (default, if available)
2093 - 1: SRP Only capable
2094 - 2: No HNP/SRP capable
2099 <td>Specifies whether to use slave or DMA mode for accessing the data FIFOs.
2100 The driver will automatically detect the value for this parameter if none is
2103 - 1: DMA (default, if available)
2107 <td>dma_burst_size</td>
2108 <td>The DMA Burst size (applicable only for External DMA Mode).
2109 - Values: 1, 4, 8 16, 32, 64, 128, 256 (default 32)
2114 <td>Specifies the maximum speed of operation in host and device mode. The
2115 actual speed depends on the speed of the attached device and the value of
2117 - 0: High Speed (default)
2122 <td>host_support_fs_ls_low_power</td>
2123 <td>Specifies whether low power mode is supported when attached to a Full
2124 Speed or Low Speed device in host mode.
2125 - 0: Don't support low power mode (default)
2126 - 1: Support low power mode
2130 <td>host_ls_low_power_phy_clk</td>
2131 <td>Specifies the PHY clock rate in low power mode when connected to a Low
2132 Speed device in host mode. This parameter is applicable only if
2133 HOST_SUPPORT_FS_LS_LOW_POWER is enabled.
2134 - 0: 48 MHz (default)
2139 <td>enable_dynamic_fifo</td>
2140 <td> Specifies whether FIFOs may be resized by the driver software.
2141 - 0: Use cC FIFO size parameters
2142 - 1: Allow dynamic FIFO sizing (default)
2146 <td>data_fifo_size</td>
2147 <td>Total number of 4-byte words in the data FIFO memory. This memory
2148 includes the Rx FIFO, non-periodic Tx FIFO, and periodic Tx FIFOs.
2149 - Values: 32 to 32768 (default 8192)
2151 Note: The total FIFO memory depth in the FPGA configuration is 8192.
2155 <td>dev_rx_fifo_size</td>
2156 <td>Number of 4-byte words in the Rx FIFO in device mode when dynamic
2157 FIFO sizing is enabled.
2158 - Values: 16 to 32768 (default 1064)
2162 <td>dev_nperio_tx_fifo_size</td>
2163 <td>Number of 4-byte words in the non-periodic Tx FIFO in device mode when
2164 dynamic FIFO sizing is enabled.
2165 - Values: 16 to 32768 (default 1024)
2169 <td>dev_perio_tx_fifo_size_n (n = 1 to 15)</td>
2170 <td>Number of 4-byte words in each of the periodic Tx FIFOs in device mode
2171 when dynamic FIFO sizing is enabled.
2172 - Values: 4 to 768 (default 256)
2176 <td>host_rx_fifo_size</td>
2177 <td>Number of 4-byte words in the Rx FIFO in host mode when dynamic FIFO
2179 - Values: 16 to 32768 (default 1024)
2183 <td>host_nperio_tx_fifo_size</td>
2184 <td>Number of 4-byte words in the non-periodic Tx FIFO in host mode when
2185 dynamic FIFO sizing is enabled in the core.
2186 - Values: 16 to 32768 (default 1024)
2190 <td>host_perio_tx_fifo_size</td>
2191 <td>Number of 4-byte words in the host periodic Tx FIFO when dynamic FIFO
2193 - Values: 16 to 32768 (default 1024)
2197 <td>max_transfer_size</td>
2198 <td>The maximum transfer size supported in bytes.
2199 - Values: 2047 to 65,535 (default 65,535)
2203 <td>max_packet_count</td>
2204 <td>The maximum number of packets in a transfer.
2205 - Values: 15 to 511 (default 511)
2209 <td>host_channels</td>
2210 <td>The number of host channel registers to use.
2211 - Values: 1 to 16 (default 12)
2213 Note: The FPGA configuration supports a maximum of 12 host channels.
2217 <td>dev_endpoints</td>
2218 <td>The number of endpoints in addition to EP0 available for device mode
2220 - Values: 1 to 15 (default 6 IN and OUT)
2222 Note: The FPGA configuration supports a maximum of 6 IN and OUT endpoints in
2228 <td>Specifies the type of PHY interface to use. By default, the driver will
2229 automatically detect the phy_type.
2231 - 1: UTMI+ (default, if available)
2236 <td>phy_utmi_width</td>
2237 <td>Specifies the UTMI+ Data Width. This parameter is applicable for a
2238 phy_type of UTMI+. Also, this parameter is applicable only if the
2239 OTG_HSPHY_WIDTH cC parameter was set to "8 and 16 bits", meaning that the
2240 core has been configured to work at either data path width.
2241 - Values: 8 or 16 bits (default 16)
2245 <td>phy_ulpi_ddr</td>
2246 <td>Specifies whether the ULPI operates at double or single data rate. This
2247 parameter is only applicable if phy_type is ULPI.
2248 - 0: single data rate ULPI interface with 8 bit wide data bus (default)
2249 - 1: double data rate ULPI interface with 4 bit wide data bus
2254 <td>Specifies whether to use the I2C interface for full speed PHY. This
2255 parameter is only applicable if PHY_TYPE is FS.
2256 - 0: Disabled (default)
2262 <td>Specifies whether to use ULPI FS/LS mode only.
2263 - 0: Disabled (default)
2269 <td>Specifies whether term select D-Line pulsing for all PHYs is enabled.
2270 - 0: Disabled (default)
2275 <td>en_multiple_tx_fifo</td>
2276 <td>Specifies whether dedicatedto tx fifos are enabled for non periodic IN EPs.
2277 The driver will automatically detect the value for this parameter if none is
2280 - 1: Enabled (default, if available)
2284 <td>dev_tx_fifo_size_n (n = 1 to 15)</td>
2285 <td>Number of 4-byte words in each of the Tx FIFOs in device mode
2286 when dynamic FIFO sizing is enabled.
2287 - Values: 4 to 768 (default 256)
2291 <td>tx_thr_length</td>
2292 <td>Transmit Threshold length in 32 bit double words
2293 - Values: 8 to 128 (default 64)
2297 <td>rx_thr_length</td>
2298 <td>Receive Threshold length in 32 bit double words
2299 - Values: 8 to 128 (default 64)
2304 <td>Specifies whether to enable Thresholding for Device mode. Bits 0, 1, 2 of
2305 this parmater specifies if thresholding is enabled for non-Iso Tx, Iso Tx and
2306 Rx transfers accordingly.
2307 The driver will automatically detect the value for this parameter if none is
2309 - Values: 0 to 7 (default 0)
2310 Bit values indicate:
2311 - 0: Thresholding disabled
2312 - 1: Thresholding enabled
2316 <td>dma_desc_enable</td>
2317 <td>Specifies whether to enable Descriptor DMA mode.
2318 The driver will automatically detect the value for this parameter if none is
2320 - 0: Descriptor DMA disabled
2321 - 1: Descriptor DMA (default, if available)
2326 <td>Specifies whether to enable MPI enhancement mode.
2327 The driver will automatically detect the value for this parameter if none is
2329 - 0: MPI disabled (default)
2335 <td>Specifies whether to enable PTI enhancement support.
2336 The driver will automatically detect the value for this parameter if none is
2338 - 0: PTI disabled (default)
2344 <td>Specifies whether to enable LPM support.
2345 The driver will automatically detect the value for this parameter if none is
2348 - 1: LPM enable (default, if available)
2352 <td>besl_enable</td>
2353 <td>Specifies whether to enable LPM Errata support.
2354 The driver will automatically detect the value for this parameter if none is
2356 - 0: LPM Errata disabled (default)
2357 - 1: LPM Errata enable
2361 <td>baseline_besl</td>
2362 <td>Specifies the baseline besl value.
2363 - Values: 0 to 15 (default 0)
2368 <td>Specifies the deep besl value.
2369 - Values: 0 to 15 (default 15)
2374 <td>Specifies whether to enable IC_USB capability.
2375 The driver will automatically detect the value for this parameter if none is
2377 - 0: IC_USB disabled (default, if available)
2382 <td>ahb_thr_ratio</td>
2383 <td>Specifies AHB Threshold ratio.
2384 - Values: 0 to 3 (default 0)
2389 <td>Specifies Power Down(Hibernation) Mode.
2390 The driver will automatically detect the value for this parameter if none is
2392 - 0: Power Down disabled (default)
2393 - 2: Power Down enabled
2398 <td>Specifies whether dynamic reloading of the HFIR register is allowed during
2399 run time. The driver will automatically detect the value for this parameter if
2400 none is specified. In case the HFIR value is reloaded when HFIR.RldCtrl == 1'b0
2401 the core might misbehave.
2402 - 0: Reload Control disabled (default)
2403 - 1: Reload Control enabled
2407 <td>dev_out_nak</td>
2408 <td>Specifies whether Device OUT NAK enhancement enabled or no.
2409 The driver will automatically detect the value for this parameter if
2410 none is specified. This parameter is valid only when OTG_EN_DESC_DMA == 1
\92b1.
2411 - 0: The core does not set NAK after Bulk OUT transfer complete (default)
2412 - 1: The core sets NAK after Bulk OUT transfer complete
2416 <td>cont_on_bna</td>
2417 <td>Specifies whether Enable Continue on BNA enabled or no.
2418 After receiving BNA interrupt the core disables the endpoint,when the
2419 endpoint is re-enabled by the application the
2420 - 0: Core starts processing from the DOEPDMA descriptor (default)
2421 - 1: Core starts processing from the descriptor which received the BNA.
2422 This parameter is valid only when OTG_EN_DESC_DMA == 1
\92b1.
2427 <td>This bit when programmed supports SINGLE transfers for remainder data
2428 in a transfer for DMA mode of operation.
2429 - 0: The remainder data will be sent using INCR burst size (default)
2430 - 1: The remainder data will be sent using SINGLE burst size.
2435 <td>Specifies whether ADP feature is enabled.
2436 The driver will automatically detect the value for this parameter if none is
2438 - 0: ADP feature disabled (default)
2439 - 1: ADP feature enabled
2444 <td>Specifies whether OTG is performing as USB OTG Revision 2.0 or Revision 1.3
2446 - 0: OTG 2.0 support disabled (default)
2447 - 1: OTG 2.0 support enabled