1 /* ==========================================================================
2 * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_driver.c $
7 * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
8 * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
9 * otherwise expressly agreed to in writing between Synopsys and you.
11 * The Software IS NOT an item of Licensed Software or Licensed Product under
12 * any End User Software License Agreement or Agreement for Licensed Product
13 * with Synopsys or any supplement thereto. You are permitted to use and
14 * redistribute this Software in source and binary forms, with or without
15 * modification, provided that redistributions of source code must retain this
16 * notice. You may not view, use, disclose, copy or distribute this file or
17 * any information contained herein except pursuant to this license grant from
18 * Synopsys. If you do not agree with this notice, including the disclaimer
19 * below, then you are not authorized to use the Software.
21 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
25 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
26 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
27 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
28 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
32 * ========================================================================== */
35 * The dwc_otg_driver module provides the initialization and cleanup entry
36 * points for the DWC_otg driver. This module will be dynamically installed
37 * after Linux is booted using the insmod command. When the module is
38 * installed, the dwc_otg_driver_init function is called. When the module is
39 * removed (using rmmod), the dwc_otg_driver_cleanup function is called.
41 * This module also defines a data structure for the dwc_otg_driver, which is
42 * used in conjunction with the standard ARM lm_device structure. These
43 * structures allow the OTG driver to comply with the standard Linux driver
44 * model in which devices and drivers are registered with a bus driver. This
45 * has the benefit that Linux can expose attributes of the driver and device
46 * in its special sysfs file system. Users can then read or write files in
47 * this file system to perform diagnostics on the driver components or the
51 #include "dwc_otg_os_dep.h"
52 #include "common_port/dwc_os.h"
53 #include "dwc_otg_dbg.h"
54 #include "dwc_otg_driver.h"
55 #include "dwc_otg_attr.h"
56 #include "dwc_otg_core_if.h"
57 #include "dwc_otg_pcd_if.h"
58 #include "dwc_otg_hcd_if.h"
59 #include "dwc_otg_cil.h"
60 #include "dwc_otg_pcd.h"
62 #include "usbdev_rk.h"
64 #define DWC_DRIVER_VERSION "3.10a 21-DEC-2012"
65 #define DWC_DRIVER_DESC "HS OTG USB Controller driver"
67 static const char dwc_host20_driver_name[] = "usb20_host";
68 static const char dwc_otg20_driver_name[] = "usb20_otg";
70 dwc_otg_device_t* g_otgdev = NULL;
72 extern int pcd_init( struct platform_device *_dev );
73 extern int otg20_hcd_init( struct platform_device *_dev );
74 extern int host20_hcd_init( struct platform_device *_dev );
75 extern int pcd_remove( struct platform_device *_dev );
76 extern void hcd_remove( struct platform_device *_dev);
77 extern void dwc_otg_adp_start( dwc_otg_core_if_t * core_if, uint8_t is_host);
79 #ifdef CONFIG_USB20_OTG
80 static struct usb20otg_pdata_id usb20otg_pdata[] = {
82 .name = "rk3188-usb20otg",
83 .pdata = &usb20otg_pdata_rk3188,
86 .name = "rk3288-usb20otg",
87 .pdata = &usb20otg_pdata_rk3288,
93 #ifdef CONFIG_USB20_HOST
94 static struct usb20host_pdata_id usb20host_pdata[] = {
96 .name = "rk3188-usb20host",
97 .pdata = &usb20host_pdata_rk3188,
100 .name = "rk3288-usb20host",
101 .pdata = &usb20host_pdata_rk3288,
107 /*-------------------------------------------------------------------------*/
108 /* Encapsulate the module parameter settings */
110 struct dwc_otg_driver_module_params {
114 int32_t dma_desc_enable;
115 int32_t dma_burst_size;
117 int32_t host_support_fs_ls_low_power;
118 int32_t host_ls_low_power_phy_clk;
119 int32_t enable_dynamic_fifo;
120 int32_t data_fifo_size;
121 int32_t dev_rx_fifo_size;
122 int32_t dev_nperio_tx_fifo_size;
123 uint32_t dev_perio_tx_fifo_size[MAX_PERIO_FIFOS];
124 int32_t host_rx_fifo_size;
125 int32_t host_nperio_tx_fifo_size;
126 int32_t host_perio_tx_fifo_size;
127 int32_t max_transfer_size;
128 int32_t max_packet_count;
129 int32_t host_channels;
130 int32_t dev_endpoints;
132 int32_t phy_utmi_width;
133 int32_t phy_ulpi_ddr;
134 int32_t phy_ulpi_ext_vbus;
138 int32_t en_multiple_tx_fifo;
139 uint32_t dev_tx_fifo_size[MAX_TX_FIFOS];
141 uint32_t tx_thr_length;
142 uint32_t rx_thr_length;
147 int32_t baseline_besl;
150 int32_t ahb_thr_ratio;
160 static struct dwc_otg_driver_module_params dwc_otg_module_params = {
162 .otg_cap = DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE,
164 .dma_desc_enable = 0,
165 .dma_burst_size = -1,
167 .host_support_fs_ls_low_power = -1,
168 .host_ls_low_power_phy_clk = -1,
169 .enable_dynamic_fifo = 1,
170 .data_fifo_size = -1,
171 .dev_rx_fifo_size = 0x120,
172 .dev_nperio_tx_fifo_size = 0x10,
173 .dev_perio_tx_fifo_size = {
174 /* dev_perio_tx_fifo_size_1 */
192 .host_rx_fifo_size = -1,
193 .host_nperio_tx_fifo_size = -1,
194 .host_perio_tx_fifo_size = -1,
195 .max_transfer_size = -1,
196 .max_packet_count = -1,
200 .phy_utmi_width = -1,
202 .phy_ulpi_ext_vbus = -1,
206 .en_multiple_tx_fifo = -1,
207 .dev_tx_fifo_size = {
208 /* dev_tx_fifo_size */
246 #ifdef CONFIG_USB20_HOST
247 static struct dwc_otg_driver_module_params dwc_host_module_params = {
249 .otg_cap = DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE,
251 .dma_desc_enable = 0,
252 .dma_burst_size = -1,
254 .host_support_fs_ls_low_power = -1,
255 .host_ls_low_power_phy_clk = -1,
256 .enable_dynamic_fifo = -1,
257 .data_fifo_size = -1,
258 .dev_rx_fifo_size = -1,
259 .dev_nperio_tx_fifo_size = -1,
260 .dev_perio_tx_fifo_size = {
261 /* dev_perio_tx_fifo_size_1 */
279 .host_rx_fifo_size = -1,
280 .host_nperio_tx_fifo_size = -1,
281 .host_perio_tx_fifo_size = -1,
282 .max_transfer_size = -1,
283 .max_packet_count = -1,
287 .phy_utmi_width = -1,
289 .phy_ulpi_ext_vbus = -1,
293 .en_multiple_tx_fifo = -1,
294 .dev_tx_fifo_size = {
295 /* dev_tx_fifo_size */
335 * This function shows the Driver Version.
337 static ssize_t version_show(struct device_driver *dev, char *buf)
339 return snprintf(buf, sizeof(DWC_DRIVER_VERSION) + 2, "%s\n",
343 static DRIVER_ATTR(version, S_IRUGO, version_show, NULL);
346 * Global Debug Level Mask.
348 uint32_t g_dbg_lvl = DBG_OFF; /* OFF */
351 * This function shows the driver Debug Level.
353 static ssize_t dbg_level_show(struct device_driver *drv, char *buf)
355 return sprintf(buf, "0x%0x\n", g_dbg_lvl);
359 * This function stores the driver Debug Level.
361 static ssize_t dbg_level_store(struct device_driver *drv, const char *buf,
364 g_dbg_lvl = simple_strtoul(buf, NULL, 16);
368 static DRIVER_ATTR(debuglevel, S_IRUGO | S_IWUSR, dbg_level_show,
371 extern void hcd_start(dwc_otg_core_if_t *core_if);
372 extern struct usb_hub *g_dwc_otg_root_hub20;
373 extern void dwc_otg_hub_disconnect_device(struct usb_hub *hub);
375 void dwc_otg_force_host(dwc_otg_core_if_t *core_if)
377 dwc_otg_device_t *otg_dev = core_if->otg_dev;
378 dctl_data_t dctl = {.d32=0};
381 if(core_if->op_state == A_HOST)
383 printk("dwc_otg_force_host,already in A_HOST mode,everest\n");
386 core_if->op_state = A_HOST;
388 cancel_delayed_work(&otg_dev->pcd->check_vbus_work);
389 dctl.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dctl);
390 dctl.b.sftdiscon = 1;
391 DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dctl, dctl.d32);
393 local_irq_save(flags);
394 cil_pcd_stop(core_if);
396 * Initialize the Core for Host mode.
399 dwc_otg_core_init(core_if);
400 dwc_otg_enable_global_interrupts(core_if);
401 cil_hcd_start(core_if);
402 local_irq_restore(flags);
404 void dwc_otg_force_device(dwc_otg_core_if_t *core_if)
406 dwc_otg_device_t *otg_dev = core_if->otg_dev;
409 local_irq_save(flags);
411 if(core_if->op_state == B_PERIPHERAL) {
412 printk("dwc_otg_force_device,already in B_PERIPHERAL,everest\n");
415 core_if->op_state = B_PERIPHERAL;
416 cil_hcd_stop(core_if);
417 //dwc_otg_hub_disconnect_device(g_dwc_otg_root_hub20);
418 otg_dev->pcd->phy_suspend = 1;
419 otg_dev->pcd->vbus_status = 0;
420 dwc_otg_pcd_start_check_vbus_work(otg_dev->pcd);
422 /* Reset the Controller */
423 dwc_otg_core_reset( core_if );
425 dwc_otg_core_init(core_if);
426 dwc_otg_disable_global_interrupts(core_if);
427 cil_pcd_start(core_if);
429 local_irq_restore(flags);
431 static void dwc_otg_set_force_mode(dwc_otg_core_if_t *core_if, int mode)
433 gusbcfg_data_t usbcfg = { .d32 = 0 };
434 printk("!!!dwc_otg_set_force_mode\n");
435 usbcfg.d32 = DWC_READ_REG32( &core_if->core_global_regs->gusbcfg);
437 case USB_MODE_FORCE_HOST:
438 usbcfg.b.force_host_mode = 1;
439 usbcfg.b.force_dev_mode = 0;
441 case USB_MODE_FORCE_DEVICE:
442 usbcfg.b.force_host_mode = 0;
443 usbcfg.b.force_dev_mode = 1;
445 case USB_MODE_NORMAL:
446 usbcfg.b.force_host_mode = 0;
447 usbcfg.b.force_dev_mode = 0;
450 DWC_WRITE_REG32( &core_if->core_global_regs->gusbcfg, usbcfg.d32 );
453 static ssize_t force_usb_mode_show(struct device_driver *drv, char *buf)
455 dwc_otg_device_t *otg_dev = g_otgdev;
456 dwc_otg_core_if_t *core_if = otg_dev->core_if;
458 return sprintf(buf, "%d\n", core_if->usb_mode);
461 static ssize_t force_usb_mode_store(struct device_driver *drv, const char *buf,
464 int new_mode = simple_strtoul(buf, NULL, 16);
465 dwc_otg_device_t *otg_dev = g_otgdev;
466 dwc_otg_core_if_t *core_if;
467 struct dwc_otg_platform_data *pldata;
472 core_if = otg_dev->core_if;
473 pldata = otg_dev->pldata;
475 DWC_PRINTF("%s %d->%d\n",__func__, core_if->usb_mode, new_mode);
477 if(core_if->usb_mode == new_mode) {
481 if(pldata->phy_status == USB_PHY_SUSPEND) {
482 pldata->clock_enable(pldata, 1);
483 pldata->phy_suspend(pldata, USB_PHY_ENABLED);
487 case USB_MODE_FORCE_HOST:
488 if(USB_MODE_FORCE_DEVICE == core_if->usb_mode) {
490 core_if->usb_mode = new_mode;
491 dwc_otg_force_host(core_if);
492 } else if(USB_MODE_NORMAL == core_if->usb_mode) {
493 core_if->usb_mode = new_mode;
494 if(dwc_otg_is_host_mode(core_if)) {
495 dwc_otg_set_force_mode(core_if, new_mode);
497 dwc_otg_force_host(core_if);
502 case USB_MODE_FORCE_DEVICE:
503 if(USB_MODE_FORCE_HOST == core_if->usb_mode) {
504 core_if->usb_mode = new_mode;
505 dwc_otg_force_device(core_if);
506 } else if(USB_MODE_NORMAL == core_if->usb_mode) {
507 core_if->usb_mode = new_mode;
508 if(dwc_otg_is_device_mode(core_if)) {
509 dwc_otg_set_force_mode(core_if, new_mode);
511 dwc_otg_force_device(core_if);
516 case USB_MODE_NORMAL:
517 if(USB_MODE_FORCE_DEVICE == core_if->usb_mode) {
518 core_if->usb_mode = new_mode;
519 cancel_delayed_work(&otg_dev->pcd->check_vbus_work);
520 dwc_otg_set_force_mode(core_if, new_mode);
522 if(dwc_otg_is_host_mode(core_if)) {
523 dwc_otg_force_host(core_if);
525 dwc_otg_pcd_start_check_vbus_work(otg_dev->pcd);
527 } else if(USB_MODE_FORCE_HOST == core_if->usb_mode) {
528 core_if->usb_mode = new_mode;
529 dwc_otg_set_force_mode(core_if, new_mode);
531 if(dwc_otg_is_device_mode(core_if)) {
532 dwc_otg_force_device(core_if);
543 static DRIVER_ATTR(force_usb_mode, S_IRUGO | S_IWUSR, force_usb_mode_show, force_usb_mode_store);
546 static ssize_t dwc_otg_conn_en_show(struct device_driver *_drv, char *_buf)
549 dwc_otg_device_t *otg_dev = g_otgdev;
550 dwc_otg_pcd_t *_pcd = otg_dev->pcd;
551 return sprintf (_buf, "%d\n", _pcd->conn_en);
555 static ssize_t dwc_otg_conn_en_store(struct device_driver *_drv, const char *_buf,
558 int enable = simple_strtoul(_buf, NULL, 10);
559 dwc_otg_device_t *otg_dev = g_otgdev;
560 dwc_otg_pcd_t *_pcd = otg_dev->pcd;
561 DWC_PRINTF("%s %d->%d\n",__func__, _pcd->conn_en, enable);
563 _pcd->conn_en = enable;
566 static DRIVER_ATTR(dwc_otg_conn_en, S_IRUGO|S_IWUSR, dwc_otg_conn_en_show, dwc_otg_conn_en_store);
568 static ssize_t vbus_status_show(struct device_driver *_drv, char *_buf)
570 dwc_otg_device_t *otg_dev = g_otgdev;
571 dwc_otg_pcd_t *_pcd = otg_dev->pcd;
572 return sprintf (_buf, "%d\n", _pcd->vbus_status);
574 static DRIVER_ATTR(vbus_status, S_IRUGO, vbus_status_show, NULL);
577 * This function is called during module intialization
578 * to pass module parameters to the DWC_OTG CORE.
580 static int set_parameters(dwc_otg_core_if_t * core_if, struct dwc_otg_driver_module_params module_params)
585 if (module_params.otg_cap != -1) {
587 dwc_otg_set_param_otg_cap(core_if,
588 module_params.otg_cap);
590 if (module_params.dma_enable != -1) {
592 dwc_otg_set_param_dma_enable(core_if,
596 if (module_params.dma_desc_enable != -1) {
598 dwc_otg_set_param_dma_desc_enable(core_if,
602 if (module_params.opt != -1) {
604 dwc_otg_set_param_opt(core_if, module_params.opt);
606 if (module_params.dma_burst_size != -1) {
608 dwc_otg_set_param_dma_burst_size(core_if,
612 if (module_params.host_support_fs_ls_low_power != -1) {
614 dwc_otg_set_param_host_support_fs_ls_low_power(core_if,
616 host_support_fs_ls_low_power);
618 if (module_params.enable_dynamic_fifo != -1) {
620 dwc_otg_set_param_enable_dynamic_fifo(core_if,
622 enable_dynamic_fifo);
624 if (module_params.data_fifo_size != -1) {
626 dwc_otg_set_param_data_fifo_size(core_if,
630 if (module_params.dev_rx_fifo_size != -1) {
632 dwc_otg_set_param_dev_rx_fifo_size(core_if,
636 if (module_params.dev_nperio_tx_fifo_size != -1) {
638 dwc_otg_set_param_dev_nperio_tx_fifo_size(core_if,
640 dev_nperio_tx_fifo_size);
642 if (module_params.host_rx_fifo_size != -1) {
644 dwc_otg_set_param_host_rx_fifo_size(core_if,
645 module_params.host_rx_fifo_size);
647 if (module_params.host_nperio_tx_fifo_size != -1) {
649 dwc_otg_set_param_host_nperio_tx_fifo_size(core_if,
651 host_nperio_tx_fifo_size);
653 if (module_params.host_perio_tx_fifo_size != -1) {
655 dwc_otg_set_param_host_perio_tx_fifo_size(core_if,
657 host_perio_tx_fifo_size);
659 if (module_params.max_transfer_size != -1) {
661 dwc_otg_set_param_max_transfer_size(core_if,
665 if (module_params.max_packet_count != -1) {
667 dwc_otg_set_param_max_packet_count(core_if,
671 if (module_params.host_channels != -1) {
673 dwc_otg_set_param_host_channels(core_if,
677 if (module_params.dev_endpoints != -1) {
679 dwc_otg_set_param_dev_endpoints(core_if,
683 if (module_params.phy_type != -1) {
685 dwc_otg_set_param_phy_type(core_if,
686 module_params.phy_type);
688 if (module_params.speed != -1) {
690 dwc_otg_set_param_speed(core_if,
691 module_params.speed);
693 if (module_params.host_ls_low_power_phy_clk != -1) {
695 dwc_otg_set_param_host_ls_low_power_phy_clk(core_if,
697 host_ls_low_power_phy_clk);
699 if (module_params.phy_ulpi_ddr != -1) {
701 dwc_otg_set_param_phy_ulpi_ddr(core_if,
705 if (module_params.phy_ulpi_ext_vbus != -1) {
707 dwc_otg_set_param_phy_ulpi_ext_vbus(core_if,
711 if (module_params.phy_utmi_width != -1) {
713 dwc_otg_set_param_phy_utmi_width(core_if,
717 if (module_params.ulpi_fs_ls != -1) {
719 dwc_otg_set_param_ulpi_fs_ls(core_if,
720 module_params.ulpi_fs_ls);
722 if (module_params.ts_dline != -1) {
724 dwc_otg_set_param_ts_dline(core_if,
725 module_params.ts_dline);
727 if (module_params.i2c_enable != -1) {
729 dwc_otg_set_param_i2c_enable(core_if,
733 if (module_params.en_multiple_tx_fifo != -1) {
735 dwc_otg_set_param_en_multiple_tx_fifo(core_if,
737 en_multiple_tx_fifo);
739 for (i = 0; i < 15; i++) {
740 if (module_params.dev_perio_tx_fifo_size[i] != -1) {
742 dwc_otg_set_param_dev_perio_tx_fifo_size(core_if,
744 dev_perio_tx_fifo_size
749 for (i = 0; i < 15; i++) {
750 if (module_params.dev_tx_fifo_size[i] != -1) {
751 retval += dwc_otg_set_param_dev_tx_fifo_size(core_if,
757 if (module_params.thr_ctl != -1) {
759 dwc_otg_set_param_thr_ctl(core_if,
760 module_params.thr_ctl);
762 if (module_params.mpi_enable != -1) {
764 dwc_otg_set_param_mpi_enable(core_if,
768 if (module_params.pti_enable != -1) {
770 dwc_otg_set_param_pti_enable(core_if,
774 if (module_params.lpm_enable != -1) {
776 dwc_otg_set_param_lpm_enable(core_if,
780 if (module_params.besl_enable != -1) {
782 dwc_otg_set_param_besl_enable(core_if,
786 if (module_params.baseline_besl != -1) {
788 dwc_otg_set_param_baseline_besl(core_if,
792 if (module_params.deep_besl != -1) {
794 dwc_otg_set_param_deep_besl(core_if,
798 if (module_params.ic_usb_cap != -1) {
800 dwc_otg_set_param_ic_usb_cap(core_if,
804 if (module_params.tx_thr_length != -1) {
806 dwc_otg_set_param_tx_thr_length(core_if,
807 module_params.tx_thr_length);
809 if (module_params.rx_thr_length != -1) {
811 dwc_otg_set_param_rx_thr_length(core_if,
815 if (module_params.ahb_thr_ratio != -1) {
817 dwc_otg_set_param_ahb_thr_ratio(core_if,
818 module_params.ahb_thr_ratio);
820 if (module_params.power_down != -1) {
822 dwc_otg_set_param_power_down(core_if,
823 module_params.power_down);
825 if (module_params.reload_ctl != -1) {
827 dwc_otg_set_param_reload_ctl(core_if,
828 module_params.reload_ctl);
831 if (module_params.dev_out_nak != -1) {
833 dwc_otg_set_param_dev_out_nak(core_if,
834 module_params.dev_out_nak);
837 if (module_params.cont_on_bna != -1) {
839 dwc_otg_set_param_cont_on_bna(core_if,
840 module_params.cont_on_bna);
843 if (module_params.ahb_single != -1) {
845 dwc_otg_set_param_ahb_single(core_if,
846 module_params.ahb_single);
849 if (module_params.otg_ver != -1) {
851 dwc_otg_set_param_otg_ver(core_if,
852 module_params.otg_ver);
854 if (module_params.adp_enable != -1) {
856 dwc_otg_set_param_adp_enable(core_if,
864 * This function is the top level interrupt handler for the Common
865 * (Device and host modes) interrupts.
867 static irqreturn_t dwc_otg_common_irq(int irq, void *dev)
869 int32_t retval = IRQ_NONE;
871 retval = dwc_otg_handle_common_intr(dev);
873 //S3C2410X_CLEAR_EINTPEND();
875 return IRQ_RETVAL(retval);
878 #ifdef CONFIG_USB20_HOST
880 * This function is called when a lm_device is unregistered with the
881 * dwc_otg_driver. This happens, for example, when the rmmod command is
882 * executed. The device may or may not be electrically present. If it is
883 * present, the driver stops device processing. Any resources used on behalf
884 * of this device are freed.
888 static int host20_driver_remove( struct platform_device *_dev )
891 dwc_otg_device_t *otg_dev = dwc_get_device_platform_data(_dev);
892 DWC_DEBUGPL(DBG_ANY, "%s(%p)\n", __func__, _dev);
895 /* Memory allocation for the dwc_otg_device failed. */
896 DWC_DEBUGPL(DBG_ANY, "%s: otg_dev NULL!\n", __func__);
900 #ifndef DWC_DEVICE_ONLY
904 DWC_DEBUGPL(DBG_ANY, "%s: otg_dev->hcd NULL!\n", __func__);
909 #ifndef DWC_HOST_ONLY
913 DWC_DEBUGPL(DBG_ANY, "%s: otg_dev->pcd NULL!\n", __func__);
921 if (otg_dev->common_irq_installed) {
922 //free_irq(_dev->irq, otg_dev);
923 free_irq(platform_get_irq(_dev,0), otg_dev );
925 DWC_DEBUGPL(DBG_ANY, "%s: There is no installed irq!\n", __func__);
929 if (otg_dev->core_if) {
930 dwc_otg_cil_remove(otg_dev->core_if);
932 DWC_DEBUGPL(DBG_ANY, "%s: otg_dev->core_if NULL!\n", __func__);
937 * Remove the device attributes
939 dwc_otg_attr_remove(_dev);
944 if (otg_dev->os_dep.base) {
945 iounmap(otg_dev->os_dep.base);
950 * Clear the drvdata pointer.
953 dwc_set_device_platform_data(_dev, 0);
958 static const struct of_device_id usb20_host_of_match[] = {
960 .compatible = "rockchip,rk3188_usb20_host",
961 .data = &usb20host_pdata[RK3188_USB_CTLR],
964 .compatible = "rockchip,rk3288_usb20_host",
965 .data = &usb20host_pdata[RK3288_USB_CTLR],
969 MODULE_DEVICE_TABLE(of, usb20_host_of_match);
972 * This function is called when an lm_device is bound to a
973 * dwc_otg_driver. It creates the driver components required to
974 * control the device (CIL, HCD, and PCD) and it initializes the
975 * device. The driver components are stored in a dwc_otg_device
976 * structure. A reference to the dwc_otg_device is saved in the
977 * lm_device. This allows the driver to access the dwc_otg_device
978 * structure on subsequent calls to driver methods for this device.
980 * @param _dev Bus device
982 static int host20_driver_probe(struct platform_device *_dev)
986 struct resource *res_base;
987 dwc_otg_device_t *dwc_otg_device;
988 struct device *dev = &_dev->dev;
989 struct device_node *node = _dev->dev.of_node;
990 struct dwc_otg_platform_data *pldata;
991 struct usb20host_pdata_id *p;
992 const struct of_device_id *match =
993 of_match_device(of_match_ptr( usb20_host_of_match ), &_dev->dev);
996 p = (struct usb20host_pdata_id *)match->data;
998 dev_err(dev, "usb20host match failed\n");
1002 dev->platform_data = p->pdata;
1003 pldata = dev->platform_data;
1007 dev_err(dev, "device node not found\n");
1014 if(pldata->clock_init){
1015 pldata->clock_init(pldata);
1016 pldata->clock_enable(pldata, 1);
1019 if(pldata->phy_suspend)
1020 pldata->phy_suspend(pldata, USB_PHY_ENABLED);
1022 if(pldata->soft_reset)
1023 pldata->soft_reset();
1025 res_base=platform_get_resource(_dev, IORESOURCE_MEM, 0);
1027 dwc_otg_device = DWC_ALLOC(sizeof(dwc_otg_device_t));
1029 if (!dwc_otg_device) {
1030 dev_err(&_dev->dev, "kmalloc of dwc_otg_device failed\n");
1035 memset(dwc_otg_device, 0, sizeof(*dwc_otg_device));
1036 dwc_otg_device->os_dep.reg_offset = 0xFFFFFFFF;
1039 * Map the DWC_otg Core memory into virtual address space.
1042 dwc_otg_device->os_dep.base = devm_ioremap_resource(dev, res_base);
1044 if (!dwc_otg_device->os_dep.base) {
1045 dev_err(&_dev->dev, "ioremap() failed\n");
1046 DWC_FREE(dwc_otg_device);
1050 dev_dbg(&_dev->dev, "base=0x%08x\n",
1051 (unsigned)dwc_otg_device->os_dep.base);
1054 * Initialize driver data to point to the global DWC_otg
1058 dwc_set_device_platform_data(_dev, dwc_otg_device);
1059 pldata->privdata = dwc_otg_device;
1060 dwc_otg_device->pldata = (void *)pldata;
1062 dev_dbg(&_dev->dev, "dwc_otg_device=0x%p\n", dwc_otg_device);
1064 dwc_otg_device->core_if = dwc_otg_cil_init(dwc_otg_device->os_dep.base);
1067 if (!dwc_otg_device->core_if) {
1068 dev_err(&_dev->dev, "CIL initialization failed!\n");
1073 dwc_otg_device->core_if->otg_dev= dwc_otg_device;
1076 * Attempt to ensure this device is really a DWC_otg Controller.
1077 * Read and verify the SNPSID register contents. The value should be
1078 * 0x45F42XXX or 0x45F42XXX, which corresponds to either "OT2" or "OTG3",
1079 * as in "OTG version 2.XX" or "OTG version 3.XX".
1082 if (((dwc_otg_get_gsnpsid(dwc_otg_device->core_if) & 0xFFFFF000) != 0x4F542000) &&
1083 ((dwc_otg_get_gsnpsid(dwc_otg_device->core_if) & 0xFFFFF000) != 0x4F543000)) {
1084 dev_err(&_dev->dev, "Bad value for SNPSID: 0x%08x\n",
1085 dwc_otg_get_gsnpsid(dwc_otg_device->core_if));
1091 * Validate parameter values.
1093 if (set_parameters(dwc_otg_device->core_if ,dwc_host_module_params )) {
1099 * Create Device Attributes in sysfs
1101 dwc_otg_attr_create(_dev);
1104 * Disable the global interrupt until all the interrupt
1105 * handlers are installed.
1107 dwc_otg_disable_global_interrupts(dwc_otg_device->core_if);
1110 * Install the interrupt handler for the common interrupts before
1111 * enabling common interrupts in core_init below.
1113 irq = platform_get_irq(_dev,0);
1114 DWC_DEBUGPL(DBG_CIL, "registering (common) handler for irq%d\n",
1116 retval = request_irq(irq, dwc_otg_common_irq,
1117 IRQF_SHARED , "dwc_otg",
1120 DWC_ERROR("request of irq%d failed\n", irq);
1124 dwc_otg_device->common_irq_installed = 1;
1128 * Initialize the DWC_otg core.
1129 * In order to reduce the time of initialization,
1130 * we do core soft reset after connection detected.
1132 dwc_otg_core_init_no_reset(dwc_otg_device->core_if);
1135 * Initialize the HCD
1137 retval = host20_hcd_init(_dev);
1139 DWC_ERROR("hcd_init failed\n");
1140 dwc_otg_device->hcd = NULL;
1144 clk_set_rate(pldata->phyclk_480m, 480000000);
1146 * Enable the global interrupt after all the interrupt
1147 * handlers are installed if there is no ADP support else
1148 * perform initial actions required for Internal ADP logic.
1150 if (!dwc_otg_get_param_adp_enable(dwc_otg_device->core_if)) {
1151 if( pldata->phy_status == USB_PHY_ENABLED ){
1152 pldata->phy_suspend(pldata, USB_PHY_SUSPEND);
1154 pldata->clock_enable( pldata, 0);
1156 // dwc_otg_enable_global_interrupts(dwc_otg_device->core_if);
1159 dwc_otg_adp_start(dwc_otg_device->core_if,
1160 dwc_otg_is_host_mode(dwc_otg_device->core_if));
1165 host20_driver_remove(_dev);
1167 if(pldata->clock_enable)
1168 pldata->clock_enable(pldata, 0);
1174 static int dwc_otg_driver_suspend(struct platform_device *_dev , pm_message_t state )
1179 static int dwc_otg_driver_resume(struct platform_device *_dev )
1184 static void dwc_otg_driver_shutdown(struct platform_device *_dev )
1186 struct device *dev = &_dev->dev;
1187 dwc_otg_device_t *otg_dev = dev->platform_data;
1188 dwc_otg_core_if_t *core_if = otg_dev->core_if;
1189 dctl_data_t dctl = {.d32=0};
1191 DWC_PRINTF("%s: disconnect USB %s mode\n" , __func__ ,
1192 dwc_otg_is_host_mode(core_if) ? "host" : "device");
1193 if(dwc_otg_is_host_mode(core_if))
1195 if (core_if->hcd_cb && core_if->hcd_cb->stop)
1197 core_if->hcd_cb->stop( core_if->hcd_cb_p);
1202 /* soft disconnect */
1203 dctl.d32 = DWC_READ_REG32( &core_if->dev_if->dev_global_regs->dctl );
1204 dctl.b.sftdiscon = 1;
1205 DWC_WRITE_REG32( &core_if->dev_if->dev_global_regs->dctl, dctl.d32 );
1207 /* Clear any pending interrupts */
1208 DWC_WRITE_REG32( &core_if->core_global_regs->gintsts, 0xFFFFFFFF);
1214 * This structure defines the methods to be called by a bus driver
1215 * during the lifecycle of a device on that bus. Both drivers and
1216 * devices are registered with a bus driver. The bus driver matches
1217 * devices to drivers based on information in the device and driver
1220 * The probe function is called when the bus driver matches a device
1221 * to this driver. The remove function is called when a device is
1222 * unregistered with the bus driver.
1224 #ifdef CONFIG_USB20_HOST
1225 static struct platform_driver dwc_host_driver = {
1227 .name = (char *)dwc_host20_driver_name,
1228 .of_match_table = of_match_ptr(usb20_host_of_match),
1230 .probe = host20_driver_probe,
1231 .remove = host20_driver_remove,
1232 .suspend = dwc_otg_driver_suspend,
1233 .resume = dwc_otg_driver_resume,
1237 #ifdef CONFIG_USB20_OTG
1239 * This function is called when a lm_device is unregistered with the
1240 * dwc_otg_driver. This happens, for example, when the rmmod command is
1241 * executed. The device may or may not be electrically present. If it is
1242 * present, the driver stops device processing. Any resources used on behalf
1243 * of this device are freed.
1247 static int otg20_driver_remove( struct platform_device *_dev )
1250 dwc_otg_device_t *otg_dev = dwc_get_device_platform_data(_dev);
1251 DWC_DEBUGPL(DBG_ANY, "%s(%p)\n", __func__, _dev);
1254 /* Memory allocation for the dwc_otg_device failed. */
1255 DWC_DEBUGPL(DBG_ANY, "%s: otg_dev NULL!\n", __func__);
1258 #ifndef DWC_DEVICE_ONLY
1262 DWC_DEBUGPL(DBG_ANY, "%s: otg_dev->hcd NULL!\n", __func__);
1267 #ifndef DWC_HOST_ONLY
1271 DWC_DEBUGPL(DBG_ANY, "%s: otg_dev->pcd NULL!\n", __func__);
1278 if (otg_dev->common_irq_installed) {
1279 //free_irq(_dev->irq, otg_dev);
1280 free_irq(platform_get_irq(_dev,0), otg_dev );
1282 DWC_DEBUGPL(DBG_ANY, "%s: There is no installed irq!\n", __func__);
1286 if (otg_dev->core_if) {
1287 dwc_otg_cil_remove(otg_dev->core_if);
1289 DWC_DEBUGPL(DBG_ANY, "%s: otg_dev->core_if NULL!\n", __func__);
1294 * Remove the device attributes
1296 dwc_otg_attr_remove(_dev);
1299 * Return the memory.
1301 if (otg_dev->os_dep.base) {
1302 iounmap(otg_dev->os_dep.base);
1307 * Clear the drvdata pointer.
1310 dwc_set_device_platform_data(_dev, 0);
1315 static const struct of_device_id usb20_otg_of_match[] = {
1317 .compatible = "rockchip,rk3188_usb20_otg",
1318 .data = &usb20otg_pdata[RK3188_USB_CTLR],
1321 .compatible = "rockchip,rk3288_usb20_otg",
1322 .data = &usb20otg_pdata[RK3288_USB_CTLR],
1327 MODULE_DEVICE_TABLE(of, usb20_otg_of_match);
1330 * This function is called when an lm_device is bound to a
1331 * dwc_otg_driver. It creates the driver components required to
1332 * control the device (CIL, HCD, and PCD) and it initializes the
1333 * device. The driver components are stored in a dwc_otg_device
1334 * structure. A reference to the dwc_otg_device is saved in the
1335 * lm_device. This allows the driver to access the dwc_otg_device
1336 * structure on subsequent calls to driver methods for this device.
1338 * @param _dev Bus device
1340 static int otg20_driver_probe(struct platform_device *_dev)
1345 struct resource *res_base;
1346 dwc_otg_device_t *dwc_otg_device;
1347 struct device *dev = &_dev->dev;
1348 struct device_node *node = _dev->dev.of_node;
1349 struct dwc_otg_platform_data *pldata;
1350 struct usb20otg_pdata_id *p;
1351 const struct of_device_id *match =
1352 of_match_device(of_match_ptr( usb20_otg_of_match ), &_dev->dev);
1355 p = (struct usb20otg_pdata_id *)match->data;
1357 dev_err(dev, "usb20otg match failed\n");
1361 dev->platform_data = p->pdata;
1362 // dev->platform_data = &usb20otg_pdata;
1363 pldata = dev->platform_data;
1367 dev_err(dev, "device node not found\n");
1370 /*todo : move to usbdev_rk-XX.c*/
1374 if(pldata->clock_init){
1375 pldata->clock_init(pldata);
1376 pldata->clock_enable(pldata, 1);
1379 if(pldata->phy_suspend)
1380 pldata->phy_suspend(pldata, USB_PHY_ENABLED);
1382 if(pldata->dwc_otg_uart_mode)
1383 pldata->dwc_otg_uart_mode(pldata, PHY_USB_MODE);
1385 /* do reset later, because reset need about
1386 * 100ms to ensure otg id state change.
1389 if(pldata->soft_reset)
1390 pldata->soft_reset();
1394 res_base=platform_get_resource(_dev, IORESOURCE_MEM, 0);
1396 dwc_otg_device = DWC_ALLOC(sizeof(dwc_otg_device_t));
1398 if (!dwc_otg_device) {
1399 dev_err(&_dev->dev, "kmalloc of dwc_otg_device failed\n");
1404 memset(dwc_otg_device, 0, sizeof(*dwc_otg_device));
1405 dwc_otg_device->os_dep.reg_offset = 0xFFFFFFFF;
1408 * Map the DWC_otg Core memory into virtual address space.
1411 dwc_otg_device->os_dep.base = devm_ioremap_resource(dev, res_base);
1413 if (!dwc_otg_device->os_dep.base) {
1414 dev_err(&_dev->dev, "ioremap() failed\n");
1415 DWC_FREE(dwc_otg_device);
1419 dev_dbg(&_dev->dev, "base=0x%08x\n",
1420 (unsigned)dwc_otg_device->os_dep.base);
1423 * Initialize driver data to point to the global DWC_otg
1427 g_otgdev = dwc_otg_device;
1428 pldata->privdata = dwc_otg_device;
1429 dwc_otg_device->pldata = pldata;
1431 dwc_set_device_platform_data(_dev, dwc_otg_device);
1433 dev_dbg(&_dev->dev, "dwc_otg_device=0x%p\n", dwc_otg_device);
1435 dwc_otg_device->core_if = dwc_otg_cil_init(dwc_otg_device->os_dep.base);
1436 if (!dwc_otg_device->core_if) {
1437 dev_err(&_dev->dev, "CIL initialization failed!\n");
1442 dwc_otg_device->core_if->otg_dev = dwc_otg_device;
1444 * Attempt to ensure this device is really a DWC_otg Controller.
1445 * Read and verify the SNPSID register contents. The value should be
1446 * 0x45F42XXX or 0x45F42XXX, which corresponds to either "OT2" or "OTG3",
1447 * as in "OTG version 2.XX" or "OTG version 3.XX".
1450 if (((dwc_otg_get_gsnpsid(dwc_otg_device->core_if) & 0xFFFFF000) != 0x4F542000) &&
1451 ((dwc_otg_get_gsnpsid(dwc_otg_device->core_if) & 0xFFFFF000) != 0x4F543000)) {
1452 dev_err(&_dev->dev, "Bad value for SNPSID: 0x%08x\n",
1453 dwc_otg_get_gsnpsid(dwc_otg_device->core_if));
1459 * Validate parameter values.
1461 if (set_parameters(dwc_otg_device->core_if ,dwc_otg_module_params)) {
1467 * Create Device Attributes in sysfs
1469 dwc_otg_attr_create(_dev);
1472 * Disable the global interrupt until all the interrupt
1473 * handlers are installed.
1475 dwc_otg_disable_global_interrupts(dwc_otg_device->core_if);
1478 * Install the interrupt handler for the common interrupts before
1479 * enabling common interrupts in core_init below.
1481 irq = platform_get_irq(_dev,0);
1482 DWC_DEBUGPL(DBG_CIL, "registering (common) handler for irq%d\n",
1484 retval = request_irq(irq, dwc_otg_common_irq,
1485 IRQF_SHARED , "dwc_otg",
1488 DWC_ERROR("request of irq%d failed\n", irq);
1492 dwc_otg_device->common_irq_installed = 1;
1496 * Initialize the DWC_otg core.
1497 * In order to reduce the time of initialization,
1498 * we do core soft reset after connection detected.
1500 dwc_otg_core_init_no_reset(dwc_otg_device->core_if);
1503 * 0 - USB_MODE_NORMAL
1504 * 1 - USB_MODE_FORCE_HOST
1505 * 2 - USB_MODE_FORCE_DEVICE
1507 of_property_read_u32(node, "rockchip,usb-mode", &val);
1508 dwc_otg_device->core_if->usb_mode = val;
1510 #ifndef DWC_HOST_ONLY
1512 * Initialize the PCD
1514 retval = pcd_init(_dev);
1516 DWC_ERROR("pcd_init failed\n");
1517 dwc_otg_device->pcd = NULL;
1521 #ifndef DWC_DEVICE_ONLY
1523 * Initialize the HCD
1525 retval = otg20_hcd_init(_dev);
1527 DWC_ERROR("hcd_init failed\n");
1528 dwc_otg_device->hcd = NULL;
1533 * Enable the global interrupt after all the interrupt
1534 * handlers are installed if there is no ADP support else
1535 * perform initial actions required for Internal ADP logic.
1537 if (!dwc_otg_get_param_adp_enable(dwc_otg_device->core_if)){
1538 if( pldata->phy_status == USB_PHY_ENABLED ){
1539 pldata->phy_suspend(pldata, USB_PHY_SUSPEND);
1541 pldata->clock_enable( pldata, 0);
1543 // dwc_otg_enable_global_interrupts(dwc_otg_device->core_if);
1546 dwc_otg_adp_start(dwc_otg_device->core_if,
1547 dwc_otg_is_host_mode(dwc_otg_device->core_if));
1552 otg20_driver_remove(_dev);
1555 if(pldata->clock_enable)
1556 pldata->clock_enable(pldata, 0);
1561 static struct platform_driver dwc_otg_driver = {
1563 .name = (char *)dwc_otg20_driver_name,
1564 .of_match_table = of_match_ptr(usb20_otg_of_match),
1566 .probe = otg20_driver_probe,
1567 .remove = otg20_driver_remove,
1568 .suspend = dwc_otg_driver_suspend,
1569 .resume = dwc_otg_driver_resume,
1570 .shutdown = dwc_otg_driver_shutdown,
1575 * This function is called when the dwc_otg_driver is installed with the
1576 * insmod command. It registers the dwc_otg_driver structure with the
1577 * appropriate bus driver. This will cause the dwc_otg_driver_probe function
1578 * to be called. In addition, the bus driver will automatically expose
1579 * attributes defined for the device and driver in the special sysfs file
1584 static int __init dwc_otg_driver_init(void)
1589 #ifdef CONFIG_USB20_OTG
1591 printk(KERN_INFO "%s: version %s\n", dwc_otg20_driver_name,
1592 DWC_DRIVER_VERSION);
1594 retval = platform_driver_register(&dwc_otg_driver);
1596 printk(KERN_ERR "%s retval=%d\n", __func__, retval);
1600 error = driver_create_file(&dwc_otg_driver.driver, &driver_attr_version);
1601 error = driver_create_file(&dwc_otg_driver.driver, &driver_attr_debuglevel);
1602 error = driver_create_file(&dwc_otg_driver.driver, &driver_attr_dwc_otg_conn_en);
1603 error = driver_create_file(&dwc_otg_driver.driver, &driver_attr_vbus_status);
1604 error = driver_create_file(&dwc_otg_driver.driver, &driver_attr_force_usb_mode);
1609 #ifdef CONFIG_USB20_HOST
1610 printk(KERN_INFO "%s: version %s\n", dwc_host20_driver_name,
1611 DWC_DRIVER_VERSION);
1613 retval = platform_driver_register(&dwc_host_driver);
1615 printk(KERN_ERR "%s retval=%d\n", __func__, retval);
1619 error = driver_create_file(&dwc_host_driver.driver, &driver_attr_version);
1620 error = driver_create_file(&dwc_host_driver.driver, &driver_attr_debuglevel);
1625 module_init(dwc_otg_driver_init);
1628 * This function is called when the driver is removed from the kernel
1629 * with the rmmod command. The driver unregisters itself with its bus
1633 static void __exit dwc_otg_driver_cleanup(void)
1635 printk(KERN_DEBUG "dwc_otg_driver_cleanup()\n");
1637 #ifdef CONFIG_USB20_HOST
1639 driver_remove_file(&dwc_host_driver.driver, &driver_attr_debuglevel);
1640 driver_remove_file(&dwc_host_driver.driver, &driver_attr_version);
1641 platform_driver_unregister(&dwc_host_driver);
1642 printk(KERN_INFO "%s module removed\n", dwc_host20_driver_name);
1645 #ifdef CONFIG_USB20_OTG
1647 driver_remove_file(&dwc_otg_driver.driver, &driver_attr_dwc_otg_conn_en);
1648 driver_remove_file(&dwc_otg_driver.driver, &driver_attr_debuglevel);
1649 driver_remove_file(&dwc_otg_driver.driver, &driver_attr_version);
1650 driver_remove_file(&dwc_otg_driver.driver, &driver_attr_vbus_status);
1651 driver_remove_file(&dwc_otg_driver.driver, &driver_attr_force_usb_mode);
1652 platform_driver_unregister(&dwc_otg_driver);
1653 printk(KERN_INFO "%s module removed\n", dwc_otg20_driver_name);
1657 module_exit(dwc_otg_driver_cleanup);
1659 MODULE_DESCRIPTION(DWC_DRIVER_DESC);
1660 MODULE_AUTHOR("Synopsys Inc.");
1661 MODULE_LICENSE("GPL");
1663 module_param_named(otg_cap, dwc_otg_module_params.otg_cap, int, 0444);
1664 MODULE_PARM_DESC(otg_cap, "OTG Capabilities 0=HNP&SRP 1=SRP Only 2=None");
1665 module_param_named(opt, dwc_otg_module_params.opt, int, 0444);
1666 MODULE_PARM_DESC(opt, "OPT Mode");
1667 module_param_named(dma_enable, dwc_otg_module_params.dma_enable, int, 0444);
1668 MODULE_PARM_DESC(dma_enable, "DMA Mode 0=Slave 1=DMA enabled");
1670 module_param_named(dma_desc_enable, dwc_otg_module_params.dma_desc_enable, int,
1672 MODULE_PARM_DESC(dma_desc_enable,
1673 "DMA Desc Mode 0=Address DMA 1=DMA Descriptor enabled");
1675 module_param_named(dma_burst_size, dwc_otg_module_params.dma_burst_size, int,
1677 MODULE_PARM_DESC(dma_burst_size,
1678 "DMA Burst Size 1, 4, 8, 16, 32, 64, 128, 256");
1679 module_param_named(speed, dwc_otg_module_params.speed, int, 0444);
1680 MODULE_PARM_DESC(speed, "Speed 0=High Speed 1=Full Speed");
1681 module_param_named(host_support_fs_ls_low_power,
1682 dwc_otg_module_params.host_support_fs_ls_low_power, int,
1684 MODULE_PARM_DESC(host_support_fs_ls_low_power,
1685 "Support Low Power w/FS or LS 0=Support 1=Don't Support");
1686 module_param_named(host_ls_low_power_phy_clk,
1687 dwc_otg_module_params.host_ls_low_power_phy_clk, int, 0444);
1688 MODULE_PARM_DESC(host_ls_low_power_phy_clk,
1689 "Low Speed Low Power Clock 0=48Mhz 1=6Mhz");
1690 module_param_named(enable_dynamic_fifo,
1691 dwc_otg_module_params.enable_dynamic_fifo, int, 0444);
1692 MODULE_PARM_DESC(enable_dynamic_fifo, "0=cC Setting 1=Allow Dynamic Sizing");
1693 module_param_named(data_fifo_size, dwc_otg_module_params.data_fifo_size, int,
1695 MODULE_PARM_DESC(data_fifo_size,
1696 "Total number of words in the data FIFO memory 32-32768");
1697 module_param_named(dev_rx_fifo_size, dwc_otg_module_params.dev_rx_fifo_size,
1699 MODULE_PARM_DESC(dev_rx_fifo_size, "Number of words in the Rx FIFO 16-32768");
1700 module_param_named(dev_nperio_tx_fifo_size,
1701 dwc_otg_module_params.dev_nperio_tx_fifo_size, int, 0444);
1702 MODULE_PARM_DESC(dev_nperio_tx_fifo_size,
1703 "Number of words in the non-periodic Tx FIFO 16-32768");
1704 module_param_named(dev_perio_tx_fifo_size_1,
1705 dwc_otg_module_params.dev_perio_tx_fifo_size[0], int, 0444);
1706 MODULE_PARM_DESC(dev_perio_tx_fifo_size_1,
1707 "Number of words in the periodic Tx FIFO 4-768");
1708 module_param_named(dev_perio_tx_fifo_size_2,
1709 dwc_otg_module_params.dev_perio_tx_fifo_size[1], int, 0444);
1710 MODULE_PARM_DESC(dev_perio_tx_fifo_size_2,
1711 "Number of words in the periodic Tx FIFO 4-768");
1712 module_param_named(dev_perio_tx_fifo_size_3,
1713 dwc_otg_module_params.dev_perio_tx_fifo_size[2], int, 0444);
1714 MODULE_PARM_DESC(dev_perio_tx_fifo_size_3,
1715 "Number of words in the periodic Tx FIFO 4-768");
1716 module_param_named(dev_perio_tx_fifo_size_4,
1717 dwc_otg_module_params.dev_perio_tx_fifo_size[3], int, 0444);
1718 MODULE_PARM_DESC(dev_perio_tx_fifo_size_4,
1719 "Number of words in the periodic Tx FIFO 4-768");
1720 module_param_named(dev_perio_tx_fifo_size_5,
1721 dwc_otg_module_params.dev_perio_tx_fifo_size[4], int, 0444);
1722 MODULE_PARM_DESC(dev_perio_tx_fifo_size_5,
1723 "Number of words in the periodic Tx FIFO 4-768");
1724 module_param_named(dev_perio_tx_fifo_size_6,
1725 dwc_otg_module_params.dev_perio_tx_fifo_size[5], int, 0444);
1726 MODULE_PARM_DESC(dev_perio_tx_fifo_size_6,
1727 "Number of words in the periodic Tx FIFO 4-768");
1728 module_param_named(dev_perio_tx_fifo_size_7,
1729 dwc_otg_module_params.dev_perio_tx_fifo_size[6], int, 0444);
1730 MODULE_PARM_DESC(dev_perio_tx_fifo_size_7,
1731 "Number of words in the periodic Tx FIFO 4-768");
1732 module_param_named(dev_perio_tx_fifo_size_8,
1733 dwc_otg_module_params.dev_perio_tx_fifo_size[7], int, 0444);
1734 MODULE_PARM_DESC(dev_perio_tx_fifo_size_8,
1735 "Number of words in the periodic Tx FIFO 4-768");
1736 module_param_named(dev_perio_tx_fifo_size_9,
1737 dwc_otg_module_params.dev_perio_tx_fifo_size[8], int, 0444);
1738 MODULE_PARM_DESC(dev_perio_tx_fifo_size_9,
1739 "Number of words in the periodic Tx FIFO 4-768");
1740 module_param_named(dev_perio_tx_fifo_size_10,
1741 dwc_otg_module_params.dev_perio_tx_fifo_size[9], int, 0444);
1742 MODULE_PARM_DESC(dev_perio_tx_fifo_size_10,
1743 "Number of words in the periodic Tx FIFO 4-768");
1744 module_param_named(dev_perio_tx_fifo_size_11,
1745 dwc_otg_module_params.dev_perio_tx_fifo_size[10], int, 0444);
1746 MODULE_PARM_DESC(dev_perio_tx_fifo_size_11,
1747 "Number of words in the periodic Tx FIFO 4-768");
1748 module_param_named(dev_perio_tx_fifo_size_12,
1749 dwc_otg_module_params.dev_perio_tx_fifo_size[11], int, 0444);
1750 MODULE_PARM_DESC(dev_perio_tx_fifo_size_12,
1751 "Number of words in the periodic Tx FIFO 4-768");
1752 module_param_named(dev_perio_tx_fifo_size_13,
1753 dwc_otg_module_params.dev_perio_tx_fifo_size[12], int, 0444);
1754 MODULE_PARM_DESC(dev_perio_tx_fifo_size_13,
1755 "Number of words in the periodic Tx FIFO 4-768");
1756 module_param_named(dev_perio_tx_fifo_size_14,
1757 dwc_otg_module_params.dev_perio_tx_fifo_size[13], int, 0444);
1758 MODULE_PARM_DESC(dev_perio_tx_fifo_size_14,
1759 "Number of words in the periodic Tx FIFO 4-768");
1760 module_param_named(dev_perio_tx_fifo_size_15,
1761 dwc_otg_module_params.dev_perio_tx_fifo_size[14], int, 0444);
1762 MODULE_PARM_DESC(dev_perio_tx_fifo_size_15,
1763 "Number of words in the periodic Tx FIFO 4-768");
1764 module_param_named(host_rx_fifo_size, dwc_otg_module_params.host_rx_fifo_size,
1766 MODULE_PARM_DESC(host_rx_fifo_size, "Number of words in the Rx FIFO 16-32768");
1767 module_param_named(host_nperio_tx_fifo_size,
1768 dwc_otg_module_params.host_nperio_tx_fifo_size, int, 0444);
1769 MODULE_PARM_DESC(host_nperio_tx_fifo_size,
1770 "Number of words in the non-periodic Tx FIFO 16-32768");
1771 module_param_named(host_perio_tx_fifo_size,
1772 dwc_otg_module_params.host_perio_tx_fifo_size, int, 0444);
1773 MODULE_PARM_DESC(host_perio_tx_fifo_size,
1774 "Number of words in the host periodic Tx FIFO 16-32768");
1775 module_param_named(max_transfer_size, dwc_otg_module_params.max_transfer_size,
1777 /** @todo Set the max to 512K, modify checks */
1778 MODULE_PARM_DESC(max_transfer_size,
1779 "The maximum transfer size supported in bytes 2047-65535");
1780 module_param_named(max_packet_count, dwc_otg_module_params.max_packet_count,
1782 MODULE_PARM_DESC(max_packet_count,
1783 "The maximum number of packets in a transfer 15-511");
1784 module_param_named(host_channels, dwc_otg_module_params.host_channels, int,
1786 MODULE_PARM_DESC(host_channels,
1787 "The number of host channel registers to use 1-16");
1788 module_param_named(dev_endpoints, dwc_otg_module_params.dev_endpoints, int,
1790 MODULE_PARM_DESC(dev_endpoints,
1791 "The number of endpoints in addition to EP0 available for device mode 1-15");
1792 module_param_named(phy_type, dwc_otg_module_params.phy_type, int, 0444);
1793 MODULE_PARM_DESC(phy_type, "0=Reserved 1=UTMI+ 2=ULPI");
1794 module_param_named(phy_utmi_width, dwc_otg_module_params.phy_utmi_width, int,
1796 MODULE_PARM_DESC(phy_utmi_width, "Specifies the UTMI+ Data Width 8 or 16 bits");
1797 module_param_named(phy_ulpi_ddr, dwc_otg_module_params.phy_ulpi_ddr, int, 0444);
1798 MODULE_PARM_DESC(phy_ulpi_ddr,
1799 "ULPI at double or single data rate 0=Single 1=Double");
1800 module_param_named(phy_ulpi_ext_vbus, dwc_otg_module_params.phy_ulpi_ext_vbus,
1802 MODULE_PARM_DESC(phy_ulpi_ext_vbus,
1803 "ULPI PHY using internal or external vbus 0=Internal");
1804 module_param_named(i2c_enable, dwc_otg_module_params.i2c_enable, int, 0444);
1805 MODULE_PARM_DESC(i2c_enable, "FS PHY Interface");
1806 module_param_named(ulpi_fs_ls, dwc_otg_module_params.ulpi_fs_ls, int, 0444);
1807 MODULE_PARM_DESC(ulpi_fs_ls, "ULPI PHY FS/LS mode only");
1808 module_param_named(ts_dline, dwc_otg_module_params.ts_dline, int, 0444);
1809 MODULE_PARM_DESC(ts_dline, "Term select Dline pulsing for all PHYs");
1810 module_param_named(debug, g_dbg_lvl, int, 0444);
1811 MODULE_PARM_DESC(debug, "");
1813 module_param_named(en_multiple_tx_fifo,
1814 dwc_otg_module_params.en_multiple_tx_fifo, int, 0444);
1815 MODULE_PARM_DESC(en_multiple_tx_fifo,
1816 "Dedicated Non Periodic Tx FIFOs 0=disabled 1=enabled");
1817 module_param_named(dev_tx_fifo_size_1,
1818 dwc_otg_module_params.dev_tx_fifo_size[0], int, 0444);
1819 MODULE_PARM_DESC(dev_tx_fifo_size_1, "Number of words in the Tx FIFO 4-768");
1820 module_param_named(dev_tx_fifo_size_2,
1821 dwc_otg_module_params.dev_tx_fifo_size[1], int, 0444);
1822 MODULE_PARM_DESC(dev_tx_fifo_size_2, "Number of words in the Tx FIFO 4-768");
1823 module_param_named(dev_tx_fifo_size_3,
1824 dwc_otg_module_params.dev_tx_fifo_size[2], int, 0444);
1825 MODULE_PARM_DESC(dev_tx_fifo_size_3, "Number of words in the Tx FIFO 4-768");
1826 module_param_named(dev_tx_fifo_size_4,
1827 dwc_otg_module_params.dev_tx_fifo_size[3], int, 0444);
1828 MODULE_PARM_DESC(dev_tx_fifo_size_4, "Number of words in the Tx FIFO 4-768");
1829 module_param_named(dev_tx_fifo_size_5,
1830 dwc_otg_module_params.dev_tx_fifo_size[4], int, 0444);
1831 MODULE_PARM_DESC(dev_tx_fifo_size_5, "Number of words in the Tx FIFO 4-768");
1832 module_param_named(dev_tx_fifo_size_6,
1833 dwc_otg_module_params.dev_tx_fifo_size[5], int, 0444);
1834 MODULE_PARM_DESC(dev_tx_fifo_size_6, "Number of words in the Tx FIFO 4-768");
1835 module_param_named(dev_tx_fifo_size_7,
1836 dwc_otg_module_params.dev_tx_fifo_size[6], int, 0444);
1837 MODULE_PARM_DESC(dev_tx_fifo_size_7, "Number of words in the Tx FIFO 4-768");
1838 module_param_named(dev_tx_fifo_size_8,
1839 dwc_otg_module_params.dev_tx_fifo_size[7], int, 0444);
1840 MODULE_PARM_DESC(dev_tx_fifo_size_8, "Number of words in the Tx FIFO 4-768");
1841 module_param_named(dev_tx_fifo_size_9,
1842 dwc_otg_module_params.dev_tx_fifo_size[8], int, 0444);
1843 MODULE_PARM_DESC(dev_tx_fifo_size_9, "Number of words in the Tx FIFO 4-768");
1844 module_param_named(dev_tx_fifo_size_10,
1845 dwc_otg_module_params.dev_tx_fifo_size[9], int, 0444);
1846 MODULE_PARM_DESC(dev_tx_fifo_size_10, "Number of words in the Tx FIFO 4-768");
1847 module_param_named(dev_tx_fifo_size_11,
1848 dwc_otg_module_params.dev_tx_fifo_size[10], int, 0444);
1849 MODULE_PARM_DESC(dev_tx_fifo_size_11, "Number of words in the Tx FIFO 4-768");
1850 module_param_named(dev_tx_fifo_size_12,
1851 dwc_otg_module_params.dev_tx_fifo_size[11], int, 0444);
1852 MODULE_PARM_DESC(dev_tx_fifo_size_12, "Number of words in the Tx FIFO 4-768");
1853 module_param_named(dev_tx_fifo_size_13,
1854 dwc_otg_module_params.dev_tx_fifo_size[12], int, 0444);
1855 MODULE_PARM_DESC(dev_tx_fifo_size_13, "Number of words in the Tx FIFO 4-768");
1856 module_param_named(dev_tx_fifo_size_14,
1857 dwc_otg_module_params.dev_tx_fifo_size[13], int, 0444);
1858 MODULE_PARM_DESC(dev_tx_fifo_size_14, "Number of words in the Tx FIFO 4-768");
1859 module_param_named(dev_tx_fifo_size_15,
1860 dwc_otg_module_params.dev_tx_fifo_size[14], int, 0444);
1861 MODULE_PARM_DESC(dev_tx_fifo_size_15, "Number of words in the Tx FIFO 4-768");
1863 module_param_named(thr_ctl, dwc_otg_module_params.thr_ctl, int, 0444);
1864 MODULE_PARM_DESC(thr_ctl,
1865 "Thresholding enable flag bit 0 - non ISO Tx thr., 1 - ISO Tx thr., 2 - Rx thr.- bit 0=disabled 1=enabled");
1866 module_param_named(tx_thr_length, dwc_otg_module_params.tx_thr_length, int,
1868 MODULE_PARM_DESC(tx_thr_length, "Tx Threshold length in 32 bit DWORDs");
1869 module_param_named(rx_thr_length, dwc_otg_module_params.rx_thr_length, int,
1871 MODULE_PARM_DESC(rx_thr_length, "Rx Threshold length in 32 bit DWORDs");
1873 module_param_named(pti_enable, dwc_otg_module_params.pti_enable, int, 0444);
1874 module_param_named(mpi_enable, dwc_otg_module_params.mpi_enable, int, 0444);
1875 module_param_named(lpm_enable, dwc_otg_module_params.lpm_enable, int, 0444);
1876 MODULE_PARM_DESC(lpm_enable, "LPM Enable 0=LPM Disabled 1=LPM Enabled");
1878 module_param_named(besl_enable, dwc_otg_module_params.besl_enable, int, 0444);
1879 MODULE_PARM_DESC(besl_enable, "BESL Enable 0=BESL Disabled 1=BESL Enabled");
1880 module_param_named(baseline_besl, dwc_otg_module_params.baseline_besl, int, 0444);
1881 MODULE_PARM_DESC(baseline_besl, "Set the baseline besl value");
1882 module_param_named(deep_besl, dwc_otg_module_params.deep_besl, int, 0444);
1883 MODULE_PARM_DESC(deep_besl, "Set the deep besl value");
1885 module_param_named(ic_usb_cap, dwc_otg_module_params.ic_usb_cap, int, 0444);
1886 MODULE_PARM_DESC(ic_usb_cap,
1887 "IC_USB Capability 0=IC_USB Disabled 1=IC_USB Enabled");
1888 module_param_named(ahb_thr_ratio, dwc_otg_module_params.ahb_thr_ratio, int,
1890 MODULE_PARM_DESC(ahb_thr_ratio, "AHB Threshold Ratio");
1891 module_param_named(power_down, dwc_otg_module_params.power_down, int, 0444);
1892 MODULE_PARM_DESC(power_down, "Power Down Mode");
1893 module_param_named(reload_ctl, dwc_otg_module_params.reload_ctl, int, 0444);
1894 MODULE_PARM_DESC(reload_ctl, "HFIR Reload Control");
1895 module_param_named(dev_out_nak, dwc_otg_module_params.dev_out_nak, int, 0444);
1896 MODULE_PARM_DESC(dev_out_nak, "Enable Device OUT NAK");
1897 module_param_named(cont_on_bna, dwc_otg_module_params.cont_on_bna, int, 0444);
1898 MODULE_PARM_DESC(cont_on_bna, "Enable Enable Continue on BNA");
1899 module_param_named(ahb_single, dwc_otg_module_params.ahb_single, int, 0444);
1900 MODULE_PARM_DESC(ahb_single, "Enable AHB Single Support");
1901 module_param_named(adp_enable, dwc_otg_module_params.adp_enable, int, 0444);
1902 MODULE_PARM_DESC(adp_enable, "ADP Enable 0=ADP Disabled 1=ADP Enabled");
1903 module_param_named(otg_ver, dwc_otg_module_params.otg_ver, int, 0444);
1904 MODULE_PARM_DESC(otg_ver, "OTG revision supported 0=OTG 1.3 1=OTG 2.0");
1906 /** @page "Module Parameters"
1908 * The following parameters may be specified when starting the module.
1909 * These parameters define how the DWC_otg controller should be
1910 * configured. Parameter values are passed to the CIL initialization
1911 * function dwc_otg_cil_init
1913 * Example: <code>modprobe dwc_otg speed=1 otg_cap=1</code>
1917 <tr><td>Parameter Name</td><td>Meaning</td></tr>
1921 <td>Specifies the OTG capabilities. The driver will automatically detect the
1922 value for this parameter if none is specified.
1923 - 0: HNP and SRP capable (default, if available)
1924 - 1: SRP Only capable
1925 - 2: No HNP/SRP capable
1930 <td>Specifies whether to use slave or DMA mode for accessing the data FIFOs.
1931 The driver will automatically detect the value for this parameter if none is
1934 - 1: DMA (default, if available)
1938 <td>dma_burst_size</td>
1939 <td>The DMA Burst size (applicable only for External DMA Mode).
1940 - Values: 1, 4, 8 16, 32, 64, 128, 256 (default 32)
1945 <td>Specifies the maximum speed of operation in host and device mode. The
1946 actual speed depends on the speed of the attached device and the value of
1948 - 0: High Speed (default)
1953 <td>host_support_fs_ls_low_power</td>
1954 <td>Specifies whether low power mode is supported when attached to a Full
1955 Speed or Low Speed device in host mode.
1956 - 0: Don't support low power mode (default)
1957 - 1: Support low power mode
1961 <td>host_ls_low_power_phy_clk</td>
1962 <td>Specifies the PHY clock rate in low power mode when connected to a Low
1963 Speed device in host mode. This parameter is applicable only if
1964 HOST_SUPPORT_FS_LS_LOW_POWER is enabled.
1965 - 0: 48 MHz (default)
1970 <td>enable_dynamic_fifo</td>
1971 <td> Specifies whether FIFOs may be resized by the driver software.
1972 - 0: Use cC FIFO size parameters
1973 - 1: Allow dynamic FIFO sizing (default)
1977 <td>data_fifo_size</td>
1978 <td>Total number of 4-byte words in the data FIFO memory. This memory
1979 includes the Rx FIFO, non-periodic Tx FIFO, and periodic Tx FIFOs.
1980 - Values: 32 to 32768 (default 8192)
1982 Note: The total FIFO memory depth in the FPGA configuration is 8192.
1986 <td>dev_rx_fifo_size</td>
1987 <td>Number of 4-byte words in the Rx FIFO in device mode when dynamic
1988 FIFO sizing is enabled.
1989 - Values: 16 to 32768 (default 1064)
1993 <td>dev_nperio_tx_fifo_size</td>
1994 <td>Number of 4-byte words in the non-periodic Tx FIFO in device mode when
1995 dynamic FIFO sizing is enabled.
1996 - Values: 16 to 32768 (default 1024)
2000 <td>dev_perio_tx_fifo_size_n (n = 1 to 15)</td>
2001 <td>Number of 4-byte words in each of the periodic Tx FIFOs in device mode
2002 when dynamic FIFO sizing is enabled.
2003 - Values: 4 to 768 (default 256)
2007 <td>host_rx_fifo_size</td>
2008 <td>Number of 4-byte words in the Rx FIFO in host mode when dynamic FIFO
2010 - Values: 16 to 32768 (default 1024)
2014 <td>host_nperio_tx_fifo_size</td>
2015 <td>Number of 4-byte words in the non-periodic Tx FIFO in host mode when
2016 dynamic FIFO sizing is enabled in the core.
2017 - Values: 16 to 32768 (default 1024)
2021 <td>host_perio_tx_fifo_size</td>
2022 <td>Number of 4-byte words in the host periodic Tx FIFO when dynamic FIFO
2024 - Values: 16 to 32768 (default 1024)
2028 <td>max_transfer_size</td>
2029 <td>The maximum transfer size supported in bytes.
2030 - Values: 2047 to 65,535 (default 65,535)
2034 <td>max_packet_count</td>
2035 <td>The maximum number of packets in a transfer.
2036 - Values: 15 to 511 (default 511)
2040 <td>host_channels</td>
2041 <td>The number of host channel registers to use.
2042 - Values: 1 to 16 (default 12)
2044 Note: The FPGA configuration supports a maximum of 12 host channels.
2048 <td>dev_endpoints</td>
2049 <td>The number of endpoints in addition to EP0 available for device mode
2051 - Values: 1 to 15 (default 6 IN and OUT)
2053 Note: The FPGA configuration supports a maximum of 6 IN and OUT endpoints in
2059 <td>Specifies the type of PHY interface to use. By default, the driver will
2060 automatically detect the phy_type.
2062 - 1: UTMI+ (default, if available)
2067 <td>phy_utmi_width</td>
2068 <td>Specifies the UTMI+ Data Width. This parameter is applicable for a
2069 phy_type of UTMI+. Also, this parameter is applicable only if the
2070 OTG_HSPHY_WIDTH cC parameter was set to "8 and 16 bits", meaning that the
2071 core has been configured to work at either data path width.
2072 - Values: 8 or 16 bits (default 16)
2076 <td>phy_ulpi_ddr</td>
2077 <td>Specifies whether the ULPI operates at double or single data rate. This
2078 parameter is only applicable if phy_type is ULPI.
2079 - 0: single data rate ULPI interface with 8 bit wide data bus (default)
2080 - 1: double data rate ULPI interface with 4 bit wide data bus
2085 <td>Specifies whether to use the I2C interface for full speed PHY. This
2086 parameter is only applicable if PHY_TYPE is FS.
2087 - 0: Disabled (default)
2093 <td>Specifies whether to use ULPI FS/LS mode only.
2094 - 0: Disabled (default)
2100 <td>Specifies whether term select D-Line pulsing for all PHYs is enabled.
2101 - 0: Disabled (default)
2106 <td>en_multiple_tx_fifo</td>
2107 <td>Specifies whether dedicatedto tx fifos are enabled for non periodic IN EPs.
2108 The driver will automatically detect the value for this parameter if none is
2111 - 1: Enabled (default, if available)
2115 <td>dev_tx_fifo_size_n (n = 1 to 15)</td>
2116 <td>Number of 4-byte words in each of the Tx FIFOs in device mode
2117 when dynamic FIFO sizing is enabled.
2118 - Values: 4 to 768 (default 256)
2122 <td>tx_thr_length</td>
2123 <td>Transmit Threshold length in 32 bit double words
2124 - Values: 8 to 128 (default 64)
2128 <td>rx_thr_length</td>
2129 <td>Receive Threshold length in 32 bit double words
2130 - Values: 8 to 128 (default 64)
2135 <td>Specifies whether to enable Thresholding for Device mode. Bits 0, 1, 2 of
2136 this parmater specifies if thresholding is enabled for non-Iso Tx, Iso Tx and
2137 Rx transfers accordingly.
2138 The driver will automatically detect the value for this parameter if none is
2140 - Values: 0 to 7 (default 0)
2141 Bit values indicate:
2142 - 0: Thresholding disabled
2143 - 1: Thresholding enabled
2147 <td>dma_desc_enable</td>
2148 <td>Specifies whether to enable Descriptor DMA mode.
2149 The driver will automatically detect the value for this parameter if none is
2151 - 0: Descriptor DMA disabled
2152 - 1: Descriptor DMA (default, if available)
2157 <td>Specifies whether to enable MPI enhancement mode.
2158 The driver will automatically detect the value for this parameter if none is
2160 - 0: MPI disabled (default)
2166 <td>Specifies whether to enable PTI enhancement support.
2167 The driver will automatically detect the value for this parameter if none is
2169 - 0: PTI disabled (default)
2175 <td>Specifies whether to enable LPM support.
2176 The driver will automatically detect the value for this parameter if none is
2179 - 1: LPM enable (default, if available)
2183 <td>besl_enable</td>
2184 <td>Specifies whether to enable LPM Errata support.
2185 The driver will automatically detect the value for this parameter if none is
2187 - 0: LPM Errata disabled (default)
2188 - 1: LPM Errata enable
2192 <td>baseline_besl</td>
2193 <td>Specifies the baseline besl value.
2194 - Values: 0 to 15 (default 0)
2199 <td>Specifies the deep besl value.
2200 - Values: 0 to 15 (default 15)
2205 <td>Specifies whether to enable IC_USB capability.
2206 The driver will automatically detect the value for this parameter if none is
2208 - 0: IC_USB disabled (default, if available)
2213 <td>ahb_thr_ratio</td>
2214 <td>Specifies AHB Threshold ratio.
2215 - Values: 0 to 3 (default 0)
2220 <td>Specifies Power Down(Hibernation) Mode.
2221 The driver will automatically detect the value for this parameter if none is
2223 - 0: Power Down disabled (default)
2224 - 2: Power Down enabled
2229 <td>Specifies whether dynamic reloading of the HFIR register is allowed during
2230 run time. The driver will automatically detect the value for this parameter if
2231 none is specified. In case the HFIR value is reloaded when HFIR.RldCtrl == 1'b0
2232 the core might misbehave.
2233 - 0: Reload Control disabled (default)
2234 - 1: Reload Control enabled
2238 <td>dev_out_nak</td>
2239 <td>Specifies whether Device OUT NAK enhancement enabled or no.
2240 The driver will automatically detect the value for this parameter if
2241 none is specified. This parameter is valid only when OTG_EN_DESC_DMA == 1
\92b1.
2242 - 0: The core does not set NAK after Bulk OUT transfer complete (default)
2243 - 1: The core sets NAK after Bulk OUT transfer complete
2247 <td>cont_on_bna</td>
2248 <td>Specifies whether Enable Continue on BNA enabled or no.
2249 After receiving BNA interrupt the core disables the endpoint,when the
2250 endpoint is re-enabled by the application the
2251 - 0: Core starts processing from the DOEPDMA descriptor (default)
2252 - 1: Core starts processing from the descriptor which received the BNA.
2253 This parameter is valid only when OTG_EN_DESC_DMA == 1
\92b1.
2258 <td>This bit when programmed supports SINGLE transfers for remainder data
2259 in a transfer for DMA mode of operation.
2260 - 0: The remainder data will be sent using INCR burst size (default)
2261 - 1: The remainder data will be sent using SINGLE burst size.
2266 <td>Specifies whether ADP feature is enabled.
2267 The driver will automatically detect the value for this parameter if none is
2269 - 0: ADP feature disabled (default)
2270 - 1: ADP feature enabled
2275 <td>Specifies whether OTG is performing as USB OTG Revision 2.0 or Revision 1.3
2277 - 0: OTG 2.0 support disabled (default)
2278 - 1: OTG 2.0 support enabled