1 /* ==========================================================================
2 * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_driver.c $
7 * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
8 * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
9 * otherwise expressly agreed to in writing between Synopsys and you.
11 * The Software IS NOT an item of Licensed Software or Licensed Product under
12 * any End User Software License Agreement or Agreement for Licensed Product
13 * with Synopsys or any supplement thereto. You are permitted to use and
14 * redistribute this Software in source and binary forms, with or without
15 * modification, provided that redistributions of source code must retain this
16 * notice. You may not view, use, disclose, copy or distribute this file or
17 * any information contained herein except pursuant to this license grant from
18 * Synopsys. If you do not agree with this notice, including the disclaimer
19 * below, then you are not authorized to use the Software.
21 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
25 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
26 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
27 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
28 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
32 * ========================================================================== */
35 * The dwc_otg_driver module provides the initialization and cleanup entry
36 * points for the DWC_otg driver. This module will be dynamically installed
37 * after Linux is booted using the insmod command. When the module is
38 * installed, the dwc_otg_driver_init function is called. When the module is
39 * removed (using rmmod), the dwc_otg_driver_cleanup function is called.
41 * This module also defines a data structure for the dwc_otg_driver, which is
42 * used in conjunction with the standard ARM lm_device structure. These
43 * structures allow the OTG driver to comply with the standard Linux driver
44 * model in which devices and drivers are registered with a bus driver. This
45 * has the benefit that Linux can expose attributes of the driver and device
46 * in its special sysfs file system. Users can then read or write files in
47 * this file system to perform diagnostics on the driver components or the
51 #include "dwc_otg_os_dep.h"
52 #include "common_port/dwc_os.h"
53 #include "dwc_otg_dbg.h"
54 #include "dwc_otg_driver.h"
55 #include "dwc_otg_attr.h"
56 #include "dwc_otg_core_if.h"
57 #include "dwc_otg_pcd_if.h"
58 #include "dwc_otg_hcd_if.h"
59 #include "dwc_otg_cil.h"
60 #include "dwc_otg_pcd.h"
62 #include "usbdev_rk.h"
64 #define DWC_DRIVER_VERSION "3.10a 21-DEC-2012"
65 #define DWC_DRIVER_DESC "HS OTG USB Controller driver"
67 static const char dwc_host20_driver_name[] = "usb20_host";
68 static const char dwc_otg20_driver_name[] = "usb20_otg";
70 dwc_otg_device_t *g_otgdev;
72 extern int pcd_init(struct platform_device *_dev);
73 extern int otg20_hcd_init(struct platform_device *_dev);
74 extern int host20_hcd_init(struct platform_device *_dev);
75 extern int pcd_remove(struct platform_device *_dev);
76 extern void hcd_remove(struct platform_device *_dev);
77 extern void dwc_otg_adp_start(dwc_otg_core_if_t *core_if, uint8_t is_host);
81 static u32 usb_to_uart_status;
82 /*-------------------------------------------------------------------------*/
83 /* Encapsulate the module parameter settings */
85 struct dwc_otg_driver_module_params {
89 int32_t dma_desc_enable;
90 int32_t dma_burst_size;
92 int32_t host_support_fs_ls_low_power;
93 int32_t host_ls_low_power_phy_clk;
94 int32_t enable_dynamic_fifo;
95 int32_t data_fifo_size;
96 int32_t dev_rx_fifo_size;
97 int32_t dev_nperio_tx_fifo_size;
98 uint32_t dev_perio_tx_fifo_size[MAX_PERIO_FIFOS];
99 int32_t host_rx_fifo_size;
100 int32_t host_nperio_tx_fifo_size;
101 int32_t host_perio_tx_fifo_size;
102 int32_t max_transfer_size;
103 int32_t max_packet_count;
104 int32_t host_channels;
105 int32_t dev_endpoints;
107 int32_t phy_utmi_width;
108 int32_t phy_ulpi_ddr;
109 int32_t phy_ulpi_ext_vbus;
113 int32_t en_multiple_tx_fifo;
114 uint32_t dev_tx_fifo_size[MAX_TX_FIFOS];
116 uint32_t tx_thr_length;
117 uint32_t rx_thr_length;
122 int32_t baseline_besl;
125 int32_t ahb_thr_ratio;
135 static struct dwc_otg_driver_module_params dwc_otg_module_params = {
137 .otg_cap = DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE,
139 .dma_desc_enable = 0,
140 .dma_burst_size = -1,
142 .host_support_fs_ls_low_power = -1,
143 .host_ls_low_power_phy_clk = -1,
144 .enable_dynamic_fifo = 1,
145 .data_fifo_size = -1,
146 .dev_rx_fifo_size = 0x120,
147 .dev_nperio_tx_fifo_size = 0x10,
148 .dev_perio_tx_fifo_size = {
149 /* dev_perio_tx_fifo_size_1 */
167 .host_rx_fifo_size = -1,
168 .host_nperio_tx_fifo_size = -1,
169 .host_perio_tx_fifo_size = -1,
170 .max_transfer_size = -1,
171 .max_packet_count = -1,
175 .phy_utmi_width = -1,
177 .phy_ulpi_ext_vbus = -1,
181 .en_multiple_tx_fifo = -1,
182 .dev_tx_fifo_size = {
183 /* dev_tx_fifo_size */
221 #ifdef CONFIG_USB20_HOST
222 static struct dwc_otg_driver_module_params dwc_host_module_params = {
224 .otg_cap = DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE,
226 .dma_desc_enable = 0,
227 .dma_burst_size = -1,
229 .host_support_fs_ls_low_power = -1,
230 .host_ls_low_power_phy_clk = -1,
231 .enable_dynamic_fifo = -1,
232 .data_fifo_size = -1,
233 .dev_rx_fifo_size = -1,
234 .dev_nperio_tx_fifo_size = -1,
235 .dev_perio_tx_fifo_size = {
236 /* dev_perio_tx_fifo_size_1 */
254 .host_rx_fifo_size = -1,
255 .host_nperio_tx_fifo_size = -1,
256 .host_perio_tx_fifo_size = -1,
257 .max_transfer_size = -1,
258 .max_packet_count = -1,
262 .phy_utmi_width = -1,
264 .phy_ulpi_ext_vbus = -1,
268 .en_multiple_tx_fifo = -1,
269 .dev_tx_fifo_size = {
270 /* dev_tx_fifo_size */
310 * This function shows the Driver Version.
312 static ssize_t version_show(struct device_driver *dev, char *buf)
314 return snprintf(buf, sizeof(DWC_DRIVER_VERSION) + 2, "%s\n",
318 static DRIVER_ATTR(version, S_IRUGO, version_show, NULL);
321 * Global Debug Level Mask.
323 uint32_t g_dbg_lvl = DBG_OFF; /* OFF */
326 * This function shows the driver Debug Level.
328 static ssize_t dbg_level_show(struct device_driver *drv, char *buf)
330 return sprintf(buf, "0x%0x\n", g_dbg_lvl);
334 * This function stores the driver Debug Level.
336 static ssize_t dbg_level_store(struct device_driver *drv, const char *buf,
339 g_dbg_lvl = simple_strtoul(buf, NULL, 16);
343 static DRIVER_ATTR(debuglevel, S_IRUGO | S_IWUSR, dbg_level_show,
346 extern void hcd_start(dwc_otg_core_if_t *core_if);
347 extern struct usb_hub *g_dwc_otg_root_hub20;
348 extern void dwc_otg_hub_disconnect_device(struct usb_hub *hub);
350 void dwc_otg_force_host(dwc_otg_core_if_t *core_if)
352 dwc_otg_device_t *otg_dev = core_if->otg_dev;
353 dctl_data_t dctl = {.d32 = 0 };
356 if (core_if->op_state == A_HOST) {
357 printk("dwc_otg_force_host,already in A_HOST mode,everest\n");
360 core_if->op_state = A_HOST;
362 cancel_delayed_work(&otg_dev->pcd->check_vbus_work);
363 dctl.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dctl);
364 dctl.b.sftdiscon = 1;
365 DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dctl, dctl.d32);
367 local_irq_save(flags);
368 cil_pcd_stop(core_if);
370 * Initialize the Core for Host mode.
373 dwc_otg_core_init(core_if);
374 dwc_otg_enable_global_interrupts(core_if);
375 cil_hcd_start(core_if);
376 local_irq_restore(flags);
379 void dwc_otg_force_device(dwc_otg_core_if_t *core_if)
381 dwc_otg_device_t *otg_dev = core_if->otg_dev;
384 local_irq_save(flags);
386 if (core_if->op_state == B_PERIPHERAL) {
388 ("dwc_otg_force_device,already in B_PERIPHERAL,everest\n");
391 core_if->op_state = B_PERIPHERAL;
392 cil_hcd_stop(core_if);
393 /* dwc_otg_hub_disconnect_device(g_dwc_otg_root_hub20); */
394 otg_dev->pcd->phy_suspend = 1;
395 otg_dev->pcd->vbus_status = 0;
396 dwc_otg_pcd_start_check_vbus_work(otg_dev->pcd);
398 /* Reset the Controller */
399 dwc_otg_core_reset(core_if);
401 dwc_otg_core_init(core_if);
402 dwc_otg_disable_global_interrupts(core_if);
403 cil_pcd_start(core_if);
405 local_irq_restore(flags);
408 static ssize_t force_usb_mode_show(struct device_driver *drv, char *buf)
410 dwc_otg_device_t *otg_dev = g_otgdev;
411 dwc_otg_core_if_t *core_if = otg_dev->core_if;
413 return sprintf(buf, "%d\n", core_if->usb_mode);
416 static ssize_t force_usb_mode_store(struct device_driver *drv, const char *buf,
419 int new_mode = simple_strtoul(buf, NULL, 16);
420 dwc_otg_device_t *otg_dev = g_otgdev;
421 dwc_otg_core_if_t *core_if;
422 struct dwc_otg_platform_data *pldata;
427 core_if = otg_dev->core_if;
428 pldata = otg_dev->pldata;
430 DWC_PRINTF("%s %d->%d\n", __func__, core_if->usb_mode, new_mode);
432 if (core_if->usb_mode == new_mode) {
436 if (pldata->phy_status == USB_PHY_SUSPEND) {
437 pldata->clock_enable(pldata, 1);
438 pldata->phy_suspend(pldata, USB_PHY_ENABLED);
442 case USB_MODE_FORCE_HOST:
443 if (USB_MODE_FORCE_DEVICE == core_if->usb_mode) {
445 core_if->usb_mode = new_mode;
446 dwc_otg_force_host(core_if);
447 } else if (USB_MODE_NORMAL == core_if->usb_mode) {
448 core_if->usb_mode = new_mode;
449 if (dwc_otg_is_host_mode(core_if))
450 dwc_otg_set_force_mode(core_if, new_mode);
452 dwc_otg_force_host(core_if);
456 case USB_MODE_FORCE_DEVICE:
457 if (USB_MODE_FORCE_HOST == core_if->usb_mode) {
458 core_if->usb_mode = new_mode;
459 dwc_otg_force_device(core_if);
460 } else if (USB_MODE_NORMAL == core_if->usb_mode) {
461 core_if->usb_mode = new_mode;
462 if (dwc_otg_is_device_mode(core_if))
463 dwc_otg_set_force_mode(core_if, new_mode);
465 dwc_otg_force_device(core_if);
469 case USB_MODE_NORMAL:
470 if (USB_MODE_FORCE_DEVICE == core_if->usb_mode) {
471 core_if->usb_mode = new_mode;
472 cancel_delayed_work(&otg_dev->pcd->check_vbus_work);
473 dwc_otg_set_force_mode(core_if, new_mode);
475 if (dwc_otg_is_host_mode(core_if)) {
476 dwc_otg_force_host(core_if);
478 dwc_otg_pcd_start_check_vbus_work(otg_dev->pcd);
480 } else if (USB_MODE_FORCE_HOST == core_if->usb_mode) {
481 core_if->usb_mode = new_mode;
482 dwc_otg_set_force_mode(core_if, new_mode);
484 if (dwc_otg_is_device_mode(core_if)) {
485 dwc_otg_force_device(core_if);
496 static DRIVER_ATTR(force_usb_mode, S_IRUGO | S_IWUSR, force_usb_mode_show,
497 force_usb_mode_store);
499 static ssize_t dwc_otg_conn_en_show(struct device_driver *_drv, char *_buf)
502 dwc_otg_device_t *otg_dev = g_otgdev;
503 dwc_otg_pcd_t *_pcd = otg_dev->pcd;
504 return sprintf(_buf, "%d\n", _pcd->conn_en);
508 static ssize_t dwc_otg_conn_en_store(struct device_driver *_drv,
509 const char *_buf, size_t _count)
511 int enable = simple_strtoul(_buf, NULL, 10);
512 dwc_otg_device_t *otg_dev = g_otgdev;
513 dwc_otg_pcd_t *_pcd = otg_dev->pcd;
514 DWC_PRINTF("%s %d->%d\n", __func__, _pcd->conn_en, enable);
516 _pcd->conn_en = enable;
520 static DRIVER_ATTR(dwc_otg_conn_en, S_IRUGO | S_IWUSR, dwc_otg_conn_en_show,
521 dwc_otg_conn_en_store);
523 /* used for product vbus power control, SDK not need.
524 * If dwc_otg is host mode, enable vbus power.
525 * If dwc_otg is device mode, disable vbus power.
526 * return 1 - host mode, 0 - device mode.
528 int dwc_otg_usb_state(void)
530 dwc_otg_device_t *otg_dev = g_otgdev;
533 /* op_state is A_HOST */
534 if (1 == otg_dev->core_if->op_state)
536 /* op_state is B_PERIPHERAL */
537 else if (4 == otg_dev->core_if->op_state)
542 DWC_WARN("g_otgdev is NULL, maybe otg probe is failed!\n");
546 EXPORT_SYMBOL(dwc_otg_usb_state);
548 static ssize_t dwc_otg_op_state_show(struct device_driver *_drv, char *_buf)
550 dwc_otg_device_t *otg_dev = g_otgdev;
553 return sprintf(_buf, "%d\n", otg_dev->core_if->op_state);
555 return sprintf(_buf, "%d\n", 0);
558 static DRIVER_ATTR(op_state, S_IRUGO, dwc_otg_op_state_show, NULL);
560 static ssize_t vbus_status_show(struct device_driver *_drv, char *_buf)
562 dwc_otg_device_t *otg_dev = g_otgdev;
563 dwc_otg_pcd_t *_pcd = otg_dev->pcd;
564 return sprintf(_buf, "%d\n", _pcd->vbus_status);
567 static DRIVER_ATTR(vbus_status, S_IRUGO, vbus_status_show, NULL);
570 * This function is called during module intialization
571 * to pass module parameters to the DWC_OTG CORE.
573 static int set_parameters(dwc_otg_core_if_t *core_if,
574 struct dwc_otg_driver_module_params module_params)
579 if (module_params.otg_cap != -1) {
581 dwc_otg_set_param_otg_cap(core_if, module_params.otg_cap);
583 if (module_params.dma_enable != -1) {
585 dwc_otg_set_param_dma_enable(core_if,
586 module_params.dma_enable);
588 if (module_params.dma_desc_enable != -1) {
590 dwc_otg_set_param_dma_desc_enable(core_if,
591 module_params.dma_desc_enable);
593 if (module_params.opt != -1) {
594 retval += dwc_otg_set_param_opt(core_if, module_params.opt);
596 if (module_params.dma_burst_size != -1) {
598 dwc_otg_set_param_dma_burst_size(core_if,
599 module_params.dma_burst_size);
601 if (module_params.host_support_fs_ls_low_power != -1) {
603 dwc_otg_set_param_host_support_fs_ls_low_power(core_if,
604 module_params.host_support_fs_ls_low_power);
606 if (module_params.enable_dynamic_fifo != -1) {
608 dwc_otg_set_param_enable_dynamic_fifo(core_if,
609 module_params.enable_dynamic_fifo);
611 if (module_params.data_fifo_size != -1) {
613 dwc_otg_set_param_data_fifo_size(core_if,
614 module_params.data_fifo_size);
616 if (module_params.dev_rx_fifo_size != -1) {
618 dwc_otg_set_param_dev_rx_fifo_size(core_if,
619 module_params.dev_rx_fifo_size);
621 if (module_params.dev_nperio_tx_fifo_size != -1) {
623 dwc_otg_set_param_dev_nperio_tx_fifo_size(core_if,
624 module_params.dev_nperio_tx_fifo_size);
626 if (module_params.host_rx_fifo_size != -1) {
628 dwc_otg_set_param_host_rx_fifo_size(core_if,
632 if (module_params.host_nperio_tx_fifo_size != -1) {
634 dwc_otg_set_param_host_nperio_tx_fifo_size(core_if,
635 module_params.host_nperio_tx_fifo_size);
637 if (module_params.host_perio_tx_fifo_size != -1) {
639 dwc_otg_set_param_host_perio_tx_fifo_size(core_if,
640 module_params.host_perio_tx_fifo_size);
642 if (module_params.max_transfer_size != -1) {
644 dwc_otg_set_param_max_transfer_size(core_if,
645 module_params.max_transfer_size);
647 if (module_params.max_packet_count != -1) {
649 dwc_otg_set_param_max_packet_count(core_if,
650 module_params.max_packet_count);
652 if (module_params.host_channels != -1) {
654 dwc_otg_set_param_host_channels(core_if,
655 module_params.host_channels);
657 if (module_params.dev_endpoints != -1) {
659 dwc_otg_set_param_dev_endpoints(core_if,
660 module_params.dev_endpoints);
662 if (module_params.phy_type != -1) {
664 dwc_otg_set_param_phy_type(core_if, module_params.phy_type);
666 if (module_params.speed != -1) {
667 retval += dwc_otg_set_param_speed(core_if, module_params.speed);
669 if (module_params.host_ls_low_power_phy_clk != -1) {
671 dwc_otg_set_param_host_ls_low_power_phy_clk(core_if,
672 module_params.host_ls_low_power_phy_clk);
674 if (module_params.phy_ulpi_ddr != -1) {
676 dwc_otg_set_param_phy_ulpi_ddr(core_if,
677 module_params.phy_ulpi_ddr);
679 if (module_params.phy_ulpi_ext_vbus != -1) {
681 dwc_otg_set_param_phy_ulpi_ext_vbus(core_if,
682 module_params.phy_ulpi_ext_vbus);
684 if (module_params.phy_utmi_width != -1) {
686 dwc_otg_set_param_phy_utmi_width(core_if,
687 module_params.phy_utmi_width);
689 if (module_params.ulpi_fs_ls != -1) {
691 dwc_otg_set_param_ulpi_fs_ls(core_if,
692 module_params.ulpi_fs_ls);
694 if (module_params.ts_dline != -1) {
696 dwc_otg_set_param_ts_dline(core_if, module_params.ts_dline);
698 if (module_params.i2c_enable != -1) {
700 dwc_otg_set_param_i2c_enable(core_if,
701 module_params.i2c_enable);
703 if (module_params.en_multiple_tx_fifo != -1) {
705 dwc_otg_set_param_en_multiple_tx_fifo(core_if,
706 module_params.en_multiple_tx_fifo);
708 for (i = 0; i < 15; i++) {
709 if (module_params.dev_perio_tx_fifo_size[i] != -1) {
711 dwc_otg_set_param_dev_perio_tx_fifo_size(core_if,
712 module_params.dev_perio_tx_fifo_size
717 for (i = 0; i < 15; i++) {
718 if (module_params.dev_tx_fifo_size[i] != -1) {
719 retval += dwc_otg_set_param_dev_tx_fifo_size(core_if,
720 module_params.dev_tx_fifo_size
724 if (module_params.thr_ctl != -1) {
726 dwc_otg_set_param_thr_ctl(core_if, module_params.thr_ctl);
728 if (module_params.mpi_enable != -1) {
730 dwc_otg_set_param_mpi_enable(core_if,
731 module_params.mpi_enable);
733 if (module_params.pti_enable != -1) {
735 dwc_otg_set_param_pti_enable(core_if,
736 module_params.pti_enable);
738 if (module_params.lpm_enable != -1) {
740 dwc_otg_set_param_lpm_enable(core_if,
741 module_params.lpm_enable);
743 if (module_params.besl_enable != -1) {
745 dwc_otg_set_param_besl_enable(core_if,
746 module_params.besl_enable);
748 if (module_params.baseline_besl != -1) {
750 dwc_otg_set_param_baseline_besl(core_if,
751 module_params.baseline_besl);
753 if (module_params.deep_besl != -1) {
755 dwc_otg_set_param_deep_besl(core_if,
756 module_params.deep_besl);
758 if (module_params.ic_usb_cap != -1) {
760 dwc_otg_set_param_ic_usb_cap(core_if,
761 module_params.ic_usb_cap);
763 if (module_params.tx_thr_length != -1) {
765 dwc_otg_set_param_tx_thr_length(core_if,
769 if (module_params.rx_thr_length != -1) {
771 dwc_otg_set_param_rx_thr_length(core_if,
772 module_params.rx_thr_length);
774 if (module_params.ahb_thr_ratio != -1) {
776 dwc_otg_set_param_ahb_thr_ratio(core_if,
780 if (module_params.power_down != -1) {
782 dwc_otg_set_param_power_down(core_if,
783 module_params.power_down);
785 if (module_params.reload_ctl != -1) {
787 dwc_otg_set_param_reload_ctl(core_if,
788 module_params.reload_ctl);
791 if (module_params.dev_out_nak != -1) {
793 dwc_otg_set_param_dev_out_nak(core_if,
794 module_params.dev_out_nak);
797 if (module_params.cont_on_bna != -1) {
799 dwc_otg_set_param_cont_on_bna(core_if,
800 module_params.cont_on_bna);
803 if (module_params.ahb_single != -1) {
805 dwc_otg_set_param_ahb_single(core_if,
806 module_params.ahb_single);
809 if (module_params.otg_ver != -1) {
811 dwc_otg_set_param_otg_ver(core_if, module_params.otg_ver);
813 if (module_params.adp_enable != -1) {
815 dwc_otg_set_param_adp_enable(core_if,
816 module_params.adp_enable);
822 * This function is the top level interrupt handler for the Common
823 * (Device and host modes) interrupts.
825 static irqreturn_t dwc_otg_common_irq(int irq, void *dev)
827 int32_t retval = IRQ_NONE;
829 retval = dwc_otg_handle_common_intr(dev);
831 /* S3C2410X_CLEAR_EINTPEND(); */
833 return IRQ_RETVAL(retval);
836 #ifdef CONFIG_USB20_HOST
838 * This function is called when a lm_device is unregistered with the
839 * dwc_otg_driver. This happens, for example, when the rmmod command is
840 * executed. The device may or may not be electrically present. If it is
841 * present, the driver stops device processing. Any resources used on behalf
842 * of this device are freed.
846 static int host20_driver_remove(struct platform_device *_dev)
849 dwc_otg_device_t *otg_dev = dwc_get_device_platform_data(_dev);
850 DWC_DEBUGPL(DBG_ANY, "%s(%p)\n", __func__, _dev);
853 /* Memory allocation for the dwc_otg_device failed. */
854 DWC_DEBUGPL(DBG_ANY, "%s: otg_dev NULL!\n", __func__);
857 #ifndef DWC_DEVICE_ONLY
861 DWC_DEBUGPL(DBG_ANY, "%s: otg_dev->hcd NULL!\n", __func__);
866 #ifndef DWC_HOST_ONLY
870 DWC_DEBUGPL(DBG_ANY, "%s: otg_dev->pcd NULL!\n", __func__);
878 if (otg_dev->common_irq_installed) {
879 /* free_irq(_dev->irq, otg_dev); */
880 free_irq(platform_get_irq(_dev, 0), otg_dev);
882 DWC_DEBUGPL(DBG_ANY, "%s: There is no installed irq!\n",
887 if (otg_dev->core_if) {
888 dwc_otg_cil_remove(otg_dev->core_if);
890 DWC_DEBUGPL(DBG_ANY, "%s: otg_dev->core_if NULL!\n", __func__);
895 * Remove the device attributes
897 dwc_otg_attr_remove(_dev);
902 if (otg_dev->os_dep.base) {
903 iounmap(otg_dev->os_dep.base);
908 * Clear the drvdata pointer.
911 dwc_set_device_platform_data(_dev, 0);
916 static const struct of_device_id usb20_host_of_match[] = {
918 .compatible = "rockchip,rk3188_usb20_host",
919 .data = &usb20host_pdata_rk3188,
922 .compatible = "rockchip,rk3288_usb20_host",
923 .data = &usb20host_pdata_rk3288,
926 .compatible = "rockchip,rk3036_usb20_host",
927 .data = &usb20host_pdata_rk3036,
930 .compatible = "rockchip,rk3126_usb20_host",
931 .data = &usb20host_pdata_rk3126,
936 MODULE_DEVICE_TABLE(of, usb20_host_of_match);
939 * This function is called when an lm_device is bound to a
940 * dwc_otg_driver. It creates the driver components required to
941 * control the device (CIL, HCD, and PCD) and it initializes the
942 * device. The driver components are stored in a dwc_otg_device
943 * structure. A reference to the dwc_otg_device is saved in the
944 * lm_device. This allows the driver to access the dwc_otg_device
945 * structure on subsequent calls to driver methods for this device.
947 * @param _dev Bus device
949 static int host20_driver_probe(struct platform_device *_dev)
953 struct resource *res_base;
954 dwc_otg_device_t *dwc_otg_device;
955 struct device *dev = &_dev->dev;
956 struct device_node *node = _dev->dev.of_node;
957 struct dwc_otg_platform_data *pldata;
958 const struct of_device_id *match =
959 of_match_device(of_match_ptr(usb20_host_of_match), &_dev->dev);
961 if (match && match->data) {
962 dev->platform_data = (void *)match->data;
964 dev_err(dev, "usb20host match failed\n");
968 pldata = dev->platform_data;
972 dev_err(dev, "device node not found\n");
979 if (pldata->clock_init) {
980 pldata->clock_init(pldata);
981 pldata->clock_enable(pldata, 1);
984 if (pldata->phy_suspend)
985 pldata->phy_suspend(pldata, USB_PHY_ENABLED);
987 if (pldata->soft_reset)
988 pldata->soft_reset(pldata, RST_POR);
990 res_base = platform_get_resource(_dev, IORESOURCE_MEM, 0);
992 dwc_otg_device = DWC_ALLOC(sizeof(dwc_otg_device_t));
994 if (!dwc_otg_device) {
995 dev_err(&_dev->dev, "kmalloc of dwc_otg_device failed\n");
1000 memset(dwc_otg_device, 0, sizeof(*dwc_otg_device));
1001 dwc_otg_device->os_dep.reg_offset = 0xFFFFFFFF;
1004 * Map the DWC_otg Core memory into virtual address space.
1007 dwc_otg_device->os_dep.base = devm_ioremap_resource(dev, res_base);
1009 if (!dwc_otg_device->os_dep.base) {
1010 dev_err(&_dev->dev, "ioremap() failed\n");
1011 DWC_FREE(dwc_otg_device);
1015 dev_dbg(&_dev->dev, "base=0x%08x\n",
1016 (unsigned)dwc_otg_device->os_dep.base);
1019 * Initialize driver data to point to the global DWC_otg
1023 dwc_set_device_platform_data(_dev, dwc_otg_device);
1024 pldata->privdata = dwc_otg_device;
1025 dwc_otg_device->pldata = (void *)pldata;
1027 dev_dbg(&_dev->dev, "dwc_otg_device=0x%p\n", dwc_otg_device);
1029 dwc_otg_device->core_if = dwc_otg_cil_init(dwc_otg_device->os_dep.base);
1031 if (!dwc_otg_device->core_if) {
1032 dev_err(&_dev->dev, "CIL initialization failed!\n");
1037 dwc_otg_device->core_if->otg_dev = dwc_otg_device;
1040 * Attempt to ensure this device is really a DWC_otg Controller.
1041 * Read and verify the SNPSID register contents. The value should be
1042 * 0x45F42XXX or 0x45F42XXX, which corresponds to either "OT2" or "OTG3",
1043 * as in "OTG version 2.XX" or "OTG version 3.XX".
1046 if (((dwc_otg_get_gsnpsid(dwc_otg_device->core_if) & 0xFFFFF000) !=
1048 && ((dwc_otg_get_gsnpsid(dwc_otg_device->core_if) & 0xFFFFF000) !=
1050 dev_err(&_dev->dev, "Bad value for SNPSID: 0x%08x\n",
1051 dwc_otg_get_gsnpsid(dwc_otg_device->core_if));
1057 * Validate parameter values.
1059 if (set_parameters(dwc_otg_device->core_if, dwc_host_module_params)) {
1065 * Create Device Attributes in sysfs
1067 dwc_otg_attr_create(_dev);
1070 * Disable the global interrupt until all the interrupt
1071 * handlers are installed.
1073 dwc_otg_disable_global_interrupts(dwc_otg_device->core_if);
1076 * Install the interrupt handler for the common interrupts before
1077 * enabling common interrupts in core_init below.
1079 irq = platform_get_irq(_dev, 0);
1080 DWC_DEBUGPL(DBG_CIL, "registering (common) handler for irq%d\n", irq);
1081 retval = request_irq(irq, dwc_otg_common_irq,
1082 IRQF_SHARED, "dwc_otg", dwc_otg_device);
1084 DWC_ERROR("request of irq%d failed\n", irq);
1088 dwc_otg_device->common_irq_installed = 1;
1092 * Initialize the DWC_otg core.
1093 * In order to reduce the time of initialization,
1094 * we do core soft reset after connection detected.
1096 dwc_otg_core_init_no_reset(dwc_otg_device->core_if);
1099 * Initialize the HCD
1101 retval = host20_hcd_init(_dev);
1103 DWC_ERROR("hcd_init failed\n");
1104 dwc_otg_device->hcd = NULL;
1108 clk_set_rate(pldata->phyclk_480m, 480000000);
1110 * Enable the global interrupt after all the interrupt
1111 * handlers are installed if there is no ADP support else
1112 * perform initial actions required for Internal ADP logic.
1114 if (!dwc_otg_get_param_adp_enable(dwc_otg_device->core_if)) {
1115 if (pldata->phy_status == USB_PHY_ENABLED) {
1116 pldata->phy_suspend(pldata, USB_PHY_SUSPEND);
1118 pldata->clock_enable(pldata, 0);
1120 /* dwc_otg_enable_global_interrupts(dwc_otg_device->core_if); */
1122 dwc_otg_adp_start(dwc_otg_device->core_if,
1123 dwc_otg_is_host_mode(dwc_otg_device->
1129 host20_driver_remove(_dev);
1131 if (pldata->clock_enable)
1132 pldata->clock_enable(pldata, 0);
1138 static int dwc_otg_driver_suspend(struct platform_device *_dev,
1144 static int dwc_otg_driver_resume(struct platform_device *_dev)
1149 static void dwc_otg_driver_shutdown(struct platform_device *_dev)
1151 struct device *dev = &_dev->dev;
1152 struct dwc_otg_platform_data *pldata = dev->platform_data;
1153 dwc_otg_device_t *otg_dev = dev->platform_data;
1154 dwc_otg_core_if_t *core_if = otg_dev->core_if;
1155 dctl_data_t dctl = {.d32 = 0 };
1157 DWC_PRINTF("%s: disconnect USB %s mode\n", __func__,
1158 dwc_otg_is_host_mode(core_if) ? "host" : "device");
1160 if( pldata->dwc_otg_uart_mode != NULL)
1161 pldata->dwc_otg_uart_mode( pldata, PHY_USB_MODE);
1162 if(pldata->phy_suspend != NULL)
1163 pldata->phy_suspend(pldata, USB_PHY_ENABLED);
1164 if (dwc_otg_is_host_mode(core_if)) {
1165 if (core_if->hcd_cb && core_if->hcd_cb->stop)
1166 core_if->hcd_cb->stop(core_if->hcd_cb_p);
1168 /* soft disconnect */
1170 DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dctl);
1171 dctl.b.sftdiscon = 1;
1172 DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dctl,
1175 /* Clear any pending interrupts */
1176 DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, 0xFFFFFFFF);
1181 * This structure defines the methods to be called by a bus driver
1182 * during the lifecycle of a device on that bus. Both drivers and
1183 * devices are registered with a bus driver. The bus driver matches
1184 * devices to drivers based on information in the device and driver
1187 * The probe function is called when the bus driver matches a device
1188 * to this driver. The remove function is called when a device is
1189 * unregistered with the bus driver.
1191 #ifdef CONFIG_USB20_HOST
1192 static struct platform_driver dwc_host_driver = {
1194 .name = (char *)dwc_host20_driver_name,
1195 .of_match_table = of_match_ptr(usb20_host_of_match),
1197 .probe = host20_driver_probe,
1198 .remove = host20_driver_remove,
1199 .suspend = dwc_otg_driver_suspend,
1200 .resume = dwc_otg_driver_resume,
1204 #ifdef CONFIG_USB20_OTG
1206 * This function is called when a lm_device is unregistered with the
1207 * dwc_otg_driver. This happens, for example, when the rmmod command is
1208 * executed. The device may or may not be electrically present. If it is
1209 * present, the driver stops device processing. Any resources used on behalf
1210 * of this device are freed.
1214 static int otg20_driver_remove(struct platform_device *_dev)
1217 dwc_otg_device_t *otg_dev = dwc_get_device_platform_data(_dev);
1218 DWC_DEBUGPL(DBG_ANY, "%s(%p)\n", __func__, _dev);
1221 /* Memory allocation for the dwc_otg_device failed. */
1222 DWC_DEBUGPL(DBG_ANY, "%s: otg_dev NULL!\n", __func__);
1225 #ifndef DWC_DEVICE_ONLY
1229 DWC_DEBUGPL(DBG_ANY, "%s: otg_dev->hcd NULL!\n", __func__);
1234 #ifndef DWC_HOST_ONLY
1238 DWC_DEBUGPL(DBG_ANY, "%s: otg_dev->pcd NULL!\n", __func__);
1245 if (otg_dev->common_irq_installed) {
1246 /* free_irq(_dev->irq, otg_dev); */
1247 free_irq(platform_get_irq(_dev, 0), otg_dev);
1249 DWC_DEBUGPL(DBG_ANY, "%s: There is no installed irq!\n",
1254 if (otg_dev->core_if) {
1255 dwc_otg_cil_remove(otg_dev->core_if);
1257 DWC_DEBUGPL(DBG_ANY, "%s: otg_dev->core_if NULL!\n", __func__);
1262 * Remove the device attributes
1264 dwc_otg_attr_remove(_dev);
1267 * Return the memory.
1269 if (otg_dev->os_dep.base)
1270 iounmap(otg_dev->os_dep.base);
1274 * Clear the drvdata pointer.
1277 dwc_set_device_platform_data(_dev, 0);
1282 static const struct of_device_id usb20_otg_of_match[] = {
1284 .compatible = "rockchip,rk3188_usb20_otg",
1285 .data = &usb20otg_pdata_rk3188,
1288 .compatible = "rockchip,rk3288_usb20_otg",
1289 .data = &usb20otg_pdata_rk3288,
1292 .compatible = "rockchip,rk3036_usb20_otg",
1293 .data = &usb20otg_pdata_rk3036,
1296 .compatible = "rockchip,rk3126_usb20_otg",
1297 .data = &usb20otg_pdata_rk3126,
1302 MODULE_DEVICE_TABLE(of, usb20_otg_of_match);
1305 * This function is called when an lm_device is bound to a
1306 * dwc_otg_driver. It creates the driver components required to
1307 * control the device (CIL, HCD, and PCD) and it initializes the
1308 * device. The driver components are stored in a dwc_otg_device
1309 * structure. A reference to the dwc_otg_device is saved in the
1310 * lm_device. This allows the driver to access the dwc_otg_device
1311 * structure on subsequent calls to driver methods for this device.
1313 * @param _dev Bus device
1315 static int otg20_driver_probe(struct platform_device *_dev)
1320 struct resource *res_base;
1321 dwc_otg_device_t *dwc_otg_device;
1322 struct device *dev = &_dev->dev;
1323 struct device_node *node = _dev->dev.of_node;
1324 struct dwc_otg_platform_data *pldata;
1325 const struct of_device_id *match =
1326 of_match_device(of_match_ptr(usb20_otg_of_match), &_dev->dev);
1329 dev->platform_data = (void *)match->data;
1331 dev_err(dev, "usb20otg match failed\n");
1335 pldata = dev->platform_data;
1339 dev_err(dev, "device node not found\n");
1342 /*todo : move to usbdev_rk-XX.c */
1343 if (pldata->hw_init)
1346 if (pldata->clock_init) {
1347 pldata->clock_init(pldata);
1348 pldata->clock_enable(pldata, 1);
1351 if (pldata->phy_suspend)
1352 pldata->phy_suspend(pldata, USB_PHY_ENABLED);
1354 if (pldata->dwc_otg_uart_mode)
1355 pldata->dwc_otg_uart_mode(pldata, PHY_USB_MODE);
1357 /* do reset later, because reset need about
1358 * 100ms to ensure otg id state change.
1361 if(pldata->soft_reset)
1362 pldata->soft_reset();
1366 res_base = platform_get_resource(_dev, IORESOURCE_MEM, 0);
1368 dwc_otg_device = DWC_ALLOC(sizeof(dwc_otg_device_t));
1370 if (!dwc_otg_device) {
1371 dev_err(&_dev->dev, "kmalloc of dwc_otg_device failed\n");
1376 memset(dwc_otg_device, 0, sizeof(*dwc_otg_device));
1377 dwc_otg_device->os_dep.reg_offset = 0xFFFFFFFF;
1380 * Map the DWC_otg Core memory into virtual address space.
1383 dwc_otg_device->os_dep.base = devm_ioremap_resource(dev, res_base);
1385 if (!dwc_otg_device->os_dep.base) {
1386 dev_err(&_dev->dev, "ioremap() failed\n");
1387 DWC_FREE(dwc_otg_device);
1391 dev_dbg(&_dev->dev, "base=0x%08x\n",
1392 (unsigned)dwc_otg_device->os_dep.base);
1395 * Initialize driver data to point to the global DWC_otg
1399 g_otgdev = dwc_otg_device;
1400 pldata->privdata = dwc_otg_device;
1401 dwc_otg_device->pldata = pldata;
1403 dwc_set_device_platform_data(_dev, dwc_otg_device);
1405 dev_dbg(&_dev->dev, "dwc_otg_device=0x%p\n", dwc_otg_device);
1407 dwc_otg_device->core_if = dwc_otg_cil_init(dwc_otg_device->os_dep.base);
1408 if (!dwc_otg_device->core_if) {
1409 dev_err(&_dev->dev, "CIL initialization failed!\n");
1414 dwc_otg_device->core_if->otg_dev = dwc_otg_device;
1416 * Attempt to ensure this device is really a DWC_otg Controller.
1417 * Read and verify the SNPSID register contents. The value should be
1418 * 0x45F42XXX or 0x45F42XXX, which corresponds to either "OT2" or "OTG3",
1419 * as in "OTG version 2.XX" or "OTG version 3.XX".
1422 if (((dwc_otg_get_gsnpsid(dwc_otg_device->core_if) & 0xFFFFF000) !=
1424 && ((dwc_otg_get_gsnpsid(dwc_otg_device->core_if) & 0xFFFFF000) !=
1426 dev_err(&_dev->dev, "Bad value for SNPSID: 0x%08x\n",
1427 dwc_otg_get_gsnpsid(dwc_otg_device->core_if));
1433 * Validate parameter values.
1435 if (set_parameters(dwc_otg_device->core_if, dwc_otg_module_params)) {
1441 * Create Device Attributes in sysfs
1443 dwc_otg_attr_create(_dev);
1446 * Disable the global interrupt until all the interrupt
1447 * handlers are installed.
1449 dwc_otg_disable_global_interrupts(dwc_otg_device->core_if);
1452 * Install the interrupt handler for the common interrupts before
1453 * enabling common interrupts in core_init below.
1455 irq = platform_get_irq(_dev, 0);
1456 DWC_DEBUGPL(DBG_CIL, "registering (common) handler for irq%d\n", irq);
1457 retval = request_irq(irq, dwc_otg_common_irq,
1458 IRQF_SHARED, "dwc_otg", dwc_otg_device);
1460 DWC_ERROR("request of irq%d failed\n", irq);
1464 dwc_otg_device->common_irq_installed = 1;
1468 * Initialize the DWC_otg core.
1469 * In order to reduce the time of initialization,
1470 * we do core soft reset after connection detected.
1472 dwc_otg_core_init_no_reset(dwc_otg_device->core_if);
1475 * 0 - USB_MODE_NORMAL
1476 * 1 - USB_MODE_FORCE_HOST
1477 * 2 - USB_MODE_FORCE_DEVICE
1479 of_property_read_u32(node, "rockchip,usb-mode", &val);
1480 dwc_otg_device->core_if->usb_mode = val;
1482 #ifndef DWC_HOST_ONLY
1484 * Initialize the PCD
1486 retval = pcd_init(_dev);
1488 DWC_ERROR("pcd_init failed\n");
1489 dwc_otg_device->pcd = NULL;
1493 #ifndef DWC_DEVICE_ONLY
1495 * Initialize the HCD
1497 retval = otg20_hcd_init(_dev);
1499 DWC_ERROR("hcd_init failed\n");
1500 dwc_otg_device->hcd = NULL;
1505 * Enable the global interrupt after all the interrupt
1506 * handlers are installed if there is no ADP support else
1507 * perform initial actions required for Internal ADP logic.
1509 if (!dwc_otg_get_param_adp_enable(dwc_otg_device->core_if)) {
1510 if (pldata->phy_status == USB_PHY_ENABLED) {
1511 pldata->phy_suspend(pldata, USB_PHY_SUSPEND);
1513 pldata->clock_enable(pldata, 0);
1515 /* dwc_otg_enable_global_interrupts(dwc_otg_device->core_if); */
1517 dwc_otg_adp_start(dwc_otg_device->core_if,
1518 dwc_otg_is_host_mode(dwc_otg_device->
1524 otg20_driver_remove(_dev);
1527 if (pldata->clock_enable)
1528 pldata->clock_enable(pldata, 0);
1533 static struct platform_driver dwc_otg_driver = {
1535 .name = (char *)dwc_otg20_driver_name,
1536 .of_match_table = of_match_ptr(usb20_otg_of_match),
1538 .probe = otg20_driver_probe,
1539 .remove = otg20_driver_remove,
1540 .suspend = dwc_otg_driver_suspend,
1541 .resume = dwc_otg_driver_resume,
1542 .shutdown = dwc_otg_driver_shutdown,
1546 void rk_usb_power_up(void)
1548 struct dwc_otg_platform_data *pldata_otg;
1549 struct dwc_otg_platform_data *pldata_host;
1550 struct rkehci_platform_data *pldata_ehci;
1551 if (cpu_is_rk312x()) {
1552 pldata_otg = &usb20otg_pdata_rk3126;
1553 if (usb_to_uart_status)
1554 pldata_otg->dwc_otg_uart_mode(pldata_otg, PHY_UART_MODE);
1556 if (cpu_is_rk3288()) {
1557 #ifdef CONFIG_RK_USB_UART
1558 /* enable USB bypass UART function */
1559 writel_relaxed(0x00c00000 | usb_to_uart_status,
1560 RK_GRF_VIRT + RK3288_GRF_UOC0_CON3);
1563 /* unset siddq,the analog blocks are powered up */
1564 #ifdef CONFIG_USB20_OTG
1565 pldata_otg = &usb20otg_pdata_rk3288;
1567 if (pldata_otg->phy_status == USB_PHY_SUSPEND)
1568 writel_relaxed((0x01 << 13) << 16,
1570 RK3288_GRF_UOC0_CON0);
1573 #ifdef CONFIG_USB20_HOST
1574 pldata_host = &usb20host_pdata_rk3288;
1576 if (pldata_host->phy_status == USB_PHY_SUSPEND)
1577 writel_relaxed((0x01 << 13) << 16,
1579 RK3288_GRF_UOC2_CON0);
1582 #ifdef CONFIG_USB_EHCI_RK
1583 pldata_ehci = &rkehci_pdata_rk3288;
1585 if (pldata_ehci->phy_status == USB_PHY_SUSPEND)
1586 writel_relaxed((0x01 << 13) << 16,
1588 RK3288_GRF_UOC1_CON0);
1595 void rk_usb_power_down(void)
1597 struct dwc_otg_platform_data *pldata_otg;
1598 struct dwc_otg_platform_data *pldata_host;
1599 struct rkehci_platform_data *pldata_ehci;
1601 if (cpu_is_rk312x()) {
1602 pldata_otg = &usb20otg_pdata_rk3126;
1603 usb_to_uart_status = pldata_otg->get_status(USB_STATUS_UARTMODE);
1604 pldata_otg->dwc_otg_uart_mode(pldata_otg, PHY_USB_MODE);
1606 if (cpu_is_rk3288()) {
1607 #ifdef CONFIG_RK_USB_UART
1608 /* disable USB bypass UART function */
1609 usb_to_uart_status =
1610 readl_relaxed(RK_GRF_VIRT + RK3288_GRF_UOC0_CON3);
1611 writel_relaxed(0x00c00000, RK_GRF_VIRT + RK3288_GRF_UOC0_CON3);
1613 /* set siddq,the analog blocks are powered down
1615 * 1. Before asserting SIDDQ, ensure that VDATSRCENB0,
1616 * VDATDETENB0, DCDENB0, BYPASSSEL0, ADPPRBENB0,
1617 * and TESTBURNIN are set to 1'b0.
1618 * 2. Before asserting SIDDQ, ensure that phy enter suspend.*/
1619 #ifdef CONFIG_USB20_OTG
1620 pldata_otg = &usb20otg_pdata_rk3288;
1622 if (pldata_otg->phy_status == USB_PHY_SUSPEND)
1623 writel_relaxed((0x01 << 13) |
1624 ((0x01 << 13) << 16),
1626 RK3288_GRF_UOC0_CON0);
1629 #ifdef CONFIG_USB20_HOST
1630 pldata_host = &usb20host_pdata_rk3288;
1632 if (pldata_host->phy_status == USB_PHY_SUSPEND)
1633 writel_relaxed((0x01 << 13) |
1634 ((0x01 << 13) << 16),
1636 RK3288_GRF_UOC2_CON0);
1639 #ifdef CONFIG_USB_EHCI_RK
1640 pldata_ehci = &rkehci_pdata_rk3288;
1642 if (pldata_ehci->phy_status == USB_PHY_SUSPEND)
1643 writel_relaxed((0x01 << 13) |
1644 ((0x01 << 13) << 16),
1646 RK3288_GRF_UOC1_CON0);
1652 EXPORT_SYMBOL(rk_usb_power_up);
1653 EXPORT_SYMBOL(rk_usb_power_down);
1655 * This function is called when the dwc_otg_driver is installed with the
1656 * insmod command. It registers the dwc_otg_driver structure with the
1657 * appropriate bus driver. This will cause the dwc_otg_driver_probe function
1658 * to be called. In addition, the bus driver will automatically expose
1659 * attributes defined for the device and driver in the special sysfs file
1664 static int __init dwc_otg_driver_init(void)
1669 #ifdef CONFIG_USB20_OTG
1670 /* register otg20 */
1671 printk(KERN_INFO "%s: version %s\n", dwc_otg20_driver_name,
1672 DWC_DRIVER_VERSION);
1674 retval = platform_driver_register(&dwc_otg_driver);
1676 printk(KERN_ERR "%s retval=%d\n", __func__, retval);
1681 driver_create_file(&dwc_otg_driver.driver, &driver_attr_version);
1683 driver_create_file(&dwc_otg_driver.driver, &driver_attr_debuglevel);
1685 driver_create_file(&dwc_otg_driver.driver,
1686 &driver_attr_dwc_otg_conn_en);
1688 driver_create_file(&dwc_otg_driver.driver,
1689 &driver_attr_vbus_status);
1691 driver_create_file(&dwc_otg_driver.driver,
1692 &driver_attr_force_usb_mode);
1694 driver_create_file(&dwc_otg_driver.driver,
1695 &driver_attr_op_state);
1699 /* register host20 */
1700 #ifdef CONFIG_USB20_HOST
1701 printk(KERN_INFO "%s: version %s\n", dwc_host20_driver_name,
1702 DWC_DRIVER_VERSION);
1704 retval = platform_driver_register(&dwc_host_driver);
1706 printk(KERN_ERR "%s retval=%d\n", __func__, retval);
1711 driver_create_file(&dwc_host_driver.driver, &driver_attr_version);
1713 driver_create_file(&dwc_host_driver.driver,
1714 &driver_attr_debuglevel);
1719 module_init(dwc_otg_driver_init);
1722 * This function is called when the driver is removed from the kernel
1723 * with the rmmod command. The driver unregisters itself with its bus
1727 static void __exit dwc_otg_driver_cleanup(void)
1729 printk(KERN_DEBUG "dwc_otg_driver_cleanup()\n");
1731 #ifdef CONFIG_USB20_HOST
1733 driver_remove_file(&dwc_host_driver.driver, &driver_attr_debuglevel);
1734 driver_remove_file(&dwc_host_driver.driver, &driver_attr_version);
1735 platform_driver_unregister(&dwc_host_driver);
1736 printk(KERN_INFO "%s module removed\n", dwc_host20_driver_name);
1739 #ifdef CONFIG_USB20_OTG
1741 driver_remove_file(&dwc_otg_driver.driver,
1742 &driver_attr_dwc_otg_conn_en);
1743 driver_remove_file(&dwc_otg_driver.driver, &driver_attr_debuglevel);
1744 driver_remove_file(&dwc_otg_driver.driver, &driver_attr_version);
1745 driver_remove_file(&dwc_otg_driver.driver, &driver_attr_vbus_status);
1746 driver_remove_file(&dwc_otg_driver.driver, &driver_attr_force_usb_mode);
1747 driver_remove_file(&dwc_otg_driver.driver, &driver_attr_op_state);
1748 platform_driver_unregister(&dwc_otg_driver);
1749 printk(KERN_INFO "%s module removed\n", dwc_otg20_driver_name);
1753 module_exit(dwc_otg_driver_cleanup);
1755 MODULE_DESCRIPTION(DWC_DRIVER_DESC);
1756 MODULE_AUTHOR("Synopsys Inc.");
1757 MODULE_LICENSE("GPL");
1759 module_param_named(otg_cap, dwc_otg_module_params.otg_cap, int, 0444);
1760 MODULE_PARM_DESC(otg_cap, "OTG Capabilities 0=HNP&SRP 1=SRP Only 2=None");
1761 module_param_named(opt, dwc_otg_module_params.opt, int, 0444);
1762 MODULE_PARM_DESC(opt, "OPT Mode");
1763 module_param_named(dma_enable, dwc_otg_module_params.dma_enable, int, 0444);
1764 MODULE_PARM_DESC(dma_enable, "DMA Mode 0=Slave 1=DMA enabled");
1766 module_param_named(dma_desc_enable, dwc_otg_module_params.dma_desc_enable, int,
1768 MODULE_PARM_DESC(dma_desc_enable,
1769 "DMA Desc Mode 0=Address DMA 1=DMA Descriptor enabled");
1771 module_param_named(dma_burst_size, dwc_otg_module_params.dma_burst_size, int,
1773 MODULE_PARM_DESC(dma_burst_size,
1774 "DMA Burst Size 1, 4, 8, 16, 32, 64, 128, 256");
1775 module_param_named(speed, dwc_otg_module_params.speed, int, 0444);
1776 MODULE_PARM_DESC(speed, "Speed 0=High Speed 1=Full Speed");
1777 module_param_named(host_support_fs_ls_low_power,
1778 dwc_otg_module_params.host_support_fs_ls_low_power, int,
1780 MODULE_PARM_DESC(host_support_fs_ls_low_power,
1781 "Support Low Power w/FS or LS 0=Support 1=Don't Support");
1782 module_param_named(host_ls_low_power_phy_clk,
1783 dwc_otg_module_params.host_ls_low_power_phy_clk, int, 0444);
1784 MODULE_PARM_DESC(host_ls_low_power_phy_clk,
1785 "Low Speed Low Power Clock 0=48Mhz 1=6Mhz");
1786 module_param_named(enable_dynamic_fifo,
1787 dwc_otg_module_params.enable_dynamic_fifo, int, 0444);
1788 MODULE_PARM_DESC(enable_dynamic_fifo, "0=cC Setting 1=Allow Dynamic Sizing");
1789 module_param_named(data_fifo_size, dwc_otg_module_params.data_fifo_size, int,
1791 MODULE_PARM_DESC(data_fifo_size,
1792 "Total number of words in the data FIFO memory 32-32768");
1793 module_param_named(dev_rx_fifo_size, dwc_otg_module_params.dev_rx_fifo_size,
1795 MODULE_PARM_DESC(dev_rx_fifo_size, "Number of words in the Rx FIFO 16-32768");
1796 module_param_named(dev_nperio_tx_fifo_size,
1797 dwc_otg_module_params.dev_nperio_tx_fifo_size, int, 0444);
1798 MODULE_PARM_DESC(dev_nperio_tx_fifo_size,
1799 "Number of words in the non-periodic Tx FIFO 16-32768");
1800 module_param_named(dev_perio_tx_fifo_size_1,
1801 dwc_otg_module_params.dev_perio_tx_fifo_size[0], int, 0444);
1802 MODULE_PARM_DESC(dev_perio_tx_fifo_size_1,
1803 "Number of words in the periodic Tx FIFO 4-768");
1804 module_param_named(dev_perio_tx_fifo_size_2,
1805 dwc_otg_module_params.dev_perio_tx_fifo_size[1], int, 0444);
1806 MODULE_PARM_DESC(dev_perio_tx_fifo_size_2,
1807 "Number of words in the periodic Tx FIFO 4-768");
1808 module_param_named(dev_perio_tx_fifo_size_3,
1809 dwc_otg_module_params.dev_perio_tx_fifo_size[2], int, 0444);
1810 MODULE_PARM_DESC(dev_perio_tx_fifo_size_3,
1811 "Number of words in the periodic Tx FIFO 4-768");
1812 module_param_named(dev_perio_tx_fifo_size_4,
1813 dwc_otg_module_params.dev_perio_tx_fifo_size[3], int, 0444);
1814 MODULE_PARM_DESC(dev_perio_tx_fifo_size_4,
1815 "Number of words in the periodic Tx FIFO 4-768");
1816 module_param_named(dev_perio_tx_fifo_size_5,
1817 dwc_otg_module_params.dev_perio_tx_fifo_size[4], int, 0444);
1818 MODULE_PARM_DESC(dev_perio_tx_fifo_size_5,
1819 "Number of words in the periodic Tx FIFO 4-768");
1820 module_param_named(dev_perio_tx_fifo_size_6,
1821 dwc_otg_module_params.dev_perio_tx_fifo_size[5], int, 0444);
1822 MODULE_PARM_DESC(dev_perio_tx_fifo_size_6,
1823 "Number of words in the periodic Tx FIFO 4-768");
1824 module_param_named(dev_perio_tx_fifo_size_7,
1825 dwc_otg_module_params.dev_perio_tx_fifo_size[6], int, 0444);
1826 MODULE_PARM_DESC(dev_perio_tx_fifo_size_7,
1827 "Number of words in the periodic Tx FIFO 4-768");
1828 module_param_named(dev_perio_tx_fifo_size_8,
1829 dwc_otg_module_params.dev_perio_tx_fifo_size[7], int, 0444);
1830 MODULE_PARM_DESC(dev_perio_tx_fifo_size_8,
1831 "Number of words in the periodic Tx FIFO 4-768");
1832 module_param_named(dev_perio_tx_fifo_size_9,
1833 dwc_otg_module_params.dev_perio_tx_fifo_size[8], int, 0444);
1834 MODULE_PARM_DESC(dev_perio_tx_fifo_size_9,
1835 "Number of words in the periodic Tx FIFO 4-768");
1836 module_param_named(dev_perio_tx_fifo_size_10,
1837 dwc_otg_module_params.dev_perio_tx_fifo_size[9], int, 0444);
1838 MODULE_PARM_DESC(dev_perio_tx_fifo_size_10,
1839 "Number of words in the periodic Tx FIFO 4-768");
1840 module_param_named(dev_perio_tx_fifo_size_11,
1841 dwc_otg_module_params.dev_perio_tx_fifo_size[10], int, 0444);
1842 MODULE_PARM_DESC(dev_perio_tx_fifo_size_11,
1843 "Number of words in the periodic Tx FIFO 4-768");
1844 module_param_named(dev_perio_tx_fifo_size_12,
1845 dwc_otg_module_params.dev_perio_tx_fifo_size[11], int, 0444);
1846 MODULE_PARM_DESC(dev_perio_tx_fifo_size_12,
1847 "Number of words in the periodic Tx FIFO 4-768");
1848 module_param_named(dev_perio_tx_fifo_size_13,
1849 dwc_otg_module_params.dev_perio_tx_fifo_size[12], int, 0444);
1850 MODULE_PARM_DESC(dev_perio_tx_fifo_size_13,
1851 "Number of words in the periodic Tx FIFO 4-768");
1852 module_param_named(dev_perio_tx_fifo_size_14,
1853 dwc_otg_module_params.dev_perio_tx_fifo_size[13], int, 0444);
1854 MODULE_PARM_DESC(dev_perio_tx_fifo_size_14,
1855 "Number of words in the periodic Tx FIFO 4-768");
1856 module_param_named(dev_perio_tx_fifo_size_15,
1857 dwc_otg_module_params.dev_perio_tx_fifo_size[14], int, 0444);
1858 MODULE_PARM_DESC(dev_perio_tx_fifo_size_15,
1859 "Number of words in the periodic Tx FIFO 4-768");
1860 module_param_named(host_rx_fifo_size, dwc_otg_module_params.host_rx_fifo_size,
1862 MODULE_PARM_DESC(host_rx_fifo_size, "Number of words in the Rx FIFO 16-32768");
1863 module_param_named(host_nperio_tx_fifo_size,
1864 dwc_otg_module_params.host_nperio_tx_fifo_size, int, 0444);
1865 MODULE_PARM_DESC(host_nperio_tx_fifo_size,
1866 "Number of words in the non-periodic Tx FIFO 16-32768");
1867 module_param_named(host_perio_tx_fifo_size,
1868 dwc_otg_module_params.host_perio_tx_fifo_size, int, 0444);
1869 MODULE_PARM_DESC(host_perio_tx_fifo_size,
1870 "Number of words in the host periodic Tx FIFO 16-32768");
1871 module_param_named(max_transfer_size, dwc_otg_module_params.max_transfer_size,
1873 /** @todo Set the max to 512K, modify checks */
1874 MODULE_PARM_DESC(max_transfer_size,
1875 "The maximum transfer size supported in bytes 2047-65535");
1876 module_param_named(max_packet_count, dwc_otg_module_params.max_packet_count,
1878 MODULE_PARM_DESC(max_packet_count,
1879 "The maximum number of packets in a transfer 15-511");
1880 module_param_named(host_channels, dwc_otg_module_params.host_channels, int,
1882 MODULE_PARM_DESC(host_channels,
1883 "The number of host channel registers to use 1-16");
1884 module_param_named(dev_endpoints, dwc_otg_module_params.dev_endpoints, int,
1886 MODULE_PARM_DESC(dev_endpoints,
1887 "The number of endpoints in addition to EP0 available for device mode 1-15");
1888 module_param_named(phy_type, dwc_otg_module_params.phy_type, int, 0444);
1889 MODULE_PARM_DESC(phy_type, "0=Reserved 1=UTMI+ 2=ULPI");
1890 module_param_named(phy_utmi_width, dwc_otg_module_params.phy_utmi_width, int,
1892 MODULE_PARM_DESC(phy_utmi_width, "Specifies the UTMI+ Data Width 8 or 16 bits");
1893 module_param_named(phy_ulpi_ddr, dwc_otg_module_params.phy_ulpi_ddr, int, 0444);
1894 MODULE_PARM_DESC(phy_ulpi_ddr,
1895 "ULPI at double or single data rate 0=Single 1=Double");
1896 module_param_named(phy_ulpi_ext_vbus, dwc_otg_module_params.phy_ulpi_ext_vbus,
1898 MODULE_PARM_DESC(phy_ulpi_ext_vbus,
1899 "ULPI PHY using internal or external vbus 0=Internal");
1900 module_param_named(i2c_enable, dwc_otg_module_params.i2c_enable, int, 0444);
1901 MODULE_PARM_DESC(i2c_enable, "FS PHY Interface");
1902 module_param_named(ulpi_fs_ls, dwc_otg_module_params.ulpi_fs_ls, int, 0444);
1903 MODULE_PARM_DESC(ulpi_fs_ls, "ULPI PHY FS/LS mode only");
1904 module_param_named(ts_dline, dwc_otg_module_params.ts_dline, int, 0444);
1905 MODULE_PARM_DESC(ts_dline, "Term select Dline pulsing for all PHYs");
1906 module_param_named(debug, g_dbg_lvl, int, 0444);
1907 MODULE_PARM_DESC(debug, "");
1909 module_param_named(en_multiple_tx_fifo,
1910 dwc_otg_module_params.en_multiple_tx_fifo, int, 0444);
1911 MODULE_PARM_DESC(en_multiple_tx_fifo,
1912 "Dedicated Non Periodic Tx FIFOs 0=disabled 1=enabled");
1913 module_param_named(dev_tx_fifo_size_1,
1914 dwc_otg_module_params.dev_tx_fifo_size[0], int, 0444);
1915 MODULE_PARM_DESC(dev_tx_fifo_size_1, "Number of words in the Tx FIFO 4-768");
1916 module_param_named(dev_tx_fifo_size_2,
1917 dwc_otg_module_params.dev_tx_fifo_size[1], int, 0444);
1918 MODULE_PARM_DESC(dev_tx_fifo_size_2, "Number of words in the Tx FIFO 4-768");
1919 module_param_named(dev_tx_fifo_size_3,
1920 dwc_otg_module_params.dev_tx_fifo_size[2], int, 0444);
1921 MODULE_PARM_DESC(dev_tx_fifo_size_3, "Number of words in the Tx FIFO 4-768");
1922 module_param_named(dev_tx_fifo_size_4,
1923 dwc_otg_module_params.dev_tx_fifo_size[3], int, 0444);
1924 MODULE_PARM_DESC(dev_tx_fifo_size_4, "Number of words in the Tx FIFO 4-768");
1925 module_param_named(dev_tx_fifo_size_5,
1926 dwc_otg_module_params.dev_tx_fifo_size[4], int, 0444);
1927 MODULE_PARM_DESC(dev_tx_fifo_size_5, "Number of words in the Tx FIFO 4-768");
1928 module_param_named(dev_tx_fifo_size_6,
1929 dwc_otg_module_params.dev_tx_fifo_size[5], int, 0444);
1930 MODULE_PARM_DESC(dev_tx_fifo_size_6, "Number of words in the Tx FIFO 4-768");
1931 module_param_named(dev_tx_fifo_size_7,
1932 dwc_otg_module_params.dev_tx_fifo_size[6], int, 0444);
1933 MODULE_PARM_DESC(dev_tx_fifo_size_7, "Number of words in the Tx FIFO 4-768");
1934 module_param_named(dev_tx_fifo_size_8,
1935 dwc_otg_module_params.dev_tx_fifo_size[7], int, 0444);
1936 MODULE_PARM_DESC(dev_tx_fifo_size_8, "Number of words in the Tx FIFO 4-768");
1937 module_param_named(dev_tx_fifo_size_9,
1938 dwc_otg_module_params.dev_tx_fifo_size[8], int, 0444);
1939 MODULE_PARM_DESC(dev_tx_fifo_size_9, "Number of words in the Tx FIFO 4-768");
1940 module_param_named(dev_tx_fifo_size_10,
1941 dwc_otg_module_params.dev_tx_fifo_size[9], int, 0444);
1942 MODULE_PARM_DESC(dev_tx_fifo_size_10, "Number of words in the Tx FIFO 4-768");
1943 module_param_named(dev_tx_fifo_size_11,
1944 dwc_otg_module_params.dev_tx_fifo_size[10], int, 0444);
1945 MODULE_PARM_DESC(dev_tx_fifo_size_11, "Number of words in the Tx FIFO 4-768");
1946 module_param_named(dev_tx_fifo_size_12,
1947 dwc_otg_module_params.dev_tx_fifo_size[11], int, 0444);
1948 MODULE_PARM_DESC(dev_tx_fifo_size_12, "Number of words in the Tx FIFO 4-768");
1949 module_param_named(dev_tx_fifo_size_13,
1950 dwc_otg_module_params.dev_tx_fifo_size[12], int, 0444);
1951 MODULE_PARM_DESC(dev_tx_fifo_size_13, "Number of words in the Tx FIFO 4-768");
1952 module_param_named(dev_tx_fifo_size_14,
1953 dwc_otg_module_params.dev_tx_fifo_size[13], int, 0444);
1954 MODULE_PARM_DESC(dev_tx_fifo_size_14, "Number of words in the Tx FIFO 4-768");
1955 module_param_named(dev_tx_fifo_size_15,
1956 dwc_otg_module_params.dev_tx_fifo_size[14], int, 0444);
1957 MODULE_PARM_DESC(dev_tx_fifo_size_15, "Number of words in the Tx FIFO 4-768");
1959 module_param_named(thr_ctl, dwc_otg_module_params.thr_ctl, int, 0444);
1960 MODULE_PARM_DESC(thr_ctl,
1961 "Thresholding enable flag bit 0 - non ISO Tx thr., 1 - ISO Tx thr., 2 - Rx thr.- bit 0=disabled 1=enabled");
1962 module_param_named(tx_thr_length, dwc_otg_module_params.tx_thr_length, int,
1964 MODULE_PARM_DESC(tx_thr_length, "Tx Threshold length in 32 bit DWORDs");
1965 module_param_named(rx_thr_length, dwc_otg_module_params.rx_thr_length, int,
1967 MODULE_PARM_DESC(rx_thr_length, "Rx Threshold length in 32 bit DWORDs");
1969 module_param_named(pti_enable, dwc_otg_module_params.pti_enable, int, 0444);
1970 module_param_named(mpi_enable, dwc_otg_module_params.mpi_enable, int, 0444);
1971 module_param_named(lpm_enable, dwc_otg_module_params.lpm_enable, int, 0444);
1972 MODULE_PARM_DESC(lpm_enable, "LPM Enable 0=LPM Disabled 1=LPM Enabled");
1974 module_param_named(besl_enable, dwc_otg_module_params.besl_enable, int, 0444);
1975 MODULE_PARM_DESC(besl_enable, "BESL Enable 0=BESL Disabled 1=BESL Enabled");
1976 module_param_named(baseline_besl, dwc_otg_module_params.baseline_besl, int,
1978 MODULE_PARM_DESC(baseline_besl, "Set the baseline besl value");
1979 module_param_named(deep_besl, dwc_otg_module_params.deep_besl, int, 0444);
1980 MODULE_PARM_DESC(deep_besl, "Set the deep besl value");
1982 module_param_named(ic_usb_cap, dwc_otg_module_params.ic_usb_cap, int, 0444);
1983 MODULE_PARM_DESC(ic_usb_cap,
1984 "IC_USB Capability 0=IC_USB Disabled 1=IC_USB Enabled");
1985 module_param_named(ahb_thr_ratio, dwc_otg_module_params.ahb_thr_ratio, int,
1987 MODULE_PARM_DESC(ahb_thr_ratio, "AHB Threshold Ratio");
1988 module_param_named(power_down, dwc_otg_module_params.power_down, int, 0444);
1989 MODULE_PARM_DESC(power_down, "Power Down Mode");
1990 module_param_named(reload_ctl, dwc_otg_module_params.reload_ctl, int, 0444);
1991 MODULE_PARM_DESC(reload_ctl, "HFIR Reload Control");
1992 module_param_named(dev_out_nak, dwc_otg_module_params.dev_out_nak, int, 0444);
1993 MODULE_PARM_DESC(dev_out_nak, "Enable Device OUT NAK");
1994 module_param_named(cont_on_bna, dwc_otg_module_params.cont_on_bna, int, 0444);
1995 MODULE_PARM_DESC(cont_on_bna, "Enable Enable Continue on BNA");
1996 module_param_named(ahb_single, dwc_otg_module_params.ahb_single, int, 0444);
1997 MODULE_PARM_DESC(ahb_single, "Enable AHB Single Support");
1998 module_param_named(adp_enable, dwc_otg_module_params.adp_enable, int, 0444);
1999 MODULE_PARM_DESC(adp_enable, "ADP Enable 0=ADP Disabled 1=ADP Enabled");
2000 module_param_named(otg_ver, dwc_otg_module_params.otg_ver, int, 0444);
2001 MODULE_PARM_DESC(otg_ver, "OTG revision supported 0=OTG 1.3 1=OTG 2.0");
2003 /** @page "Module Parameters"
2005 * The following parameters may be specified when starting the module.
2006 * These parameters define how the DWC_otg controller should be
2007 * configured. Parameter values are passed to the CIL initialization
2008 * function dwc_otg_cil_init
2010 * Example: <code>modprobe dwc_otg speed=1 otg_cap=1</code>
2014 <tr><td>Parameter Name</td><td>Meaning</td></tr>
2018 <td>Specifies the OTG capabilities. The driver will automatically detect the
2019 value for this parameter if none is specified.
2020 - 0: HNP and SRP capable (default, if available)
2021 - 1: SRP Only capable
2022 - 2: No HNP/SRP capable
2027 <td>Specifies whether to use slave or DMA mode for accessing the data FIFOs.
2028 The driver will automatically detect the value for this parameter if none is
2031 - 1: DMA (default, if available)
2035 <td>dma_burst_size</td>
2036 <td>The DMA Burst size (applicable only for External DMA Mode).
2037 - Values: 1, 4, 8 16, 32, 64, 128, 256 (default 32)
2042 <td>Specifies the maximum speed of operation in host and device mode. The
2043 actual speed depends on the speed of the attached device and the value of
2045 - 0: High Speed (default)
2050 <td>host_support_fs_ls_low_power</td>
2051 <td>Specifies whether low power mode is supported when attached to a Full
2052 Speed or Low Speed device in host mode.
2053 - 0: Don't support low power mode (default)
2054 - 1: Support low power mode
2058 <td>host_ls_low_power_phy_clk</td>
2059 <td>Specifies the PHY clock rate in low power mode when connected to a Low
2060 Speed device in host mode. This parameter is applicable only if
2061 HOST_SUPPORT_FS_LS_LOW_POWER is enabled.
2062 - 0: 48 MHz (default)
2067 <td>enable_dynamic_fifo</td>
2068 <td> Specifies whether FIFOs may be resized by the driver software.
2069 - 0: Use cC FIFO size parameters
2070 - 1: Allow dynamic FIFO sizing (default)
2074 <td>data_fifo_size</td>
2075 <td>Total number of 4-byte words in the data FIFO memory. This memory
2076 includes the Rx FIFO, non-periodic Tx FIFO, and periodic Tx FIFOs.
2077 - Values: 32 to 32768 (default 8192)
2079 Note: The total FIFO memory depth in the FPGA configuration is 8192.
2083 <td>dev_rx_fifo_size</td>
2084 <td>Number of 4-byte words in the Rx FIFO in device mode when dynamic
2085 FIFO sizing is enabled.
2086 - Values: 16 to 32768 (default 1064)
2090 <td>dev_nperio_tx_fifo_size</td>
2091 <td>Number of 4-byte words in the non-periodic Tx FIFO in device mode when
2092 dynamic FIFO sizing is enabled.
2093 - Values: 16 to 32768 (default 1024)
2097 <td>dev_perio_tx_fifo_size_n (n = 1 to 15)</td>
2098 <td>Number of 4-byte words in each of the periodic Tx FIFOs in device mode
2099 when dynamic FIFO sizing is enabled.
2100 - Values: 4 to 768 (default 256)
2104 <td>host_rx_fifo_size</td>
2105 <td>Number of 4-byte words in the Rx FIFO in host mode when dynamic FIFO
2107 - Values: 16 to 32768 (default 1024)
2111 <td>host_nperio_tx_fifo_size</td>
2112 <td>Number of 4-byte words in the non-periodic Tx FIFO in host mode when
2113 dynamic FIFO sizing is enabled in the core.
2114 - Values: 16 to 32768 (default 1024)
2118 <td>host_perio_tx_fifo_size</td>
2119 <td>Number of 4-byte words in the host periodic Tx FIFO when dynamic FIFO
2121 - Values: 16 to 32768 (default 1024)
2125 <td>max_transfer_size</td>
2126 <td>The maximum transfer size supported in bytes.
2127 - Values: 2047 to 65,535 (default 65,535)
2131 <td>max_packet_count</td>
2132 <td>The maximum number of packets in a transfer.
2133 - Values: 15 to 511 (default 511)
2137 <td>host_channels</td>
2138 <td>The number of host channel registers to use.
2139 - Values: 1 to 16 (default 12)
2141 Note: The FPGA configuration supports a maximum of 12 host channels.
2145 <td>dev_endpoints</td>
2146 <td>The number of endpoints in addition to EP0 available for device mode
2148 - Values: 1 to 15 (default 6 IN and OUT)
2150 Note: The FPGA configuration supports a maximum of 6 IN and OUT endpoints in
2156 <td>Specifies the type of PHY interface to use. By default, the driver will
2157 automatically detect the phy_type.
2159 - 1: UTMI+ (default, if available)
2164 <td>phy_utmi_width</td>
2165 <td>Specifies the UTMI+ Data Width. This parameter is applicable for a
2166 phy_type of UTMI+. Also, this parameter is applicable only if the
2167 OTG_HSPHY_WIDTH cC parameter was set to "8 and 16 bits", meaning that the
2168 core has been configured to work at either data path width.
2169 - Values: 8 or 16 bits (default 16)
2173 <td>phy_ulpi_ddr</td>
2174 <td>Specifies whether the ULPI operates at double or single data rate. This
2175 parameter is only applicable if phy_type is ULPI.
2176 - 0: single data rate ULPI interface with 8 bit wide data bus (default)
2177 - 1: double data rate ULPI interface with 4 bit wide data bus
2182 <td>Specifies whether to use the I2C interface for full speed PHY. This
2183 parameter is only applicable if PHY_TYPE is FS.
2184 - 0: Disabled (default)
2190 <td>Specifies whether to use ULPI FS/LS mode only.
2191 - 0: Disabled (default)
2197 <td>Specifies whether term select D-Line pulsing for all PHYs is enabled.
2198 - 0: Disabled (default)
2203 <td>en_multiple_tx_fifo</td>
2204 <td>Specifies whether dedicatedto tx fifos are enabled for non periodic IN EPs.
2205 The driver will automatically detect the value for this parameter if none is
2208 - 1: Enabled (default, if available)
2212 <td>dev_tx_fifo_size_n (n = 1 to 15)</td>
2213 <td>Number of 4-byte words in each of the Tx FIFOs in device mode
2214 when dynamic FIFO sizing is enabled.
2215 - Values: 4 to 768 (default 256)
2219 <td>tx_thr_length</td>
2220 <td>Transmit Threshold length in 32 bit double words
2221 - Values: 8 to 128 (default 64)
2225 <td>rx_thr_length</td>
2226 <td>Receive Threshold length in 32 bit double words
2227 - Values: 8 to 128 (default 64)
2232 <td>Specifies whether to enable Thresholding for Device mode. Bits 0, 1, 2 of
2233 this parmater specifies if thresholding is enabled for non-Iso Tx, Iso Tx and
2234 Rx transfers accordingly.
2235 The driver will automatically detect the value for this parameter if none is
2237 - Values: 0 to 7 (default 0)
2238 Bit values indicate:
2239 - 0: Thresholding disabled
2240 - 1: Thresholding enabled
2244 <td>dma_desc_enable</td>
2245 <td>Specifies whether to enable Descriptor DMA mode.
2246 The driver will automatically detect the value for this parameter if none is
2248 - 0: Descriptor DMA disabled
2249 - 1: Descriptor DMA (default, if available)
2254 <td>Specifies whether to enable MPI enhancement mode.
2255 The driver will automatically detect the value for this parameter if none is
2257 - 0: MPI disabled (default)
2263 <td>Specifies whether to enable PTI enhancement support.
2264 The driver will automatically detect the value for this parameter if none is
2266 - 0: PTI disabled (default)
2272 <td>Specifies whether to enable LPM support.
2273 The driver will automatically detect the value for this parameter if none is
2276 - 1: LPM enable (default, if available)
2280 <td>besl_enable</td>
2281 <td>Specifies whether to enable LPM Errata support.
2282 The driver will automatically detect the value for this parameter if none is
2284 - 0: LPM Errata disabled (default)
2285 - 1: LPM Errata enable
2289 <td>baseline_besl</td>
2290 <td>Specifies the baseline besl value.
2291 - Values: 0 to 15 (default 0)
2296 <td>Specifies the deep besl value.
2297 - Values: 0 to 15 (default 15)
2302 <td>Specifies whether to enable IC_USB capability.
2303 The driver will automatically detect the value for this parameter if none is
2305 - 0: IC_USB disabled (default, if available)
2310 <td>ahb_thr_ratio</td>
2311 <td>Specifies AHB Threshold ratio.
2312 - Values: 0 to 3 (default 0)
2317 <td>Specifies Power Down(Hibernation) Mode.
2318 The driver will automatically detect the value for this parameter if none is
2320 - 0: Power Down disabled (default)
2321 - 2: Power Down enabled
2326 <td>Specifies whether dynamic reloading of the HFIR register is allowed during
2327 run time. The driver will automatically detect the value for this parameter if
2328 none is specified. In case the HFIR value is reloaded when HFIR.RldCtrl == 1'b0
2329 the core might misbehave.
2330 - 0: Reload Control disabled (default)
2331 - 1: Reload Control enabled
2335 <td>dev_out_nak</td>
2336 <td>Specifies whether Device OUT NAK enhancement enabled or no.
2337 The driver will automatically detect the value for this parameter if
2338 none is specified. This parameter is valid only when OTG_EN_DESC_DMA == 1
\92b1.
2339 - 0: The core does not set NAK after Bulk OUT transfer complete (default)
2340 - 1: The core sets NAK after Bulk OUT transfer complete
2344 <td>cont_on_bna</td>
2345 <td>Specifies whether Enable Continue on BNA enabled or no.
2346 After receiving BNA interrupt the core disables the endpoint,when the
2347 endpoint is re-enabled by the application the
2348 - 0: Core starts processing from the DOEPDMA descriptor (default)
2349 - 1: Core starts processing from the descriptor which received the BNA.
2350 This parameter is valid only when OTG_EN_DESC_DMA == 1
\92b1.
2355 <td>This bit when programmed supports SINGLE transfers for remainder data
2356 in a transfer for DMA mode of operation.
2357 - 0: The remainder data will be sent using INCR burst size (default)
2358 - 1: The remainder data will be sent using SINGLE burst size.
2363 <td>Specifies whether ADP feature is enabled.
2364 The driver will automatically detect the value for this parameter if none is
2366 - 0: ADP feature disabled (default)
2367 - 1: ADP feature enabled
2372 <td>Specifies whether OTG is performing as USB OTG Revision 2.0 or Revision 1.3
2374 - 0: OTG 2.0 support disabled (default)
2375 - 1: OTG 2.0 support enabled