1 /* ==========================================================================
2 * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_driver.c $
7 * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
8 * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
9 * otherwise expressly agreed to in writing between Synopsys and you.
11 * The Software IS NOT an item of Licensed Software or Licensed Product under
12 * any End User Software License Agreement or Agreement for Licensed Product
13 * with Synopsys or any supplement thereto. You are permitted to use and
14 * redistribute this Software in source and binary forms, with or without
15 * modification, provided that redistributions of source code must retain this
16 * notice. You may not view, use, disclose, copy or distribute this file or
17 * any information contained herein except pursuant to this license grant from
18 * Synopsys. If you do not agree with this notice, including the disclaimer
19 * below, then you are not authorized to use the Software.
21 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
25 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
26 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
27 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
28 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
32 * ========================================================================== */
35 * The dwc_otg_driver module provides the initialization and cleanup entry
36 * points for the DWC_otg driver. This module will be dynamically installed
37 * after Linux is booted using the insmod command. When the module is
38 * installed, the dwc_otg_driver_init function is called. When the module is
39 * removed (using rmmod), the dwc_otg_driver_cleanup function is called.
41 * This module also defines a data structure for the dwc_otg_driver, which is
42 * used in conjunction with the standard ARM lm_device structure. These
43 * structures allow the OTG driver to comply with the standard Linux driver
44 * model in which devices and drivers are registered with a bus driver. This
45 * has the benefit that Linux can expose attributes of the driver and device
46 * in its special sysfs file system. Users can then read or write files in
47 * this file system to perform diagnostics on the driver components or the
51 #include "dwc_otg_os_dep.h"
52 #include "common_port/dwc_os.h"
53 #include "dwc_otg_dbg.h"
54 #include "dwc_otg_driver.h"
55 #include "dwc_otg_attr.h"
56 #include "dwc_otg_core_if.h"
57 #include "dwc_otg_pcd_if.h"
58 #include "dwc_otg_hcd_if.h"
59 #include "dwc_otg_cil.h"
60 #include "dwc_otg_pcd.h"
62 #include "usbdev_rk.h"
64 #define DWC_DRIVER_VERSION "3.10a 21-DEC-2012"
65 #define DWC_DRIVER_DESC "HS OTG USB Controller driver"
67 static const char dwc_host20_driver_name[] = "usb20_host";
68 static const char dwc_otg20_driver_name[] = "usb20_otg";
70 dwc_otg_device_t *g_otgdev;
72 extern int pcd_init(struct platform_device *_dev);
73 extern int otg20_hcd_init(struct platform_device *_dev);
74 extern int host20_hcd_init(struct platform_device *_dev);
75 extern int pcd_remove(struct platform_device *_dev);
76 extern void hcd_remove(struct platform_device *_dev);
77 extern void dwc_otg_adp_start(dwc_otg_core_if_t *core_if, uint8_t is_host);
79 #ifdef CONFIG_USB20_OTG
80 static struct usb20otg_pdata_id usb20otg_pdata[] = {
82 .name = "rk3188-usb20otg",
83 .pdata = &usb20otg_pdata_rk3188,
86 .name = "rk3288-usb20otg",
87 .pdata = &usb20otg_pdata_rk3288,
93 #ifdef CONFIG_USB20_HOST
94 static struct usb20host_pdata_id usb20host_pdata[] = {
96 .name = "rk3188-usb20host",
97 .pdata = &usb20host_pdata_rk3188,
100 .name = "rk3288-usb20host",
101 .pdata = &usb20host_pdata_rk3288,
107 #ifdef CONFIG_RK_USB_UART
108 static u32 usb_to_uart_status;
110 /*-------------------------------------------------------------------------*/
111 /* Encapsulate the module parameter settings */
113 struct dwc_otg_driver_module_params {
117 int32_t dma_desc_enable;
118 int32_t dma_burst_size;
120 int32_t host_support_fs_ls_low_power;
121 int32_t host_ls_low_power_phy_clk;
122 int32_t enable_dynamic_fifo;
123 int32_t data_fifo_size;
124 int32_t dev_rx_fifo_size;
125 int32_t dev_nperio_tx_fifo_size;
126 uint32_t dev_perio_tx_fifo_size[MAX_PERIO_FIFOS];
127 int32_t host_rx_fifo_size;
128 int32_t host_nperio_tx_fifo_size;
129 int32_t host_perio_tx_fifo_size;
130 int32_t max_transfer_size;
131 int32_t max_packet_count;
132 int32_t host_channels;
133 int32_t dev_endpoints;
135 int32_t phy_utmi_width;
136 int32_t phy_ulpi_ddr;
137 int32_t phy_ulpi_ext_vbus;
141 int32_t en_multiple_tx_fifo;
142 uint32_t dev_tx_fifo_size[MAX_TX_FIFOS];
144 uint32_t tx_thr_length;
145 uint32_t rx_thr_length;
150 int32_t baseline_besl;
153 int32_t ahb_thr_ratio;
163 static struct dwc_otg_driver_module_params dwc_otg_module_params = {
165 .otg_cap = DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE,
167 .dma_desc_enable = 0,
168 .dma_burst_size = -1,
170 .host_support_fs_ls_low_power = -1,
171 .host_ls_low_power_phy_clk = -1,
172 .enable_dynamic_fifo = 1,
173 .data_fifo_size = -1,
174 .dev_rx_fifo_size = 0x120,
175 .dev_nperio_tx_fifo_size = 0x10,
176 .dev_perio_tx_fifo_size = {
177 /* dev_perio_tx_fifo_size_1 */
195 .host_rx_fifo_size = -1,
196 .host_nperio_tx_fifo_size = -1,
197 .host_perio_tx_fifo_size = -1,
198 .max_transfer_size = -1,
199 .max_packet_count = -1,
203 .phy_utmi_width = -1,
205 .phy_ulpi_ext_vbus = -1,
209 .en_multiple_tx_fifo = -1,
210 .dev_tx_fifo_size = {
211 /* dev_tx_fifo_size */
249 #ifdef CONFIG_USB20_HOST
250 static struct dwc_otg_driver_module_params dwc_host_module_params = {
252 .otg_cap = DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE,
254 .dma_desc_enable = 0,
255 .dma_burst_size = -1,
257 .host_support_fs_ls_low_power = -1,
258 .host_ls_low_power_phy_clk = -1,
259 .enable_dynamic_fifo = -1,
260 .data_fifo_size = -1,
261 .dev_rx_fifo_size = -1,
262 .dev_nperio_tx_fifo_size = -1,
263 .dev_perio_tx_fifo_size = {
264 /* dev_perio_tx_fifo_size_1 */
282 .host_rx_fifo_size = -1,
283 .host_nperio_tx_fifo_size = -1,
284 .host_perio_tx_fifo_size = -1,
285 .max_transfer_size = -1,
286 .max_packet_count = -1,
290 .phy_utmi_width = -1,
292 .phy_ulpi_ext_vbus = -1,
296 .en_multiple_tx_fifo = -1,
297 .dev_tx_fifo_size = {
298 /* dev_tx_fifo_size */
338 * This function shows the Driver Version.
340 static ssize_t version_show(struct device_driver *dev, char *buf)
342 return snprintf(buf, sizeof(DWC_DRIVER_VERSION) + 2, "%s\n",
346 static DRIVER_ATTR(version, S_IRUGO, version_show, NULL);
349 * Global Debug Level Mask.
351 uint32_t g_dbg_lvl = DBG_OFF; /* OFF */
354 * This function shows the driver Debug Level.
356 static ssize_t dbg_level_show(struct device_driver *drv, char *buf)
358 return sprintf(buf, "0x%0x\n", g_dbg_lvl);
362 * This function stores the driver Debug Level.
364 static ssize_t dbg_level_store(struct device_driver *drv, const char *buf,
367 g_dbg_lvl = simple_strtoul(buf, NULL, 16);
371 static DRIVER_ATTR(debuglevel, S_IRUGO | S_IWUSR, dbg_level_show,
374 extern void hcd_start(dwc_otg_core_if_t *core_if);
375 extern struct usb_hub *g_dwc_otg_root_hub20;
376 extern void dwc_otg_hub_disconnect_device(struct usb_hub *hub);
378 void dwc_otg_force_host(dwc_otg_core_if_t *core_if)
380 dwc_otg_device_t *otg_dev = core_if->otg_dev;
381 dctl_data_t dctl = {.d32 = 0 };
384 if (core_if->op_state == A_HOST) {
385 printk("dwc_otg_force_host,already in A_HOST mode,everest\n");
388 core_if->op_state = A_HOST;
390 cancel_delayed_work(&otg_dev->pcd->check_vbus_work);
391 dctl.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dctl);
392 dctl.b.sftdiscon = 1;
393 DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dctl, dctl.d32);
395 local_irq_save(flags);
396 cil_pcd_stop(core_if);
398 * Initialize the Core for Host mode.
401 dwc_otg_core_init(core_if);
402 dwc_otg_enable_global_interrupts(core_if);
403 cil_hcd_start(core_if);
404 local_irq_restore(flags);
407 void dwc_otg_force_device(dwc_otg_core_if_t *core_if)
409 dwc_otg_device_t *otg_dev = core_if->otg_dev;
412 local_irq_save(flags);
414 if (core_if->op_state == B_PERIPHERAL) {
416 ("dwc_otg_force_device,already in B_PERIPHERAL,everest\n");
419 core_if->op_state = B_PERIPHERAL;
420 cil_hcd_stop(core_if);
421 /* dwc_otg_hub_disconnect_device(g_dwc_otg_root_hub20); */
422 otg_dev->pcd->phy_suspend = 1;
423 otg_dev->pcd->vbus_status = 0;
424 dwc_otg_pcd_start_check_vbus_work(otg_dev->pcd);
426 /* Reset the Controller */
427 dwc_otg_core_reset(core_if);
429 dwc_otg_core_init(core_if);
430 dwc_otg_disable_global_interrupts(core_if);
431 cil_pcd_start(core_if);
433 local_irq_restore(flags);
436 static void dwc_otg_set_force_mode(dwc_otg_core_if_t *core_if, int mode)
438 gusbcfg_data_t usbcfg = {.d32 = 0 };
439 printk("!!!dwc_otg_set_force_mode\n");
440 usbcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->gusbcfg);
442 case USB_MODE_FORCE_HOST:
443 usbcfg.b.force_host_mode = 1;
444 usbcfg.b.force_dev_mode = 0;
446 case USB_MODE_FORCE_DEVICE:
447 usbcfg.b.force_host_mode = 0;
448 usbcfg.b.force_dev_mode = 1;
450 case USB_MODE_NORMAL:
451 usbcfg.b.force_host_mode = 0;
452 usbcfg.b.force_dev_mode = 0;
455 DWC_WRITE_REG32(&core_if->core_global_regs->gusbcfg, usbcfg.d32);
458 static ssize_t force_usb_mode_show(struct device_driver *drv, char *buf)
460 dwc_otg_device_t *otg_dev = g_otgdev;
461 dwc_otg_core_if_t *core_if = otg_dev->core_if;
463 return sprintf(buf, "%d\n", core_if->usb_mode);
466 static ssize_t force_usb_mode_store(struct device_driver *drv, const char *buf,
469 int new_mode = simple_strtoul(buf, NULL, 16);
470 dwc_otg_device_t *otg_dev = g_otgdev;
471 dwc_otg_core_if_t *core_if;
472 struct dwc_otg_platform_data *pldata;
477 core_if = otg_dev->core_if;
478 pldata = otg_dev->pldata;
480 DWC_PRINTF("%s %d->%d\n", __func__, core_if->usb_mode, new_mode);
482 if (core_if->usb_mode == new_mode) {
486 if (pldata->phy_status == USB_PHY_SUSPEND) {
487 pldata->clock_enable(pldata, 1);
488 pldata->phy_suspend(pldata, USB_PHY_ENABLED);
492 case USB_MODE_FORCE_HOST:
493 if (USB_MODE_FORCE_DEVICE == core_if->usb_mode) {
495 core_if->usb_mode = new_mode;
496 dwc_otg_force_host(core_if);
497 } else if (USB_MODE_NORMAL == core_if->usb_mode) {
498 core_if->usb_mode = new_mode;
499 if (dwc_otg_is_host_mode(core_if))
500 dwc_otg_set_force_mode(core_if, new_mode);
502 dwc_otg_force_host(core_if);
506 case USB_MODE_FORCE_DEVICE:
507 if (USB_MODE_FORCE_HOST == core_if->usb_mode) {
508 core_if->usb_mode = new_mode;
509 dwc_otg_force_device(core_if);
510 } else if (USB_MODE_NORMAL == core_if->usb_mode) {
511 core_if->usb_mode = new_mode;
512 if (dwc_otg_is_device_mode(core_if))
513 dwc_otg_set_force_mode(core_if, new_mode);
515 dwc_otg_force_device(core_if);
519 case USB_MODE_NORMAL:
520 if (USB_MODE_FORCE_DEVICE == core_if->usb_mode) {
521 core_if->usb_mode = new_mode;
522 cancel_delayed_work(&otg_dev->pcd->check_vbus_work);
523 dwc_otg_set_force_mode(core_if, new_mode);
525 if (dwc_otg_is_host_mode(core_if)) {
526 dwc_otg_force_host(core_if);
528 dwc_otg_pcd_start_check_vbus_work(otg_dev->pcd);
530 } else if (USB_MODE_FORCE_HOST == core_if->usb_mode) {
531 core_if->usb_mode = new_mode;
532 dwc_otg_set_force_mode(core_if, new_mode);
534 if (dwc_otg_is_device_mode(core_if)) {
535 dwc_otg_force_device(core_if);
546 static DRIVER_ATTR(force_usb_mode, S_IRUGO | S_IWUSR, force_usb_mode_show,
547 force_usb_mode_store);
549 static ssize_t dwc_otg_conn_en_show(struct device_driver *_drv, char *_buf)
552 dwc_otg_device_t *otg_dev = g_otgdev;
553 dwc_otg_pcd_t *_pcd = otg_dev->pcd;
554 return sprintf(_buf, "%d\n", _pcd->conn_en);
558 static ssize_t dwc_otg_conn_en_store(struct device_driver *_drv,
559 const char *_buf, size_t _count)
561 int enable = simple_strtoul(_buf, NULL, 10);
562 dwc_otg_device_t *otg_dev = g_otgdev;
563 dwc_otg_pcd_t *_pcd = otg_dev->pcd;
564 DWC_PRINTF("%s %d->%d\n", __func__, _pcd->conn_en, enable);
566 _pcd->conn_en = enable;
570 static DRIVER_ATTR(dwc_otg_conn_en, S_IRUGO | S_IWUSR, dwc_otg_conn_en_show,
571 dwc_otg_conn_en_store);
573 /* used for product vbus power control, SDK not need.
574 * If dwc_otg is host mode, enable vbus power.
575 * If dwc_otg is device mode, disable vbus power.
576 * return 1 - host mode, 0 - device mode.
578 int dwc_otg_usb_state(void)
580 dwc_otg_device_t *otg_dev = g_otgdev;
583 /* op_state is A_HOST */
584 if (1 == otg_dev->core_if->op_state)
586 /* op_state is B_PERIPHERAL */
587 else if (4 == otg_dev->core_if->op_state)
592 DWC_WARN("g_otgdev is NULL, maybe otg probe is failed!\n");
596 EXPORT_SYMBOL(dwc_otg_usb_state);
598 static ssize_t dwc_otg_op_state_show(struct device_driver *_drv, char *_buf)
600 dwc_otg_device_t *otg_dev = g_otgdev;
603 return sprintf(_buf, "%d\n", otg_dev->core_if->op_state);
605 return sprintf(_buf, "%d\n", 0);
608 static DRIVER_ATTR(op_state, S_IRUGO, dwc_otg_op_state_show, NULL);
610 static ssize_t vbus_status_show(struct device_driver *_drv, char *_buf)
612 dwc_otg_device_t *otg_dev = g_otgdev;
613 dwc_otg_pcd_t *_pcd = otg_dev->pcd;
614 return sprintf(_buf, "%d\n", _pcd->vbus_status);
617 static DRIVER_ATTR(vbus_status, S_IRUGO, vbus_status_show, NULL);
620 * This function is called during module intialization
621 * to pass module parameters to the DWC_OTG CORE.
623 static int set_parameters(dwc_otg_core_if_t *core_if,
624 struct dwc_otg_driver_module_params module_params)
629 if (module_params.otg_cap != -1) {
631 dwc_otg_set_param_otg_cap(core_if, module_params.otg_cap);
633 if (module_params.dma_enable != -1) {
635 dwc_otg_set_param_dma_enable(core_if,
636 module_params.dma_enable);
638 if (module_params.dma_desc_enable != -1) {
640 dwc_otg_set_param_dma_desc_enable(core_if,
641 module_params.dma_desc_enable);
643 if (module_params.opt != -1) {
644 retval += dwc_otg_set_param_opt(core_if, module_params.opt);
646 if (module_params.dma_burst_size != -1) {
648 dwc_otg_set_param_dma_burst_size(core_if,
649 module_params.dma_burst_size);
651 if (module_params.host_support_fs_ls_low_power != -1) {
653 dwc_otg_set_param_host_support_fs_ls_low_power(core_if,
654 module_params.host_support_fs_ls_low_power);
656 if (module_params.enable_dynamic_fifo != -1) {
658 dwc_otg_set_param_enable_dynamic_fifo(core_if,
659 module_params.enable_dynamic_fifo);
661 if (module_params.data_fifo_size != -1) {
663 dwc_otg_set_param_data_fifo_size(core_if,
664 module_params.data_fifo_size);
666 if (module_params.dev_rx_fifo_size != -1) {
668 dwc_otg_set_param_dev_rx_fifo_size(core_if,
669 module_params.dev_rx_fifo_size);
671 if (module_params.dev_nperio_tx_fifo_size != -1) {
673 dwc_otg_set_param_dev_nperio_tx_fifo_size(core_if,
674 module_params.dev_nperio_tx_fifo_size);
676 if (module_params.host_rx_fifo_size != -1) {
678 dwc_otg_set_param_host_rx_fifo_size(core_if,
682 if (module_params.host_nperio_tx_fifo_size != -1) {
684 dwc_otg_set_param_host_nperio_tx_fifo_size(core_if,
685 module_params.host_nperio_tx_fifo_size);
687 if (module_params.host_perio_tx_fifo_size != -1) {
689 dwc_otg_set_param_host_perio_tx_fifo_size(core_if,
690 module_params.host_perio_tx_fifo_size);
692 if (module_params.max_transfer_size != -1) {
694 dwc_otg_set_param_max_transfer_size(core_if,
695 module_params.max_transfer_size);
697 if (module_params.max_packet_count != -1) {
699 dwc_otg_set_param_max_packet_count(core_if,
700 module_params.max_packet_count);
702 if (module_params.host_channels != -1) {
704 dwc_otg_set_param_host_channels(core_if,
705 module_params.host_channels);
707 if (module_params.dev_endpoints != -1) {
709 dwc_otg_set_param_dev_endpoints(core_if,
710 module_params.dev_endpoints);
712 if (module_params.phy_type != -1) {
714 dwc_otg_set_param_phy_type(core_if, module_params.phy_type);
716 if (module_params.speed != -1) {
717 retval += dwc_otg_set_param_speed(core_if, module_params.speed);
719 if (module_params.host_ls_low_power_phy_clk != -1) {
721 dwc_otg_set_param_host_ls_low_power_phy_clk(core_if,
722 module_params.host_ls_low_power_phy_clk);
724 if (module_params.phy_ulpi_ddr != -1) {
726 dwc_otg_set_param_phy_ulpi_ddr(core_if,
727 module_params.phy_ulpi_ddr);
729 if (module_params.phy_ulpi_ext_vbus != -1) {
731 dwc_otg_set_param_phy_ulpi_ext_vbus(core_if,
732 module_params.phy_ulpi_ext_vbus);
734 if (module_params.phy_utmi_width != -1) {
736 dwc_otg_set_param_phy_utmi_width(core_if,
737 module_params.phy_utmi_width);
739 if (module_params.ulpi_fs_ls != -1) {
741 dwc_otg_set_param_ulpi_fs_ls(core_if,
742 module_params.ulpi_fs_ls);
744 if (module_params.ts_dline != -1) {
746 dwc_otg_set_param_ts_dline(core_if, module_params.ts_dline);
748 if (module_params.i2c_enable != -1) {
750 dwc_otg_set_param_i2c_enable(core_if,
751 module_params.i2c_enable);
753 if (module_params.en_multiple_tx_fifo != -1) {
755 dwc_otg_set_param_en_multiple_tx_fifo(core_if,
756 module_params.en_multiple_tx_fifo);
758 for (i = 0; i < 15; i++) {
759 if (module_params.dev_perio_tx_fifo_size[i] != -1) {
761 dwc_otg_set_param_dev_perio_tx_fifo_size(core_if,
762 module_params.dev_perio_tx_fifo_size
767 for (i = 0; i < 15; i++) {
768 if (module_params.dev_tx_fifo_size[i] != -1) {
769 retval += dwc_otg_set_param_dev_tx_fifo_size(core_if,
770 module_params.dev_tx_fifo_size
774 if (module_params.thr_ctl != -1) {
776 dwc_otg_set_param_thr_ctl(core_if, module_params.thr_ctl);
778 if (module_params.mpi_enable != -1) {
780 dwc_otg_set_param_mpi_enable(core_if,
781 module_params.mpi_enable);
783 if (module_params.pti_enable != -1) {
785 dwc_otg_set_param_pti_enable(core_if,
786 module_params.pti_enable);
788 if (module_params.lpm_enable != -1) {
790 dwc_otg_set_param_lpm_enable(core_if,
791 module_params.lpm_enable);
793 if (module_params.besl_enable != -1) {
795 dwc_otg_set_param_besl_enable(core_if,
796 module_params.besl_enable);
798 if (module_params.baseline_besl != -1) {
800 dwc_otg_set_param_baseline_besl(core_if,
801 module_params.baseline_besl);
803 if (module_params.deep_besl != -1) {
805 dwc_otg_set_param_deep_besl(core_if,
806 module_params.deep_besl);
808 if (module_params.ic_usb_cap != -1) {
810 dwc_otg_set_param_ic_usb_cap(core_if,
811 module_params.ic_usb_cap);
813 if (module_params.tx_thr_length != -1) {
815 dwc_otg_set_param_tx_thr_length(core_if,
819 if (module_params.rx_thr_length != -1) {
821 dwc_otg_set_param_rx_thr_length(core_if,
822 module_params.rx_thr_length);
824 if (module_params.ahb_thr_ratio != -1) {
826 dwc_otg_set_param_ahb_thr_ratio(core_if,
830 if (module_params.power_down != -1) {
832 dwc_otg_set_param_power_down(core_if,
833 module_params.power_down);
835 if (module_params.reload_ctl != -1) {
837 dwc_otg_set_param_reload_ctl(core_if,
838 module_params.reload_ctl);
841 if (module_params.dev_out_nak != -1) {
843 dwc_otg_set_param_dev_out_nak(core_if,
844 module_params.dev_out_nak);
847 if (module_params.cont_on_bna != -1) {
849 dwc_otg_set_param_cont_on_bna(core_if,
850 module_params.cont_on_bna);
853 if (module_params.ahb_single != -1) {
855 dwc_otg_set_param_ahb_single(core_if,
856 module_params.ahb_single);
859 if (module_params.otg_ver != -1) {
861 dwc_otg_set_param_otg_ver(core_if, module_params.otg_ver);
863 if (module_params.adp_enable != -1) {
865 dwc_otg_set_param_adp_enable(core_if,
866 module_params.adp_enable);
872 * This function is the top level interrupt handler for the Common
873 * (Device and host modes) interrupts.
875 static irqreturn_t dwc_otg_common_irq(int irq, void *dev)
877 int32_t retval = IRQ_NONE;
879 retval = dwc_otg_handle_common_intr(dev);
881 /* S3C2410X_CLEAR_EINTPEND(); */
883 return IRQ_RETVAL(retval);
886 #ifdef CONFIG_USB20_HOST
888 * This function is called when a lm_device is unregistered with the
889 * dwc_otg_driver. This happens, for example, when the rmmod command is
890 * executed. The device may or may not be electrically present. If it is
891 * present, the driver stops device processing. Any resources used on behalf
892 * of this device are freed.
896 static int host20_driver_remove(struct platform_device *_dev)
899 dwc_otg_device_t *otg_dev = dwc_get_device_platform_data(_dev);
900 DWC_DEBUGPL(DBG_ANY, "%s(%p)\n", __func__, _dev);
903 /* Memory allocation for the dwc_otg_device failed. */
904 DWC_DEBUGPL(DBG_ANY, "%s: otg_dev NULL!\n", __func__);
907 #ifndef DWC_DEVICE_ONLY
911 DWC_DEBUGPL(DBG_ANY, "%s: otg_dev->hcd NULL!\n", __func__);
916 #ifndef DWC_HOST_ONLY
920 DWC_DEBUGPL(DBG_ANY, "%s: otg_dev->pcd NULL!\n", __func__);
928 if (otg_dev->common_irq_installed) {
929 /* free_irq(_dev->irq, otg_dev); */
930 free_irq(platform_get_irq(_dev, 0), otg_dev);
932 DWC_DEBUGPL(DBG_ANY, "%s: There is no installed irq!\n",
937 if (otg_dev->core_if) {
938 dwc_otg_cil_remove(otg_dev->core_if);
940 DWC_DEBUGPL(DBG_ANY, "%s: otg_dev->core_if NULL!\n", __func__);
945 * Remove the device attributes
947 dwc_otg_attr_remove(_dev);
952 if (otg_dev->os_dep.base) {
953 iounmap(otg_dev->os_dep.base);
958 * Clear the drvdata pointer.
961 dwc_set_device_platform_data(_dev, 0);
966 static const struct of_device_id usb20_host_of_match[] = {
968 .compatible = "rockchip,rk3188_usb20_host",
969 .data = &usb20host_pdata[RK3188_USB_CTLR],
972 .compatible = "rockchip,rk3288_usb20_host",
973 .data = &usb20host_pdata[RK3288_USB_CTLR],
978 MODULE_DEVICE_TABLE(of, usb20_host_of_match);
981 * This function is called when an lm_device is bound to a
982 * dwc_otg_driver. It creates the driver components required to
983 * control the device (CIL, HCD, and PCD) and it initializes the
984 * device. The driver components are stored in a dwc_otg_device
985 * structure. A reference to the dwc_otg_device is saved in the
986 * lm_device. This allows the driver to access the dwc_otg_device
987 * structure on subsequent calls to driver methods for this device.
989 * @param _dev Bus device
991 static int host20_driver_probe(struct platform_device *_dev)
995 struct resource *res_base;
996 dwc_otg_device_t *dwc_otg_device;
997 struct device *dev = &_dev->dev;
998 struct device_node *node = _dev->dev.of_node;
999 struct dwc_otg_platform_data *pldata;
1000 struct usb20host_pdata_id *p;
1001 const struct of_device_id *match =
1002 of_match_device(of_match_ptr(usb20_host_of_match), &_dev->dev);
1005 p = (struct usb20host_pdata_id *)match->data;
1007 dev_err(dev, "usb20host match failed\n");
1011 dev->platform_data = p->pdata;
1012 pldata = dev->platform_data;
1016 dev_err(dev, "device node not found\n");
1020 if (pldata->hw_init)
1023 if (pldata->clock_init) {
1024 pldata->clock_init(pldata);
1025 pldata->clock_enable(pldata, 1);
1028 if (pldata->phy_suspend)
1029 pldata->phy_suspend(pldata, USB_PHY_ENABLED);
1031 if (pldata->soft_reset)
1032 pldata->soft_reset();
1034 res_base = platform_get_resource(_dev, IORESOURCE_MEM, 0);
1036 dwc_otg_device = DWC_ALLOC(sizeof(dwc_otg_device_t));
1038 if (!dwc_otg_device) {
1039 dev_err(&_dev->dev, "kmalloc of dwc_otg_device failed\n");
1044 memset(dwc_otg_device, 0, sizeof(*dwc_otg_device));
1045 dwc_otg_device->os_dep.reg_offset = 0xFFFFFFFF;
1048 * Map the DWC_otg Core memory into virtual address space.
1051 dwc_otg_device->os_dep.base = devm_ioremap_resource(dev, res_base);
1053 if (!dwc_otg_device->os_dep.base) {
1054 dev_err(&_dev->dev, "ioremap() failed\n");
1055 DWC_FREE(dwc_otg_device);
1059 dev_dbg(&_dev->dev, "base=0x%08x\n",
1060 (unsigned)dwc_otg_device->os_dep.base);
1063 * Initialize driver data to point to the global DWC_otg
1067 dwc_set_device_platform_data(_dev, dwc_otg_device);
1068 pldata->privdata = dwc_otg_device;
1069 dwc_otg_device->pldata = (void *)pldata;
1071 dev_dbg(&_dev->dev, "dwc_otg_device=0x%p\n", dwc_otg_device);
1073 dwc_otg_device->core_if = dwc_otg_cil_init(dwc_otg_device->os_dep.base);
1075 if (!dwc_otg_device->core_if) {
1076 dev_err(&_dev->dev, "CIL initialization failed!\n");
1081 dwc_otg_device->core_if->otg_dev = dwc_otg_device;
1084 * Attempt to ensure this device is really a DWC_otg Controller.
1085 * Read and verify the SNPSID register contents. The value should be
1086 * 0x45F42XXX or 0x45F42XXX, which corresponds to either "OT2" or "OTG3",
1087 * as in "OTG version 2.XX" or "OTG version 3.XX".
1090 if (((dwc_otg_get_gsnpsid(dwc_otg_device->core_if) & 0xFFFFF000) !=
1092 && ((dwc_otg_get_gsnpsid(dwc_otg_device->core_if) & 0xFFFFF000) !=
1094 dev_err(&_dev->dev, "Bad value for SNPSID: 0x%08x\n",
1095 dwc_otg_get_gsnpsid(dwc_otg_device->core_if));
1101 * Validate parameter values.
1103 if (set_parameters(dwc_otg_device->core_if, dwc_host_module_params)) {
1109 * Create Device Attributes in sysfs
1111 dwc_otg_attr_create(_dev);
1114 * Disable the global interrupt until all the interrupt
1115 * handlers are installed.
1117 dwc_otg_disable_global_interrupts(dwc_otg_device->core_if);
1120 * Install the interrupt handler for the common interrupts before
1121 * enabling common interrupts in core_init below.
1123 irq = platform_get_irq(_dev, 0);
1124 DWC_DEBUGPL(DBG_CIL, "registering (common) handler for irq%d\n", irq);
1125 retval = request_irq(irq, dwc_otg_common_irq,
1126 IRQF_SHARED, "dwc_otg", dwc_otg_device);
1128 DWC_ERROR("request of irq%d failed\n", irq);
1132 dwc_otg_device->common_irq_installed = 1;
1136 * Initialize the DWC_otg core.
1137 * In order to reduce the time of initialization,
1138 * we do core soft reset after connection detected.
1140 dwc_otg_core_init_no_reset(dwc_otg_device->core_if);
1143 * Initialize the HCD
1145 retval = host20_hcd_init(_dev);
1147 DWC_ERROR("hcd_init failed\n");
1148 dwc_otg_device->hcd = NULL;
1152 clk_set_rate(pldata->phyclk_480m, 480000000);
1154 * Enable the global interrupt after all the interrupt
1155 * handlers are installed if there is no ADP support else
1156 * perform initial actions required for Internal ADP logic.
1158 if (!dwc_otg_get_param_adp_enable(dwc_otg_device->core_if)) {
1159 if (pldata->phy_status == USB_PHY_ENABLED) {
1160 pldata->phy_suspend(pldata, USB_PHY_SUSPEND);
1162 pldata->clock_enable(pldata, 0);
1164 /* dwc_otg_enable_global_interrupts(dwc_otg_device->core_if); */
1166 dwc_otg_adp_start(dwc_otg_device->core_if,
1167 dwc_otg_is_host_mode(dwc_otg_device->
1173 host20_driver_remove(_dev);
1175 if (pldata->clock_enable)
1176 pldata->clock_enable(pldata, 0);
1182 static int dwc_otg_driver_suspend(struct platform_device *_dev,
1188 static int dwc_otg_driver_resume(struct platform_device *_dev)
1193 static void dwc_otg_driver_shutdown(struct platform_device *_dev)
1195 struct device *dev = &_dev->dev;
1196 dwc_otg_device_t *otg_dev = dev->platform_data;
1197 dwc_otg_core_if_t *core_if = otg_dev->core_if;
1198 dctl_data_t dctl = {.d32 = 0 };
1200 DWC_PRINTF("%s: disconnect USB %s mode\n", __func__,
1201 dwc_otg_is_host_mode(core_if) ? "host" : "device");
1202 if (dwc_otg_is_host_mode(core_if)) {
1203 if (core_if->hcd_cb && core_if->hcd_cb->stop)
1204 core_if->hcd_cb->stop(core_if->hcd_cb_p);
1206 /* soft disconnect */
1208 DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dctl);
1209 dctl.b.sftdiscon = 1;
1210 DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dctl,
1213 /* Clear any pending interrupts */
1214 DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, 0xFFFFFFFF);
1219 * This structure defines the methods to be called by a bus driver
1220 * during the lifecycle of a device on that bus. Both drivers and
1221 * devices are registered with a bus driver. The bus driver matches
1222 * devices to drivers based on information in the device and driver
1225 * The probe function is called when the bus driver matches a device
1226 * to this driver. The remove function is called when a device is
1227 * unregistered with the bus driver.
1229 #ifdef CONFIG_USB20_HOST
1230 static struct platform_driver dwc_host_driver = {
1232 .name = (char *)dwc_host20_driver_name,
1233 .of_match_table = of_match_ptr(usb20_host_of_match),
1235 .probe = host20_driver_probe,
1236 .remove = host20_driver_remove,
1237 .suspend = dwc_otg_driver_suspend,
1238 .resume = dwc_otg_driver_resume,
1242 #ifdef CONFIG_USB20_OTG
1244 * This function is called when a lm_device is unregistered with the
1245 * dwc_otg_driver. This happens, for example, when the rmmod command is
1246 * executed. The device may or may not be electrically present. If it is
1247 * present, the driver stops device processing. Any resources used on behalf
1248 * of this device are freed.
1252 static int otg20_driver_remove(struct platform_device *_dev)
1255 dwc_otg_device_t *otg_dev = dwc_get_device_platform_data(_dev);
1256 DWC_DEBUGPL(DBG_ANY, "%s(%p)\n", __func__, _dev);
1259 /* Memory allocation for the dwc_otg_device failed. */
1260 DWC_DEBUGPL(DBG_ANY, "%s: otg_dev NULL!\n", __func__);
1263 #ifndef DWC_DEVICE_ONLY
1267 DWC_DEBUGPL(DBG_ANY, "%s: otg_dev->hcd NULL!\n", __func__);
1272 #ifndef DWC_HOST_ONLY
1276 DWC_DEBUGPL(DBG_ANY, "%s: otg_dev->pcd NULL!\n", __func__);
1283 if (otg_dev->common_irq_installed) {
1284 /* free_irq(_dev->irq, otg_dev); */
1285 free_irq(platform_get_irq(_dev, 0), otg_dev);
1287 DWC_DEBUGPL(DBG_ANY, "%s: There is no installed irq!\n",
1292 if (otg_dev->core_if) {
1293 dwc_otg_cil_remove(otg_dev->core_if);
1295 DWC_DEBUGPL(DBG_ANY, "%s: otg_dev->core_if NULL!\n", __func__);
1300 * Remove the device attributes
1302 dwc_otg_attr_remove(_dev);
1305 * Return the memory.
1307 if (otg_dev->os_dep.base)
1308 iounmap(otg_dev->os_dep.base);
1312 * Clear the drvdata pointer.
1315 dwc_set_device_platform_data(_dev, 0);
1320 static const struct of_device_id usb20_otg_of_match[] = {
1322 .compatible = "rockchip,rk3188_usb20_otg",
1323 .data = &usb20otg_pdata[RK3188_USB_CTLR],
1326 .compatible = "rockchip,rk3288_usb20_otg",
1327 .data = &usb20otg_pdata[RK3288_USB_CTLR],
1333 MODULE_DEVICE_TABLE(of, usb20_otg_of_match);
1336 * This function is called when an lm_device is bound to a
1337 * dwc_otg_driver. It creates the driver components required to
1338 * control the device (CIL, HCD, and PCD) and it initializes the
1339 * device. The driver components are stored in a dwc_otg_device
1340 * structure. A reference to the dwc_otg_device is saved in the
1341 * lm_device. This allows the driver to access the dwc_otg_device
1342 * structure on subsequent calls to driver methods for this device.
1344 * @param _dev Bus device
1346 static int otg20_driver_probe(struct platform_device *_dev)
1351 struct resource *res_base;
1352 dwc_otg_device_t *dwc_otg_device;
1353 struct device *dev = &_dev->dev;
1354 struct device_node *node = _dev->dev.of_node;
1355 struct dwc_otg_platform_data *pldata;
1356 struct usb20otg_pdata_id *p;
1357 const struct of_device_id *match =
1358 of_match_device(of_match_ptr(usb20_otg_of_match), &_dev->dev);
1361 p = (struct usb20otg_pdata_id *)match->data;
1363 dev_err(dev, "usb20otg match failed\n");
1367 dev->platform_data = p->pdata;
1368 /* dev->platform_data = &usb20otg_pdata; */
1369 pldata = dev->platform_data;
1373 dev_err(dev, "device node not found\n");
1376 /*todo : move to usbdev_rk-XX.c */
1377 if (pldata->hw_init)
1380 if (pldata->clock_init) {
1381 pldata->clock_init(pldata);
1382 pldata->clock_enable(pldata, 1);
1385 if (pldata->phy_suspend)
1386 pldata->phy_suspend(pldata, USB_PHY_ENABLED);
1388 if (pldata->dwc_otg_uart_mode)
1389 pldata->dwc_otg_uart_mode(pldata, PHY_USB_MODE);
1391 /* do reset later, because reset need about
1392 * 100ms to ensure otg id state change.
1395 if(pldata->soft_reset)
1396 pldata->soft_reset();
1400 res_base = platform_get_resource(_dev, IORESOURCE_MEM, 0);
1402 dwc_otg_device = DWC_ALLOC(sizeof(dwc_otg_device_t));
1404 if (!dwc_otg_device) {
1405 dev_err(&_dev->dev, "kmalloc of dwc_otg_device failed\n");
1410 memset(dwc_otg_device, 0, sizeof(*dwc_otg_device));
1411 dwc_otg_device->os_dep.reg_offset = 0xFFFFFFFF;
1414 * Map the DWC_otg Core memory into virtual address space.
1417 dwc_otg_device->os_dep.base = devm_ioremap_resource(dev, res_base);
1419 if (!dwc_otg_device->os_dep.base) {
1420 dev_err(&_dev->dev, "ioremap() failed\n");
1421 DWC_FREE(dwc_otg_device);
1425 dev_dbg(&_dev->dev, "base=0x%08x\n",
1426 (unsigned)dwc_otg_device->os_dep.base);
1429 * Initialize driver data to point to the global DWC_otg
1433 g_otgdev = dwc_otg_device;
1434 pldata->privdata = dwc_otg_device;
1435 dwc_otg_device->pldata = pldata;
1437 dwc_set_device_platform_data(_dev, dwc_otg_device);
1439 dev_dbg(&_dev->dev, "dwc_otg_device=0x%p\n", dwc_otg_device);
1441 dwc_otg_device->core_if = dwc_otg_cil_init(dwc_otg_device->os_dep.base);
1442 if (!dwc_otg_device->core_if) {
1443 dev_err(&_dev->dev, "CIL initialization failed!\n");
1448 dwc_otg_device->core_if->otg_dev = dwc_otg_device;
1450 * Attempt to ensure this device is really a DWC_otg Controller.
1451 * Read and verify the SNPSID register contents. The value should be
1452 * 0x45F42XXX or 0x45F42XXX, which corresponds to either "OT2" or "OTG3",
1453 * as in "OTG version 2.XX" or "OTG version 3.XX".
1456 if (((dwc_otg_get_gsnpsid(dwc_otg_device->core_if) & 0xFFFFF000) !=
1458 && ((dwc_otg_get_gsnpsid(dwc_otg_device->core_if) & 0xFFFFF000) !=
1460 dev_err(&_dev->dev, "Bad value for SNPSID: 0x%08x\n",
1461 dwc_otg_get_gsnpsid(dwc_otg_device->core_if));
1467 * Validate parameter values.
1469 if (set_parameters(dwc_otg_device->core_if, dwc_otg_module_params)) {
1475 * Create Device Attributes in sysfs
1477 dwc_otg_attr_create(_dev);
1480 * Disable the global interrupt until all the interrupt
1481 * handlers are installed.
1483 dwc_otg_disable_global_interrupts(dwc_otg_device->core_if);
1486 * Install the interrupt handler for the common interrupts before
1487 * enabling common interrupts in core_init below.
1489 irq = platform_get_irq(_dev, 0);
1490 DWC_DEBUGPL(DBG_CIL, "registering (common) handler for irq%d\n", irq);
1491 retval = request_irq(irq, dwc_otg_common_irq,
1492 IRQF_SHARED, "dwc_otg", dwc_otg_device);
1494 DWC_ERROR("request of irq%d failed\n", irq);
1498 dwc_otg_device->common_irq_installed = 1;
1502 * Initialize the DWC_otg core.
1503 * In order to reduce the time of initialization,
1504 * we do core soft reset after connection detected.
1506 dwc_otg_core_init_no_reset(dwc_otg_device->core_if);
1509 * 0 - USB_MODE_NORMAL
1510 * 1 - USB_MODE_FORCE_HOST
1511 * 2 - USB_MODE_FORCE_DEVICE
1513 of_property_read_u32(node, "rockchip,usb-mode", &val);
1514 dwc_otg_device->core_if->usb_mode = val;
1516 #ifndef DWC_HOST_ONLY
1518 * Initialize the PCD
1520 retval = pcd_init(_dev);
1522 DWC_ERROR("pcd_init failed\n");
1523 dwc_otg_device->pcd = NULL;
1527 #ifndef DWC_DEVICE_ONLY
1529 * Initialize the HCD
1531 retval = otg20_hcd_init(_dev);
1533 DWC_ERROR("hcd_init failed\n");
1534 dwc_otg_device->hcd = NULL;
1539 * Enable the global interrupt after all the interrupt
1540 * handlers are installed if there is no ADP support else
1541 * perform initial actions required for Internal ADP logic.
1543 if (!dwc_otg_get_param_adp_enable(dwc_otg_device->core_if)) {
1544 if (pldata->phy_status == USB_PHY_ENABLED) {
1545 pldata->phy_suspend(pldata, USB_PHY_SUSPEND);
1547 pldata->clock_enable(pldata, 0);
1549 /* dwc_otg_enable_global_interrupts(dwc_otg_device->core_if); */
1551 dwc_otg_adp_start(dwc_otg_device->core_if,
1552 dwc_otg_is_host_mode(dwc_otg_device->
1558 otg20_driver_remove(_dev);
1561 if (pldata->clock_enable)
1562 pldata->clock_enable(pldata, 0);
1567 static struct platform_driver dwc_otg_driver = {
1569 .name = (char *)dwc_otg20_driver_name,
1570 .of_match_table = of_match_ptr(usb20_otg_of_match),
1572 .probe = otg20_driver_probe,
1573 .remove = otg20_driver_remove,
1574 .suspend = dwc_otg_driver_suspend,
1575 .resume = dwc_otg_driver_resume,
1576 .shutdown = dwc_otg_driver_shutdown,
1580 void rk_usb_power_up(void)
1582 struct dwc_otg_platform_data *pldata_otg;
1583 struct dwc_otg_platform_data *pldata_host;
1584 struct rkehci_platform_data *pldata_ehci;
1586 if (cpu_is_rk3288()) {
1587 #ifdef CONFIG_RK_USB_UART
1588 /* enable USB bypass UART function */
1589 writel_relaxed(0x00c00000 | usb_to_uart_status,
1590 RK_GRF_VIRT + RK3288_GRF_UOC0_CON3);
1593 /* unset siddq,the analog blocks are powered up */
1594 #ifdef CONFIG_USB20_OTG
1595 pldata_otg = &usb20otg_pdata_rk3288;
1597 if (pldata_otg->phy_status == USB_PHY_SUSPEND)
1598 writel_relaxed((0x01 << 13) << 16,
1600 RK3288_GRF_UOC0_CON0);
1603 #ifdef CONFIG_USB20_HOST
1604 pldata_host = &usb20host_pdata_rk3288;
1606 if (pldata_host->phy_status == USB_PHY_SUSPEND)
1607 writel_relaxed((0x01 << 13) << 16,
1609 RK3288_GRF_UOC2_CON0);
1612 #ifdef CONFIG_USB_EHCI_RK
1613 pldata_ehci = &rkehci_pdata_rk3288;
1615 if (pldata_ehci->phy_status == USB_PHY_SUSPEND)
1616 writel_relaxed((0x01 << 13) << 16,
1618 RK3288_GRF_UOC1_CON0);
1625 void rk_usb_power_down(void)
1627 struct dwc_otg_platform_data *pldata_otg;
1628 struct dwc_otg_platform_data *pldata_host;
1629 struct rkehci_platform_data *pldata_ehci;
1631 if (cpu_is_rk3288()) {
1632 #ifdef CONFIG_RK_USB_UART
1633 /* disable USB bypass UART function */
1634 usb_to_uart_status =
1635 readl_relaxed(RK_GRF_VIRT + RK3288_GRF_UOC0_CON3);
1636 writel_relaxed(0x00c00000, RK_GRF_VIRT + RK3288_GRF_UOC0_CON3);
1638 /* set siddq,the analog blocks are powered down
1640 * 1. Before asserting SIDDQ, ensure that VDATSRCENB0,
1641 * VDATDETENB0, DCDENB0, BYPASSSEL0, ADPPRBENB0,
1642 * and TESTBURNIN are set to 1'b0.
1643 * 2. Before asserting SIDDQ, ensure that phy enter suspend.*/
1644 #ifdef CONFIG_USB20_OTG
1645 pldata_otg = &usb20otg_pdata_rk3288;
1647 if (pldata_otg->phy_status == USB_PHY_SUSPEND)
1648 writel_relaxed((0x01 << 13) |
1649 ((0x01 << 13) << 16),
1651 RK3288_GRF_UOC0_CON0);
1654 #ifdef CONFIG_USB20_HOST
1655 pldata_host = &usb20host_pdata_rk3288;
1657 if (pldata_host->phy_status == USB_PHY_SUSPEND)
1658 writel_relaxed((0x01 << 13) |
1659 ((0x01 << 13) << 16),
1661 RK3288_GRF_UOC2_CON0);
1664 #ifdef CONFIG_USB_EHCI_RK
1665 pldata_ehci = &rkehci_pdata_rk3288;
1667 if (pldata_ehci->phy_status == USB_PHY_SUSPEND)
1668 writel_relaxed((0x01 << 13) |
1669 ((0x01 << 13) << 16),
1671 RK3288_GRF_UOC1_CON0);
1677 EXPORT_SYMBOL(rk_usb_power_up);
1678 EXPORT_SYMBOL(rk_usb_power_down);
1680 * This function is called when the dwc_otg_driver is installed with the
1681 * insmod command. It registers the dwc_otg_driver structure with the
1682 * appropriate bus driver. This will cause the dwc_otg_driver_probe function
1683 * to be called. In addition, the bus driver will automatically expose
1684 * attributes defined for the device and driver in the special sysfs file
1689 static int __init dwc_otg_driver_init(void)
1694 #ifdef CONFIG_USB20_OTG
1695 /* register otg20 */
1696 printk(KERN_INFO "%s: version %s\n", dwc_otg20_driver_name,
1697 DWC_DRIVER_VERSION);
1699 retval = platform_driver_register(&dwc_otg_driver);
1701 printk(KERN_ERR "%s retval=%d\n", __func__, retval);
1706 driver_create_file(&dwc_otg_driver.driver, &driver_attr_version);
1708 driver_create_file(&dwc_otg_driver.driver, &driver_attr_debuglevel);
1710 driver_create_file(&dwc_otg_driver.driver,
1711 &driver_attr_dwc_otg_conn_en);
1713 driver_create_file(&dwc_otg_driver.driver,
1714 &driver_attr_vbus_status);
1716 driver_create_file(&dwc_otg_driver.driver,
1717 &driver_attr_force_usb_mode);
1719 driver_create_file(&dwc_otg_driver.driver,
1720 &driver_attr_op_state);
1724 /* register host20 */
1725 #ifdef CONFIG_USB20_HOST
1726 printk(KERN_INFO "%s: version %s\n", dwc_host20_driver_name,
1727 DWC_DRIVER_VERSION);
1729 retval = platform_driver_register(&dwc_host_driver);
1731 printk(KERN_ERR "%s retval=%d\n", __func__, retval);
1736 driver_create_file(&dwc_host_driver.driver, &driver_attr_version);
1738 driver_create_file(&dwc_host_driver.driver,
1739 &driver_attr_debuglevel);
1744 module_init(dwc_otg_driver_init);
1747 * This function is called when the driver is removed from the kernel
1748 * with the rmmod command. The driver unregisters itself with its bus
1752 static void __exit dwc_otg_driver_cleanup(void)
1754 printk(KERN_DEBUG "dwc_otg_driver_cleanup()\n");
1756 #ifdef CONFIG_USB20_HOST
1758 driver_remove_file(&dwc_host_driver.driver, &driver_attr_debuglevel);
1759 driver_remove_file(&dwc_host_driver.driver, &driver_attr_version);
1760 platform_driver_unregister(&dwc_host_driver);
1761 printk(KERN_INFO "%s module removed\n", dwc_host20_driver_name);
1764 #ifdef CONFIG_USB20_OTG
1766 driver_remove_file(&dwc_otg_driver.driver,
1767 &driver_attr_dwc_otg_conn_en);
1768 driver_remove_file(&dwc_otg_driver.driver, &driver_attr_debuglevel);
1769 driver_remove_file(&dwc_otg_driver.driver, &driver_attr_version);
1770 driver_remove_file(&dwc_otg_driver.driver, &driver_attr_vbus_status);
1771 driver_remove_file(&dwc_otg_driver.driver, &driver_attr_force_usb_mode);
1772 driver_remove_file(&dwc_otg_driver.driver, &driver_attr_op_state);
1773 platform_driver_unregister(&dwc_otg_driver);
1774 printk(KERN_INFO "%s module removed\n", dwc_otg20_driver_name);
1778 module_exit(dwc_otg_driver_cleanup);
1780 MODULE_DESCRIPTION(DWC_DRIVER_DESC);
1781 MODULE_AUTHOR("Synopsys Inc.");
1782 MODULE_LICENSE("GPL");
1784 module_param_named(otg_cap, dwc_otg_module_params.otg_cap, int, 0444);
1785 MODULE_PARM_DESC(otg_cap, "OTG Capabilities 0=HNP&SRP 1=SRP Only 2=None");
1786 module_param_named(opt, dwc_otg_module_params.opt, int, 0444);
1787 MODULE_PARM_DESC(opt, "OPT Mode");
1788 module_param_named(dma_enable, dwc_otg_module_params.dma_enable, int, 0444);
1789 MODULE_PARM_DESC(dma_enable, "DMA Mode 0=Slave 1=DMA enabled");
1791 module_param_named(dma_desc_enable, dwc_otg_module_params.dma_desc_enable, int,
1793 MODULE_PARM_DESC(dma_desc_enable,
1794 "DMA Desc Mode 0=Address DMA 1=DMA Descriptor enabled");
1796 module_param_named(dma_burst_size, dwc_otg_module_params.dma_burst_size, int,
1798 MODULE_PARM_DESC(dma_burst_size,
1799 "DMA Burst Size 1, 4, 8, 16, 32, 64, 128, 256");
1800 module_param_named(speed, dwc_otg_module_params.speed, int, 0444);
1801 MODULE_PARM_DESC(speed, "Speed 0=High Speed 1=Full Speed");
1802 module_param_named(host_support_fs_ls_low_power,
1803 dwc_otg_module_params.host_support_fs_ls_low_power, int,
1805 MODULE_PARM_DESC(host_support_fs_ls_low_power,
1806 "Support Low Power w/FS or LS 0=Support 1=Don't Support");
1807 module_param_named(host_ls_low_power_phy_clk,
1808 dwc_otg_module_params.host_ls_low_power_phy_clk, int, 0444);
1809 MODULE_PARM_DESC(host_ls_low_power_phy_clk,
1810 "Low Speed Low Power Clock 0=48Mhz 1=6Mhz");
1811 module_param_named(enable_dynamic_fifo,
1812 dwc_otg_module_params.enable_dynamic_fifo, int, 0444);
1813 MODULE_PARM_DESC(enable_dynamic_fifo, "0=cC Setting 1=Allow Dynamic Sizing");
1814 module_param_named(data_fifo_size, dwc_otg_module_params.data_fifo_size, int,
1816 MODULE_PARM_DESC(data_fifo_size,
1817 "Total number of words in the data FIFO memory 32-32768");
1818 module_param_named(dev_rx_fifo_size, dwc_otg_module_params.dev_rx_fifo_size,
1820 MODULE_PARM_DESC(dev_rx_fifo_size, "Number of words in the Rx FIFO 16-32768");
1821 module_param_named(dev_nperio_tx_fifo_size,
1822 dwc_otg_module_params.dev_nperio_tx_fifo_size, int, 0444);
1823 MODULE_PARM_DESC(dev_nperio_tx_fifo_size,
1824 "Number of words in the non-periodic Tx FIFO 16-32768");
1825 module_param_named(dev_perio_tx_fifo_size_1,
1826 dwc_otg_module_params.dev_perio_tx_fifo_size[0], int, 0444);
1827 MODULE_PARM_DESC(dev_perio_tx_fifo_size_1,
1828 "Number of words in the periodic Tx FIFO 4-768");
1829 module_param_named(dev_perio_tx_fifo_size_2,
1830 dwc_otg_module_params.dev_perio_tx_fifo_size[1], int, 0444);
1831 MODULE_PARM_DESC(dev_perio_tx_fifo_size_2,
1832 "Number of words in the periodic Tx FIFO 4-768");
1833 module_param_named(dev_perio_tx_fifo_size_3,
1834 dwc_otg_module_params.dev_perio_tx_fifo_size[2], int, 0444);
1835 MODULE_PARM_DESC(dev_perio_tx_fifo_size_3,
1836 "Number of words in the periodic Tx FIFO 4-768");
1837 module_param_named(dev_perio_tx_fifo_size_4,
1838 dwc_otg_module_params.dev_perio_tx_fifo_size[3], int, 0444);
1839 MODULE_PARM_DESC(dev_perio_tx_fifo_size_4,
1840 "Number of words in the periodic Tx FIFO 4-768");
1841 module_param_named(dev_perio_tx_fifo_size_5,
1842 dwc_otg_module_params.dev_perio_tx_fifo_size[4], int, 0444);
1843 MODULE_PARM_DESC(dev_perio_tx_fifo_size_5,
1844 "Number of words in the periodic Tx FIFO 4-768");
1845 module_param_named(dev_perio_tx_fifo_size_6,
1846 dwc_otg_module_params.dev_perio_tx_fifo_size[5], int, 0444);
1847 MODULE_PARM_DESC(dev_perio_tx_fifo_size_6,
1848 "Number of words in the periodic Tx FIFO 4-768");
1849 module_param_named(dev_perio_tx_fifo_size_7,
1850 dwc_otg_module_params.dev_perio_tx_fifo_size[6], int, 0444);
1851 MODULE_PARM_DESC(dev_perio_tx_fifo_size_7,
1852 "Number of words in the periodic Tx FIFO 4-768");
1853 module_param_named(dev_perio_tx_fifo_size_8,
1854 dwc_otg_module_params.dev_perio_tx_fifo_size[7], int, 0444);
1855 MODULE_PARM_DESC(dev_perio_tx_fifo_size_8,
1856 "Number of words in the periodic Tx FIFO 4-768");
1857 module_param_named(dev_perio_tx_fifo_size_9,
1858 dwc_otg_module_params.dev_perio_tx_fifo_size[8], int, 0444);
1859 MODULE_PARM_DESC(dev_perio_tx_fifo_size_9,
1860 "Number of words in the periodic Tx FIFO 4-768");
1861 module_param_named(dev_perio_tx_fifo_size_10,
1862 dwc_otg_module_params.dev_perio_tx_fifo_size[9], int, 0444);
1863 MODULE_PARM_DESC(dev_perio_tx_fifo_size_10,
1864 "Number of words in the periodic Tx FIFO 4-768");
1865 module_param_named(dev_perio_tx_fifo_size_11,
1866 dwc_otg_module_params.dev_perio_tx_fifo_size[10], int, 0444);
1867 MODULE_PARM_DESC(dev_perio_tx_fifo_size_11,
1868 "Number of words in the periodic Tx FIFO 4-768");
1869 module_param_named(dev_perio_tx_fifo_size_12,
1870 dwc_otg_module_params.dev_perio_tx_fifo_size[11], int, 0444);
1871 MODULE_PARM_DESC(dev_perio_tx_fifo_size_12,
1872 "Number of words in the periodic Tx FIFO 4-768");
1873 module_param_named(dev_perio_tx_fifo_size_13,
1874 dwc_otg_module_params.dev_perio_tx_fifo_size[12], int, 0444);
1875 MODULE_PARM_DESC(dev_perio_tx_fifo_size_13,
1876 "Number of words in the periodic Tx FIFO 4-768");
1877 module_param_named(dev_perio_tx_fifo_size_14,
1878 dwc_otg_module_params.dev_perio_tx_fifo_size[13], int, 0444);
1879 MODULE_PARM_DESC(dev_perio_tx_fifo_size_14,
1880 "Number of words in the periodic Tx FIFO 4-768");
1881 module_param_named(dev_perio_tx_fifo_size_15,
1882 dwc_otg_module_params.dev_perio_tx_fifo_size[14], int, 0444);
1883 MODULE_PARM_DESC(dev_perio_tx_fifo_size_15,
1884 "Number of words in the periodic Tx FIFO 4-768");
1885 module_param_named(host_rx_fifo_size, dwc_otg_module_params.host_rx_fifo_size,
1887 MODULE_PARM_DESC(host_rx_fifo_size, "Number of words in the Rx FIFO 16-32768");
1888 module_param_named(host_nperio_tx_fifo_size,
1889 dwc_otg_module_params.host_nperio_tx_fifo_size, int, 0444);
1890 MODULE_PARM_DESC(host_nperio_tx_fifo_size,
1891 "Number of words in the non-periodic Tx FIFO 16-32768");
1892 module_param_named(host_perio_tx_fifo_size,
1893 dwc_otg_module_params.host_perio_tx_fifo_size, int, 0444);
1894 MODULE_PARM_DESC(host_perio_tx_fifo_size,
1895 "Number of words in the host periodic Tx FIFO 16-32768");
1896 module_param_named(max_transfer_size, dwc_otg_module_params.max_transfer_size,
1898 /** @todo Set the max to 512K, modify checks */
1899 MODULE_PARM_DESC(max_transfer_size,
1900 "The maximum transfer size supported in bytes 2047-65535");
1901 module_param_named(max_packet_count, dwc_otg_module_params.max_packet_count,
1903 MODULE_PARM_DESC(max_packet_count,
1904 "The maximum number of packets in a transfer 15-511");
1905 module_param_named(host_channels, dwc_otg_module_params.host_channels, int,
1907 MODULE_PARM_DESC(host_channels,
1908 "The number of host channel registers to use 1-16");
1909 module_param_named(dev_endpoints, dwc_otg_module_params.dev_endpoints, int,
1911 MODULE_PARM_DESC(dev_endpoints,
1912 "The number of endpoints in addition to EP0 available for device mode 1-15");
1913 module_param_named(phy_type, dwc_otg_module_params.phy_type, int, 0444);
1914 MODULE_PARM_DESC(phy_type, "0=Reserved 1=UTMI+ 2=ULPI");
1915 module_param_named(phy_utmi_width, dwc_otg_module_params.phy_utmi_width, int,
1917 MODULE_PARM_DESC(phy_utmi_width, "Specifies the UTMI+ Data Width 8 or 16 bits");
1918 module_param_named(phy_ulpi_ddr, dwc_otg_module_params.phy_ulpi_ddr, int, 0444);
1919 MODULE_PARM_DESC(phy_ulpi_ddr,
1920 "ULPI at double or single data rate 0=Single 1=Double");
1921 module_param_named(phy_ulpi_ext_vbus, dwc_otg_module_params.phy_ulpi_ext_vbus,
1923 MODULE_PARM_DESC(phy_ulpi_ext_vbus,
1924 "ULPI PHY using internal or external vbus 0=Internal");
1925 module_param_named(i2c_enable, dwc_otg_module_params.i2c_enable, int, 0444);
1926 MODULE_PARM_DESC(i2c_enable, "FS PHY Interface");
1927 module_param_named(ulpi_fs_ls, dwc_otg_module_params.ulpi_fs_ls, int, 0444);
1928 MODULE_PARM_DESC(ulpi_fs_ls, "ULPI PHY FS/LS mode only");
1929 module_param_named(ts_dline, dwc_otg_module_params.ts_dline, int, 0444);
1930 MODULE_PARM_DESC(ts_dline, "Term select Dline pulsing for all PHYs");
1931 module_param_named(debug, g_dbg_lvl, int, 0444);
1932 MODULE_PARM_DESC(debug, "");
1934 module_param_named(en_multiple_tx_fifo,
1935 dwc_otg_module_params.en_multiple_tx_fifo, int, 0444);
1936 MODULE_PARM_DESC(en_multiple_tx_fifo,
1937 "Dedicated Non Periodic Tx FIFOs 0=disabled 1=enabled");
1938 module_param_named(dev_tx_fifo_size_1,
1939 dwc_otg_module_params.dev_tx_fifo_size[0], int, 0444);
1940 MODULE_PARM_DESC(dev_tx_fifo_size_1, "Number of words in the Tx FIFO 4-768");
1941 module_param_named(dev_tx_fifo_size_2,
1942 dwc_otg_module_params.dev_tx_fifo_size[1], int, 0444);
1943 MODULE_PARM_DESC(dev_tx_fifo_size_2, "Number of words in the Tx FIFO 4-768");
1944 module_param_named(dev_tx_fifo_size_3,
1945 dwc_otg_module_params.dev_tx_fifo_size[2], int, 0444);
1946 MODULE_PARM_DESC(dev_tx_fifo_size_3, "Number of words in the Tx FIFO 4-768");
1947 module_param_named(dev_tx_fifo_size_4,
1948 dwc_otg_module_params.dev_tx_fifo_size[3], int, 0444);
1949 MODULE_PARM_DESC(dev_tx_fifo_size_4, "Number of words in the Tx FIFO 4-768");
1950 module_param_named(dev_tx_fifo_size_5,
1951 dwc_otg_module_params.dev_tx_fifo_size[4], int, 0444);
1952 MODULE_PARM_DESC(dev_tx_fifo_size_5, "Number of words in the Tx FIFO 4-768");
1953 module_param_named(dev_tx_fifo_size_6,
1954 dwc_otg_module_params.dev_tx_fifo_size[5], int, 0444);
1955 MODULE_PARM_DESC(dev_tx_fifo_size_6, "Number of words in the Tx FIFO 4-768");
1956 module_param_named(dev_tx_fifo_size_7,
1957 dwc_otg_module_params.dev_tx_fifo_size[6], int, 0444);
1958 MODULE_PARM_DESC(dev_tx_fifo_size_7, "Number of words in the Tx FIFO 4-768");
1959 module_param_named(dev_tx_fifo_size_8,
1960 dwc_otg_module_params.dev_tx_fifo_size[7], int, 0444);
1961 MODULE_PARM_DESC(dev_tx_fifo_size_8, "Number of words in the Tx FIFO 4-768");
1962 module_param_named(dev_tx_fifo_size_9,
1963 dwc_otg_module_params.dev_tx_fifo_size[8], int, 0444);
1964 MODULE_PARM_DESC(dev_tx_fifo_size_9, "Number of words in the Tx FIFO 4-768");
1965 module_param_named(dev_tx_fifo_size_10,
1966 dwc_otg_module_params.dev_tx_fifo_size[9], int, 0444);
1967 MODULE_PARM_DESC(dev_tx_fifo_size_10, "Number of words in the Tx FIFO 4-768");
1968 module_param_named(dev_tx_fifo_size_11,
1969 dwc_otg_module_params.dev_tx_fifo_size[10], int, 0444);
1970 MODULE_PARM_DESC(dev_tx_fifo_size_11, "Number of words in the Tx FIFO 4-768");
1971 module_param_named(dev_tx_fifo_size_12,
1972 dwc_otg_module_params.dev_tx_fifo_size[11], int, 0444);
1973 MODULE_PARM_DESC(dev_tx_fifo_size_12, "Number of words in the Tx FIFO 4-768");
1974 module_param_named(dev_tx_fifo_size_13,
1975 dwc_otg_module_params.dev_tx_fifo_size[12], int, 0444);
1976 MODULE_PARM_DESC(dev_tx_fifo_size_13, "Number of words in the Tx FIFO 4-768");
1977 module_param_named(dev_tx_fifo_size_14,
1978 dwc_otg_module_params.dev_tx_fifo_size[13], int, 0444);
1979 MODULE_PARM_DESC(dev_tx_fifo_size_14, "Number of words in the Tx FIFO 4-768");
1980 module_param_named(dev_tx_fifo_size_15,
1981 dwc_otg_module_params.dev_tx_fifo_size[14], int, 0444);
1982 MODULE_PARM_DESC(dev_tx_fifo_size_15, "Number of words in the Tx FIFO 4-768");
1984 module_param_named(thr_ctl, dwc_otg_module_params.thr_ctl, int, 0444);
1985 MODULE_PARM_DESC(thr_ctl,
1986 "Thresholding enable flag bit 0 - non ISO Tx thr., 1 - ISO Tx thr., 2 - Rx thr.- bit 0=disabled 1=enabled");
1987 module_param_named(tx_thr_length, dwc_otg_module_params.tx_thr_length, int,
1989 MODULE_PARM_DESC(tx_thr_length, "Tx Threshold length in 32 bit DWORDs");
1990 module_param_named(rx_thr_length, dwc_otg_module_params.rx_thr_length, int,
1992 MODULE_PARM_DESC(rx_thr_length, "Rx Threshold length in 32 bit DWORDs");
1994 module_param_named(pti_enable, dwc_otg_module_params.pti_enable, int, 0444);
1995 module_param_named(mpi_enable, dwc_otg_module_params.mpi_enable, int, 0444);
1996 module_param_named(lpm_enable, dwc_otg_module_params.lpm_enable, int, 0444);
1997 MODULE_PARM_DESC(lpm_enable, "LPM Enable 0=LPM Disabled 1=LPM Enabled");
1999 module_param_named(besl_enable, dwc_otg_module_params.besl_enable, int, 0444);
2000 MODULE_PARM_DESC(besl_enable, "BESL Enable 0=BESL Disabled 1=BESL Enabled");
2001 module_param_named(baseline_besl, dwc_otg_module_params.baseline_besl, int,
2003 MODULE_PARM_DESC(baseline_besl, "Set the baseline besl value");
2004 module_param_named(deep_besl, dwc_otg_module_params.deep_besl, int, 0444);
2005 MODULE_PARM_DESC(deep_besl, "Set the deep besl value");
2007 module_param_named(ic_usb_cap, dwc_otg_module_params.ic_usb_cap, int, 0444);
2008 MODULE_PARM_DESC(ic_usb_cap,
2009 "IC_USB Capability 0=IC_USB Disabled 1=IC_USB Enabled");
2010 module_param_named(ahb_thr_ratio, dwc_otg_module_params.ahb_thr_ratio, int,
2012 MODULE_PARM_DESC(ahb_thr_ratio, "AHB Threshold Ratio");
2013 module_param_named(power_down, dwc_otg_module_params.power_down, int, 0444);
2014 MODULE_PARM_DESC(power_down, "Power Down Mode");
2015 module_param_named(reload_ctl, dwc_otg_module_params.reload_ctl, int, 0444);
2016 MODULE_PARM_DESC(reload_ctl, "HFIR Reload Control");
2017 module_param_named(dev_out_nak, dwc_otg_module_params.dev_out_nak, int, 0444);
2018 MODULE_PARM_DESC(dev_out_nak, "Enable Device OUT NAK");
2019 module_param_named(cont_on_bna, dwc_otg_module_params.cont_on_bna, int, 0444);
2020 MODULE_PARM_DESC(cont_on_bna, "Enable Enable Continue on BNA");
2021 module_param_named(ahb_single, dwc_otg_module_params.ahb_single, int, 0444);
2022 MODULE_PARM_DESC(ahb_single, "Enable AHB Single Support");
2023 module_param_named(adp_enable, dwc_otg_module_params.adp_enable, int, 0444);
2024 MODULE_PARM_DESC(adp_enable, "ADP Enable 0=ADP Disabled 1=ADP Enabled");
2025 module_param_named(otg_ver, dwc_otg_module_params.otg_ver, int, 0444);
2026 MODULE_PARM_DESC(otg_ver, "OTG revision supported 0=OTG 1.3 1=OTG 2.0");
2028 /** @page "Module Parameters"
2030 * The following parameters may be specified when starting the module.
2031 * These parameters define how the DWC_otg controller should be
2032 * configured. Parameter values are passed to the CIL initialization
2033 * function dwc_otg_cil_init
2035 * Example: <code>modprobe dwc_otg speed=1 otg_cap=1</code>
2039 <tr><td>Parameter Name</td><td>Meaning</td></tr>
2043 <td>Specifies the OTG capabilities. The driver will automatically detect the
2044 value for this parameter if none is specified.
2045 - 0: HNP and SRP capable (default, if available)
2046 - 1: SRP Only capable
2047 - 2: No HNP/SRP capable
2052 <td>Specifies whether to use slave or DMA mode for accessing the data FIFOs.
2053 The driver will automatically detect the value for this parameter if none is
2056 - 1: DMA (default, if available)
2060 <td>dma_burst_size</td>
2061 <td>The DMA Burst size (applicable only for External DMA Mode).
2062 - Values: 1, 4, 8 16, 32, 64, 128, 256 (default 32)
2067 <td>Specifies the maximum speed of operation in host and device mode. The
2068 actual speed depends on the speed of the attached device and the value of
2070 - 0: High Speed (default)
2075 <td>host_support_fs_ls_low_power</td>
2076 <td>Specifies whether low power mode is supported when attached to a Full
2077 Speed or Low Speed device in host mode.
2078 - 0: Don't support low power mode (default)
2079 - 1: Support low power mode
2083 <td>host_ls_low_power_phy_clk</td>
2084 <td>Specifies the PHY clock rate in low power mode when connected to a Low
2085 Speed device in host mode. This parameter is applicable only if
2086 HOST_SUPPORT_FS_LS_LOW_POWER is enabled.
2087 - 0: 48 MHz (default)
2092 <td>enable_dynamic_fifo</td>
2093 <td> Specifies whether FIFOs may be resized by the driver software.
2094 - 0: Use cC FIFO size parameters
2095 - 1: Allow dynamic FIFO sizing (default)
2099 <td>data_fifo_size</td>
2100 <td>Total number of 4-byte words in the data FIFO memory. This memory
2101 includes the Rx FIFO, non-periodic Tx FIFO, and periodic Tx FIFOs.
2102 - Values: 32 to 32768 (default 8192)
2104 Note: The total FIFO memory depth in the FPGA configuration is 8192.
2108 <td>dev_rx_fifo_size</td>
2109 <td>Number of 4-byte words in the Rx FIFO in device mode when dynamic
2110 FIFO sizing is enabled.
2111 - Values: 16 to 32768 (default 1064)
2115 <td>dev_nperio_tx_fifo_size</td>
2116 <td>Number of 4-byte words in the non-periodic Tx FIFO in device mode when
2117 dynamic FIFO sizing is enabled.
2118 - Values: 16 to 32768 (default 1024)
2122 <td>dev_perio_tx_fifo_size_n (n = 1 to 15)</td>
2123 <td>Number of 4-byte words in each of the periodic Tx FIFOs in device mode
2124 when dynamic FIFO sizing is enabled.
2125 - Values: 4 to 768 (default 256)
2129 <td>host_rx_fifo_size</td>
2130 <td>Number of 4-byte words in the Rx FIFO in host mode when dynamic FIFO
2132 - Values: 16 to 32768 (default 1024)
2136 <td>host_nperio_tx_fifo_size</td>
2137 <td>Number of 4-byte words in the non-periodic Tx FIFO in host mode when
2138 dynamic FIFO sizing is enabled in the core.
2139 - Values: 16 to 32768 (default 1024)
2143 <td>host_perio_tx_fifo_size</td>
2144 <td>Number of 4-byte words in the host periodic Tx FIFO when dynamic FIFO
2146 - Values: 16 to 32768 (default 1024)
2150 <td>max_transfer_size</td>
2151 <td>The maximum transfer size supported in bytes.
2152 - Values: 2047 to 65,535 (default 65,535)
2156 <td>max_packet_count</td>
2157 <td>The maximum number of packets in a transfer.
2158 - Values: 15 to 511 (default 511)
2162 <td>host_channels</td>
2163 <td>The number of host channel registers to use.
2164 - Values: 1 to 16 (default 12)
2166 Note: The FPGA configuration supports a maximum of 12 host channels.
2170 <td>dev_endpoints</td>
2171 <td>The number of endpoints in addition to EP0 available for device mode
2173 - Values: 1 to 15 (default 6 IN and OUT)
2175 Note: The FPGA configuration supports a maximum of 6 IN and OUT endpoints in
2181 <td>Specifies the type of PHY interface to use. By default, the driver will
2182 automatically detect the phy_type.
2184 - 1: UTMI+ (default, if available)
2189 <td>phy_utmi_width</td>
2190 <td>Specifies the UTMI+ Data Width. This parameter is applicable for a
2191 phy_type of UTMI+. Also, this parameter is applicable only if the
2192 OTG_HSPHY_WIDTH cC parameter was set to "8 and 16 bits", meaning that the
2193 core has been configured to work at either data path width.
2194 - Values: 8 or 16 bits (default 16)
2198 <td>phy_ulpi_ddr</td>
2199 <td>Specifies whether the ULPI operates at double or single data rate. This
2200 parameter is only applicable if phy_type is ULPI.
2201 - 0: single data rate ULPI interface with 8 bit wide data bus (default)
2202 - 1: double data rate ULPI interface with 4 bit wide data bus
2207 <td>Specifies whether to use the I2C interface for full speed PHY. This
2208 parameter is only applicable if PHY_TYPE is FS.
2209 - 0: Disabled (default)
2215 <td>Specifies whether to use ULPI FS/LS mode only.
2216 - 0: Disabled (default)
2222 <td>Specifies whether term select D-Line pulsing for all PHYs is enabled.
2223 - 0: Disabled (default)
2228 <td>en_multiple_tx_fifo</td>
2229 <td>Specifies whether dedicatedto tx fifos are enabled for non periodic IN EPs.
2230 The driver will automatically detect the value for this parameter if none is
2233 - 1: Enabled (default, if available)
2237 <td>dev_tx_fifo_size_n (n = 1 to 15)</td>
2238 <td>Number of 4-byte words in each of the Tx FIFOs in device mode
2239 when dynamic FIFO sizing is enabled.
2240 - Values: 4 to 768 (default 256)
2244 <td>tx_thr_length</td>
2245 <td>Transmit Threshold length in 32 bit double words
2246 - Values: 8 to 128 (default 64)
2250 <td>rx_thr_length</td>
2251 <td>Receive Threshold length in 32 bit double words
2252 - Values: 8 to 128 (default 64)
2257 <td>Specifies whether to enable Thresholding for Device mode. Bits 0, 1, 2 of
2258 this parmater specifies if thresholding is enabled for non-Iso Tx, Iso Tx and
2259 Rx transfers accordingly.
2260 The driver will automatically detect the value for this parameter if none is
2262 - Values: 0 to 7 (default 0)
2263 Bit values indicate:
2264 - 0: Thresholding disabled
2265 - 1: Thresholding enabled
2269 <td>dma_desc_enable</td>
2270 <td>Specifies whether to enable Descriptor DMA mode.
2271 The driver will automatically detect the value for this parameter if none is
2273 - 0: Descriptor DMA disabled
2274 - 1: Descriptor DMA (default, if available)
2279 <td>Specifies whether to enable MPI enhancement mode.
2280 The driver will automatically detect the value for this parameter if none is
2282 - 0: MPI disabled (default)
2288 <td>Specifies whether to enable PTI enhancement support.
2289 The driver will automatically detect the value for this parameter if none is
2291 - 0: PTI disabled (default)
2297 <td>Specifies whether to enable LPM support.
2298 The driver will automatically detect the value for this parameter if none is
2301 - 1: LPM enable (default, if available)
2305 <td>besl_enable</td>
2306 <td>Specifies whether to enable LPM Errata support.
2307 The driver will automatically detect the value for this parameter if none is
2309 - 0: LPM Errata disabled (default)
2310 - 1: LPM Errata enable
2314 <td>baseline_besl</td>
2315 <td>Specifies the baseline besl value.
2316 - Values: 0 to 15 (default 0)
2321 <td>Specifies the deep besl value.
2322 - Values: 0 to 15 (default 15)
2327 <td>Specifies whether to enable IC_USB capability.
2328 The driver will automatically detect the value for this parameter if none is
2330 - 0: IC_USB disabled (default, if available)
2335 <td>ahb_thr_ratio</td>
2336 <td>Specifies AHB Threshold ratio.
2337 - Values: 0 to 3 (default 0)
2342 <td>Specifies Power Down(Hibernation) Mode.
2343 The driver will automatically detect the value for this parameter if none is
2345 - 0: Power Down disabled (default)
2346 - 2: Power Down enabled
2351 <td>Specifies whether dynamic reloading of the HFIR register is allowed during
2352 run time. The driver will automatically detect the value for this parameter if
2353 none is specified. In case the HFIR value is reloaded when HFIR.RldCtrl == 1'b0
2354 the core might misbehave.
2355 - 0: Reload Control disabled (default)
2356 - 1: Reload Control enabled
2360 <td>dev_out_nak</td>
2361 <td>Specifies whether Device OUT NAK enhancement enabled or no.
2362 The driver will automatically detect the value for this parameter if
2363 none is specified. This parameter is valid only when OTG_EN_DESC_DMA == 1
\92b1.
2364 - 0: The core does not set NAK after Bulk OUT transfer complete (default)
2365 - 1: The core sets NAK after Bulk OUT transfer complete
2369 <td>cont_on_bna</td>
2370 <td>Specifies whether Enable Continue on BNA enabled or no.
2371 After receiving BNA interrupt the core disables the endpoint,when the
2372 endpoint is re-enabled by the application the
2373 - 0: Core starts processing from the DOEPDMA descriptor (default)
2374 - 1: Core starts processing from the descriptor which received the BNA.
2375 This parameter is valid only when OTG_EN_DESC_DMA == 1
\92b1.
2380 <td>This bit when programmed supports SINGLE transfers for remainder data
2381 in a transfer for DMA mode of operation.
2382 - 0: The remainder data will be sent using INCR burst size (default)
2383 - 1: The remainder data will be sent using SINGLE burst size.
2388 <td>Specifies whether ADP feature is enabled.
2389 The driver will automatically detect the value for this parameter if none is
2391 - 0: ADP feature disabled (default)
2392 - 1: ADP feature enabled
2397 <td>Specifies whether OTG is performing as USB OTG Revision 2.0 or Revision 1.3
2399 - 0: OTG 2.0 support disabled (default)
2400 - 1: OTG 2.0 support enabled