1 /* ==========================================================================
2 * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_driver.c $
7 * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
8 * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
9 * otherwise expressly agreed to in writing between Synopsys and you.
11 * The Software IS NOT an item of Licensed Software or Licensed Product under
12 * any End User Software License Agreement or Agreement for Licensed Product
13 * with Synopsys or any supplement thereto. You are permitted to use and
14 * redistribute this Software in source and binary forms, with or without
15 * modification, provided that redistributions of source code must retain this
16 * notice. You may not view, use, disclose, copy or distribute this file or
17 * any information contained herein except pursuant to this license grant from
18 * Synopsys. If you do not agree with this notice, including the disclaimer
19 * below, then you are not authorized to use the Software.
21 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
25 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
26 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
27 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
28 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
32 * ========================================================================== */
35 * The dwc_otg_driver module provides the initialization and cleanup entry
36 * points for the DWC_otg driver. This module will be dynamically installed
37 * after Linux is booted using the insmod command. When the module is
38 * installed, the dwc_otg_driver_init function is called. When the module is
39 * removed (using rmmod), the dwc_otg_driver_cleanup function is called.
41 * This module also defines a data structure for the dwc_otg_driver, which is
42 * used in conjunction with the standard ARM lm_device structure. These
43 * structures allow the OTG driver to comply with the standard Linux driver
44 * model in which devices and drivers are registered with a bus driver. This
45 * has the benefit that Linux can expose attributes of the driver and device
46 * in its special sysfs file system. Users can then read or write files in
47 * this file system to perform diagnostics on the driver components or the
51 #include "dwc_otg_os_dep.h"
52 #include "common_port/dwc_os.h"
53 #include "dwc_otg_dbg.h"
54 #include "dwc_otg_driver.h"
55 #include "dwc_otg_attr.h"
56 #include "dwc_otg_core_if.h"
57 #include "dwc_otg_pcd_if.h"
58 #include "dwc_otg_hcd_if.h"
59 #include "dwc_otg_cil.h"
60 #include "dwc_otg_pcd.h"
62 #include "usbdev_rk.h"
64 #define DWC_DRIVER_VERSION "3.10a 21-DEC-2012"
65 #define DWC_DRIVER_DESC "HS OTG USB Controller driver"
67 static const char dwc_host20_driver_name[] = "usb20_host";
68 static const char dwc_otg20_driver_name[] = "usb20_otg";
70 dwc_otg_device_t* g_otgdev = NULL;
72 extern int pcd_init( struct platform_device *_dev );
73 extern int otg20_hcd_init( struct platform_device *_dev );
74 extern int host20_hcd_init( struct platform_device *_dev );
75 extern int pcd_remove( struct platform_device *_dev );
76 extern void hcd_remove( struct platform_device *_dev);
77 extern void dwc_otg_adp_start( dwc_otg_core_if_t * core_if, uint8_t is_host);
79 #ifdef CONFIG_USB20_OTG
80 static struct usb20otg_pdata_id usb20otg_pdata[] = {
82 .name = "rk3188-usb20otg",
83 .pdata = &usb20otg_pdata_rk3188,
86 .name = "rk3288-usb20otg",
87 .pdata = &usb20otg_pdata_rk3288,
93 #ifdef CONFIG_USB20_HOST
94 static struct usb20host_pdata_id usb20host_pdata[] = {
96 .name = "rk3188-usb20host",
97 .pdata = &usb20host_pdata_rk3188,
100 .name = "rk3288-usb20host",
101 .pdata = &usb20host_pdata_rk3288,
107 #ifdef CONFIG_RK_USB_UART
108 static u32 usb_to_uart_status;
110 /*-------------------------------------------------------------------------*/
111 /* Encapsulate the module parameter settings */
113 struct dwc_otg_driver_module_params {
117 int32_t dma_desc_enable;
118 int32_t dma_burst_size;
120 int32_t host_support_fs_ls_low_power;
121 int32_t host_ls_low_power_phy_clk;
122 int32_t enable_dynamic_fifo;
123 int32_t data_fifo_size;
124 int32_t dev_rx_fifo_size;
125 int32_t dev_nperio_tx_fifo_size;
126 uint32_t dev_perio_tx_fifo_size[MAX_PERIO_FIFOS];
127 int32_t host_rx_fifo_size;
128 int32_t host_nperio_tx_fifo_size;
129 int32_t host_perio_tx_fifo_size;
130 int32_t max_transfer_size;
131 int32_t max_packet_count;
132 int32_t host_channels;
133 int32_t dev_endpoints;
135 int32_t phy_utmi_width;
136 int32_t phy_ulpi_ddr;
137 int32_t phy_ulpi_ext_vbus;
141 int32_t en_multiple_tx_fifo;
142 uint32_t dev_tx_fifo_size[MAX_TX_FIFOS];
144 uint32_t tx_thr_length;
145 uint32_t rx_thr_length;
150 int32_t baseline_besl;
153 int32_t ahb_thr_ratio;
163 static struct dwc_otg_driver_module_params dwc_otg_module_params = {
165 .otg_cap = DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE,
167 .dma_desc_enable = 0,
168 .dma_burst_size = -1,
170 .host_support_fs_ls_low_power = -1,
171 .host_ls_low_power_phy_clk = -1,
172 .enable_dynamic_fifo = 1,
173 .data_fifo_size = -1,
174 .dev_rx_fifo_size = 0x120,
175 .dev_nperio_tx_fifo_size = 0x10,
176 .dev_perio_tx_fifo_size = {
177 /* dev_perio_tx_fifo_size_1 */
195 .host_rx_fifo_size = -1,
196 .host_nperio_tx_fifo_size = -1,
197 .host_perio_tx_fifo_size = -1,
198 .max_transfer_size = -1,
199 .max_packet_count = -1,
203 .phy_utmi_width = -1,
205 .phy_ulpi_ext_vbus = -1,
209 .en_multiple_tx_fifo = -1,
210 .dev_tx_fifo_size = {
211 /* dev_tx_fifo_size */
249 #ifdef CONFIG_USB20_HOST
250 static struct dwc_otg_driver_module_params dwc_host_module_params = {
252 .otg_cap = DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE,
254 .dma_desc_enable = 0,
255 .dma_burst_size = -1,
257 .host_support_fs_ls_low_power = -1,
258 .host_ls_low_power_phy_clk = -1,
259 .enable_dynamic_fifo = -1,
260 .data_fifo_size = -1,
261 .dev_rx_fifo_size = -1,
262 .dev_nperio_tx_fifo_size = -1,
263 .dev_perio_tx_fifo_size = {
264 /* dev_perio_tx_fifo_size_1 */
282 .host_rx_fifo_size = -1,
283 .host_nperio_tx_fifo_size = -1,
284 .host_perio_tx_fifo_size = -1,
285 .max_transfer_size = -1,
286 .max_packet_count = -1,
290 .phy_utmi_width = -1,
292 .phy_ulpi_ext_vbus = -1,
296 .en_multiple_tx_fifo = -1,
297 .dev_tx_fifo_size = {
298 /* dev_tx_fifo_size */
338 * This function shows the Driver Version.
340 static ssize_t version_show(struct device_driver *dev, char *buf)
342 return snprintf(buf, sizeof(DWC_DRIVER_VERSION) + 2, "%s\n",
346 static DRIVER_ATTR(version, S_IRUGO, version_show, NULL);
349 * Global Debug Level Mask.
351 uint32_t g_dbg_lvl = DBG_OFF; /* OFF */
354 * This function shows the driver Debug Level.
356 static ssize_t dbg_level_show(struct device_driver *drv, char *buf)
358 return sprintf(buf, "0x%0x\n", g_dbg_lvl);
362 * This function stores the driver Debug Level.
364 static ssize_t dbg_level_store(struct device_driver *drv, const char *buf,
367 g_dbg_lvl = simple_strtoul(buf, NULL, 16);
371 static DRIVER_ATTR(debuglevel, S_IRUGO | S_IWUSR, dbg_level_show,
374 extern void hcd_start(dwc_otg_core_if_t *core_if);
375 extern struct usb_hub *g_dwc_otg_root_hub20;
376 extern void dwc_otg_hub_disconnect_device(struct usb_hub *hub);
378 void dwc_otg_force_host(dwc_otg_core_if_t *core_if)
380 dwc_otg_device_t *otg_dev = core_if->otg_dev;
381 dctl_data_t dctl = {.d32=0};
384 if(core_if->op_state == A_HOST)
386 printk("dwc_otg_force_host,already in A_HOST mode,everest\n");
389 core_if->op_state = A_HOST;
391 cancel_delayed_work(&otg_dev->pcd->check_vbus_work);
392 dctl.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dctl);
393 dctl.b.sftdiscon = 1;
394 DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dctl, dctl.d32);
396 local_irq_save(flags);
397 cil_pcd_stop(core_if);
399 * Initialize the Core for Host mode.
402 dwc_otg_core_init(core_if);
403 dwc_otg_enable_global_interrupts(core_if);
404 cil_hcd_start(core_if);
405 local_irq_restore(flags);
407 void dwc_otg_force_device(dwc_otg_core_if_t *core_if)
409 dwc_otg_device_t *otg_dev = core_if->otg_dev;
412 local_irq_save(flags);
414 if(core_if->op_state == B_PERIPHERAL) {
415 printk("dwc_otg_force_device,already in B_PERIPHERAL,everest\n");
418 core_if->op_state = B_PERIPHERAL;
419 cil_hcd_stop(core_if);
420 //dwc_otg_hub_disconnect_device(g_dwc_otg_root_hub20);
421 otg_dev->pcd->phy_suspend = 1;
422 otg_dev->pcd->vbus_status = 0;
423 dwc_otg_pcd_start_check_vbus_work(otg_dev->pcd);
425 /* Reset the Controller */
426 dwc_otg_core_reset( core_if );
428 dwc_otg_core_init(core_if);
429 dwc_otg_disable_global_interrupts(core_if);
430 cil_pcd_start(core_if);
432 local_irq_restore(flags);
434 static void dwc_otg_set_force_mode(dwc_otg_core_if_t *core_if, int mode)
436 gusbcfg_data_t usbcfg = { .d32 = 0 };
437 printk("!!!dwc_otg_set_force_mode\n");
438 usbcfg.d32 = DWC_READ_REG32( &core_if->core_global_regs->gusbcfg);
440 case USB_MODE_FORCE_HOST:
441 usbcfg.b.force_host_mode = 1;
442 usbcfg.b.force_dev_mode = 0;
444 case USB_MODE_FORCE_DEVICE:
445 usbcfg.b.force_host_mode = 0;
446 usbcfg.b.force_dev_mode = 1;
448 case USB_MODE_NORMAL:
449 usbcfg.b.force_host_mode = 0;
450 usbcfg.b.force_dev_mode = 0;
453 DWC_WRITE_REG32( &core_if->core_global_regs->gusbcfg, usbcfg.d32 );
456 static ssize_t force_usb_mode_show(struct device_driver *drv, char *buf)
458 dwc_otg_device_t *otg_dev = g_otgdev;
459 dwc_otg_core_if_t *core_if = otg_dev->core_if;
461 return sprintf(buf, "%d\n", core_if->usb_mode);
464 static ssize_t force_usb_mode_store(struct device_driver *drv, const char *buf,
467 int new_mode = simple_strtoul(buf, NULL, 16);
468 dwc_otg_device_t *otg_dev = g_otgdev;
469 dwc_otg_core_if_t *core_if;
470 struct dwc_otg_platform_data *pldata;
475 core_if = otg_dev->core_if;
476 pldata = otg_dev->pldata;
478 DWC_PRINTF("%s %d->%d\n",__func__, core_if->usb_mode, new_mode);
480 if(core_if->usb_mode == new_mode) {
484 if(pldata->phy_status == USB_PHY_SUSPEND) {
485 pldata->clock_enable(pldata, 1);
486 pldata->phy_suspend(pldata, USB_PHY_ENABLED);
490 case USB_MODE_FORCE_HOST:
491 if(USB_MODE_FORCE_DEVICE == core_if->usb_mode) {
493 core_if->usb_mode = new_mode;
494 dwc_otg_force_host(core_if);
495 } else if(USB_MODE_NORMAL == core_if->usb_mode) {
496 core_if->usb_mode = new_mode;
497 if(dwc_otg_is_host_mode(core_if)) {
498 dwc_otg_set_force_mode(core_if, new_mode);
500 dwc_otg_force_host(core_if);
505 case USB_MODE_FORCE_DEVICE:
506 if(USB_MODE_FORCE_HOST == core_if->usb_mode) {
507 core_if->usb_mode = new_mode;
508 dwc_otg_force_device(core_if);
509 } else if(USB_MODE_NORMAL == core_if->usb_mode) {
510 core_if->usb_mode = new_mode;
511 if(dwc_otg_is_device_mode(core_if)) {
512 dwc_otg_set_force_mode(core_if, new_mode);
514 dwc_otg_force_device(core_if);
519 case USB_MODE_NORMAL:
520 if(USB_MODE_FORCE_DEVICE == core_if->usb_mode) {
521 core_if->usb_mode = new_mode;
522 cancel_delayed_work(&otg_dev->pcd->check_vbus_work);
523 dwc_otg_set_force_mode(core_if, new_mode);
525 if(dwc_otg_is_host_mode(core_if)) {
526 dwc_otg_force_host(core_if);
528 dwc_otg_pcd_start_check_vbus_work(otg_dev->pcd);
530 } else if(USB_MODE_FORCE_HOST == core_if->usb_mode) {
531 core_if->usb_mode = new_mode;
532 dwc_otg_set_force_mode(core_if, new_mode);
534 if(dwc_otg_is_device_mode(core_if)) {
535 dwc_otg_force_device(core_if);
546 static DRIVER_ATTR(force_usb_mode, S_IRUGO | S_IWUSR, force_usb_mode_show, force_usb_mode_store);
549 static ssize_t dwc_otg_conn_en_show(struct device_driver *_drv, char *_buf)
552 dwc_otg_device_t *otg_dev = g_otgdev;
553 dwc_otg_pcd_t *_pcd = otg_dev->pcd;
554 return sprintf (_buf, "%d\n", _pcd->conn_en);
558 static ssize_t dwc_otg_conn_en_store(struct device_driver *_drv, const char *_buf,
561 int enable = simple_strtoul(_buf, NULL, 10);
562 dwc_otg_device_t *otg_dev = g_otgdev;
563 dwc_otg_pcd_t *_pcd = otg_dev->pcd;
564 DWC_PRINTF("%s %d->%d\n",__func__, _pcd->conn_en, enable);
566 _pcd->conn_en = enable;
569 static DRIVER_ATTR(dwc_otg_conn_en, S_IRUGO|S_IWUSR, dwc_otg_conn_en_show, dwc_otg_conn_en_store);
571 static ssize_t vbus_status_show(struct device_driver *_drv, char *_buf)
573 dwc_otg_device_t *otg_dev = g_otgdev;
574 dwc_otg_pcd_t *_pcd = otg_dev->pcd;
575 return sprintf (_buf, "%d\n", _pcd->vbus_status);
577 static DRIVER_ATTR(vbus_status, S_IRUGO, vbus_status_show, NULL);
580 * This function is called during module intialization
581 * to pass module parameters to the DWC_OTG CORE.
583 static int set_parameters(dwc_otg_core_if_t * core_if, struct dwc_otg_driver_module_params module_params)
588 if (module_params.otg_cap != -1) {
590 dwc_otg_set_param_otg_cap(core_if,
591 module_params.otg_cap);
593 if (module_params.dma_enable != -1) {
595 dwc_otg_set_param_dma_enable(core_if,
599 if (module_params.dma_desc_enable != -1) {
601 dwc_otg_set_param_dma_desc_enable(core_if,
605 if (module_params.opt != -1) {
607 dwc_otg_set_param_opt(core_if, module_params.opt);
609 if (module_params.dma_burst_size != -1) {
611 dwc_otg_set_param_dma_burst_size(core_if,
615 if (module_params.host_support_fs_ls_low_power != -1) {
617 dwc_otg_set_param_host_support_fs_ls_low_power(core_if,
619 host_support_fs_ls_low_power);
621 if (module_params.enable_dynamic_fifo != -1) {
623 dwc_otg_set_param_enable_dynamic_fifo(core_if,
625 enable_dynamic_fifo);
627 if (module_params.data_fifo_size != -1) {
629 dwc_otg_set_param_data_fifo_size(core_if,
633 if (module_params.dev_rx_fifo_size != -1) {
635 dwc_otg_set_param_dev_rx_fifo_size(core_if,
639 if (module_params.dev_nperio_tx_fifo_size != -1) {
641 dwc_otg_set_param_dev_nperio_tx_fifo_size(core_if,
643 dev_nperio_tx_fifo_size);
645 if (module_params.host_rx_fifo_size != -1) {
647 dwc_otg_set_param_host_rx_fifo_size(core_if,
648 module_params.host_rx_fifo_size);
650 if (module_params.host_nperio_tx_fifo_size != -1) {
652 dwc_otg_set_param_host_nperio_tx_fifo_size(core_if,
654 host_nperio_tx_fifo_size);
656 if (module_params.host_perio_tx_fifo_size != -1) {
658 dwc_otg_set_param_host_perio_tx_fifo_size(core_if,
660 host_perio_tx_fifo_size);
662 if (module_params.max_transfer_size != -1) {
664 dwc_otg_set_param_max_transfer_size(core_if,
668 if (module_params.max_packet_count != -1) {
670 dwc_otg_set_param_max_packet_count(core_if,
674 if (module_params.host_channels != -1) {
676 dwc_otg_set_param_host_channels(core_if,
680 if (module_params.dev_endpoints != -1) {
682 dwc_otg_set_param_dev_endpoints(core_if,
686 if (module_params.phy_type != -1) {
688 dwc_otg_set_param_phy_type(core_if,
689 module_params.phy_type);
691 if (module_params.speed != -1) {
693 dwc_otg_set_param_speed(core_if,
694 module_params.speed);
696 if (module_params.host_ls_low_power_phy_clk != -1) {
698 dwc_otg_set_param_host_ls_low_power_phy_clk(core_if,
700 host_ls_low_power_phy_clk);
702 if (module_params.phy_ulpi_ddr != -1) {
704 dwc_otg_set_param_phy_ulpi_ddr(core_if,
708 if (module_params.phy_ulpi_ext_vbus != -1) {
710 dwc_otg_set_param_phy_ulpi_ext_vbus(core_if,
714 if (module_params.phy_utmi_width != -1) {
716 dwc_otg_set_param_phy_utmi_width(core_if,
720 if (module_params.ulpi_fs_ls != -1) {
722 dwc_otg_set_param_ulpi_fs_ls(core_if,
723 module_params.ulpi_fs_ls);
725 if (module_params.ts_dline != -1) {
727 dwc_otg_set_param_ts_dline(core_if,
728 module_params.ts_dline);
730 if (module_params.i2c_enable != -1) {
732 dwc_otg_set_param_i2c_enable(core_if,
736 if (module_params.en_multiple_tx_fifo != -1) {
738 dwc_otg_set_param_en_multiple_tx_fifo(core_if,
740 en_multiple_tx_fifo);
742 for (i = 0; i < 15; i++) {
743 if (module_params.dev_perio_tx_fifo_size[i] != -1) {
745 dwc_otg_set_param_dev_perio_tx_fifo_size(core_if,
747 dev_perio_tx_fifo_size
752 for (i = 0; i < 15; i++) {
753 if (module_params.dev_tx_fifo_size[i] != -1) {
754 retval += dwc_otg_set_param_dev_tx_fifo_size(core_if,
760 if (module_params.thr_ctl != -1) {
762 dwc_otg_set_param_thr_ctl(core_if,
763 module_params.thr_ctl);
765 if (module_params.mpi_enable != -1) {
767 dwc_otg_set_param_mpi_enable(core_if,
771 if (module_params.pti_enable != -1) {
773 dwc_otg_set_param_pti_enable(core_if,
777 if (module_params.lpm_enable != -1) {
779 dwc_otg_set_param_lpm_enable(core_if,
783 if (module_params.besl_enable != -1) {
785 dwc_otg_set_param_besl_enable(core_if,
789 if (module_params.baseline_besl != -1) {
791 dwc_otg_set_param_baseline_besl(core_if,
795 if (module_params.deep_besl != -1) {
797 dwc_otg_set_param_deep_besl(core_if,
801 if (module_params.ic_usb_cap != -1) {
803 dwc_otg_set_param_ic_usb_cap(core_if,
807 if (module_params.tx_thr_length != -1) {
809 dwc_otg_set_param_tx_thr_length(core_if,
810 module_params.tx_thr_length);
812 if (module_params.rx_thr_length != -1) {
814 dwc_otg_set_param_rx_thr_length(core_if,
818 if (module_params.ahb_thr_ratio != -1) {
820 dwc_otg_set_param_ahb_thr_ratio(core_if,
821 module_params.ahb_thr_ratio);
823 if (module_params.power_down != -1) {
825 dwc_otg_set_param_power_down(core_if,
826 module_params.power_down);
828 if (module_params.reload_ctl != -1) {
830 dwc_otg_set_param_reload_ctl(core_if,
831 module_params.reload_ctl);
834 if (module_params.dev_out_nak != -1) {
836 dwc_otg_set_param_dev_out_nak(core_if,
837 module_params.dev_out_nak);
840 if (module_params.cont_on_bna != -1) {
842 dwc_otg_set_param_cont_on_bna(core_if,
843 module_params.cont_on_bna);
846 if (module_params.ahb_single != -1) {
848 dwc_otg_set_param_ahb_single(core_if,
849 module_params.ahb_single);
852 if (module_params.otg_ver != -1) {
854 dwc_otg_set_param_otg_ver(core_if,
855 module_params.otg_ver);
857 if (module_params.adp_enable != -1) {
859 dwc_otg_set_param_adp_enable(core_if,
867 * This function is the top level interrupt handler for the Common
868 * (Device and host modes) interrupts.
870 static irqreturn_t dwc_otg_common_irq(int irq, void *dev)
872 int32_t retval = IRQ_NONE;
874 retval = dwc_otg_handle_common_intr(dev);
876 //S3C2410X_CLEAR_EINTPEND();
878 return IRQ_RETVAL(retval);
881 #ifdef CONFIG_USB20_HOST
883 * This function is called when a lm_device is unregistered with the
884 * dwc_otg_driver. This happens, for example, when the rmmod command is
885 * executed. The device may or may not be electrically present. If it is
886 * present, the driver stops device processing. Any resources used on behalf
887 * of this device are freed.
891 static int host20_driver_remove( struct platform_device *_dev )
894 dwc_otg_device_t *otg_dev = dwc_get_device_platform_data(_dev);
895 DWC_DEBUGPL(DBG_ANY, "%s(%p)\n", __func__, _dev);
898 /* Memory allocation for the dwc_otg_device failed. */
899 DWC_DEBUGPL(DBG_ANY, "%s: otg_dev NULL!\n", __func__);
903 #ifndef DWC_DEVICE_ONLY
907 DWC_DEBUGPL(DBG_ANY, "%s: otg_dev->hcd NULL!\n", __func__);
912 #ifndef DWC_HOST_ONLY
916 DWC_DEBUGPL(DBG_ANY, "%s: otg_dev->pcd NULL!\n", __func__);
924 if (otg_dev->common_irq_installed) {
925 //free_irq(_dev->irq, otg_dev);
926 free_irq(platform_get_irq(_dev,0), otg_dev );
928 DWC_DEBUGPL(DBG_ANY, "%s: There is no installed irq!\n", __func__);
932 if (otg_dev->core_if) {
933 dwc_otg_cil_remove(otg_dev->core_if);
935 DWC_DEBUGPL(DBG_ANY, "%s: otg_dev->core_if NULL!\n", __func__);
940 * Remove the device attributes
942 dwc_otg_attr_remove(_dev);
947 if (otg_dev->os_dep.base) {
948 iounmap(otg_dev->os_dep.base);
953 * Clear the drvdata pointer.
956 dwc_set_device_platform_data(_dev, 0);
961 static const struct of_device_id usb20_host_of_match[] = {
963 .compatible = "rockchip,rk3188_usb20_host",
964 .data = &usb20host_pdata[RK3188_USB_CTLR],
967 .compatible = "rockchip,rk3288_usb20_host",
968 .data = &usb20host_pdata[RK3288_USB_CTLR],
972 MODULE_DEVICE_TABLE(of, usb20_host_of_match);
975 * This function is called when an lm_device is bound to a
976 * dwc_otg_driver. It creates the driver components required to
977 * control the device (CIL, HCD, and PCD) and it initializes the
978 * device. The driver components are stored in a dwc_otg_device
979 * structure. A reference to the dwc_otg_device is saved in the
980 * lm_device. This allows the driver to access the dwc_otg_device
981 * structure on subsequent calls to driver methods for this device.
983 * @param _dev Bus device
985 static int host20_driver_probe(struct platform_device *_dev)
989 struct resource *res_base;
990 dwc_otg_device_t *dwc_otg_device;
991 struct device *dev = &_dev->dev;
992 struct device_node *node = _dev->dev.of_node;
993 struct dwc_otg_platform_data *pldata;
994 struct usb20host_pdata_id *p;
995 const struct of_device_id *match =
996 of_match_device(of_match_ptr( usb20_host_of_match ), &_dev->dev);
999 p = (struct usb20host_pdata_id *)match->data;
1001 dev_err(dev, "usb20host match failed\n");
1005 dev->platform_data = p->pdata;
1006 pldata = dev->platform_data;
1010 dev_err(dev, "device node not found\n");
1017 if(pldata->clock_init){
1018 pldata->clock_init(pldata);
1019 pldata->clock_enable(pldata, 1);
1022 if(pldata->phy_suspend)
1023 pldata->phy_suspend(pldata, USB_PHY_ENABLED);
1025 if(pldata->soft_reset)
1026 pldata->soft_reset();
1028 res_base=platform_get_resource(_dev, IORESOURCE_MEM, 0);
1030 dwc_otg_device = DWC_ALLOC(sizeof(dwc_otg_device_t));
1032 if (!dwc_otg_device) {
1033 dev_err(&_dev->dev, "kmalloc of dwc_otg_device failed\n");
1038 memset(dwc_otg_device, 0, sizeof(*dwc_otg_device));
1039 dwc_otg_device->os_dep.reg_offset = 0xFFFFFFFF;
1042 * Map the DWC_otg Core memory into virtual address space.
1045 dwc_otg_device->os_dep.base = devm_ioremap_resource(dev, res_base);
1047 if (!dwc_otg_device->os_dep.base) {
1048 dev_err(&_dev->dev, "ioremap() failed\n");
1049 DWC_FREE(dwc_otg_device);
1053 dev_dbg(&_dev->dev, "base=0x%08x\n",
1054 (unsigned)dwc_otg_device->os_dep.base);
1057 * Initialize driver data to point to the global DWC_otg
1061 dwc_set_device_platform_data(_dev, dwc_otg_device);
1062 pldata->privdata = dwc_otg_device;
1063 dwc_otg_device->pldata = (void *)pldata;
1065 dev_dbg(&_dev->dev, "dwc_otg_device=0x%p\n", dwc_otg_device);
1067 dwc_otg_device->core_if = dwc_otg_cil_init(dwc_otg_device->os_dep.base);
1070 if (!dwc_otg_device->core_if) {
1071 dev_err(&_dev->dev, "CIL initialization failed!\n");
1076 dwc_otg_device->core_if->otg_dev= dwc_otg_device;
1079 * Attempt to ensure this device is really a DWC_otg Controller.
1080 * Read and verify the SNPSID register contents. The value should be
1081 * 0x45F42XXX or 0x45F42XXX, which corresponds to either "OT2" or "OTG3",
1082 * as in "OTG version 2.XX" or "OTG version 3.XX".
1085 if (((dwc_otg_get_gsnpsid(dwc_otg_device->core_if) & 0xFFFFF000) != 0x4F542000) &&
1086 ((dwc_otg_get_gsnpsid(dwc_otg_device->core_if) & 0xFFFFF000) != 0x4F543000)) {
1087 dev_err(&_dev->dev, "Bad value for SNPSID: 0x%08x\n",
1088 dwc_otg_get_gsnpsid(dwc_otg_device->core_if));
1094 * Validate parameter values.
1096 if (set_parameters(dwc_otg_device->core_if ,dwc_host_module_params )) {
1102 * Create Device Attributes in sysfs
1104 dwc_otg_attr_create(_dev);
1107 * Disable the global interrupt until all the interrupt
1108 * handlers are installed.
1110 dwc_otg_disable_global_interrupts(dwc_otg_device->core_if);
1113 * Install the interrupt handler for the common interrupts before
1114 * enabling common interrupts in core_init below.
1116 irq = platform_get_irq(_dev,0);
1117 DWC_DEBUGPL(DBG_CIL, "registering (common) handler for irq%d\n",
1119 retval = request_irq(irq, dwc_otg_common_irq,
1120 IRQF_SHARED , "dwc_otg",
1123 DWC_ERROR("request of irq%d failed\n", irq);
1127 dwc_otg_device->common_irq_installed = 1;
1131 * Initialize the DWC_otg core.
1132 * In order to reduce the time of initialization,
1133 * we do core soft reset after connection detected.
1135 dwc_otg_core_init_no_reset(dwc_otg_device->core_if);
1138 * Initialize the HCD
1140 retval = host20_hcd_init(_dev);
1142 DWC_ERROR("hcd_init failed\n");
1143 dwc_otg_device->hcd = NULL;
1147 clk_set_rate(pldata->phyclk_480m, 480000000);
1149 * Enable the global interrupt after all the interrupt
1150 * handlers are installed if there is no ADP support else
1151 * perform initial actions required for Internal ADP logic.
1153 if (!dwc_otg_get_param_adp_enable(dwc_otg_device->core_if)) {
1154 if( pldata->phy_status == USB_PHY_ENABLED ){
1155 pldata->phy_suspend(pldata, USB_PHY_SUSPEND);
1157 pldata->clock_enable( pldata, 0);
1159 // dwc_otg_enable_global_interrupts(dwc_otg_device->core_if);
1162 dwc_otg_adp_start(dwc_otg_device->core_if,
1163 dwc_otg_is_host_mode(dwc_otg_device->core_if));
1168 host20_driver_remove(_dev);
1170 if(pldata->clock_enable)
1171 pldata->clock_enable(pldata, 0);
1177 static int dwc_otg_driver_suspend(struct platform_device *_dev , pm_message_t state )
1182 static int dwc_otg_driver_resume(struct platform_device *_dev )
1187 static void dwc_otg_driver_shutdown(struct platform_device *_dev )
1189 struct device *dev = &_dev->dev;
1190 dwc_otg_device_t *otg_dev = dev->platform_data;
1191 dwc_otg_core_if_t *core_if = otg_dev->core_if;
1192 dctl_data_t dctl = {.d32=0};
1194 DWC_PRINTF("%s: disconnect USB %s mode\n" , __func__ ,
1195 dwc_otg_is_host_mode(core_if) ? "host" : "device");
1196 if(dwc_otg_is_host_mode(core_if))
1198 if (core_if->hcd_cb && core_if->hcd_cb->stop)
1200 core_if->hcd_cb->stop( core_if->hcd_cb_p);
1205 /* soft disconnect */
1206 dctl.d32 = DWC_READ_REG32( &core_if->dev_if->dev_global_regs->dctl );
1207 dctl.b.sftdiscon = 1;
1208 DWC_WRITE_REG32( &core_if->dev_if->dev_global_regs->dctl, dctl.d32 );
1210 /* Clear any pending interrupts */
1211 DWC_WRITE_REG32( &core_if->core_global_regs->gintsts, 0xFFFFFFFF);
1217 * This structure defines the methods to be called by a bus driver
1218 * during the lifecycle of a device on that bus. Both drivers and
1219 * devices are registered with a bus driver. The bus driver matches
1220 * devices to drivers based on information in the device and driver
1223 * The probe function is called when the bus driver matches a device
1224 * to this driver. The remove function is called when a device is
1225 * unregistered with the bus driver.
1227 #ifdef CONFIG_USB20_HOST
1228 static struct platform_driver dwc_host_driver = {
1230 .name = (char *)dwc_host20_driver_name,
1231 .of_match_table = of_match_ptr(usb20_host_of_match),
1233 .probe = host20_driver_probe,
1234 .remove = host20_driver_remove,
1235 .suspend = dwc_otg_driver_suspend,
1236 .resume = dwc_otg_driver_resume,
1240 #ifdef CONFIG_USB20_OTG
1242 * This function is called when a lm_device is unregistered with the
1243 * dwc_otg_driver. This happens, for example, when the rmmod command is
1244 * executed. The device may or may not be electrically present. If it is
1245 * present, the driver stops device processing. Any resources used on behalf
1246 * of this device are freed.
1250 static int otg20_driver_remove( struct platform_device *_dev )
1253 dwc_otg_device_t *otg_dev = dwc_get_device_platform_data(_dev);
1254 DWC_DEBUGPL(DBG_ANY, "%s(%p)\n", __func__, _dev);
1257 /* Memory allocation for the dwc_otg_device failed. */
1258 DWC_DEBUGPL(DBG_ANY, "%s: otg_dev NULL!\n", __func__);
1261 #ifndef DWC_DEVICE_ONLY
1265 DWC_DEBUGPL(DBG_ANY, "%s: otg_dev->hcd NULL!\n", __func__);
1270 #ifndef DWC_HOST_ONLY
1274 DWC_DEBUGPL(DBG_ANY, "%s: otg_dev->pcd NULL!\n", __func__);
1281 if (otg_dev->common_irq_installed) {
1282 //free_irq(_dev->irq, otg_dev);
1283 free_irq(platform_get_irq(_dev,0), otg_dev );
1285 DWC_DEBUGPL(DBG_ANY, "%s: There is no installed irq!\n", __func__);
1289 if (otg_dev->core_if) {
1290 dwc_otg_cil_remove(otg_dev->core_if);
1292 DWC_DEBUGPL(DBG_ANY, "%s: otg_dev->core_if NULL!\n", __func__);
1297 * Remove the device attributes
1299 dwc_otg_attr_remove(_dev);
1302 * Return the memory.
1304 if (otg_dev->os_dep.base) {
1305 iounmap(otg_dev->os_dep.base);
1310 * Clear the drvdata pointer.
1313 dwc_set_device_platform_data(_dev, 0);
1318 static const struct of_device_id usb20_otg_of_match[] = {
1320 .compatible = "rockchip,rk3188_usb20_otg",
1321 .data = &usb20otg_pdata[RK3188_USB_CTLR],
1324 .compatible = "rockchip,rk3288_usb20_otg",
1325 .data = &usb20otg_pdata[RK3288_USB_CTLR],
1330 MODULE_DEVICE_TABLE(of, usb20_otg_of_match);
1333 * This function is called when an lm_device is bound to a
1334 * dwc_otg_driver. It creates the driver components required to
1335 * control the device (CIL, HCD, and PCD) and it initializes the
1336 * device. The driver components are stored in a dwc_otg_device
1337 * structure. A reference to the dwc_otg_device is saved in the
1338 * lm_device. This allows the driver to access the dwc_otg_device
1339 * structure on subsequent calls to driver methods for this device.
1341 * @param _dev Bus device
1343 static int otg20_driver_probe(struct platform_device *_dev)
1348 struct resource *res_base;
1349 dwc_otg_device_t *dwc_otg_device;
1350 struct device *dev = &_dev->dev;
1351 struct device_node *node = _dev->dev.of_node;
1352 struct dwc_otg_platform_data *pldata;
1353 struct usb20otg_pdata_id *p;
1354 const struct of_device_id *match =
1355 of_match_device(of_match_ptr( usb20_otg_of_match ), &_dev->dev);
1358 p = (struct usb20otg_pdata_id *)match->data;
1360 dev_err(dev, "usb20otg match failed\n");
1364 dev->platform_data = p->pdata;
1365 // dev->platform_data = &usb20otg_pdata;
1366 pldata = dev->platform_data;
1370 dev_err(dev, "device node not found\n");
1373 /*todo : move to usbdev_rk-XX.c*/
1377 if(pldata->clock_init){
1378 pldata->clock_init(pldata);
1379 pldata->clock_enable(pldata, 1);
1382 if(pldata->phy_suspend)
1383 pldata->phy_suspend(pldata, USB_PHY_ENABLED);
1385 if(pldata->dwc_otg_uart_mode)
1386 pldata->dwc_otg_uart_mode(pldata, PHY_USB_MODE);
1388 /* do reset later, because reset need about
1389 * 100ms to ensure otg id state change.
1392 if(pldata->soft_reset)
1393 pldata->soft_reset();
1397 res_base=platform_get_resource(_dev, IORESOURCE_MEM, 0);
1399 dwc_otg_device = DWC_ALLOC(sizeof(dwc_otg_device_t));
1401 if (!dwc_otg_device) {
1402 dev_err(&_dev->dev, "kmalloc of dwc_otg_device failed\n");
1407 memset(dwc_otg_device, 0, sizeof(*dwc_otg_device));
1408 dwc_otg_device->os_dep.reg_offset = 0xFFFFFFFF;
1411 * Map the DWC_otg Core memory into virtual address space.
1414 dwc_otg_device->os_dep.base = devm_ioremap_resource(dev, res_base);
1416 if (!dwc_otg_device->os_dep.base) {
1417 dev_err(&_dev->dev, "ioremap() failed\n");
1418 DWC_FREE(dwc_otg_device);
1422 dev_dbg(&_dev->dev, "base=0x%08x\n",
1423 (unsigned)dwc_otg_device->os_dep.base);
1426 * Initialize driver data to point to the global DWC_otg
1430 g_otgdev = dwc_otg_device;
1431 pldata->privdata = dwc_otg_device;
1432 dwc_otg_device->pldata = pldata;
1434 dwc_set_device_platform_data(_dev, dwc_otg_device);
1436 dev_dbg(&_dev->dev, "dwc_otg_device=0x%p\n", dwc_otg_device);
1438 dwc_otg_device->core_if = dwc_otg_cil_init(dwc_otg_device->os_dep.base);
1439 if (!dwc_otg_device->core_if) {
1440 dev_err(&_dev->dev, "CIL initialization failed!\n");
1445 dwc_otg_device->core_if->otg_dev = dwc_otg_device;
1447 * Attempt to ensure this device is really a DWC_otg Controller.
1448 * Read and verify the SNPSID register contents. The value should be
1449 * 0x45F42XXX or 0x45F42XXX, which corresponds to either "OT2" or "OTG3",
1450 * as in "OTG version 2.XX" or "OTG version 3.XX".
1453 if (((dwc_otg_get_gsnpsid(dwc_otg_device->core_if) & 0xFFFFF000) != 0x4F542000) &&
1454 ((dwc_otg_get_gsnpsid(dwc_otg_device->core_if) & 0xFFFFF000) != 0x4F543000)) {
1455 dev_err(&_dev->dev, "Bad value for SNPSID: 0x%08x\n",
1456 dwc_otg_get_gsnpsid(dwc_otg_device->core_if));
1462 * Validate parameter values.
1464 if (set_parameters(dwc_otg_device->core_if ,dwc_otg_module_params)) {
1470 * Create Device Attributes in sysfs
1472 dwc_otg_attr_create(_dev);
1475 * Disable the global interrupt until all the interrupt
1476 * handlers are installed.
1478 dwc_otg_disable_global_interrupts(dwc_otg_device->core_if);
1481 * Install the interrupt handler for the common interrupts before
1482 * enabling common interrupts in core_init below.
1484 irq = platform_get_irq(_dev,0);
1485 DWC_DEBUGPL(DBG_CIL, "registering (common) handler for irq%d\n",
1487 retval = request_irq(irq, dwc_otg_common_irq,
1488 IRQF_SHARED , "dwc_otg",
1491 DWC_ERROR("request of irq%d failed\n", irq);
1495 dwc_otg_device->common_irq_installed = 1;
1499 * Initialize the DWC_otg core.
1500 * In order to reduce the time of initialization,
1501 * we do core soft reset after connection detected.
1503 dwc_otg_core_init_no_reset(dwc_otg_device->core_if);
1506 * 0 - USB_MODE_NORMAL
1507 * 1 - USB_MODE_FORCE_HOST
1508 * 2 - USB_MODE_FORCE_DEVICE
1510 of_property_read_u32(node, "rockchip,usb-mode", &val);
1511 dwc_otg_device->core_if->usb_mode = val;
1513 #ifndef DWC_HOST_ONLY
1515 * Initialize the PCD
1517 retval = pcd_init(_dev);
1519 DWC_ERROR("pcd_init failed\n");
1520 dwc_otg_device->pcd = NULL;
1524 #ifndef DWC_DEVICE_ONLY
1526 * Initialize the HCD
1528 retval = otg20_hcd_init(_dev);
1530 DWC_ERROR("hcd_init failed\n");
1531 dwc_otg_device->hcd = NULL;
1536 * Enable the global interrupt after all the interrupt
1537 * handlers are installed if there is no ADP support else
1538 * perform initial actions required for Internal ADP logic.
1540 if (!dwc_otg_get_param_adp_enable(dwc_otg_device->core_if)){
1541 if( pldata->phy_status == USB_PHY_ENABLED ){
1542 pldata->phy_suspend(pldata, USB_PHY_SUSPEND);
1544 pldata->clock_enable( pldata, 0);
1546 // dwc_otg_enable_global_interrupts(dwc_otg_device->core_if);
1549 dwc_otg_adp_start(dwc_otg_device->core_if,
1550 dwc_otg_is_host_mode(dwc_otg_device->core_if));
1555 otg20_driver_remove(_dev);
1558 if(pldata->clock_enable)
1559 pldata->clock_enable(pldata, 0);
1564 static struct platform_driver dwc_otg_driver = {
1566 .name = (char *)dwc_otg20_driver_name,
1567 .of_match_table = of_match_ptr(usb20_otg_of_match),
1569 .probe = otg20_driver_probe,
1570 .remove = otg20_driver_remove,
1571 .suspend = dwc_otg_driver_suspend,
1572 .resume = dwc_otg_driver_resume,
1573 .shutdown = dwc_otg_driver_shutdown,
1577 void rk_usb_power_up(void)
1579 struct dwc_otg_platform_data *pldata_otg;
1580 struct dwc_otg_platform_data *pldata_host;
1581 struct rkehci_platform_data *pldata_ehci;
1583 if(cpu_is_rk3288()){
1584 #ifdef CONFIG_RK_USB_UART
1585 /* enable USB bypass UART function */
1586 writel_relaxed(0x00c00000 | usb_to_uart_status, RK_GRF_VIRT + RK3288_GRF_UOC0_CON3);
1589 /* unset siddq,the analog blocks are powered up */
1590 #ifdef CONFIG_USB20_OTG
1591 if((pldata_otg = &usb20otg_pdata_rk3288)){
1592 if(pldata_otg->phy_status == USB_PHY_SUSPEND)
1593 writel_relaxed((0x01<<13)<<16, RK_GRF_VIRT + RK3288_GRF_UOC0_CON0);
1596 #ifdef CONFIG_USB20_HOST
1597 if((pldata_host = &usb20host_pdata_rk3288)){
1598 if(pldata_host->phy_status == USB_PHY_SUSPEND)
1599 writel_relaxed((0x01<<13)<<16, RK_GRF_VIRT + RK3288_GRF_UOC2_CON0);
1602 #ifdef CONFIG_USB_EHCI_RK
1603 if((pldata_ehci = &rkehci_pdata_rk3288)){
1604 if(pldata_ehci->phy_status == USB_PHY_SUSPEND)
1605 writel_relaxed((0x01<<13)<<16, RK_GRF_VIRT + RK3288_GRF_UOC1_CON0);
1612 void rk_usb_power_down(void)
1614 struct dwc_otg_platform_data *pldata_otg;
1615 struct dwc_otg_platform_data *pldata_host;
1616 struct rkehci_platform_data *pldata_ehci;
1618 if(cpu_is_rk3288()){
1619 #ifdef CONFIG_RK_USB_UART
1620 /* disable USB bypass UART function */
1621 usb_to_uart_status = readl_relaxed(RK_GRF_VIRT + RK3288_GRF_UOC0_CON3);
1622 writel_relaxed(0x00c00000, RK_GRF_VIRT + RK3288_GRF_UOC0_CON3);
1624 /* set siddq,the analog blocks are powered down
1626 * 1. Before asserting SIDDQ, ensure that VDATSRCENB0,
1627 * VDATDETENB0, DCDENB0, BYPASSSEL0, ADPPRBENB0,
1628 * and TESTBURNIN are set to 1'b0.
1629 * 2. Before asserting SIDDQ, ensure that phy enter suspend.*/
1630 #ifdef CONFIG_USB20_OTG
1631 if((pldata_otg = &usb20otg_pdata_rk3288)){
1632 if(pldata_otg->phy_status == USB_PHY_SUSPEND)
1633 writel_relaxed((0x01<<13)|((0x01<<13)<<16), RK_GRF_VIRT + RK3288_GRF_UOC0_CON0);
1636 #ifdef CONFIG_USB20_HOST
1637 if((pldata_host = &usb20host_pdata_rk3288)){
1638 if(pldata_host->phy_status == USB_PHY_SUSPEND)
1639 writel_relaxed((0x01<<13)|((0x01<<13)<<16), RK_GRF_VIRT + RK3288_GRF_UOC2_CON0);
1642 #ifdef CONFIG_USB_EHCI_RK
1643 if((pldata_ehci = &rkehci_pdata_rk3288)){
1644 if(pldata_ehci->phy_status == USB_PHY_SUSPEND)
1645 writel_relaxed((0x01<<13)|((0x01<<13)<<16), RK_GRF_VIRT + RK3288_GRF_UOC1_CON0);
1651 EXPORT_SYMBOL(rk_usb_power_up);
1652 EXPORT_SYMBOL(rk_usb_power_down);
1654 * This function is called when the dwc_otg_driver is installed with the
1655 * insmod command. It registers the dwc_otg_driver structure with the
1656 * appropriate bus driver. This will cause the dwc_otg_driver_probe function
1657 * to be called. In addition, the bus driver will automatically expose
1658 * attributes defined for the device and driver in the special sysfs file
1663 static int __init dwc_otg_driver_init(void)
1668 #ifdef CONFIG_USB20_OTG
1670 printk(KERN_INFO "%s: version %s\n", dwc_otg20_driver_name,
1671 DWC_DRIVER_VERSION);
1673 retval = platform_driver_register(&dwc_otg_driver);
1675 printk(KERN_ERR "%s retval=%d\n", __func__, retval);
1679 error = driver_create_file(&dwc_otg_driver.driver, &driver_attr_version);
1680 error = driver_create_file(&dwc_otg_driver.driver, &driver_attr_debuglevel);
1681 error = driver_create_file(&dwc_otg_driver.driver, &driver_attr_dwc_otg_conn_en);
1682 error = driver_create_file(&dwc_otg_driver.driver, &driver_attr_vbus_status);
1683 error = driver_create_file(&dwc_otg_driver.driver, &driver_attr_force_usb_mode);
1688 #ifdef CONFIG_USB20_HOST
1689 printk(KERN_INFO "%s: version %s\n", dwc_host20_driver_name,
1690 DWC_DRIVER_VERSION);
1692 retval = platform_driver_register(&dwc_host_driver);
1694 printk(KERN_ERR "%s retval=%d\n", __func__, retval);
1698 error = driver_create_file(&dwc_host_driver.driver, &driver_attr_version);
1699 error = driver_create_file(&dwc_host_driver.driver, &driver_attr_debuglevel);
1704 module_init(dwc_otg_driver_init);
1707 * This function is called when the driver is removed from the kernel
1708 * with the rmmod command. The driver unregisters itself with its bus
1712 static void __exit dwc_otg_driver_cleanup(void)
1714 printk(KERN_DEBUG "dwc_otg_driver_cleanup()\n");
1716 #ifdef CONFIG_USB20_HOST
1718 driver_remove_file(&dwc_host_driver.driver, &driver_attr_debuglevel);
1719 driver_remove_file(&dwc_host_driver.driver, &driver_attr_version);
1720 platform_driver_unregister(&dwc_host_driver);
1721 printk(KERN_INFO "%s module removed\n", dwc_host20_driver_name);
1724 #ifdef CONFIG_USB20_OTG
1726 driver_remove_file(&dwc_otg_driver.driver, &driver_attr_dwc_otg_conn_en);
1727 driver_remove_file(&dwc_otg_driver.driver, &driver_attr_debuglevel);
1728 driver_remove_file(&dwc_otg_driver.driver, &driver_attr_version);
1729 driver_remove_file(&dwc_otg_driver.driver, &driver_attr_vbus_status);
1730 driver_remove_file(&dwc_otg_driver.driver, &driver_attr_force_usb_mode);
1731 platform_driver_unregister(&dwc_otg_driver);
1732 printk(KERN_INFO "%s module removed\n", dwc_otg20_driver_name);
1736 module_exit(dwc_otg_driver_cleanup);
1738 MODULE_DESCRIPTION(DWC_DRIVER_DESC);
1739 MODULE_AUTHOR("Synopsys Inc.");
1740 MODULE_LICENSE("GPL");
1742 module_param_named(otg_cap, dwc_otg_module_params.otg_cap, int, 0444);
1743 MODULE_PARM_DESC(otg_cap, "OTG Capabilities 0=HNP&SRP 1=SRP Only 2=None");
1744 module_param_named(opt, dwc_otg_module_params.opt, int, 0444);
1745 MODULE_PARM_DESC(opt, "OPT Mode");
1746 module_param_named(dma_enable, dwc_otg_module_params.dma_enable, int, 0444);
1747 MODULE_PARM_DESC(dma_enable, "DMA Mode 0=Slave 1=DMA enabled");
1749 module_param_named(dma_desc_enable, dwc_otg_module_params.dma_desc_enable, int,
1751 MODULE_PARM_DESC(dma_desc_enable,
1752 "DMA Desc Mode 0=Address DMA 1=DMA Descriptor enabled");
1754 module_param_named(dma_burst_size, dwc_otg_module_params.dma_burst_size, int,
1756 MODULE_PARM_DESC(dma_burst_size,
1757 "DMA Burst Size 1, 4, 8, 16, 32, 64, 128, 256");
1758 module_param_named(speed, dwc_otg_module_params.speed, int, 0444);
1759 MODULE_PARM_DESC(speed, "Speed 0=High Speed 1=Full Speed");
1760 module_param_named(host_support_fs_ls_low_power,
1761 dwc_otg_module_params.host_support_fs_ls_low_power, int,
1763 MODULE_PARM_DESC(host_support_fs_ls_low_power,
1764 "Support Low Power w/FS or LS 0=Support 1=Don't Support");
1765 module_param_named(host_ls_low_power_phy_clk,
1766 dwc_otg_module_params.host_ls_low_power_phy_clk, int, 0444);
1767 MODULE_PARM_DESC(host_ls_low_power_phy_clk,
1768 "Low Speed Low Power Clock 0=48Mhz 1=6Mhz");
1769 module_param_named(enable_dynamic_fifo,
1770 dwc_otg_module_params.enable_dynamic_fifo, int, 0444);
1771 MODULE_PARM_DESC(enable_dynamic_fifo, "0=cC Setting 1=Allow Dynamic Sizing");
1772 module_param_named(data_fifo_size, dwc_otg_module_params.data_fifo_size, int,
1774 MODULE_PARM_DESC(data_fifo_size,
1775 "Total number of words in the data FIFO memory 32-32768");
1776 module_param_named(dev_rx_fifo_size, dwc_otg_module_params.dev_rx_fifo_size,
1778 MODULE_PARM_DESC(dev_rx_fifo_size, "Number of words in the Rx FIFO 16-32768");
1779 module_param_named(dev_nperio_tx_fifo_size,
1780 dwc_otg_module_params.dev_nperio_tx_fifo_size, int, 0444);
1781 MODULE_PARM_DESC(dev_nperio_tx_fifo_size,
1782 "Number of words in the non-periodic Tx FIFO 16-32768");
1783 module_param_named(dev_perio_tx_fifo_size_1,
1784 dwc_otg_module_params.dev_perio_tx_fifo_size[0], int, 0444);
1785 MODULE_PARM_DESC(dev_perio_tx_fifo_size_1,
1786 "Number of words in the periodic Tx FIFO 4-768");
1787 module_param_named(dev_perio_tx_fifo_size_2,
1788 dwc_otg_module_params.dev_perio_tx_fifo_size[1], int, 0444);
1789 MODULE_PARM_DESC(dev_perio_tx_fifo_size_2,
1790 "Number of words in the periodic Tx FIFO 4-768");
1791 module_param_named(dev_perio_tx_fifo_size_3,
1792 dwc_otg_module_params.dev_perio_tx_fifo_size[2], int, 0444);
1793 MODULE_PARM_DESC(dev_perio_tx_fifo_size_3,
1794 "Number of words in the periodic Tx FIFO 4-768");
1795 module_param_named(dev_perio_tx_fifo_size_4,
1796 dwc_otg_module_params.dev_perio_tx_fifo_size[3], int, 0444);
1797 MODULE_PARM_DESC(dev_perio_tx_fifo_size_4,
1798 "Number of words in the periodic Tx FIFO 4-768");
1799 module_param_named(dev_perio_tx_fifo_size_5,
1800 dwc_otg_module_params.dev_perio_tx_fifo_size[4], int, 0444);
1801 MODULE_PARM_DESC(dev_perio_tx_fifo_size_5,
1802 "Number of words in the periodic Tx FIFO 4-768");
1803 module_param_named(dev_perio_tx_fifo_size_6,
1804 dwc_otg_module_params.dev_perio_tx_fifo_size[5], int, 0444);
1805 MODULE_PARM_DESC(dev_perio_tx_fifo_size_6,
1806 "Number of words in the periodic Tx FIFO 4-768");
1807 module_param_named(dev_perio_tx_fifo_size_7,
1808 dwc_otg_module_params.dev_perio_tx_fifo_size[6], int, 0444);
1809 MODULE_PARM_DESC(dev_perio_tx_fifo_size_7,
1810 "Number of words in the periodic Tx FIFO 4-768");
1811 module_param_named(dev_perio_tx_fifo_size_8,
1812 dwc_otg_module_params.dev_perio_tx_fifo_size[7], int, 0444);
1813 MODULE_PARM_DESC(dev_perio_tx_fifo_size_8,
1814 "Number of words in the periodic Tx FIFO 4-768");
1815 module_param_named(dev_perio_tx_fifo_size_9,
1816 dwc_otg_module_params.dev_perio_tx_fifo_size[8], int, 0444);
1817 MODULE_PARM_DESC(dev_perio_tx_fifo_size_9,
1818 "Number of words in the periodic Tx FIFO 4-768");
1819 module_param_named(dev_perio_tx_fifo_size_10,
1820 dwc_otg_module_params.dev_perio_tx_fifo_size[9], int, 0444);
1821 MODULE_PARM_DESC(dev_perio_tx_fifo_size_10,
1822 "Number of words in the periodic Tx FIFO 4-768");
1823 module_param_named(dev_perio_tx_fifo_size_11,
1824 dwc_otg_module_params.dev_perio_tx_fifo_size[10], int, 0444);
1825 MODULE_PARM_DESC(dev_perio_tx_fifo_size_11,
1826 "Number of words in the periodic Tx FIFO 4-768");
1827 module_param_named(dev_perio_tx_fifo_size_12,
1828 dwc_otg_module_params.dev_perio_tx_fifo_size[11], int, 0444);
1829 MODULE_PARM_DESC(dev_perio_tx_fifo_size_12,
1830 "Number of words in the periodic Tx FIFO 4-768");
1831 module_param_named(dev_perio_tx_fifo_size_13,
1832 dwc_otg_module_params.dev_perio_tx_fifo_size[12], int, 0444);
1833 MODULE_PARM_DESC(dev_perio_tx_fifo_size_13,
1834 "Number of words in the periodic Tx FIFO 4-768");
1835 module_param_named(dev_perio_tx_fifo_size_14,
1836 dwc_otg_module_params.dev_perio_tx_fifo_size[13], int, 0444);
1837 MODULE_PARM_DESC(dev_perio_tx_fifo_size_14,
1838 "Number of words in the periodic Tx FIFO 4-768");
1839 module_param_named(dev_perio_tx_fifo_size_15,
1840 dwc_otg_module_params.dev_perio_tx_fifo_size[14], int, 0444);
1841 MODULE_PARM_DESC(dev_perio_tx_fifo_size_15,
1842 "Number of words in the periodic Tx FIFO 4-768");
1843 module_param_named(host_rx_fifo_size, dwc_otg_module_params.host_rx_fifo_size,
1845 MODULE_PARM_DESC(host_rx_fifo_size, "Number of words in the Rx FIFO 16-32768");
1846 module_param_named(host_nperio_tx_fifo_size,
1847 dwc_otg_module_params.host_nperio_tx_fifo_size, int, 0444);
1848 MODULE_PARM_DESC(host_nperio_tx_fifo_size,
1849 "Number of words in the non-periodic Tx FIFO 16-32768");
1850 module_param_named(host_perio_tx_fifo_size,
1851 dwc_otg_module_params.host_perio_tx_fifo_size, int, 0444);
1852 MODULE_PARM_DESC(host_perio_tx_fifo_size,
1853 "Number of words in the host periodic Tx FIFO 16-32768");
1854 module_param_named(max_transfer_size, dwc_otg_module_params.max_transfer_size,
1856 /** @todo Set the max to 512K, modify checks */
1857 MODULE_PARM_DESC(max_transfer_size,
1858 "The maximum transfer size supported in bytes 2047-65535");
1859 module_param_named(max_packet_count, dwc_otg_module_params.max_packet_count,
1861 MODULE_PARM_DESC(max_packet_count,
1862 "The maximum number of packets in a transfer 15-511");
1863 module_param_named(host_channels, dwc_otg_module_params.host_channels, int,
1865 MODULE_PARM_DESC(host_channels,
1866 "The number of host channel registers to use 1-16");
1867 module_param_named(dev_endpoints, dwc_otg_module_params.dev_endpoints, int,
1869 MODULE_PARM_DESC(dev_endpoints,
1870 "The number of endpoints in addition to EP0 available for device mode 1-15");
1871 module_param_named(phy_type, dwc_otg_module_params.phy_type, int, 0444);
1872 MODULE_PARM_DESC(phy_type, "0=Reserved 1=UTMI+ 2=ULPI");
1873 module_param_named(phy_utmi_width, dwc_otg_module_params.phy_utmi_width, int,
1875 MODULE_PARM_DESC(phy_utmi_width, "Specifies the UTMI+ Data Width 8 or 16 bits");
1876 module_param_named(phy_ulpi_ddr, dwc_otg_module_params.phy_ulpi_ddr, int, 0444);
1877 MODULE_PARM_DESC(phy_ulpi_ddr,
1878 "ULPI at double or single data rate 0=Single 1=Double");
1879 module_param_named(phy_ulpi_ext_vbus, dwc_otg_module_params.phy_ulpi_ext_vbus,
1881 MODULE_PARM_DESC(phy_ulpi_ext_vbus,
1882 "ULPI PHY using internal or external vbus 0=Internal");
1883 module_param_named(i2c_enable, dwc_otg_module_params.i2c_enable, int, 0444);
1884 MODULE_PARM_DESC(i2c_enable, "FS PHY Interface");
1885 module_param_named(ulpi_fs_ls, dwc_otg_module_params.ulpi_fs_ls, int, 0444);
1886 MODULE_PARM_DESC(ulpi_fs_ls, "ULPI PHY FS/LS mode only");
1887 module_param_named(ts_dline, dwc_otg_module_params.ts_dline, int, 0444);
1888 MODULE_PARM_DESC(ts_dline, "Term select Dline pulsing for all PHYs");
1889 module_param_named(debug, g_dbg_lvl, int, 0444);
1890 MODULE_PARM_DESC(debug, "");
1892 module_param_named(en_multiple_tx_fifo,
1893 dwc_otg_module_params.en_multiple_tx_fifo, int, 0444);
1894 MODULE_PARM_DESC(en_multiple_tx_fifo,
1895 "Dedicated Non Periodic Tx FIFOs 0=disabled 1=enabled");
1896 module_param_named(dev_tx_fifo_size_1,
1897 dwc_otg_module_params.dev_tx_fifo_size[0], int, 0444);
1898 MODULE_PARM_DESC(dev_tx_fifo_size_1, "Number of words in the Tx FIFO 4-768");
1899 module_param_named(dev_tx_fifo_size_2,
1900 dwc_otg_module_params.dev_tx_fifo_size[1], int, 0444);
1901 MODULE_PARM_DESC(dev_tx_fifo_size_2, "Number of words in the Tx FIFO 4-768");
1902 module_param_named(dev_tx_fifo_size_3,
1903 dwc_otg_module_params.dev_tx_fifo_size[2], int, 0444);
1904 MODULE_PARM_DESC(dev_tx_fifo_size_3, "Number of words in the Tx FIFO 4-768");
1905 module_param_named(dev_tx_fifo_size_4,
1906 dwc_otg_module_params.dev_tx_fifo_size[3], int, 0444);
1907 MODULE_PARM_DESC(dev_tx_fifo_size_4, "Number of words in the Tx FIFO 4-768");
1908 module_param_named(dev_tx_fifo_size_5,
1909 dwc_otg_module_params.dev_tx_fifo_size[4], int, 0444);
1910 MODULE_PARM_DESC(dev_tx_fifo_size_5, "Number of words in the Tx FIFO 4-768");
1911 module_param_named(dev_tx_fifo_size_6,
1912 dwc_otg_module_params.dev_tx_fifo_size[5], int, 0444);
1913 MODULE_PARM_DESC(dev_tx_fifo_size_6, "Number of words in the Tx FIFO 4-768");
1914 module_param_named(dev_tx_fifo_size_7,
1915 dwc_otg_module_params.dev_tx_fifo_size[6], int, 0444);
1916 MODULE_PARM_DESC(dev_tx_fifo_size_7, "Number of words in the Tx FIFO 4-768");
1917 module_param_named(dev_tx_fifo_size_8,
1918 dwc_otg_module_params.dev_tx_fifo_size[7], int, 0444);
1919 MODULE_PARM_DESC(dev_tx_fifo_size_8, "Number of words in the Tx FIFO 4-768");
1920 module_param_named(dev_tx_fifo_size_9,
1921 dwc_otg_module_params.dev_tx_fifo_size[8], int, 0444);
1922 MODULE_PARM_DESC(dev_tx_fifo_size_9, "Number of words in the Tx FIFO 4-768");
1923 module_param_named(dev_tx_fifo_size_10,
1924 dwc_otg_module_params.dev_tx_fifo_size[9], int, 0444);
1925 MODULE_PARM_DESC(dev_tx_fifo_size_10, "Number of words in the Tx FIFO 4-768");
1926 module_param_named(dev_tx_fifo_size_11,
1927 dwc_otg_module_params.dev_tx_fifo_size[10], int, 0444);
1928 MODULE_PARM_DESC(dev_tx_fifo_size_11, "Number of words in the Tx FIFO 4-768");
1929 module_param_named(dev_tx_fifo_size_12,
1930 dwc_otg_module_params.dev_tx_fifo_size[11], int, 0444);
1931 MODULE_PARM_DESC(dev_tx_fifo_size_12, "Number of words in the Tx FIFO 4-768");
1932 module_param_named(dev_tx_fifo_size_13,
1933 dwc_otg_module_params.dev_tx_fifo_size[12], int, 0444);
1934 MODULE_PARM_DESC(dev_tx_fifo_size_13, "Number of words in the Tx FIFO 4-768");
1935 module_param_named(dev_tx_fifo_size_14,
1936 dwc_otg_module_params.dev_tx_fifo_size[13], int, 0444);
1937 MODULE_PARM_DESC(dev_tx_fifo_size_14, "Number of words in the Tx FIFO 4-768");
1938 module_param_named(dev_tx_fifo_size_15,
1939 dwc_otg_module_params.dev_tx_fifo_size[14], int, 0444);
1940 MODULE_PARM_DESC(dev_tx_fifo_size_15, "Number of words in the Tx FIFO 4-768");
1942 module_param_named(thr_ctl, dwc_otg_module_params.thr_ctl, int, 0444);
1943 MODULE_PARM_DESC(thr_ctl,
1944 "Thresholding enable flag bit 0 - non ISO Tx thr., 1 - ISO Tx thr., 2 - Rx thr.- bit 0=disabled 1=enabled");
1945 module_param_named(tx_thr_length, dwc_otg_module_params.tx_thr_length, int,
1947 MODULE_PARM_DESC(tx_thr_length, "Tx Threshold length in 32 bit DWORDs");
1948 module_param_named(rx_thr_length, dwc_otg_module_params.rx_thr_length, int,
1950 MODULE_PARM_DESC(rx_thr_length, "Rx Threshold length in 32 bit DWORDs");
1952 module_param_named(pti_enable, dwc_otg_module_params.pti_enable, int, 0444);
1953 module_param_named(mpi_enable, dwc_otg_module_params.mpi_enable, int, 0444);
1954 module_param_named(lpm_enable, dwc_otg_module_params.lpm_enable, int, 0444);
1955 MODULE_PARM_DESC(lpm_enable, "LPM Enable 0=LPM Disabled 1=LPM Enabled");
1957 module_param_named(besl_enable, dwc_otg_module_params.besl_enable, int, 0444);
1958 MODULE_PARM_DESC(besl_enable, "BESL Enable 0=BESL Disabled 1=BESL Enabled");
1959 module_param_named(baseline_besl, dwc_otg_module_params.baseline_besl, int, 0444);
1960 MODULE_PARM_DESC(baseline_besl, "Set the baseline besl value");
1961 module_param_named(deep_besl, dwc_otg_module_params.deep_besl, int, 0444);
1962 MODULE_PARM_DESC(deep_besl, "Set the deep besl value");
1964 module_param_named(ic_usb_cap, dwc_otg_module_params.ic_usb_cap, int, 0444);
1965 MODULE_PARM_DESC(ic_usb_cap,
1966 "IC_USB Capability 0=IC_USB Disabled 1=IC_USB Enabled");
1967 module_param_named(ahb_thr_ratio, dwc_otg_module_params.ahb_thr_ratio, int,
1969 MODULE_PARM_DESC(ahb_thr_ratio, "AHB Threshold Ratio");
1970 module_param_named(power_down, dwc_otg_module_params.power_down, int, 0444);
1971 MODULE_PARM_DESC(power_down, "Power Down Mode");
1972 module_param_named(reload_ctl, dwc_otg_module_params.reload_ctl, int, 0444);
1973 MODULE_PARM_DESC(reload_ctl, "HFIR Reload Control");
1974 module_param_named(dev_out_nak, dwc_otg_module_params.dev_out_nak, int, 0444);
1975 MODULE_PARM_DESC(dev_out_nak, "Enable Device OUT NAK");
1976 module_param_named(cont_on_bna, dwc_otg_module_params.cont_on_bna, int, 0444);
1977 MODULE_PARM_DESC(cont_on_bna, "Enable Enable Continue on BNA");
1978 module_param_named(ahb_single, dwc_otg_module_params.ahb_single, int, 0444);
1979 MODULE_PARM_DESC(ahb_single, "Enable AHB Single Support");
1980 module_param_named(adp_enable, dwc_otg_module_params.adp_enable, int, 0444);
1981 MODULE_PARM_DESC(adp_enable, "ADP Enable 0=ADP Disabled 1=ADP Enabled");
1982 module_param_named(otg_ver, dwc_otg_module_params.otg_ver, int, 0444);
1983 MODULE_PARM_DESC(otg_ver, "OTG revision supported 0=OTG 1.3 1=OTG 2.0");
1985 /** @page "Module Parameters"
1987 * The following parameters may be specified when starting the module.
1988 * These parameters define how the DWC_otg controller should be
1989 * configured. Parameter values are passed to the CIL initialization
1990 * function dwc_otg_cil_init
1992 * Example: <code>modprobe dwc_otg speed=1 otg_cap=1</code>
1996 <tr><td>Parameter Name</td><td>Meaning</td></tr>
2000 <td>Specifies the OTG capabilities. The driver will automatically detect the
2001 value for this parameter if none is specified.
2002 - 0: HNP and SRP capable (default, if available)
2003 - 1: SRP Only capable
2004 - 2: No HNP/SRP capable
2009 <td>Specifies whether to use slave or DMA mode for accessing the data FIFOs.
2010 The driver will automatically detect the value for this parameter if none is
2013 - 1: DMA (default, if available)
2017 <td>dma_burst_size</td>
2018 <td>The DMA Burst size (applicable only for External DMA Mode).
2019 - Values: 1, 4, 8 16, 32, 64, 128, 256 (default 32)
2024 <td>Specifies the maximum speed of operation in host and device mode. The
2025 actual speed depends on the speed of the attached device and the value of
2027 - 0: High Speed (default)
2032 <td>host_support_fs_ls_low_power</td>
2033 <td>Specifies whether low power mode is supported when attached to a Full
2034 Speed or Low Speed device in host mode.
2035 - 0: Don't support low power mode (default)
2036 - 1: Support low power mode
2040 <td>host_ls_low_power_phy_clk</td>
2041 <td>Specifies the PHY clock rate in low power mode when connected to a Low
2042 Speed device in host mode. This parameter is applicable only if
2043 HOST_SUPPORT_FS_LS_LOW_POWER is enabled.
2044 - 0: 48 MHz (default)
2049 <td>enable_dynamic_fifo</td>
2050 <td> Specifies whether FIFOs may be resized by the driver software.
2051 - 0: Use cC FIFO size parameters
2052 - 1: Allow dynamic FIFO sizing (default)
2056 <td>data_fifo_size</td>
2057 <td>Total number of 4-byte words in the data FIFO memory. This memory
2058 includes the Rx FIFO, non-periodic Tx FIFO, and periodic Tx FIFOs.
2059 - Values: 32 to 32768 (default 8192)
2061 Note: The total FIFO memory depth in the FPGA configuration is 8192.
2065 <td>dev_rx_fifo_size</td>
2066 <td>Number of 4-byte words in the Rx FIFO in device mode when dynamic
2067 FIFO sizing is enabled.
2068 - Values: 16 to 32768 (default 1064)
2072 <td>dev_nperio_tx_fifo_size</td>
2073 <td>Number of 4-byte words in the non-periodic Tx FIFO in device mode when
2074 dynamic FIFO sizing is enabled.
2075 - Values: 16 to 32768 (default 1024)
2079 <td>dev_perio_tx_fifo_size_n (n = 1 to 15)</td>
2080 <td>Number of 4-byte words in each of the periodic Tx FIFOs in device mode
2081 when dynamic FIFO sizing is enabled.
2082 - Values: 4 to 768 (default 256)
2086 <td>host_rx_fifo_size</td>
2087 <td>Number of 4-byte words in the Rx FIFO in host mode when dynamic FIFO
2089 - Values: 16 to 32768 (default 1024)
2093 <td>host_nperio_tx_fifo_size</td>
2094 <td>Number of 4-byte words in the non-periodic Tx FIFO in host mode when
2095 dynamic FIFO sizing is enabled in the core.
2096 - Values: 16 to 32768 (default 1024)
2100 <td>host_perio_tx_fifo_size</td>
2101 <td>Number of 4-byte words in the host periodic Tx FIFO when dynamic FIFO
2103 - Values: 16 to 32768 (default 1024)
2107 <td>max_transfer_size</td>
2108 <td>The maximum transfer size supported in bytes.
2109 - Values: 2047 to 65,535 (default 65,535)
2113 <td>max_packet_count</td>
2114 <td>The maximum number of packets in a transfer.
2115 - Values: 15 to 511 (default 511)
2119 <td>host_channels</td>
2120 <td>The number of host channel registers to use.
2121 - Values: 1 to 16 (default 12)
2123 Note: The FPGA configuration supports a maximum of 12 host channels.
2127 <td>dev_endpoints</td>
2128 <td>The number of endpoints in addition to EP0 available for device mode
2130 - Values: 1 to 15 (default 6 IN and OUT)
2132 Note: The FPGA configuration supports a maximum of 6 IN and OUT endpoints in
2138 <td>Specifies the type of PHY interface to use. By default, the driver will
2139 automatically detect the phy_type.
2141 - 1: UTMI+ (default, if available)
2146 <td>phy_utmi_width</td>
2147 <td>Specifies the UTMI+ Data Width. This parameter is applicable for a
2148 phy_type of UTMI+. Also, this parameter is applicable only if the
2149 OTG_HSPHY_WIDTH cC parameter was set to "8 and 16 bits", meaning that the
2150 core has been configured to work at either data path width.
2151 - Values: 8 or 16 bits (default 16)
2155 <td>phy_ulpi_ddr</td>
2156 <td>Specifies whether the ULPI operates at double or single data rate. This
2157 parameter is only applicable if phy_type is ULPI.
2158 - 0: single data rate ULPI interface with 8 bit wide data bus (default)
2159 - 1: double data rate ULPI interface with 4 bit wide data bus
2164 <td>Specifies whether to use the I2C interface for full speed PHY. This
2165 parameter is only applicable if PHY_TYPE is FS.
2166 - 0: Disabled (default)
2172 <td>Specifies whether to use ULPI FS/LS mode only.
2173 - 0: Disabled (default)
2179 <td>Specifies whether term select D-Line pulsing for all PHYs is enabled.
2180 - 0: Disabled (default)
2185 <td>en_multiple_tx_fifo</td>
2186 <td>Specifies whether dedicatedto tx fifos are enabled for non periodic IN EPs.
2187 The driver will automatically detect the value for this parameter if none is
2190 - 1: Enabled (default, if available)
2194 <td>dev_tx_fifo_size_n (n = 1 to 15)</td>
2195 <td>Number of 4-byte words in each of the Tx FIFOs in device mode
2196 when dynamic FIFO sizing is enabled.
2197 - Values: 4 to 768 (default 256)
2201 <td>tx_thr_length</td>
2202 <td>Transmit Threshold length in 32 bit double words
2203 - Values: 8 to 128 (default 64)
2207 <td>rx_thr_length</td>
2208 <td>Receive Threshold length in 32 bit double words
2209 - Values: 8 to 128 (default 64)
2214 <td>Specifies whether to enable Thresholding for Device mode. Bits 0, 1, 2 of
2215 this parmater specifies if thresholding is enabled for non-Iso Tx, Iso Tx and
2216 Rx transfers accordingly.
2217 The driver will automatically detect the value for this parameter if none is
2219 - Values: 0 to 7 (default 0)
2220 Bit values indicate:
2221 - 0: Thresholding disabled
2222 - 1: Thresholding enabled
2226 <td>dma_desc_enable</td>
2227 <td>Specifies whether to enable Descriptor DMA mode.
2228 The driver will automatically detect the value for this parameter if none is
2230 - 0: Descriptor DMA disabled
2231 - 1: Descriptor DMA (default, if available)
2236 <td>Specifies whether to enable MPI enhancement mode.
2237 The driver will automatically detect the value for this parameter if none is
2239 - 0: MPI disabled (default)
2245 <td>Specifies whether to enable PTI enhancement support.
2246 The driver will automatically detect the value for this parameter if none is
2248 - 0: PTI disabled (default)
2254 <td>Specifies whether to enable LPM support.
2255 The driver will automatically detect the value for this parameter if none is
2258 - 1: LPM enable (default, if available)
2262 <td>besl_enable</td>
2263 <td>Specifies whether to enable LPM Errata support.
2264 The driver will automatically detect the value for this parameter if none is
2266 - 0: LPM Errata disabled (default)
2267 - 1: LPM Errata enable
2271 <td>baseline_besl</td>
2272 <td>Specifies the baseline besl value.
2273 - Values: 0 to 15 (default 0)
2278 <td>Specifies the deep besl value.
2279 - Values: 0 to 15 (default 15)
2284 <td>Specifies whether to enable IC_USB capability.
2285 The driver will automatically detect the value for this parameter if none is
2287 - 0: IC_USB disabled (default, if available)
2292 <td>ahb_thr_ratio</td>
2293 <td>Specifies AHB Threshold ratio.
2294 - Values: 0 to 3 (default 0)
2299 <td>Specifies Power Down(Hibernation) Mode.
2300 The driver will automatically detect the value for this parameter if none is
2302 - 0: Power Down disabled (default)
2303 - 2: Power Down enabled
2308 <td>Specifies whether dynamic reloading of the HFIR register is allowed during
2309 run time. The driver will automatically detect the value for this parameter if
2310 none is specified. In case the HFIR value is reloaded when HFIR.RldCtrl == 1'b0
2311 the core might misbehave.
2312 - 0: Reload Control disabled (default)
2313 - 1: Reload Control enabled
2317 <td>dev_out_nak</td>
2318 <td>Specifies whether Device OUT NAK enhancement enabled or no.
2319 The driver will automatically detect the value for this parameter if
2320 none is specified. This parameter is valid only when OTG_EN_DESC_DMA == 1
\92b1.
2321 - 0: The core does not set NAK after Bulk OUT transfer complete (default)
2322 - 1: The core sets NAK after Bulk OUT transfer complete
2326 <td>cont_on_bna</td>
2327 <td>Specifies whether Enable Continue on BNA enabled or no.
2328 After receiving BNA interrupt the core disables the endpoint,when the
2329 endpoint is re-enabled by the application the
2330 - 0: Core starts processing from the DOEPDMA descriptor (default)
2331 - 1: Core starts processing from the descriptor which received the BNA.
2332 This parameter is valid only when OTG_EN_DESC_DMA == 1
\92b1.
2337 <td>This bit when programmed supports SINGLE transfers for remainder data
2338 in a transfer for DMA mode of operation.
2339 - 0: The remainder data will be sent using INCR burst size (default)
2340 - 1: The remainder data will be sent using SINGLE burst size.
2345 <td>Specifies whether ADP feature is enabled.
2346 The driver will automatically detect the value for this parameter if none is
2348 - 0: ADP feature disabled (default)
2349 - 1: ADP feature enabled
2354 <td>Specifies whether OTG is performing as USB OTG Revision 2.0 or Revision 1.3
2356 - 0: OTG 2.0 support disabled (default)
2357 - 1: OTG 2.0 support enabled