1 /* ==========================================================================
2 * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_driver.c $
7 * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
8 * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
9 * otherwise expressly agreed to in writing between Synopsys and you.
11 * The Software IS NOT an item of Licensed Software or Licensed Product under
12 * any End User Software License Agreement or Agreement for Licensed Product
13 * with Synopsys or any supplement thereto. You are permitted to use and
14 * redistribute this Software in source and binary forms, with or without
15 * modification, provided that redistributions of source code must retain this
16 * notice. You may not view, use, disclose, copy or distribute this file or
17 * any information contained herein except pursuant to this license grant from
18 * Synopsys. If you do not agree with this notice, including the disclaimer
19 * below, then you are not authorized to use the Software.
21 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
25 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
26 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
27 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
28 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
32 * ========================================================================== */
35 * The dwc_otg_driver module provides the initialization and cleanup entry
36 * points for the DWC_otg driver. This module will be dynamically installed
37 * after Linux is booted using the insmod command. When the module is
38 * installed, the dwc_otg_driver_init function is called. When the module is
39 * removed (using rmmod), the dwc_otg_driver_cleanup function is called.
41 * This module also defines a data structure for the dwc_otg_driver, which is
42 * used in conjunction with the standard ARM lm_device structure. These
43 * structures allow the OTG driver to comply with the standard Linux driver
44 * model in which devices and drivers are registered with a bus driver. This
45 * has the benefit that Linux can expose attributes of the driver and device
46 * in its special sysfs file system. Users can then read or write files in
47 * this file system to perform diagnostics on the driver components or the
51 #include "dwc_otg_os_dep.h"
52 #include "common_port/dwc_os.h"
53 #include "dwc_otg_dbg.h"
54 #include "dwc_otg_driver.h"
55 #include "dwc_otg_attr.h"
56 #include "dwc_otg_core_if.h"
57 #include "dwc_otg_pcd_if.h"
58 #include "dwc_otg_hcd_if.h"
59 #include "dwc_otg_cil.h"
60 #include "dwc_otg_pcd.h"
62 #include "usbdev_rk.h"
64 #define DWC_DRIVER_VERSION "3.10a 21-DEC-2012"
65 #define DWC_DRIVER_DESC "HS OTG USB Controller driver"
67 static const char dwc_host20_driver_name[] = "usb20_host";
68 static const char dwc_otg20_driver_name[] = "usb20_otg";
70 dwc_otg_device_t* g_otgdev = NULL;
72 extern int pcd_init( struct platform_device *_dev );
73 extern int otg20_hcd_init( struct platform_device *_dev );
74 extern int host20_hcd_init( struct platform_device *_dev );
75 extern int pcd_remove( struct platform_device *_dev );
76 extern void hcd_remove( struct platform_device *_dev);
77 extern void dwc_otg_adp_start( dwc_otg_core_if_t * core_if, uint8_t is_host);
79 #ifdef CONFIG_USB20_OTG
80 static struct usb20otg_pdata_id usb20otg_pdata[] = {
82 .name = "rk3188-usb20otg",
83 .pdata = &usb20otg_pdata_rk3188,
86 .name = "rk3288-usb20otg",
87 .pdata = &usb20otg_pdata_rk3288,
93 #ifdef CONFIG_USB20_HOST
94 static struct usb20host_pdata_id usb20host_pdata[] = {
96 .name = "rk3188-usb20host",
97 .pdata = &usb20host_pdata_rk3188,
100 .name = "rk3288-usb20host",
101 .pdata = &usb20host_pdata_rk3288,
107 /*-------------------------------------------------------------------------*/
108 /* Encapsulate the module parameter settings */
110 struct dwc_otg_driver_module_params {
114 int32_t dma_desc_enable;
115 int32_t dma_burst_size;
117 int32_t host_support_fs_ls_low_power;
118 int32_t host_ls_low_power_phy_clk;
119 int32_t enable_dynamic_fifo;
120 int32_t data_fifo_size;
121 int32_t dev_rx_fifo_size;
122 int32_t dev_nperio_tx_fifo_size;
123 uint32_t dev_perio_tx_fifo_size[MAX_PERIO_FIFOS];
124 int32_t host_rx_fifo_size;
125 int32_t host_nperio_tx_fifo_size;
126 int32_t host_perio_tx_fifo_size;
127 int32_t max_transfer_size;
128 int32_t max_packet_count;
129 int32_t host_channels;
130 int32_t dev_endpoints;
132 int32_t phy_utmi_width;
133 int32_t phy_ulpi_ddr;
134 int32_t phy_ulpi_ext_vbus;
138 int32_t en_multiple_tx_fifo;
139 uint32_t dev_tx_fifo_size[MAX_TX_FIFOS];
141 uint32_t tx_thr_length;
142 uint32_t rx_thr_length;
147 int32_t baseline_besl;
150 int32_t ahb_thr_ratio;
160 static struct dwc_otg_driver_module_params dwc_otg_module_params = {
162 .otg_cap = DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE,
164 .dma_desc_enable = 0,
165 .dma_burst_size = -1,
167 .host_support_fs_ls_low_power = -1,
168 .host_ls_low_power_phy_clk = -1,
169 .enable_dynamic_fifo = 1,
170 .data_fifo_size = -1,
171 .dev_rx_fifo_size = 0x120,
172 .dev_nperio_tx_fifo_size = 0x10,
173 .dev_perio_tx_fifo_size = {
174 /* dev_perio_tx_fifo_size_1 */
192 .host_rx_fifo_size = -1,
193 .host_nperio_tx_fifo_size = -1,
194 .host_perio_tx_fifo_size = -1,
195 .max_transfer_size = -1,
196 .max_packet_count = -1,
200 .phy_utmi_width = -1,
202 .phy_ulpi_ext_vbus = -1,
206 .en_multiple_tx_fifo = -1,
207 .dev_tx_fifo_size = {
208 /* dev_tx_fifo_size */
246 #ifdef CONFIG_USB20_HOST
247 static struct dwc_otg_driver_module_params dwc_host_module_params = {
249 .otg_cap = DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE,
251 .dma_desc_enable = 0,
252 .dma_burst_size = -1,
254 .host_support_fs_ls_low_power = -1,
255 .host_ls_low_power_phy_clk = -1,
256 .enable_dynamic_fifo = -1,
257 .data_fifo_size = -1,
258 .dev_rx_fifo_size = -1,
259 .dev_nperio_tx_fifo_size = -1,
260 .dev_perio_tx_fifo_size = {
261 /* dev_perio_tx_fifo_size_1 */
279 .host_rx_fifo_size = -1,
280 .host_nperio_tx_fifo_size = -1,
281 .host_perio_tx_fifo_size = -1,
282 .max_transfer_size = -1,
283 .max_packet_count = -1,
287 .phy_utmi_width = -1,
289 .phy_ulpi_ext_vbus = -1,
293 .en_multiple_tx_fifo = -1,
294 .dev_tx_fifo_size = {
295 /* dev_tx_fifo_size */
335 * This function shows the Driver Version.
337 static ssize_t version_show(struct device_driver *dev, char *buf)
339 return snprintf(buf, sizeof(DWC_DRIVER_VERSION) + 2, "%s\n",
343 static DRIVER_ATTR(version, S_IRUGO, version_show, NULL);
346 * Global Debug Level Mask.
348 uint32_t g_dbg_lvl = DBG_OFF; /* OFF */
351 * This function shows the driver Debug Level.
353 static ssize_t dbg_level_show(struct device_driver *drv, char *buf)
355 return sprintf(buf, "0x%0x\n", g_dbg_lvl);
359 * This function stores the driver Debug Level.
361 static ssize_t dbg_level_store(struct device_driver *drv, const char *buf,
364 g_dbg_lvl = simple_strtoul(buf, NULL, 16);
368 static DRIVER_ATTR(debuglevel, S_IRUGO | S_IWUSR, dbg_level_show,
372 static ssize_t dwc_otg_conn_en_show(struct device_driver *_drv, char *_buf)
375 dwc_otg_device_t *otg_dev = g_otgdev;
376 dwc_otg_pcd_t *_pcd = otg_dev->pcd;
377 return sprintf (_buf, "%d\n", _pcd->conn_en);
381 static ssize_t dwc_otg_conn_en_store(struct device_driver *_drv, const char *_buf,
384 int enable = simple_strtoul(_buf, NULL, 10);
385 dwc_otg_device_t *otg_dev = g_otgdev;
386 dwc_otg_pcd_t *_pcd = otg_dev->pcd;
387 DWC_PRINTF("%s %d->%d\n",__func__, _pcd->conn_en, enable);
389 _pcd->conn_en = enable;
392 static DRIVER_ATTR(dwc_otg_conn_en, S_IRUGO|S_IWUSR, dwc_otg_conn_en_show, dwc_otg_conn_en_store);
394 static ssize_t vbus_status_show(struct device_driver *_drv, char *_buf)
396 dwc_otg_device_t *otg_dev = g_otgdev;
397 dwc_otg_pcd_t *_pcd = otg_dev->pcd;
398 return sprintf (_buf, "%d\n", _pcd->vbus_status);
400 static DRIVER_ATTR(vbus_status, S_IRUGO, vbus_status_show, NULL);
403 * This function is called during module intialization
404 * to pass module parameters to the DWC_OTG CORE.
406 static int set_parameters(dwc_otg_core_if_t * core_if, struct dwc_otg_driver_module_params module_params)
411 if (module_params.otg_cap != -1) {
413 dwc_otg_set_param_otg_cap(core_if,
414 module_params.otg_cap);
416 if (module_params.dma_enable != -1) {
418 dwc_otg_set_param_dma_enable(core_if,
422 if (module_params.dma_desc_enable != -1) {
424 dwc_otg_set_param_dma_desc_enable(core_if,
428 if (module_params.opt != -1) {
430 dwc_otg_set_param_opt(core_if, module_params.opt);
432 if (module_params.dma_burst_size != -1) {
434 dwc_otg_set_param_dma_burst_size(core_if,
438 if (module_params.host_support_fs_ls_low_power != -1) {
440 dwc_otg_set_param_host_support_fs_ls_low_power(core_if,
442 host_support_fs_ls_low_power);
444 if (module_params.enable_dynamic_fifo != -1) {
446 dwc_otg_set_param_enable_dynamic_fifo(core_if,
448 enable_dynamic_fifo);
450 if (module_params.data_fifo_size != -1) {
452 dwc_otg_set_param_data_fifo_size(core_if,
456 if (module_params.dev_rx_fifo_size != -1) {
458 dwc_otg_set_param_dev_rx_fifo_size(core_if,
462 if (module_params.dev_nperio_tx_fifo_size != -1) {
464 dwc_otg_set_param_dev_nperio_tx_fifo_size(core_if,
466 dev_nperio_tx_fifo_size);
468 if (module_params.host_rx_fifo_size != -1) {
470 dwc_otg_set_param_host_rx_fifo_size(core_if,
471 module_params.host_rx_fifo_size);
473 if (module_params.host_nperio_tx_fifo_size != -1) {
475 dwc_otg_set_param_host_nperio_tx_fifo_size(core_if,
477 host_nperio_tx_fifo_size);
479 if (module_params.host_perio_tx_fifo_size != -1) {
481 dwc_otg_set_param_host_perio_tx_fifo_size(core_if,
483 host_perio_tx_fifo_size);
485 if (module_params.max_transfer_size != -1) {
487 dwc_otg_set_param_max_transfer_size(core_if,
491 if (module_params.max_packet_count != -1) {
493 dwc_otg_set_param_max_packet_count(core_if,
497 if (module_params.host_channels != -1) {
499 dwc_otg_set_param_host_channels(core_if,
503 if (module_params.dev_endpoints != -1) {
505 dwc_otg_set_param_dev_endpoints(core_if,
509 if (module_params.phy_type != -1) {
511 dwc_otg_set_param_phy_type(core_if,
512 module_params.phy_type);
514 if (module_params.speed != -1) {
516 dwc_otg_set_param_speed(core_if,
517 module_params.speed);
519 if (module_params.host_ls_low_power_phy_clk != -1) {
521 dwc_otg_set_param_host_ls_low_power_phy_clk(core_if,
523 host_ls_low_power_phy_clk);
525 if (module_params.phy_ulpi_ddr != -1) {
527 dwc_otg_set_param_phy_ulpi_ddr(core_if,
531 if (module_params.phy_ulpi_ext_vbus != -1) {
533 dwc_otg_set_param_phy_ulpi_ext_vbus(core_if,
537 if (module_params.phy_utmi_width != -1) {
539 dwc_otg_set_param_phy_utmi_width(core_if,
543 if (module_params.ulpi_fs_ls != -1) {
545 dwc_otg_set_param_ulpi_fs_ls(core_if,
546 module_params.ulpi_fs_ls);
548 if (module_params.ts_dline != -1) {
550 dwc_otg_set_param_ts_dline(core_if,
551 module_params.ts_dline);
553 if (module_params.i2c_enable != -1) {
555 dwc_otg_set_param_i2c_enable(core_if,
559 if (module_params.en_multiple_tx_fifo != -1) {
561 dwc_otg_set_param_en_multiple_tx_fifo(core_if,
563 en_multiple_tx_fifo);
565 for (i = 0; i < 15; i++) {
566 if (module_params.dev_perio_tx_fifo_size[i] != -1) {
568 dwc_otg_set_param_dev_perio_tx_fifo_size(core_if,
570 dev_perio_tx_fifo_size
575 for (i = 0; i < 15; i++) {
576 if (module_params.dev_tx_fifo_size[i] != -1) {
577 retval += dwc_otg_set_param_dev_tx_fifo_size(core_if,
583 if (module_params.thr_ctl != -1) {
585 dwc_otg_set_param_thr_ctl(core_if,
586 module_params.thr_ctl);
588 if (module_params.mpi_enable != -1) {
590 dwc_otg_set_param_mpi_enable(core_if,
594 if (module_params.pti_enable != -1) {
596 dwc_otg_set_param_pti_enable(core_if,
600 if (module_params.lpm_enable != -1) {
602 dwc_otg_set_param_lpm_enable(core_if,
606 if (module_params.besl_enable != -1) {
608 dwc_otg_set_param_besl_enable(core_if,
612 if (module_params.baseline_besl != -1) {
614 dwc_otg_set_param_baseline_besl(core_if,
618 if (module_params.deep_besl != -1) {
620 dwc_otg_set_param_deep_besl(core_if,
624 if (module_params.ic_usb_cap != -1) {
626 dwc_otg_set_param_ic_usb_cap(core_if,
630 if (module_params.tx_thr_length != -1) {
632 dwc_otg_set_param_tx_thr_length(core_if,
633 module_params.tx_thr_length);
635 if (module_params.rx_thr_length != -1) {
637 dwc_otg_set_param_rx_thr_length(core_if,
641 if (module_params.ahb_thr_ratio != -1) {
643 dwc_otg_set_param_ahb_thr_ratio(core_if,
644 module_params.ahb_thr_ratio);
646 if (module_params.power_down != -1) {
648 dwc_otg_set_param_power_down(core_if,
649 module_params.power_down);
651 if (module_params.reload_ctl != -1) {
653 dwc_otg_set_param_reload_ctl(core_if,
654 module_params.reload_ctl);
657 if (module_params.dev_out_nak != -1) {
659 dwc_otg_set_param_dev_out_nak(core_if,
660 module_params.dev_out_nak);
663 if (module_params.cont_on_bna != -1) {
665 dwc_otg_set_param_cont_on_bna(core_if,
666 module_params.cont_on_bna);
669 if (module_params.ahb_single != -1) {
671 dwc_otg_set_param_ahb_single(core_if,
672 module_params.ahb_single);
675 if (module_params.otg_ver != -1) {
677 dwc_otg_set_param_otg_ver(core_if,
678 module_params.otg_ver);
680 if (module_params.adp_enable != -1) {
682 dwc_otg_set_param_adp_enable(core_if,
690 * This function is the top level interrupt handler for the Common
691 * (Device and host modes) interrupts.
693 static irqreturn_t dwc_otg_common_irq(int irq, void *dev)
695 int32_t retval = IRQ_NONE;
697 retval = dwc_otg_handle_common_intr(dev);
699 //S3C2410X_CLEAR_EINTPEND();
701 return IRQ_RETVAL(retval);
704 #ifdef CONFIG_USB20_HOST
706 * This function is called when a lm_device is unregistered with the
707 * dwc_otg_driver. This happens, for example, when the rmmod command is
708 * executed. The device may or may not be electrically present. If it is
709 * present, the driver stops device processing. Any resources used on behalf
710 * of this device are freed.
714 static int host20_driver_remove( struct platform_device *_dev )
717 dwc_otg_device_t *otg_dev = dwc_get_device_platform_data(_dev);
718 DWC_DEBUGPL(DBG_ANY, "%s(%p)\n", __func__, _dev);
721 /* Memory allocation for the dwc_otg_device failed. */
722 DWC_DEBUGPL(DBG_ANY, "%s: otg_dev NULL!\n", __func__);
726 #ifndef DWC_DEVICE_ONLY
730 DWC_DEBUGPL(DBG_ANY, "%s: otg_dev->hcd NULL!\n", __func__);
735 #ifndef DWC_HOST_ONLY
739 DWC_DEBUGPL(DBG_ANY, "%s: otg_dev->pcd NULL!\n", __func__);
747 if (otg_dev->common_irq_installed) {
748 //free_irq(_dev->irq, otg_dev);
749 free_irq(platform_get_irq(_dev,0), otg_dev );
751 DWC_DEBUGPL(DBG_ANY, "%s: There is no installed irq!\n", __func__);
755 if (otg_dev->core_if) {
756 dwc_otg_cil_remove(otg_dev->core_if);
758 DWC_DEBUGPL(DBG_ANY, "%s: otg_dev->core_if NULL!\n", __func__);
763 * Remove the device attributes
765 dwc_otg_attr_remove(_dev);
770 if (otg_dev->os_dep.base) {
771 iounmap(otg_dev->os_dep.base);
776 * Clear the drvdata pointer.
779 dwc_set_device_platform_data(_dev, 0);
784 static const struct of_device_id usb20_host_of_match[] = {
786 .compatible = "rockchip,rk3188_usb20_host",
787 .data = &usb20host_pdata[RK3188_USB_CTLR],
790 .compatible = "rockchip,rk3288_usb20_host",
791 .data = &usb20host_pdata[RK3288_USB_CTLR],
795 MODULE_DEVICE_TABLE(of, usb20_host_of_match);
798 * This function is called when an lm_device is bound to a
799 * dwc_otg_driver. It creates the driver components required to
800 * control the device (CIL, HCD, and PCD) and it initializes the
801 * device. The driver components are stored in a dwc_otg_device
802 * structure. A reference to the dwc_otg_device is saved in the
803 * lm_device. This allows the driver to access the dwc_otg_device
804 * structure on subsequent calls to driver methods for this device.
806 * @param _dev Bus device
808 static int host20_driver_probe(struct platform_device *_dev)
812 struct resource *res_base;
813 dwc_otg_device_t *dwc_otg_device;
814 struct device *dev = &_dev->dev;
815 struct device_node *node = _dev->dev.of_node;
816 struct dwc_otg_platform_data *pldata;
817 struct usb20host_pdata_id *p;
818 const struct of_device_id *match =
819 of_match_device(of_match_ptr( usb20_host_of_match ), &_dev->dev);
822 p = (struct usb20host_pdata_id *)match->data;
824 dev_err(dev, "usb20host match failed\n");
828 dev->platform_data = p->pdata;
829 pldata = dev->platform_data;
833 dev_err(dev, "device node not found\n");
840 if(pldata->clock_init){
841 pldata->clock_init(pldata);
842 pldata->clock_enable(pldata, 1);
845 if(pldata->phy_suspend)
846 pldata->phy_suspend(pldata, USB_PHY_ENABLED);
848 if(pldata->soft_reset)
849 pldata->soft_reset();
851 res_base=platform_get_resource(_dev, IORESOURCE_MEM, 0);
853 dwc_otg_device = DWC_ALLOC(sizeof(dwc_otg_device_t));
855 if (!dwc_otg_device) {
856 dev_err(&_dev->dev, "kmalloc of dwc_otg_device failed\n");
861 memset(dwc_otg_device, 0, sizeof(*dwc_otg_device));
862 dwc_otg_device->os_dep.reg_offset = 0xFFFFFFFF;
865 * Map the DWC_otg Core memory into virtual address space.
868 dwc_otg_device->os_dep.base = devm_ioremap_resource(dev, res_base);
870 if (!dwc_otg_device->os_dep.base) {
871 dev_err(&_dev->dev, "ioremap() failed\n");
872 DWC_FREE(dwc_otg_device);
876 dev_dbg(&_dev->dev, "base=0x%08x\n",
877 (unsigned)dwc_otg_device->os_dep.base);
880 * Initialize driver data to point to the global DWC_otg
884 dwc_set_device_platform_data(_dev, dwc_otg_device);
885 pldata->privdata = dwc_otg_device;
886 dwc_otg_device->pldata = (void *)pldata;
888 dev_dbg(&_dev->dev, "dwc_otg_device=0x%p\n", dwc_otg_device);
890 dwc_otg_device->core_if = dwc_otg_cil_init(dwc_otg_device->os_dep.base);
893 if (!dwc_otg_device->core_if) {
894 dev_err(&_dev->dev, "CIL initialization failed!\n");
899 dwc_otg_device->core_if->otg_dev= dwc_otg_device;
902 * Attempt to ensure this device is really a DWC_otg Controller.
903 * Read and verify the SNPSID register contents. The value should be
904 * 0x45F42XXX or 0x45F42XXX, which corresponds to either "OT2" or "OTG3",
905 * as in "OTG version 2.XX" or "OTG version 3.XX".
908 if (((dwc_otg_get_gsnpsid(dwc_otg_device->core_if) & 0xFFFFF000) != 0x4F542000) &&
909 ((dwc_otg_get_gsnpsid(dwc_otg_device->core_if) & 0xFFFFF000) != 0x4F543000)) {
910 dev_err(&_dev->dev, "Bad value for SNPSID: 0x%08x\n",
911 dwc_otg_get_gsnpsid(dwc_otg_device->core_if));
917 * Validate parameter values.
919 if (set_parameters(dwc_otg_device->core_if ,dwc_host_module_params )) {
925 * Create Device Attributes in sysfs
927 dwc_otg_attr_create(_dev);
930 * Disable the global interrupt until all the interrupt
931 * handlers are installed.
933 dwc_otg_disable_global_interrupts(dwc_otg_device->core_if);
936 * Install the interrupt handler for the common interrupts before
937 * enabling common interrupts in core_init below.
939 irq = platform_get_irq(_dev,0);
940 DWC_DEBUGPL(DBG_CIL, "registering (common) handler for irq%d\n",
942 retval = request_irq(irq, dwc_otg_common_irq,
943 IRQF_SHARED , "dwc_otg",
946 DWC_ERROR("request of irq%d failed\n", irq);
950 dwc_otg_device->common_irq_installed = 1;
954 * Initialize the DWC_otg core.
956 dwc_otg_core_init(dwc_otg_device->core_if);
961 retval = host20_hcd_init(_dev);
963 DWC_ERROR("hcd_init failed\n");
964 dwc_otg_device->hcd = NULL;
969 * Enable the global interrupt after all the interrupt
970 * handlers are installed if there is no ADP support else
971 * perform initial actions required for Internal ADP logic.
973 if (!dwc_otg_get_param_adp_enable(dwc_otg_device->core_if))
974 dwc_otg_enable_global_interrupts(dwc_otg_device->core_if);
976 dwc_otg_adp_start(dwc_otg_device->core_if,
977 dwc_otg_is_host_mode(dwc_otg_device->core_if));
982 host20_driver_remove(_dev);
984 if(pldata->clock_enable)
985 pldata->clock_enable(pldata, 0);
991 static int dwc_otg_driver_suspend(struct platform_device *_dev , pm_message_t state )
996 static int dwc_otg_driver_resume(struct platform_device *_dev )
1001 static void dwc_otg_driver_shutdown(struct platform_device *_dev )
1003 struct device *dev = &_dev->dev;
1004 dwc_otg_device_t *otg_dev = dev->platform_data;
1005 dwc_otg_core_if_t *core_if = otg_dev->core_if;
1006 dctl_data_t dctl = {.d32=0};
1008 DWC_PRINTF("%s: disconnect USB %s mode\n" , __func__ ,
1009 dwc_otg_is_host_mode(core_if) ? "host" : "device");
1010 if(dwc_otg_is_host_mode(core_if))
1012 if (core_if->hcd_cb && core_if->hcd_cb->stop)
1014 core_if->hcd_cb->stop( core_if->hcd_cb_p);
1019 /* soft disconnect */
1020 dctl.d32 = DWC_READ_REG32( &core_if->dev_if->dev_global_regs->dctl );
1021 dctl.b.sftdiscon = 1;
1022 DWC_WRITE_REG32( &core_if->dev_if->dev_global_regs->dctl, dctl.d32 );
1024 /* Clear any pending interrupts */
1025 DWC_WRITE_REG32( &core_if->core_global_regs->gintsts, 0xFFFFFFFF);
1031 * This structure defines the methods to be called by a bus driver
1032 * during the lifecycle of a device on that bus. Both drivers and
1033 * devices are registered with a bus driver. The bus driver matches
1034 * devices to drivers based on information in the device and driver
1037 * The probe function is called when the bus driver matches a device
1038 * to this driver. The remove function is called when a device is
1039 * unregistered with the bus driver.
1041 #ifdef CONFIG_USB20_HOST
1042 static struct platform_driver dwc_host_driver = {
1044 .name = (char *)dwc_host20_driver_name,
1045 .of_match_table = of_match_ptr(usb20_host_of_match),
1047 .probe = host20_driver_probe,
1048 .remove = host20_driver_remove,
1049 .suspend = dwc_otg_driver_suspend,
1050 .resume = dwc_otg_driver_resume,
1054 #ifdef CONFIG_USB20_OTG
1056 * This function is called when a lm_device is unregistered with the
1057 * dwc_otg_driver. This happens, for example, when the rmmod command is
1058 * executed. The device may or may not be electrically present. If it is
1059 * present, the driver stops device processing. Any resources used on behalf
1060 * of this device are freed.
1064 static int otg20_driver_remove( struct platform_device *_dev )
1067 dwc_otg_device_t *otg_dev = dwc_get_device_platform_data(_dev);
1068 DWC_DEBUGPL(DBG_ANY, "%s(%p)\n", __func__, _dev);
1071 /* Memory allocation for the dwc_otg_device failed. */
1072 DWC_DEBUGPL(DBG_ANY, "%s: otg_dev NULL!\n", __func__);
1075 #ifndef DWC_DEVICE_ONLY
1079 DWC_DEBUGPL(DBG_ANY, "%s: otg_dev->hcd NULL!\n", __func__);
1084 #ifndef DWC_HOST_ONLY
1088 DWC_DEBUGPL(DBG_ANY, "%s: otg_dev->pcd NULL!\n", __func__);
1095 if (otg_dev->common_irq_installed) {
1096 //free_irq(_dev->irq, otg_dev);
1097 free_irq(platform_get_irq(_dev,0), otg_dev );
1099 DWC_DEBUGPL(DBG_ANY, "%s: There is no installed irq!\n", __func__);
1103 if (otg_dev->core_if) {
1104 dwc_otg_cil_remove(otg_dev->core_if);
1106 DWC_DEBUGPL(DBG_ANY, "%s: otg_dev->core_if NULL!\n", __func__);
1111 * Remove the device attributes
1113 dwc_otg_attr_remove(_dev);
1116 * Return the memory.
1118 if (otg_dev->os_dep.base) {
1119 iounmap(otg_dev->os_dep.base);
1124 * Clear the drvdata pointer.
1127 dwc_set_device_platform_data(_dev, 0);
1132 static const struct of_device_id usb20_otg_of_match[] = {
1134 .compatible = "rockchip,rk3188_usb20_otg",
1135 .data = &usb20otg_pdata[RK3188_USB_CTLR],
1138 .compatible = "rockchip,rk3288_usb20_otg",
1139 .data = &usb20otg_pdata[RK3288_USB_CTLR],
1144 MODULE_DEVICE_TABLE(of, usb20_otg_of_match);
1147 * This function is called when an lm_device is bound to a
1148 * dwc_otg_driver. It creates the driver components required to
1149 * control the device (CIL, HCD, and PCD) and it initializes the
1150 * device. The driver components are stored in a dwc_otg_device
1151 * structure. A reference to the dwc_otg_device is saved in the
1152 * lm_device. This allows the driver to access the dwc_otg_device
1153 * structure on subsequent calls to driver methods for this device.
1155 * @param _dev Bus device
1157 static int otg20_driver_probe(struct platform_device *_dev)
1161 struct resource *res_base;
1162 dwc_otg_device_t *dwc_otg_device;
1163 struct device *dev = &_dev->dev;
1164 struct device_node *node = _dev->dev.of_node;
1165 struct dwc_otg_platform_data *pldata;
1166 struct usb20otg_pdata_id *p;
1167 const struct of_device_id *match =
1168 of_match_device(of_match_ptr( usb20_otg_of_match ), &_dev->dev);
1171 p = (struct usb20otg_pdata_id *)match->data;
1173 dev_err(dev, "usb20otg match failed\n");
1177 dev->platform_data = p->pdata;
1178 // dev->platform_data = &usb20otg_pdata;
1179 pldata = dev->platform_data;
1183 dev_err(dev, "device node not found\n");
1186 /*todo : move to usbdev_rk-XX.c*/
1190 if(pldata->clock_init){
1191 pldata->clock_init(pldata);
1192 pldata->clock_enable(pldata, 1);
1195 if(pldata->phy_suspend)
1196 pldata->phy_suspend(pldata, USB_PHY_ENABLED);
1197 if(pldata->dwc_otg_uart_mode)
1198 pldata->dwc_otg_uart_mode(pldata, PHY_USB_MODE);
1199 if(pldata->soft_reset)
1200 pldata->soft_reset();
1203 res_base=platform_get_resource(_dev, IORESOURCE_MEM, 0);
1205 dwc_otg_device = DWC_ALLOC(sizeof(dwc_otg_device_t));
1207 if (!dwc_otg_device) {
1208 dev_err(&_dev->dev, "kmalloc of dwc_otg_device failed\n");
1213 memset(dwc_otg_device, 0, sizeof(*dwc_otg_device));
1214 dwc_otg_device->os_dep.reg_offset = 0xFFFFFFFF;
1217 * Map the DWC_otg Core memory into virtual address space.
1220 dwc_otg_device->os_dep.base = devm_ioremap_resource(dev, res_base);
1222 if (!dwc_otg_device->os_dep.base) {
1223 dev_err(&_dev->dev, "ioremap() failed\n");
1224 DWC_FREE(dwc_otg_device);
1228 dev_dbg(&_dev->dev, "base=0x%08x\n",
1229 (unsigned)dwc_otg_device->os_dep.base);
1232 * Initialize driver data to point to the global DWC_otg
1236 g_otgdev = dwc_otg_device;
1237 pldata->privdata = dwc_otg_device;
1238 dwc_otg_device->pldata = pldata;
1240 dwc_set_device_platform_data(_dev, dwc_otg_device);
1242 dev_dbg(&_dev->dev, "dwc_otg_device=0x%p\n", dwc_otg_device);
1244 dwc_otg_device->core_if = dwc_otg_cil_init(dwc_otg_device->os_dep.base);
1245 if (!dwc_otg_device->core_if) {
1246 dev_err(&_dev->dev, "CIL initialization failed!\n");
1251 dwc_otg_device->core_if->otg_dev = dwc_otg_device;
1253 * Attempt to ensure this device is really a DWC_otg Controller.
1254 * Read and verify the SNPSID register contents. The value should be
1255 * 0x45F42XXX or 0x45F42XXX, which corresponds to either "OT2" or "OTG3",
1256 * as in "OTG version 2.XX" or "OTG version 3.XX".
1259 if (((dwc_otg_get_gsnpsid(dwc_otg_device->core_if) & 0xFFFFF000) != 0x4F542000) &&
1260 ((dwc_otg_get_gsnpsid(dwc_otg_device->core_if) & 0xFFFFF000) != 0x4F543000)) {
1261 dev_err(&_dev->dev, "Bad value for SNPSID: 0x%08x\n",
1262 dwc_otg_get_gsnpsid(dwc_otg_device->core_if));
1268 * Validate parameter values.
1270 if (set_parameters(dwc_otg_device->core_if ,dwc_otg_module_params)) {
1276 * Create Device Attributes in sysfs
1278 dwc_otg_attr_create(_dev);
1281 * Disable the global interrupt until all the interrupt
1282 * handlers are installed.
1284 dwc_otg_disable_global_interrupts(dwc_otg_device->core_if);
1287 * Install the interrupt handler for the common interrupts before
1288 * enabling common interrupts in core_init below.
1290 irq = platform_get_irq(_dev,0);
1291 DWC_DEBUGPL(DBG_CIL, "registering (common) handler for irq%d\n",
1293 retval = request_irq(irq, dwc_otg_common_irq,
1294 IRQF_SHARED , "dwc_otg",
1297 DWC_ERROR("request of irq%d failed\n", irq);
1301 dwc_otg_device->common_irq_installed = 1;
1305 * Initialize the DWC_otg core.
1307 dwc_otg_core_init(dwc_otg_device->core_if);
1309 #ifndef DWC_HOST_ONLY
1311 * Initialize the PCD
1313 retval = pcd_init(_dev);
1315 DWC_ERROR("pcd_init failed\n");
1316 dwc_otg_device->pcd = NULL;
1320 #ifndef DWC_DEVICE_ONLY
1322 * Initialize the HCD
1324 retval = otg20_hcd_init(_dev);
1326 DWC_ERROR("hcd_init failed\n");
1327 dwc_otg_device->hcd = NULL;
1332 * Enable the global interrupt after all the interrupt
1333 * handlers are installed if there is no ADP support else
1334 * perform initial actions required for Internal ADP logic.
1336 if (!dwc_otg_get_param_adp_enable(dwc_otg_device->core_if))
1337 dwc_otg_enable_global_interrupts(dwc_otg_device->core_if);
1339 dwc_otg_adp_start(dwc_otg_device->core_if,
1340 dwc_otg_is_host_mode(dwc_otg_device->core_if));
1345 otg20_driver_remove(_dev);
1348 if(pldata->clock_enable)
1349 pldata->clock_enable(pldata, 0);
1354 static struct platform_driver dwc_otg_driver = {
1356 .name = (char *)dwc_otg20_driver_name,
1357 .of_match_table = of_match_ptr(usb20_otg_of_match),
1359 .probe = otg20_driver_probe,
1360 .remove = otg20_driver_remove,
1361 .suspend = dwc_otg_driver_suspend,
1362 .resume = dwc_otg_driver_resume,
1363 .shutdown = dwc_otg_driver_shutdown,
1368 * This function is called when the dwc_otg_driver is installed with the
1369 * insmod command. It registers the dwc_otg_driver structure with the
1370 * appropriate bus driver. This will cause the dwc_otg_driver_probe function
1371 * to be called. In addition, the bus driver will automatically expose
1372 * attributes defined for the device and driver in the special sysfs file
1377 static int __init dwc_otg_driver_init(void)
1382 #ifdef CONFIG_USB20_HOST
1383 printk(KERN_INFO "%s: version %s\n", dwc_host20_driver_name,
1384 DWC_DRIVER_VERSION);
1386 retval = platform_driver_register(&dwc_host_driver);
1388 printk(KERN_ERR "%s retval=%d\n", __func__, retval);
1392 error = driver_create_file(&dwc_host_driver.driver, &driver_attr_version);
1393 error = driver_create_file(&dwc_host_driver.driver, &driver_attr_debuglevel);
1396 #ifdef CONFIG_USB20_OTG
1398 printk(KERN_INFO "%s: version %s\n", dwc_otg20_driver_name,
1399 DWC_DRIVER_VERSION);
1401 retval = platform_driver_register(&dwc_otg_driver);
1403 printk(KERN_ERR "%s retval=%d\n", __func__, retval);
1407 error = driver_create_file(&dwc_otg_driver.driver, &driver_attr_version);
1408 error = driver_create_file(&dwc_otg_driver.driver, &driver_attr_debuglevel);
1409 error = driver_create_file(&dwc_otg_driver.driver, &driver_attr_dwc_otg_conn_en);
1410 error = driver_create_file(&dwc_otg_driver.driver, &driver_attr_vbus_status);
1415 module_init(dwc_otg_driver_init);
1418 * This function is called when the driver is removed from the kernel
1419 * with the rmmod command. The driver unregisters itself with its bus
1423 static void __exit dwc_otg_driver_cleanup(void)
1425 printk(KERN_DEBUG "dwc_otg_driver_cleanup()\n");
1427 #ifdef CONFIG_USB20_HOST
1429 driver_remove_file(&dwc_host_driver.driver, &driver_attr_debuglevel);
1430 driver_remove_file(&dwc_host_driver.driver, &driver_attr_version);
1431 platform_driver_unregister(&dwc_host_driver);
1432 printk(KERN_INFO "%s module removed\n", dwc_host20_driver_name);
1435 #ifdef CONFIG_USB20_OTG
1437 driver_remove_file(&dwc_otg_driver.driver, &driver_attr_dwc_otg_conn_en);
1438 driver_remove_file(&dwc_otg_driver.driver, &driver_attr_debuglevel);
1439 driver_remove_file(&dwc_otg_driver.driver, &driver_attr_version);
1440 driver_remove_file(&dwc_otg_driver.driver, &driver_attr_vbus_status);
1441 platform_driver_unregister(&dwc_otg_driver);
1442 printk(KERN_INFO "%s module removed\n", dwc_otg20_driver_name);
1446 module_exit(dwc_otg_driver_cleanup);
1448 MODULE_DESCRIPTION(DWC_DRIVER_DESC);
1449 MODULE_AUTHOR("Synopsys Inc.");
1450 MODULE_LICENSE("GPL");
1452 module_param_named(otg_cap, dwc_otg_module_params.otg_cap, int, 0444);
1453 MODULE_PARM_DESC(otg_cap, "OTG Capabilities 0=HNP&SRP 1=SRP Only 2=None");
1454 module_param_named(opt, dwc_otg_module_params.opt, int, 0444);
1455 MODULE_PARM_DESC(opt, "OPT Mode");
1456 module_param_named(dma_enable, dwc_otg_module_params.dma_enable, int, 0444);
1457 MODULE_PARM_DESC(dma_enable, "DMA Mode 0=Slave 1=DMA enabled");
1459 module_param_named(dma_desc_enable, dwc_otg_module_params.dma_desc_enable, int,
1461 MODULE_PARM_DESC(dma_desc_enable,
1462 "DMA Desc Mode 0=Address DMA 1=DMA Descriptor enabled");
1464 module_param_named(dma_burst_size, dwc_otg_module_params.dma_burst_size, int,
1466 MODULE_PARM_DESC(dma_burst_size,
1467 "DMA Burst Size 1, 4, 8, 16, 32, 64, 128, 256");
1468 module_param_named(speed, dwc_otg_module_params.speed, int, 0444);
1469 MODULE_PARM_DESC(speed, "Speed 0=High Speed 1=Full Speed");
1470 module_param_named(host_support_fs_ls_low_power,
1471 dwc_otg_module_params.host_support_fs_ls_low_power, int,
1473 MODULE_PARM_DESC(host_support_fs_ls_low_power,
1474 "Support Low Power w/FS or LS 0=Support 1=Don't Support");
1475 module_param_named(host_ls_low_power_phy_clk,
1476 dwc_otg_module_params.host_ls_low_power_phy_clk, int, 0444);
1477 MODULE_PARM_DESC(host_ls_low_power_phy_clk,
1478 "Low Speed Low Power Clock 0=48Mhz 1=6Mhz");
1479 module_param_named(enable_dynamic_fifo,
1480 dwc_otg_module_params.enable_dynamic_fifo, int, 0444);
1481 MODULE_PARM_DESC(enable_dynamic_fifo, "0=cC Setting 1=Allow Dynamic Sizing");
1482 module_param_named(data_fifo_size, dwc_otg_module_params.data_fifo_size, int,
1484 MODULE_PARM_DESC(data_fifo_size,
1485 "Total number of words in the data FIFO memory 32-32768");
1486 module_param_named(dev_rx_fifo_size, dwc_otg_module_params.dev_rx_fifo_size,
1488 MODULE_PARM_DESC(dev_rx_fifo_size, "Number of words in the Rx FIFO 16-32768");
1489 module_param_named(dev_nperio_tx_fifo_size,
1490 dwc_otg_module_params.dev_nperio_tx_fifo_size, int, 0444);
1491 MODULE_PARM_DESC(dev_nperio_tx_fifo_size,
1492 "Number of words in the non-periodic Tx FIFO 16-32768");
1493 module_param_named(dev_perio_tx_fifo_size_1,
1494 dwc_otg_module_params.dev_perio_tx_fifo_size[0], int, 0444);
1495 MODULE_PARM_DESC(dev_perio_tx_fifo_size_1,
1496 "Number of words in the periodic Tx FIFO 4-768");
1497 module_param_named(dev_perio_tx_fifo_size_2,
1498 dwc_otg_module_params.dev_perio_tx_fifo_size[1], int, 0444);
1499 MODULE_PARM_DESC(dev_perio_tx_fifo_size_2,
1500 "Number of words in the periodic Tx FIFO 4-768");
1501 module_param_named(dev_perio_tx_fifo_size_3,
1502 dwc_otg_module_params.dev_perio_tx_fifo_size[2], int, 0444);
1503 MODULE_PARM_DESC(dev_perio_tx_fifo_size_3,
1504 "Number of words in the periodic Tx FIFO 4-768");
1505 module_param_named(dev_perio_tx_fifo_size_4,
1506 dwc_otg_module_params.dev_perio_tx_fifo_size[3], int, 0444);
1507 MODULE_PARM_DESC(dev_perio_tx_fifo_size_4,
1508 "Number of words in the periodic Tx FIFO 4-768");
1509 module_param_named(dev_perio_tx_fifo_size_5,
1510 dwc_otg_module_params.dev_perio_tx_fifo_size[4], int, 0444);
1511 MODULE_PARM_DESC(dev_perio_tx_fifo_size_5,
1512 "Number of words in the periodic Tx FIFO 4-768");
1513 module_param_named(dev_perio_tx_fifo_size_6,
1514 dwc_otg_module_params.dev_perio_tx_fifo_size[5], int, 0444);
1515 MODULE_PARM_DESC(dev_perio_tx_fifo_size_6,
1516 "Number of words in the periodic Tx FIFO 4-768");
1517 module_param_named(dev_perio_tx_fifo_size_7,
1518 dwc_otg_module_params.dev_perio_tx_fifo_size[6], int, 0444);
1519 MODULE_PARM_DESC(dev_perio_tx_fifo_size_7,
1520 "Number of words in the periodic Tx FIFO 4-768");
1521 module_param_named(dev_perio_tx_fifo_size_8,
1522 dwc_otg_module_params.dev_perio_tx_fifo_size[7], int, 0444);
1523 MODULE_PARM_DESC(dev_perio_tx_fifo_size_8,
1524 "Number of words in the periodic Tx FIFO 4-768");
1525 module_param_named(dev_perio_tx_fifo_size_9,
1526 dwc_otg_module_params.dev_perio_tx_fifo_size[8], int, 0444);
1527 MODULE_PARM_DESC(dev_perio_tx_fifo_size_9,
1528 "Number of words in the periodic Tx FIFO 4-768");
1529 module_param_named(dev_perio_tx_fifo_size_10,
1530 dwc_otg_module_params.dev_perio_tx_fifo_size[9], int, 0444);
1531 MODULE_PARM_DESC(dev_perio_tx_fifo_size_10,
1532 "Number of words in the periodic Tx FIFO 4-768");
1533 module_param_named(dev_perio_tx_fifo_size_11,
1534 dwc_otg_module_params.dev_perio_tx_fifo_size[10], int, 0444);
1535 MODULE_PARM_DESC(dev_perio_tx_fifo_size_11,
1536 "Number of words in the periodic Tx FIFO 4-768");
1537 module_param_named(dev_perio_tx_fifo_size_12,
1538 dwc_otg_module_params.dev_perio_tx_fifo_size[11], int, 0444);
1539 MODULE_PARM_DESC(dev_perio_tx_fifo_size_12,
1540 "Number of words in the periodic Tx FIFO 4-768");
1541 module_param_named(dev_perio_tx_fifo_size_13,
1542 dwc_otg_module_params.dev_perio_tx_fifo_size[12], int, 0444);
1543 MODULE_PARM_DESC(dev_perio_tx_fifo_size_13,
1544 "Number of words in the periodic Tx FIFO 4-768");
1545 module_param_named(dev_perio_tx_fifo_size_14,
1546 dwc_otg_module_params.dev_perio_tx_fifo_size[13], int, 0444);
1547 MODULE_PARM_DESC(dev_perio_tx_fifo_size_14,
1548 "Number of words in the periodic Tx FIFO 4-768");
1549 module_param_named(dev_perio_tx_fifo_size_15,
1550 dwc_otg_module_params.dev_perio_tx_fifo_size[14], int, 0444);
1551 MODULE_PARM_DESC(dev_perio_tx_fifo_size_15,
1552 "Number of words in the periodic Tx FIFO 4-768");
1553 module_param_named(host_rx_fifo_size, dwc_otg_module_params.host_rx_fifo_size,
1555 MODULE_PARM_DESC(host_rx_fifo_size, "Number of words in the Rx FIFO 16-32768");
1556 module_param_named(host_nperio_tx_fifo_size,
1557 dwc_otg_module_params.host_nperio_tx_fifo_size, int, 0444);
1558 MODULE_PARM_DESC(host_nperio_tx_fifo_size,
1559 "Number of words in the non-periodic Tx FIFO 16-32768");
1560 module_param_named(host_perio_tx_fifo_size,
1561 dwc_otg_module_params.host_perio_tx_fifo_size, int, 0444);
1562 MODULE_PARM_DESC(host_perio_tx_fifo_size,
1563 "Number of words in the host periodic Tx FIFO 16-32768");
1564 module_param_named(max_transfer_size, dwc_otg_module_params.max_transfer_size,
1566 /** @todo Set the max to 512K, modify checks */
1567 MODULE_PARM_DESC(max_transfer_size,
1568 "The maximum transfer size supported in bytes 2047-65535");
1569 module_param_named(max_packet_count, dwc_otg_module_params.max_packet_count,
1571 MODULE_PARM_DESC(max_packet_count,
1572 "The maximum number of packets in a transfer 15-511");
1573 module_param_named(host_channels, dwc_otg_module_params.host_channels, int,
1575 MODULE_PARM_DESC(host_channels,
1576 "The number of host channel registers to use 1-16");
1577 module_param_named(dev_endpoints, dwc_otg_module_params.dev_endpoints, int,
1579 MODULE_PARM_DESC(dev_endpoints,
1580 "The number of endpoints in addition to EP0 available for device mode 1-15");
1581 module_param_named(phy_type, dwc_otg_module_params.phy_type, int, 0444);
1582 MODULE_PARM_DESC(phy_type, "0=Reserved 1=UTMI+ 2=ULPI");
1583 module_param_named(phy_utmi_width, dwc_otg_module_params.phy_utmi_width, int,
1585 MODULE_PARM_DESC(phy_utmi_width, "Specifies the UTMI+ Data Width 8 or 16 bits");
1586 module_param_named(phy_ulpi_ddr, dwc_otg_module_params.phy_ulpi_ddr, int, 0444);
1587 MODULE_PARM_DESC(phy_ulpi_ddr,
1588 "ULPI at double or single data rate 0=Single 1=Double");
1589 module_param_named(phy_ulpi_ext_vbus, dwc_otg_module_params.phy_ulpi_ext_vbus,
1591 MODULE_PARM_DESC(phy_ulpi_ext_vbus,
1592 "ULPI PHY using internal or external vbus 0=Internal");
1593 module_param_named(i2c_enable, dwc_otg_module_params.i2c_enable, int, 0444);
1594 MODULE_PARM_DESC(i2c_enable, "FS PHY Interface");
1595 module_param_named(ulpi_fs_ls, dwc_otg_module_params.ulpi_fs_ls, int, 0444);
1596 MODULE_PARM_DESC(ulpi_fs_ls, "ULPI PHY FS/LS mode only");
1597 module_param_named(ts_dline, dwc_otg_module_params.ts_dline, int, 0444);
1598 MODULE_PARM_DESC(ts_dline, "Term select Dline pulsing for all PHYs");
1599 module_param_named(debug, g_dbg_lvl, int, 0444);
1600 MODULE_PARM_DESC(debug, "");
1602 module_param_named(en_multiple_tx_fifo,
1603 dwc_otg_module_params.en_multiple_tx_fifo, int, 0444);
1604 MODULE_PARM_DESC(en_multiple_tx_fifo,
1605 "Dedicated Non Periodic Tx FIFOs 0=disabled 1=enabled");
1606 module_param_named(dev_tx_fifo_size_1,
1607 dwc_otg_module_params.dev_tx_fifo_size[0], int, 0444);
1608 MODULE_PARM_DESC(dev_tx_fifo_size_1, "Number of words in the Tx FIFO 4-768");
1609 module_param_named(dev_tx_fifo_size_2,
1610 dwc_otg_module_params.dev_tx_fifo_size[1], int, 0444);
1611 MODULE_PARM_DESC(dev_tx_fifo_size_2, "Number of words in the Tx FIFO 4-768");
1612 module_param_named(dev_tx_fifo_size_3,
1613 dwc_otg_module_params.dev_tx_fifo_size[2], int, 0444);
1614 MODULE_PARM_DESC(dev_tx_fifo_size_3, "Number of words in the Tx FIFO 4-768");
1615 module_param_named(dev_tx_fifo_size_4,
1616 dwc_otg_module_params.dev_tx_fifo_size[3], int, 0444);
1617 MODULE_PARM_DESC(dev_tx_fifo_size_4, "Number of words in the Tx FIFO 4-768");
1618 module_param_named(dev_tx_fifo_size_5,
1619 dwc_otg_module_params.dev_tx_fifo_size[4], int, 0444);
1620 MODULE_PARM_DESC(dev_tx_fifo_size_5, "Number of words in the Tx FIFO 4-768");
1621 module_param_named(dev_tx_fifo_size_6,
1622 dwc_otg_module_params.dev_tx_fifo_size[5], int, 0444);
1623 MODULE_PARM_DESC(dev_tx_fifo_size_6, "Number of words in the Tx FIFO 4-768");
1624 module_param_named(dev_tx_fifo_size_7,
1625 dwc_otg_module_params.dev_tx_fifo_size[6], int, 0444);
1626 MODULE_PARM_DESC(dev_tx_fifo_size_7, "Number of words in the Tx FIFO 4-768");
1627 module_param_named(dev_tx_fifo_size_8,
1628 dwc_otg_module_params.dev_tx_fifo_size[7], int, 0444);
1629 MODULE_PARM_DESC(dev_tx_fifo_size_8, "Number of words in the Tx FIFO 4-768");
1630 module_param_named(dev_tx_fifo_size_9,
1631 dwc_otg_module_params.dev_tx_fifo_size[8], int, 0444);
1632 MODULE_PARM_DESC(dev_tx_fifo_size_9, "Number of words in the Tx FIFO 4-768");
1633 module_param_named(dev_tx_fifo_size_10,
1634 dwc_otg_module_params.dev_tx_fifo_size[9], int, 0444);
1635 MODULE_PARM_DESC(dev_tx_fifo_size_10, "Number of words in the Tx FIFO 4-768");
1636 module_param_named(dev_tx_fifo_size_11,
1637 dwc_otg_module_params.dev_tx_fifo_size[10], int, 0444);
1638 MODULE_PARM_DESC(dev_tx_fifo_size_11, "Number of words in the Tx FIFO 4-768");
1639 module_param_named(dev_tx_fifo_size_12,
1640 dwc_otg_module_params.dev_tx_fifo_size[11], int, 0444);
1641 MODULE_PARM_DESC(dev_tx_fifo_size_12, "Number of words in the Tx FIFO 4-768");
1642 module_param_named(dev_tx_fifo_size_13,
1643 dwc_otg_module_params.dev_tx_fifo_size[12], int, 0444);
1644 MODULE_PARM_DESC(dev_tx_fifo_size_13, "Number of words in the Tx FIFO 4-768");
1645 module_param_named(dev_tx_fifo_size_14,
1646 dwc_otg_module_params.dev_tx_fifo_size[13], int, 0444);
1647 MODULE_PARM_DESC(dev_tx_fifo_size_14, "Number of words in the Tx FIFO 4-768");
1648 module_param_named(dev_tx_fifo_size_15,
1649 dwc_otg_module_params.dev_tx_fifo_size[14], int, 0444);
1650 MODULE_PARM_DESC(dev_tx_fifo_size_15, "Number of words in the Tx FIFO 4-768");
1652 module_param_named(thr_ctl, dwc_otg_module_params.thr_ctl, int, 0444);
1653 MODULE_PARM_DESC(thr_ctl,
1654 "Thresholding enable flag bit 0 - non ISO Tx thr., 1 - ISO Tx thr., 2 - Rx thr.- bit 0=disabled 1=enabled");
1655 module_param_named(tx_thr_length, dwc_otg_module_params.tx_thr_length, int,
1657 MODULE_PARM_DESC(tx_thr_length, "Tx Threshold length in 32 bit DWORDs");
1658 module_param_named(rx_thr_length, dwc_otg_module_params.rx_thr_length, int,
1660 MODULE_PARM_DESC(rx_thr_length, "Rx Threshold length in 32 bit DWORDs");
1662 module_param_named(pti_enable, dwc_otg_module_params.pti_enable, int, 0444);
1663 module_param_named(mpi_enable, dwc_otg_module_params.mpi_enable, int, 0444);
1664 module_param_named(lpm_enable, dwc_otg_module_params.lpm_enable, int, 0444);
1665 MODULE_PARM_DESC(lpm_enable, "LPM Enable 0=LPM Disabled 1=LPM Enabled");
1667 module_param_named(besl_enable, dwc_otg_module_params.besl_enable, int, 0444);
1668 MODULE_PARM_DESC(besl_enable, "BESL Enable 0=BESL Disabled 1=BESL Enabled");
1669 module_param_named(baseline_besl, dwc_otg_module_params.baseline_besl, int, 0444);
1670 MODULE_PARM_DESC(baseline_besl, "Set the baseline besl value");
1671 module_param_named(deep_besl, dwc_otg_module_params.deep_besl, int, 0444);
1672 MODULE_PARM_DESC(deep_besl, "Set the deep besl value");
1674 module_param_named(ic_usb_cap, dwc_otg_module_params.ic_usb_cap, int, 0444);
1675 MODULE_PARM_DESC(ic_usb_cap,
1676 "IC_USB Capability 0=IC_USB Disabled 1=IC_USB Enabled");
1677 module_param_named(ahb_thr_ratio, dwc_otg_module_params.ahb_thr_ratio, int,
1679 MODULE_PARM_DESC(ahb_thr_ratio, "AHB Threshold Ratio");
1680 module_param_named(power_down, dwc_otg_module_params.power_down, int, 0444);
1681 MODULE_PARM_DESC(power_down, "Power Down Mode");
1682 module_param_named(reload_ctl, dwc_otg_module_params.reload_ctl, int, 0444);
1683 MODULE_PARM_DESC(reload_ctl, "HFIR Reload Control");
1684 module_param_named(dev_out_nak, dwc_otg_module_params.dev_out_nak, int, 0444);
1685 MODULE_PARM_DESC(dev_out_nak, "Enable Device OUT NAK");
1686 module_param_named(cont_on_bna, dwc_otg_module_params.cont_on_bna, int, 0444);
1687 MODULE_PARM_DESC(cont_on_bna, "Enable Enable Continue on BNA");
1688 module_param_named(ahb_single, dwc_otg_module_params.ahb_single, int, 0444);
1689 MODULE_PARM_DESC(ahb_single, "Enable AHB Single Support");
1690 module_param_named(adp_enable, dwc_otg_module_params.adp_enable, int, 0444);
1691 MODULE_PARM_DESC(adp_enable, "ADP Enable 0=ADP Disabled 1=ADP Enabled");
1692 module_param_named(otg_ver, dwc_otg_module_params.otg_ver, int, 0444);
1693 MODULE_PARM_DESC(otg_ver, "OTG revision supported 0=OTG 1.3 1=OTG 2.0");
1695 /** @page "Module Parameters"
1697 * The following parameters may be specified when starting the module.
1698 * These parameters define how the DWC_otg controller should be
1699 * configured. Parameter values are passed to the CIL initialization
1700 * function dwc_otg_cil_init
1702 * Example: <code>modprobe dwc_otg speed=1 otg_cap=1</code>
1706 <tr><td>Parameter Name</td><td>Meaning</td></tr>
1710 <td>Specifies the OTG capabilities. The driver will automatically detect the
1711 value for this parameter if none is specified.
1712 - 0: HNP and SRP capable (default, if available)
1713 - 1: SRP Only capable
1714 - 2: No HNP/SRP capable
1719 <td>Specifies whether to use slave or DMA mode for accessing the data FIFOs.
1720 The driver will automatically detect the value for this parameter if none is
1723 - 1: DMA (default, if available)
1727 <td>dma_burst_size</td>
1728 <td>The DMA Burst size (applicable only for External DMA Mode).
1729 - Values: 1, 4, 8 16, 32, 64, 128, 256 (default 32)
1734 <td>Specifies the maximum speed of operation in host and device mode. The
1735 actual speed depends on the speed of the attached device and the value of
1737 - 0: High Speed (default)
1742 <td>host_support_fs_ls_low_power</td>
1743 <td>Specifies whether low power mode is supported when attached to a Full
1744 Speed or Low Speed device in host mode.
1745 - 0: Don't support low power mode (default)
1746 - 1: Support low power mode
1750 <td>host_ls_low_power_phy_clk</td>
1751 <td>Specifies the PHY clock rate in low power mode when connected to a Low
1752 Speed device in host mode. This parameter is applicable only if
1753 HOST_SUPPORT_FS_LS_LOW_POWER is enabled.
1754 - 0: 48 MHz (default)
1759 <td>enable_dynamic_fifo</td>
1760 <td> Specifies whether FIFOs may be resized by the driver software.
1761 - 0: Use cC FIFO size parameters
1762 - 1: Allow dynamic FIFO sizing (default)
1766 <td>data_fifo_size</td>
1767 <td>Total number of 4-byte words in the data FIFO memory. This memory
1768 includes the Rx FIFO, non-periodic Tx FIFO, and periodic Tx FIFOs.
1769 - Values: 32 to 32768 (default 8192)
1771 Note: The total FIFO memory depth in the FPGA configuration is 8192.
1775 <td>dev_rx_fifo_size</td>
1776 <td>Number of 4-byte words in the Rx FIFO in device mode when dynamic
1777 FIFO sizing is enabled.
1778 - Values: 16 to 32768 (default 1064)
1782 <td>dev_nperio_tx_fifo_size</td>
1783 <td>Number of 4-byte words in the non-periodic Tx FIFO in device mode when
1784 dynamic FIFO sizing is enabled.
1785 - Values: 16 to 32768 (default 1024)
1789 <td>dev_perio_tx_fifo_size_n (n = 1 to 15)</td>
1790 <td>Number of 4-byte words in each of the periodic Tx FIFOs in device mode
1791 when dynamic FIFO sizing is enabled.
1792 - Values: 4 to 768 (default 256)
1796 <td>host_rx_fifo_size</td>
1797 <td>Number of 4-byte words in the Rx FIFO in host mode when dynamic FIFO
1799 - Values: 16 to 32768 (default 1024)
1803 <td>host_nperio_tx_fifo_size</td>
1804 <td>Number of 4-byte words in the non-periodic Tx FIFO in host mode when
1805 dynamic FIFO sizing is enabled in the core.
1806 - Values: 16 to 32768 (default 1024)
1810 <td>host_perio_tx_fifo_size</td>
1811 <td>Number of 4-byte words in the host periodic Tx FIFO when dynamic FIFO
1813 - Values: 16 to 32768 (default 1024)
1817 <td>max_transfer_size</td>
1818 <td>The maximum transfer size supported in bytes.
1819 - Values: 2047 to 65,535 (default 65,535)
1823 <td>max_packet_count</td>
1824 <td>The maximum number of packets in a transfer.
1825 - Values: 15 to 511 (default 511)
1829 <td>host_channels</td>
1830 <td>The number of host channel registers to use.
1831 - Values: 1 to 16 (default 12)
1833 Note: The FPGA configuration supports a maximum of 12 host channels.
1837 <td>dev_endpoints</td>
1838 <td>The number of endpoints in addition to EP0 available for device mode
1840 - Values: 1 to 15 (default 6 IN and OUT)
1842 Note: The FPGA configuration supports a maximum of 6 IN and OUT endpoints in
1848 <td>Specifies the type of PHY interface to use. By default, the driver will
1849 automatically detect the phy_type.
1851 - 1: UTMI+ (default, if available)
1856 <td>phy_utmi_width</td>
1857 <td>Specifies the UTMI+ Data Width. This parameter is applicable for a
1858 phy_type of UTMI+. Also, this parameter is applicable only if the
1859 OTG_HSPHY_WIDTH cC parameter was set to "8 and 16 bits", meaning that the
1860 core has been configured to work at either data path width.
1861 - Values: 8 or 16 bits (default 16)
1865 <td>phy_ulpi_ddr</td>
1866 <td>Specifies whether the ULPI operates at double or single data rate. This
1867 parameter is only applicable if phy_type is ULPI.
1868 - 0: single data rate ULPI interface with 8 bit wide data bus (default)
1869 - 1: double data rate ULPI interface with 4 bit wide data bus
1874 <td>Specifies whether to use the I2C interface for full speed PHY. This
1875 parameter is only applicable if PHY_TYPE is FS.
1876 - 0: Disabled (default)
1882 <td>Specifies whether to use ULPI FS/LS mode only.
1883 - 0: Disabled (default)
1889 <td>Specifies whether term select D-Line pulsing for all PHYs is enabled.
1890 - 0: Disabled (default)
1895 <td>en_multiple_tx_fifo</td>
1896 <td>Specifies whether dedicatedto tx fifos are enabled for non periodic IN EPs.
1897 The driver will automatically detect the value for this parameter if none is
1900 - 1: Enabled (default, if available)
1904 <td>dev_tx_fifo_size_n (n = 1 to 15)</td>
1905 <td>Number of 4-byte words in each of the Tx FIFOs in device mode
1906 when dynamic FIFO sizing is enabled.
1907 - Values: 4 to 768 (default 256)
1911 <td>tx_thr_length</td>
1912 <td>Transmit Threshold length in 32 bit double words
1913 - Values: 8 to 128 (default 64)
1917 <td>rx_thr_length</td>
1918 <td>Receive Threshold length in 32 bit double words
1919 - Values: 8 to 128 (default 64)
1924 <td>Specifies whether to enable Thresholding for Device mode. Bits 0, 1, 2 of
1925 this parmater specifies if thresholding is enabled for non-Iso Tx, Iso Tx and
1926 Rx transfers accordingly.
1927 The driver will automatically detect the value for this parameter if none is
1929 - Values: 0 to 7 (default 0)
1930 Bit values indicate:
1931 - 0: Thresholding disabled
1932 - 1: Thresholding enabled
1936 <td>dma_desc_enable</td>
1937 <td>Specifies whether to enable Descriptor DMA mode.
1938 The driver will automatically detect the value for this parameter if none is
1940 - 0: Descriptor DMA disabled
1941 - 1: Descriptor DMA (default, if available)
1946 <td>Specifies whether to enable MPI enhancement mode.
1947 The driver will automatically detect the value for this parameter if none is
1949 - 0: MPI disabled (default)
1955 <td>Specifies whether to enable PTI enhancement support.
1956 The driver will automatically detect the value for this parameter if none is
1958 - 0: PTI disabled (default)
1964 <td>Specifies whether to enable LPM support.
1965 The driver will automatically detect the value for this parameter if none is
1968 - 1: LPM enable (default, if available)
1972 <td>besl_enable</td>
1973 <td>Specifies whether to enable LPM Errata support.
1974 The driver will automatically detect the value for this parameter if none is
1976 - 0: LPM Errata disabled (default)
1977 - 1: LPM Errata enable
1981 <td>baseline_besl</td>
1982 <td>Specifies the baseline besl value.
1983 - Values: 0 to 15 (default 0)
1988 <td>Specifies the deep besl value.
1989 - Values: 0 to 15 (default 15)
1994 <td>Specifies whether to enable IC_USB capability.
1995 The driver will automatically detect the value for this parameter if none is
1997 - 0: IC_USB disabled (default, if available)
2002 <td>ahb_thr_ratio</td>
2003 <td>Specifies AHB Threshold ratio.
2004 - Values: 0 to 3 (default 0)
2009 <td>Specifies Power Down(Hibernation) Mode.
2010 The driver will automatically detect the value for this parameter if none is
2012 - 0: Power Down disabled (default)
2013 - 2: Power Down enabled
2018 <td>Specifies whether dynamic reloading of the HFIR register is allowed during
2019 run time. The driver will automatically detect the value for this parameter if
2020 none is specified. In case the HFIR value is reloaded when HFIR.RldCtrl == 1'b0
2021 the core might misbehave.
2022 - 0: Reload Control disabled (default)
2023 - 1: Reload Control enabled
2027 <td>dev_out_nak</td>
2028 <td>Specifies whether Device OUT NAK enhancement enabled or no.
2029 The driver will automatically detect the value for this parameter if
2030 none is specified. This parameter is valid only when OTG_EN_DESC_DMA == 1
\92b1.
2031 - 0: The core does not set NAK after Bulk OUT transfer complete (default)
2032 - 1: The core sets NAK after Bulk OUT transfer complete
2036 <td>cont_on_bna</td>
2037 <td>Specifies whether Enable Continue on BNA enabled or no.
2038 After receiving BNA interrupt the core disables the endpoint,when the
2039 endpoint is re-enabled by the application the
2040 - 0: Core starts processing from the DOEPDMA descriptor (default)
2041 - 1: Core starts processing from the descriptor which received the BNA.
2042 This parameter is valid only when OTG_EN_DESC_DMA == 1
\92b1.
2047 <td>This bit when programmed supports SINGLE transfers for remainder data
2048 in a transfer for DMA mode of operation.
2049 - 0: The remainder data will be sent using INCR burst size (default)
2050 - 1: The remainder data will be sent using SINGLE burst size.
2055 <td>Specifies whether ADP feature is enabled.
2056 The driver will automatically detect the value for this parameter if none is
2058 - 0: ADP feature disabled (default)
2059 - 1: ADP feature enabled
2064 <td>Specifies whether OTG is performing as USB OTG Revision 2.0 or Revision 1.3
2066 - 0: OTG 2.0 support disabled (default)
2067 - 1: OTG 2.0 support enabled