drivers/usb/dwc3/core.c

   1 /**
   2  * core.c - DesignWare USB3 DRD Controller Core file
   3  *
   4  * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
   5  *
   6  * Authors: Felipe Balbi <balbi@ti.com>,
   7  *          Sebastian Andrzej Siewior <bigeasy@linutronix.de>
   8  *
   9  * This program is free software: you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2  of
  11  * the License as published by the Free Software Foundation.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  20  */
  21
  22 #include <linux/version.h>
  23 #include <linux/module.h>
  24 #include <linux/kernel.h>
  25 #include <linux/slab.h>
  26 #include <linux/spinlock.h>
  27 #include <linux/platform_device.h>
  28 #include <linux/pm_runtime.h>
  29 #include <linux/interrupt.h>
  30 #include <linux/ioport.h>
  31 #include <linux/io.h>
  32 #include <linux/list.h>
  33 #include <linux/delay.h>
  34 #include <linux/dma-mapping.h>
  35 #include <linux/of.h>
  36 #include <linux/acpi.h>
  37 #include <linux/pinctrl/consumer.h>
  38
  39 #include <linux/usb/ch9.h>
  40 #include <linux/usb/gadget.h>
  41 #include <linux/usb/of.h>
  42 #include <linux/usb/otg.h>
  43
  44 #include "platform_data.h"
  45 #include "core.h"
  46 #include "gadget.h"
  47 #include "io.h"
  48
  49 #include "debug.h"
  50
  51 /* -------------------------------------------------------------------------- */
  52
  53 void dwc3_set_mode(struct dwc3 *dwc, u32 mode)
  54 {
  55         u32 reg;
  56
  57         reg = dwc3_readl(dwc->regs, DWC3_GCTL);
  58         reg &= ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG));
  59         reg |= DWC3_GCTL_PRTCAPDIR(mode);
  60         dwc3_writel(dwc->regs, DWC3_GCTL, reg);
  61 }
  62
  63 /**
  64  * dwc3_core_soft_reset - Issues core soft reset and PHY reset
  65  * @dwc: pointer to our context structure
  66  */
  67 static int dwc3_core_soft_reset(struct dwc3 *dwc)
  68 {
  69         u32             reg;
  70         int             retries = 1000;
  71         int             ret;
  72
  73         usb_phy_init(dwc->usb2_phy);
  74         usb_phy_init(dwc->usb3_phy);
  75         ret = phy_init(dwc->usb2_generic_phy);
  76         if (ret < 0)
  77                 return ret;
  78
  79         ret = phy_init(dwc->usb3_generic_phy);
  80         if (ret < 0) {
  81                 phy_exit(dwc->usb2_generic_phy);
  82                 return ret;
  83         }
  84
  85         /*
  86          * We're resetting only the device side because, if we're in host mode,
  87          * XHCI driver will reset the host block. If dwc3 was configured for
  88          * host-only mode, then we can return early.
  89          */
  90         if (dwc->dr_mode == USB_DR_MODE_HOST)
  91                 return 0;
  92
  93         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
  94         reg |= DWC3_DCTL_CSFTRST;
  95         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
  96
  97         do {
  98                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
  99                 if (!(reg & DWC3_DCTL_CSFTRST))
 100                         return 0;
 101
 102                 udelay(1);
 103         } while (--retries);
 104
 105         return -ETIMEDOUT;
 106 }
 107
 108 /**
 109  * dwc3_soft_reset - Issue soft reset
 110  * @dwc: Pointer to our controller context structure
 111  */
 112 static int dwc3_soft_reset(struct dwc3 *dwc)
 113 {
 114         unsigned long timeout;
 115         u32 reg;
 116
 117         timeout = jiffies + msecs_to_jiffies(500);
 118         dwc3_writel(dwc->regs, DWC3_DCTL, DWC3_DCTL_CSFTRST);
 119         do {
 120                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 121                 if (!(reg & DWC3_DCTL_CSFTRST))
 122                         break;
 123
 124                 if (time_after(jiffies, timeout)) {
 125                         dev_err(dwc->dev, "Reset Timed Out\n");
 126                         return -ETIMEDOUT;
 127                 }
 128
 129                 cpu_relax();
 130         } while (true);
 131
 132         return 0;
 133 }
 134
 135 /*
 136  * dwc3_frame_length_adjustment - Adjusts frame length if required
 137  * @dwc3: Pointer to our controller context structure
 138  * @fladj: Value of GFLADJ_30MHZ to adjust frame length
 139  */
 140 static void dwc3_frame_length_adjustment(struct dwc3 *dwc, u32 fladj)
 141 {
 142         u32 reg;
 143         u32 dft;
 144
 145         if (dwc->revision < DWC3_REVISION_250A)
 146                 return;
 147
 148         if (fladj == 0)
 149                 return;
 150
 151         reg = dwc3_readl(dwc->regs, DWC3_GFLADJ);
 152         dft = reg & DWC3_GFLADJ_30MHZ_MASK;
 153         if (!dev_WARN_ONCE(dwc->dev, dft == fladj,
 154             "request value same as default, ignoring\n")) {
 155                 reg &= ~DWC3_GFLADJ_30MHZ_MASK;
 156                 reg |= DWC3_GFLADJ_30MHZ_SDBND_SEL | fladj;
 157                 dwc3_writel(dwc->regs, DWC3_GFLADJ, reg);
 158         }
 159 }
 160
 161 /**
 162  * dwc3_free_one_event_buffer - Frees one event buffer
 163  * @dwc: Pointer to our controller context structure
 164  * @evt: Pointer to event buffer to be freed
 165  */
 166 static void dwc3_free_one_event_buffer(struct dwc3 *dwc,
 167                 struct dwc3_event_buffer *evt)
 168 {
 169         dma_free_coherent(dwc->dev, evt->length, evt->buf, evt->dma);
 170 }
 171
 172 /**
 173  * dwc3_alloc_one_event_buffer - Allocates one event buffer structure
 174  * @dwc: Pointer to our controller context structure
 175  * @length: size of the event buffer
 176  *
 177  * Returns a pointer to the allocated event buffer structure on success
 178  * otherwise ERR_PTR(errno).
 179  */
 180 static struct dwc3_event_buffer *dwc3_alloc_one_event_buffer(struct dwc3 *dwc,
 181                 unsigned length)
 182 {
 183         struct dwc3_event_buffer        *evt;
 184
 185         evt = devm_kzalloc(dwc->dev, sizeof(*evt), GFP_KERNEL);
 186         if (!evt)
 187                 return ERR_PTR(-ENOMEM);
 188
 189         evt->dwc        = dwc;
 190         evt->length     = length;
 191         evt->buf        = dma_alloc_coherent(dwc->dev, length,
 192                         &evt->dma, GFP_KERNEL);
 193         if (!evt->buf)
 194                 return ERR_PTR(-ENOMEM);
 195
 196         return evt;
 197 }
 198
 199 /**
 200  * dwc3_free_event_buffers - frees all allocated event buffers
 201  * @dwc: Pointer to our controller context structure
 202  */
 203 static void dwc3_free_event_buffers(struct dwc3 *dwc)
 204 {
 205         struct dwc3_event_buffer        *evt;
 206         int i;
 207
 208         for (i = 0; i < dwc->num_event_buffers; i++) {
 209                 evt = dwc->ev_buffs[i];
 210                 if (evt)
 211                         dwc3_free_one_event_buffer(dwc, evt);
 212         }
 213 }
 214
 215 /**
 216  * dwc3_alloc_event_buffers - Allocates @num event buffers of size @length
 217  * @dwc: pointer to our controller context structure
 218  * @length: size of event buffer
 219  *
 220  * Returns 0 on success otherwise negative errno. In the error case, dwc
 221  * may contain some buffers allocated but not all which were requested.
 222  */
 223 static int dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned length)
 224 {
 225         int                     num;
 226         int                     i;
 227
 228         num = DWC3_NUM_INT(dwc->hwparams.hwparams1);
 229         dwc->num_event_buffers = num;
 230
 231         dwc->ev_buffs = devm_kzalloc(dwc->dev, sizeof(*dwc->ev_buffs) * num,
 232                         GFP_KERNEL);
 233         if (!dwc->ev_buffs)
 234                 return -ENOMEM;
 235
 236         for (i = 0; i < num; i++) {
 237                 struct dwc3_event_buffer        *evt;
 238
 239                 evt = dwc3_alloc_one_event_buffer(dwc, length);
 240                 if (IS_ERR(evt)) {
 241                         dev_err(dwc->dev, "can't allocate event buffer\n");
 242                         return PTR_ERR(evt);
 243                 }
 244                 dwc->ev_buffs[i] = evt;
 245         }
 246
 247         return 0;
 248 }
 249
 250 /**
 251  * dwc3_event_buffers_setup - setup our allocated event buffers
 252  * @dwc: pointer to our controller context structure
 253  *
 254  * Returns 0 on success otherwise negative errno.
 255  */
 256 static int dwc3_event_buffers_setup(struct dwc3 *dwc)
 257 {
 258         struct dwc3_event_buffer        *evt;
 259         int                             n;
 260
 261         for (n = 0; n < dwc->num_event_buffers; n++) {
 262                 evt = dwc->ev_buffs[n];
 263                 dwc3_trace(trace_dwc3_core,
 264                                 "Event buf %p dma %08llx length %d\n",
 265                                 evt->buf, (unsigned long long) evt->dma,
 266                                 evt->length);
 267
 268                 evt->lpos = 0;
 269
 270                 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(n),
 271                                 lower_32_bits(evt->dma));
 272                 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(n),
 273                                 upper_32_bits(evt->dma));
 274                 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(n),
 275                                 DWC3_GEVNTSIZ_SIZE(evt->length));
 276                 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(n), 0);
 277         }
 278
 279         return 0;
 280 }
 281
 282 static void dwc3_event_buffers_cleanup(struct dwc3 *dwc)
 283 {
 284         struct dwc3_event_buffer        *evt;
 285         int                             n;
 286
 287         for (n = 0; n < dwc->num_event_buffers; n++) {
 288                 evt = dwc->ev_buffs[n];
 289
 290                 evt->lpos = 0;
 291
 292                 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(n), 0);
 293                 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(n), 0);
 294                 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(n), DWC3_GEVNTSIZ_INTMASK
 295                                 | DWC3_GEVNTSIZ_SIZE(0));
 296                 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(n), 0);
 297         }
 298 }
 299
 300 static int dwc3_alloc_scratch_buffers(struct dwc3 *dwc)
 301 {
 302         if (!dwc->has_hibernation)
 303                 return 0;
 304
 305         if (!dwc->nr_scratch)
 306                 return 0;
 307
 308         dwc->scratchbuf = kmalloc_array(dwc->nr_scratch,
 309                         DWC3_SCRATCHBUF_SIZE, GFP_KERNEL);
 310         if (!dwc->scratchbuf)
 311                 return -ENOMEM;
 312
 313         return 0;
 314 }
 315
 316 static int dwc3_setup_scratch_buffers(struct dwc3 *dwc)
 317 {
 318         dma_addr_t scratch_addr;
 319         u32 param;
 320         int ret;
 321
 322         if (!dwc->has_hibernation)
 323                 return 0;
 324
 325         if (!dwc->nr_scratch)
 326                 return 0;
 327
 328          /* should never fall here */
 329         if (!WARN_ON(dwc->scratchbuf))
 330                 return 0;
 331
 332         scratch_addr = dma_map_single(dwc->dev, dwc->scratchbuf,
 333                         dwc->nr_scratch * DWC3_SCRATCHBUF_SIZE,
 334                         DMA_BIDIRECTIONAL);
 335         if (dma_mapping_error(dwc->dev, scratch_addr)) {
 336                 dev_err(dwc->dev, "failed to map scratch buffer\n");
 337                 ret = -EFAULT;
 338                 goto err0;
 339         }
 340
 341         dwc->scratch_addr = scratch_addr;
 342
 343         param = lower_32_bits(scratch_addr);
 344
 345         ret = dwc3_send_gadget_generic_command(dwc,
 346                         DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO, param);
 347         if (ret < 0)
 348                 goto err1;
 349
 350         param = upper_32_bits(scratch_addr);
 351
 352         ret = dwc3_send_gadget_generic_command(dwc,
 353                         DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI, param);
 354         if (ret < 0)
 355                 goto err1;
 356
 357         return 0;
 358
 359 err1:
 360         dma_unmap_single(dwc->dev, dwc->scratch_addr, dwc->nr_scratch *
 361                         DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL);
 362
 363 err0:
 364         return ret;
 365 }
 366
 367 static void dwc3_free_scratch_buffers(struct dwc3 *dwc)
 368 {
 369         if (!dwc->has_hibernation)
 370                 return;
 371
 372         if (!dwc->nr_scratch)
 373                 return;
 374
 375          /* should never fall here */
 376         if (!WARN_ON(dwc->scratchbuf))
 377                 return;
 378
 379         dma_unmap_single(dwc->dev, dwc->scratch_addr, dwc->nr_scratch *
 380                         DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL);
 381         kfree(dwc->scratchbuf);
 382 }
 383
 384 static void dwc3_core_num_eps(struct dwc3 *dwc)
 385 {
 386         struct dwc3_hwparams    *parms = &dwc->hwparams;
 387
 388         dwc->num_in_eps = DWC3_NUM_IN_EPS(parms);
 389         dwc->num_out_eps = DWC3_NUM_EPS(parms) - dwc->num_in_eps;
 390
 391         dwc3_trace(trace_dwc3_core, "found %d IN and %d OUT endpoints",
 392                         dwc->num_in_eps, dwc->num_out_eps);
 393 }
 394
 395 static void dwc3_cache_hwparams(struct dwc3 *dwc)
 396 {
 397         struct dwc3_hwparams    *parms = &dwc->hwparams;
 398
 399         parms->hwparams0 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS0);
 400         parms->hwparams1 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS1);
 401         parms->hwparams2 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS2);
 402         parms->hwparams3 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS3);
 403         parms->hwparams4 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS4);
 404         parms->hwparams5 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS5);
 405         parms->hwparams6 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS6);
 406         parms->hwparams7 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS7);
 407         parms->hwparams8 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS8);
 408 }
 409
 410 /**
 411  * dwc3_phy_setup - Configure USB PHY Interface of DWC3 Core
 412  * @dwc: Pointer to our controller context structure
 413  *
 414  * Returns 0 on success. The USB PHY interfaces are configured but not
 415  * initialized. The PHY interfaces and the PHYs get initialized together with
 416  * the core in dwc3_core_init.
 417  */
 418 static int dwc3_phy_setup(struct dwc3 *dwc)
 419 {
 420         u32 reg;
 421         u32 usbtrdtim;
 422         int ret;
 423
 424         reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
 425
 426         /*
 427          * Above 1.94a, it is recommended to set DWC3_GUSB3PIPECTL_SUSPHY
 428          * to '0' during coreConsultant configuration. So default value
 429          * will be '0' when the core is reset. Application needs to set it
 430          * to '1' after the core initialization is completed.
 431          */
 432         if (dwc->revision > DWC3_REVISION_194A)
 433                 reg |= DWC3_GUSB3PIPECTL_SUSPHY;
 434
 435         if (dwc->u2ss_inp3_quirk)
 436                 reg |= DWC3_GUSB3PIPECTL_U2SSINP3OK;
 437
 438         if (dwc->req_p1p2p3_quirk)
 439                 reg |= DWC3_GUSB3PIPECTL_REQP1P2P3;
 440
 441         if (dwc->del_p1p2p3_quirk)
 442                 reg |= DWC3_GUSB3PIPECTL_DEP1P2P3_EN;
 443
 444         if (dwc->del_phy_power_chg_quirk)
 445                 reg |= DWC3_GUSB3PIPECTL_DEPOCHANGE;
 446
 447         if (dwc->lfps_filter_quirk)
 448                 reg |= DWC3_GUSB3PIPECTL_LFPSFILT;
 449
 450         if (dwc->rx_detect_poll_quirk)
 451                 reg |= DWC3_GUSB3PIPECTL_RX_DETOPOLL;
 452
 453         if (dwc->tx_de_emphasis_quirk)
 454                 reg |= DWC3_GUSB3PIPECTL_TX_DEEPH(dwc->tx_de_emphasis);
 455
 456         if (dwc->dis_u3_susphy_quirk)
 457                 reg &= ~DWC3_GUSB3PIPECTL_SUSPHY;
 458
 459         dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
 460
 461         reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
 462
 463         /* Select the HS PHY interface */
 464         switch (DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3)) {
 465         case DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI:
 466                 if (dwc->hsphy_interface &&
 467                                 !strncmp(dwc->hsphy_interface, "utmi", 4)) {
 468                         reg &= ~DWC3_GUSB2PHYCFG_ULPI_UTMI;
 469                         break;
 470                 } else if (dwc->hsphy_interface &&
 471                                 !strncmp(dwc->hsphy_interface, "ulpi", 4)) {
 472                         reg |= DWC3_GUSB2PHYCFG_ULPI_UTMI;
 473                         dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
 474                 } else {
 475                         /* Relying on default value. */
 476                         if (!(reg & DWC3_GUSB2PHYCFG_ULPI_UTMI))
 477                                 break;
 478                 }
 479                 /* FALLTHROUGH */
 480         case DWC3_GHWPARAMS3_HSPHY_IFC_ULPI:
 481                 /* Making sure the interface and PHY are operational */
 482                 ret = dwc3_soft_reset(dwc);
 483                 if (ret)
 484                         return ret;
 485
 486                 udelay(1);
 487
 488                 ret = dwc3_ulpi_init(dwc);
 489                 if (ret)
 490                         return ret;
 491                 /* FALLTHROUGH */
 492         default:
 493                 break;
 494         }
 495
 496         /*
 497          * Above 1.94a, it is recommended to set DWC3_GUSB2PHYCFG_SUSPHY to
 498          * '0' during coreConsultant configuration. So default value will
 499          * be '0' when the core is reset. Application needs to set it to
 500          * '1' after the core initialization is completed.
 501          */
 502         if (dwc->revision > DWC3_REVISION_194A)
 503                 reg |= DWC3_GUSB2PHYCFG_SUSPHY;
 504
 505         if (dwc->dis_u2_susphy_quirk)
 506                 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
 507
 508         if (dwc->dis_enblslpm_quirk)
 509                 reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
 510
 511         if (dwc->dis_u2_freeclk_exists_quirk)
 512                 reg &= ~DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS;
 513
 514         if (dwc->phyif_utmi_16_bits)
 515                 reg |= DWC3_GUSB2PHYCFG_PHYIF;
 516
 517         usbtrdtim = (reg & DWC3_GUSB2PHYCFG_PHYIF) ?
 518                     USBTRDTIM_UTMI_16_BIT : USBTRDTIM_UTMI_8_BIT;
 519
 520         reg &= ~DWC3_GUSB2PHYCFG_USBTRDTIM_MASK;
 521         reg |= (usbtrdtim << DWC3_GUSB2PHYCFG_USBTRDTIM_SHIFT);
 522
 523         dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
 524
 525         return 0;
 526 }
 527
 528 /**
 529  * dwc3_core_init - Low-level initialization of DWC3 Core
 530  * @dwc: Pointer to our controller context structure
 531  *
 532  * Returns 0 on success otherwise negative errno.
 533  */
 534 static int dwc3_core_init(struct dwc3 *dwc)
 535 {
 536         u32                     hwparams4 = dwc->hwparams.hwparams4;
 537         u32                     reg;
 538         int                     ret;
 539
 540         reg = dwc3_readl(dwc->regs, DWC3_GSNPSID);
 541         /* This should read as U3 followed by revision number */
 542         if ((reg & DWC3_GSNPSID_MASK) == 0x55330000) {
 543                 /* Detected DWC_usb3 IP */
 544                 dwc->revision = reg;
 545         } else if ((reg & DWC3_GSNPSID_MASK) == 0x33310000) {
 546                 /* Detected DWC_usb31 IP */
 547                 dwc->revision = dwc3_readl(dwc->regs, DWC3_VER_NUMBER);
 548                 dwc->revision |= DWC3_REVISION_IS_DWC31;
 549         } else {
 550                 dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n");
 551                 ret = -ENODEV;
 552                 goto err0;
 553         }
 554
 555         /*
 556          * Write Linux Version Code to our GUID register so it's easy to figure
 557          * out which kernel version a bug was found.
 558          */
 559         dwc3_writel(dwc->regs, DWC3_GUID, LINUX_VERSION_CODE);
 560
 561         /* Handle USB2.0-only core configuration */
 562         if (DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3) ==
 563                         DWC3_GHWPARAMS3_SSPHY_IFC_DIS) {
 564                 if (dwc->maximum_speed == USB_SPEED_SUPER)
 565                         dwc->maximum_speed = USB_SPEED_HIGH;
 566         }
 567
 568         /* issue device SoftReset too */
 569         ret = dwc3_soft_reset(dwc);
 570         if (ret)
 571                 goto err0;
 572
 573         ret = dwc3_core_soft_reset(dwc);
 574         if (ret)
 575                 goto err0;
 576
 577         reg = dwc3_readl(dwc->regs, DWC3_GCTL);
 578         reg &= ~DWC3_GCTL_SCALEDOWN_MASK;
 579
 580         switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1)) {
 581         case DWC3_GHWPARAMS1_EN_PWROPT_CLK:
 582                 /**
 583                  * WORKAROUND: DWC3 revisions between 2.10a and 2.50a have an
 584                  * issue which would cause xHCI compliance tests to fail.
 585                  *
 586                  * Because of that we cannot enable clock gating on such
 587                  * configurations.
 588                  *
 589                  * Refers to:
 590                  *
 591                  * STAR#9000588375: Clock Gating, SOF Issues when ref_clk-Based
 592                  * SOF/ITP Mode Used
 593                  */
 594                 if ((dwc->dr_mode == USB_DR_MODE_HOST ||
 595                                 dwc->dr_mode == USB_DR_MODE_OTG) &&
 596                                 (dwc->revision >= DWC3_REVISION_210A &&
 597                                 dwc->revision <= DWC3_REVISION_250A))
 598                         reg |= DWC3_GCTL_DSBLCLKGTNG | DWC3_GCTL_SOFITPSYNC;
 599                 else
 600                         reg &= ~DWC3_GCTL_DSBLCLKGTNG;
 601                 break;
 602         case DWC3_GHWPARAMS1_EN_PWROPT_HIB:
 603                 /* enable hibernation here */
 604                 dwc->nr_scratch = DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(hwparams4);
 605
 606                 /*
 607                  * REVISIT Enabling this bit so that host-mode hibernation
 608                  * will work. Device-mode hibernation is not yet implemented.
 609                  */
 610                 reg |= DWC3_GCTL_GBLHIBERNATIONEN;
 611                 break;
 612         default:
 613                 dwc3_trace(trace_dwc3_core, "No power optimization available\n");
 614         }
 615
 616         /* check if current dwc3 is on simulation board */
 617         if (dwc->hwparams.hwparams6 & DWC3_GHWPARAMS6_EN_FPGA) {
 618                 dwc3_trace(trace_dwc3_core,
 619                                 "running on FPGA platform\n");
 620                 dwc->is_fpga = true;
 621         }
 622
 623         WARN_ONCE(dwc->disable_scramble_quirk && !dwc->is_fpga,
 624                         "disable_scramble cannot be used on non-FPGA builds\n");
 625
 626         if (dwc->disable_scramble_quirk && dwc->is_fpga)
 627                 reg |= DWC3_GCTL_DISSCRAMBLE;
 628         else
 629                 reg &= ~DWC3_GCTL_DISSCRAMBLE;
 630
 631         if (dwc->u2exit_lfps_quirk)
 632                 reg |= DWC3_GCTL_U2EXIT_LFPS;
 633
 634         /*
 635          * WORKAROUND: DWC3 revisions <1.90a have a bug
 636          * where the device can fail to connect at SuperSpeed
 637          * and falls back to high-speed mode which causes
 638          * the device to enter a Connect/Disconnect loop
 639          */
 640         if (dwc->revision < DWC3_REVISION_190A)
 641                 reg |= DWC3_GCTL_U2RSTECN;
 642
 643         dwc3_core_num_eps(dwc);
 644
 645         dwc3_writel(dwc->regs, DWC3_GCTL, reg);
 646
 647         ret = dwc3_alloc_scratch_buffers(dwc);
 648         if (ret)
 649                 goto err1;
 650
 651         ret = dwc3_setup_scratch_buffers(dwc);
 652         if (ret)
 653                 goto err2;
 654
 655         return 0;
 656
 657 err2:
 658         dwc3_free_scratch_buffers(dwc);
 659
 660 err1:
 661         usb_phy_shutdown(dwc->usb2_phy);
 662         usb_phy_shutdown(dwc->usb3_phy);
 663         phy_exit(dwc->usb2_generic_phy);
 664         phy_exit(dwc->usb3_generic_phy);
 665
 666 err0:
 667         return ret;
 668 }
 669
 670 static void dwc3_core_exit(struct dwc3 *dwc)
 671 {
 672         dwc3_free_scratch_buffers(dwc);
 673         usb_phy_shutdown(dwc->usb2_phy);
 674         usb_phy_shutdown(dwc->usb3_phy);
 675         phy_exit(dwc->usb2_generic_phy);
 676         phy_exit(dwc->usb3_generic_phy);
 677 }
 678
 679 static int dwc3_core_get_phy(struct dwc3 *dwc)
 680 {
 681         struct device           *dev = dwc->dev;
 682         struct device_node      *node = dev->of_node;
 683         int ret;
 684
 685         if (node) {
 686                 dwc->usb2_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 0);
 687                 dwc->usb3_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 1);
 688         } else {
 689                 dwc->usb2_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2);
 690                 dwc->usb3_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB3);
 691         }
 692
 693         if (IS_ERR(dwc->usb2_phy)) {
 694                 ret = PTR_ERR(dwc->usb2_phy);
 695                 if (ret == -ENXIO || ret == -ENODEV) {
 696                         dwc->usb2_phy = NULL;
 697                 } else if (ret == -EPROBE_DEFER) {
 698                         return ret;
 699                 } else {
 700                         dev_err(dev, "no usb2 phy configured\n");
 701                         return ret;
 702                 }
 703         }
 704
 705         if (IS_ERR(dwc->usb3_phy)) {
 706                 ret = PTR_ERR(dwc->usb3_phy);
 707                 if (ret == -ENXIO || ret == -ENODEV) {
 708                         dwc->usb3_phy = NULL;
 709                 } else if (ret == -EPROBE_DEFER) {
 710                         return ret;
 711                 } else {
 712                         dev_err(dev, "no usb3 phy configured\n");
 713                         return ret;
 714                 }
 715         }
 716
 717         dwc->usb2_generic_phy = devm_phy_get(dev, "usb2-phy");
 718         if (IS_ERR(dwc->usb2_generic_phy)) {
 719                 ret = PTR_ERR(dwc->usb2_generic_phy);
 720                 if (ret == -ENOSYS || ret == -ENODEV) {
 721                         dwc->usb2_generic_phy = NULL;
 722                 } else if (ret == -EPROBE_DEFER) {
 723                         return ret;
 724                 } else {
 725                         dev_err(dev, "no usb2 phy configured\n");
 726                         return ret;
 727                 }
 728         }
 729
 730         dwc->usb3_generic_phy = devm_phy_get(dev, "usb3-phy");
 731         if (IS_ERR(dwc->usb3_generic_phy)) {
 732                 ret = PTR_ERR(dwc->usb3_generic_phy);
 733                 if (ret == -ENOSYS || ret == -ENODEV) {
 734                         dwc->usb3_generic_phy = NULL;
 735                 } else if (ret == -EPROBE_DEFER) {
 736                         return ret;
 737                 } else {
 738                         dev_err(dev, "no usb3 phy configured\n");
 739                         return ret;
 740                 }
 741         }
 742
 743         return 0;
 744 }
 745
 746 static int dwc3_core_init_mode(struct dwc3 *dwc)
 747 {
 748         struct device *dev = dwc->dev;
 749         int ret;
 750
 751         switch (dwc->dr_mode) {
 752         case USB_DR_MODE_PERIPHERAL:
 753                 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_DEVICE);
 754                 ret = dwc3_gadget_init(dwc);
 755                 if (ret) {
 756                         dev_err(dev, "failed to initialize gadget\n");
 757                         return ret;
 758                 }
 759                 break;
 760         case USB_DR_MODE_HOST:
 761                 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_HOST);
 762                 ret = dwc3_host_init(dwc);
 763                 if (ret) {
 764                         dev_err(dev, "failed to initialize host\n");
 765                         return ret;
 766                 }
 767                 break;
 768         case USB_DR_MODE_OTG:
 769                 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_OTG);
 770                 ret = dwc3_host_init(dwc);
 771                 if (ret) {
 772                         dev_err(dev, "failed to initialize host\n");
 773                         return ret;
 774                 }
 775
 776                 ret = dwc3_gadget_init(dwc);
 777                 if (ret) {
 778                         dev_err(dev, "failed to initialize gadget\n");
 779                         return ret;
 780                 }
 781                 break;
 782         default:
 783                 dev_err(dev, "Unsupported mode of operation %d\n", dwc->dr_mode);
 784                 return -EINVAL;
 785         }
 786
 787         return 0;
 788 }
 789
 790 static void dwc3_core_exit_mode(struct dwc3 *dwc)
 791 {
 792         switch (dwc->dr_mode) {
 793         case USB_DR_MODE_PERIPHERAL:
 794                 dwc3_gadget_exit(dwc);
 795                 break;
 796         case USB_DR_MODE_HOST:
 797                 dwc3_host_exit(dwc);
 798                 break;
 799         case USB_DR_MODE_OTG:
 800                 dwc3_host_exit(dwc);
 801                 dwc3_gadget_exit(dwc);
 802                 break;
 803         default:
 804                 /* do nothing */
 805                 break;
 806         }
 807 }
 808
 809 #define DWC3_ALIGN_MASK         (16 - 1)
 810
 811 static int dwc3_probe(struct platform_device *pdev)
 812 {
 813         struct device           *dev = &pdev->dev;
 814         struct dwc3_platform_data *pdata = dev_get_platdata(dev);
 815         struct resource         *res;
 816         struct dwc3             *dwc;
 817         u8                      lpm_nyet_threshold;
 818         u8                      tx_de_emphasis;
 819         u8                      hird_threshold;
 820         u32                     fladj = 0;
 821
 822         int                     ret;
 823
 824         void __iomem            *regs;
 825         void                    *mem;
 826
 827         mem = devm_kzalloc(dev, sizeof(*dwc) + DWC3_ALIGN_MASK, GFP_KERNEL);
 828         if (!mem)
 829                 return -ENOMEM;
 830
 831         dwc = PTR_ALIGN(mem, DWC3_ALIGN_MASK + 1);
 832         dwc->mem = mem;
 833         dwc->dev = dev;
 834
 835         /* Try to set 64-bit DMA first */
 836         if (!pdev->dev.dma_mask)
 837                 /* Platform did not initialize dma_mask */
 838                 ret = dma_coerce_mask_and_coherent(&pdev->dev,
 839                                                    DMA_BIT_MASK(64));
 840         else
 841                 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
 842
 843         /* If seting 64-bit DMA mask fails, fall back to 32-bit DMA mask */
 844         if (ret) {
 845                 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
 846                 if (ret)
 847                         return ret;
 848         }
 849
 850         res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
 851         if (!res) {
 852                 dev_err(dev, "missing IRQ\n");
 853                 return -ENODEV;
 854         }
 855         dwc->xhci_resources[1].start = res->start;
 856         dwc->xhci_resources[1].end = res->end;
 857         dwc->xhci_resources[1].flags = res->flags;
 858         dwc->xhci_resources[1].name = res->name;
 859
 860         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 861         if (!res) {
 862                 dev_err(dev, "missing memory resource\n");
 863                 return -ENODEV;
 864         }
 865
 866         dwc->xhci_resources[0].start = res->start;
 867         dwc->xhci_resources[0].end = dwc->xhci_resources[0].start +
 868                                         DWC3_XHCI_REGS_END;
 869         dwc->xhci_resources[0].flags = res->flags;
 870         dwc->xhci_resources[0].name = res->name;
 871
 872         res->start += DWC3_GLOBALS_REGS_START;
 873
 874         /*
 875          * Request memory region but exclude xHCI regs,
 876          * since it will be requested by the xhci-plat driver.
 877          */
 878         regs = devm_ioremap_resource(dev, res);
 879         if (IS_ERR(regs)) {
 880                 ret = PTR_ERR(regs);
 881                 goto err0;
 882         }
 883
 884         dwc->regs       = regs;
 885         dwc->regs_size  = resource_size(res);
 886
 887         /* default to highest possible threshold */
 888         lpm_nyet_threshold = 0xff;
 889
 890         /* default to -3.5dB de-emphasis */
 891         tx_de_emphasis = 1;
 892
 893         /*
 894          * default to assert utmi_sleep_n and use maximum allowed HIRD
 895          * threshold value of 0b1100
 896          */
 897         hird_threshold = 12;
 898
 899         dwc->maximum_speed = usb_get_maximum_speed(dev);
 900         dwc->dr_mode = usb_get_dr_mode(dev);
 901
 902         dwc->has_lpm_erratum = device_property_read_bool(dev,
 903                                 "snps,has-lpm-erratum");
 904         device_property_read_u8(dev, "snps,lpm-nyet-threshold",
 905                                 &lpm_nyet_threshold);
 906         dwc->is_utmi_l1_suspend = device_property_read_bool(dev,
 907                                 "snps,is-utmi-l1-suspend");
 908         device_property_read_u8(dev, "snps,hird-threshold",
 909                                 &hird_threshold);
 910         dwc->usb3_lpm_capable = device_property_read_bool(dev,
 911                                 "snps,usb3_lpm_capable");
 912
 913         dwc->needs_fifo_resize = device_property_read_bool(dev,
 914                                 "tx-fifo-resize");
 915
 916         dwc->disable_scramble_quirk = device_property_read_bool(dev,
 917                                 "snps,disable_scramble_quirk");
 918         dwc->u2exit_lfps_quirk = device_property_read_bool(dev,
 919                                 "snps,u2exit_lfps_quirk");
 920         dwc->u2ss_inp3_quirk = device_property_read_bool(dev,
 921                                 "snps,u2ss_inp3_quirk");
 922         dwc->req_p1p2p3_quirk = device_property_read_bool(dev,
 923                                 "snps,req_p1p2p3_quirk");
 924         dwc->del_p1p2p3_quirk = device_property_read_bool(dev,
 925                                 "snps,del_p1p2p3_quirk");
 926         dwc->del_phy_power_chg_quirk = device_property_read_bool(dev,
 927                                 "snps,del_phy_power_chg_quirk");
 928         dwc->lfps_filter_quirk = device_property_read_bool(dev,
 929                                 "snps,lfps_filter_quirk");
 930         dwc->rx_detect_poll_quirk = device_property_read_bool(dev,
 931                                 "snps,rx_detect_poll_quirk");
 932         dwc->dis_u3_susphy_quirk = device_property_read_bool(dev,
 933                                 "snps,dis_u3_susphy_quirk");
 934         dwc->dis_u2_susphy_quirk = device_property_read_bool(dev,
 935                                 "snps,dis_u2_susphy_quirk");
 936         dwc->dis_enblslpm_quirk = device_property_read_bool(dev,
 937                                 "snps,dis_enblslpm_quirk");
 938         dwc->dis_u2_freeclk_exists_quirk = device_property_read_bool(dev,
 939                                 "snps,dis_u2_freeclk_exists_quirk");
 940         dwc->phyif_utmi_16_bits = device_property_read_bool(dev,
 941                                 "snps,phyif_utmi_16_bits");
 942
 943         dwc->tx_de_emphasis_quirk = device_property_read_bool(dev,
 944                                 "snps,tx_de_emphasis_quirk");
 945         device_property_read_u8(dev, "snps,tx_de_emphasis",
 946                                 &tx_de_emphasis);
 947         device_property_read_string(dev, "snps,hsphy_interface",
 948                                     &dwc->hsphy_interface);
 949         device_property_read_u32(dev, "snps,quirk-frame-length-adjustment",
 950                                  &fladj);
 951
 952         if (pdata) {
 953                 dwc->maximum_speed = pdata->maximum_speed;
 954                 dwc->has_lpm_erratum = pdata->has_lpm_erratum;
 955                 if (pdata->lpm_nyet_threshold)
 956                         lpm_nyet_threshold = pdata->lpm_nyet_threshold;
 957                 dwc->is_utmi_l1_suspend = pdata->is_utmi_l1_suspend;
 958                 if (pdata->hird_threshold)
 959                         hird_threshold = pdata->hird_threshold;
 960
 961                 dwc->needs_fifo_resize = pdata->tx_fifo_resize;
 962                 dwc->usb3_lpm_capable = pdata->usb3_lpm_capable;
 963                 dwc->dr_mode = pdata->dr_mode;
 964
 965                 dwc->disable_scramble_quirk = pdata->disable_scramble_quirk;
 966                 dwc->u2exit_lfps_quirk = pdata->u2exit_lfps_quirk;
 967                 dwc->u2ss_inp3_quirk = pdata->u2ss_inp3_quirk;
 968                 dwc->req_p1p2p3_quirk = pdata->req_p1p2p3_quirk;
 969                 dwc->del_p1p2p3_quirk = pdata->del_p1p2p3_quirk;
 970                 dwc->del_phy_power_chg_quirk = pdata->del_phy_power_chg_quirk;
 971                 dwc->lfps_filter_quirk = pdata->lfps_filter_quirk;
 972                 dwc->rx_detect_poll_quirk = pdata->rx_detect_poll_quirk;
 973                 dwc->dis_u3_susphy_quirk = pdata->dis_u3_susphy_quirk;
 974                 dwc->dis_u2_susphy_quirk = pdata->dis_u2_susphy_quirk;
 975                 dwc->dis_enblslpm_quirk = pdata->dis_enblslpm_quirk;
 976                 dwc->dis_u2_freeclk_exists_quirk =
 977                                         pdata->dis_u2_freeclk_exists_quirk;
 978                 dwc->phyif_utmi_16_bits = pdata->phyif_utmi_16_bits;
 979
 980                 dwc->tx_de_emphasis_quirk = pdata->tx_de_emphasis_quirk;
 981                 if (pdata->tx_de_emphasis)
 982                         tx_de_emphasis = pdata->tx_de_emphasis;
 983
 984                 dwc->hsphy_interface = pdata->hsphy_interface;
 985                 fladj = pdata->fladj_value;
 986         }
 987
 988         /* default to superspeed if no maximum_speed passed */
 989         if (dwc->maximum_speed == USB_SPEED_UNKNOWN)
 990                 dwc->maximum_speed = USB_SPEED_SUPER;
 991
 992         dwc->lpm_nyet_threshold = lpm_nyet_threshold;
 993         dwc->tx_de_emphasis = tx_de_emphasis;
 994
 995         dwc->hird_threshold = hird_threshold
 996                 | (dwc->is_utmi_l1_suspend << 4);
 997
 998         platform_set_drvdata(pdev, dwc);
 999         dwc3_cache_hwparams(dwc);
1000
1001         ret = dwc3_phy_setup(dwc);
1002         if (ret)
1003                 goto err0;
1004
1005         ret = dwc3_core_get_phy(dwc);
1006         if (ret)
1007                 goto err0;
1008
1009         spin_lock_init(&dwc->lock);
1010
1011         if (!dev->dma_mask) {
1012                 dev->dma_mask = dev->parent->dma_mask;
1013                 dev->dma_parms = dev->parent->dma_parms;
1014                 dma_set_coherent_mask(dev, dev->parent->coherent_dma_mask);
1015         }
1016
1017         pm_runtime_enable(dev);
1018         pm_runtime_get_sync(dev);
1019         pm_runtime_forbid(dev);
1020
1021         ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE);
1022         if (ret) {
1023                 dev_err(dwc->dev, "failed to allocate event buffers\n");
1024                 ret = -ENOMEM;
1025                 goto err1;
1026         }
1027
1028         if (IS_ENABLED(CONFIG_USB_DWC3_HOST))
1029                 dwc->dr_mode = USB_DR_MODE_HOST;
1030         else if (IS_ENABLED(CONFIG_USB_DWC3_GADGET))
1031                 dwc->dr_mode = USB_DR_MODE_PERIPHERAL;
1032
1033         if (dwc->dr_mode == USB_DR_MODE_UNKNOWN)
1034                 dwc->dr_mode = USB_DR_MODE_OTG;
1035
1036         ret = dwc3_core_init(dwc);
1037         if (ret) {
1038                 dev_err(dev, "failed to initialize core\n");
1039                 goto err1;
1040         }
1041
1042         /* Adjust Frame Length */
1043         dwc3_frame_length_adjustment(dwc, fladj);
1044
1045         usb_phy_set_suspend(dwc->usb2_phy, 0);
1046         usb_phy_set_suspend(dwc->usb3_phy, 0);
1047         ret = phy_power_on(dwc->usb2_generic_phy);
1048         if (ret < 0)
1049                 goto err2;
1050
1051         ret = phy_power_on(dwc->usb3_generic_phy);
1052         if (ret < 0)
1053                 goto err3;
1054
1055         ret = dwc3_event_buffers_setup(dwc);
1056         if (ret) {
1057                 dev_err(dwc->dev, "failed to setup event buffers\n");
1058                 goto err4;
1059         }
1060
1061         ret = dwc3_core_init_mode(dwc);
1062         if (ret)
1063                 goto err5;
1064
1065         ret = dwc3_debugfs_init(dwc);
1066         if (ret) {
1067                 dev_err(dev, "failed to initialize debugfs\n");
1068                 goto err6;
1069         }
1070
1071         pm_runtime_allow(dev);
1072
1073         return 0;
1074
1075 err6:
1076         dwc3_core_exit_mode(dwc);
1077
1078 err5:
1079         dwc3_event_buffers_cleanup(dwc);
1080
1081 err4:
1082         phy_power_off(dwc->usb3_generic_phy);
1083
1084 err3:
1085         phy_power_off(dwc->usb2_generic_phy);
1086
1087 err2:
1088         usb_phy_set_suspend(dwc->usb2_phy, 1);
1089         usb_phy_set_suspend(dwc->usb3_phy, 1);
1090         dwc3_core_exit(dwc);
1091
1092 err1:
1093         dwc3_free_event_buffers(dwc);
1094         dwc3_ulpi_exit(dwc);
1095
1096 err0:
1097         /*
1098          * restore res->start back to its original value so that, in case the
1099          * probe is deferred, we don't end up getting error in request the
1100          * memory region the next time probe is called.
1101          */
1102         res->start -= DWC3_GLOBALS_REGS_START;
1103
1104         return ret;
1105 }
1106
1107 static int dwc3_remove(struct platform_device *pdev)
1108 {
1109         struct dwc3     *dwc = platform_get_drvdata(pdev);
1110         struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1111
1112         /*
1113          * restore res->start back to its original value so that, in case the
1114          * probe is deferred, we don't end up getting error in request the
1115          * memory region the next time probe is called.
1116          */
1117         res->start -= DWC3_GLOBALS_REGS_START;
1118
1119         dwc3_debugfs_exit(dwc);
1120         dwc3_core_exit_mode(dwc);
1121         dwc3_event_buffers_cleanup(dwc);
1122         dwc3_free_event_buffers(dwc);
1123
1124         usb_phy_set_suspend(dwc->usb2_phy, 1);
1125         usb_phy_set_suspend(dwc->usb3_phy, 1);
1126         phy_power_off(dwc->usb2_generic_phy);
1127         phy_power_off(dwc->usb3_generic_phy);
1128
1129         dwc3_core_exit(dwc);
1130         dwc3_ulpi_exit(dwc);
1131
1132         pm_runtime_put_sync(&pdev->dev);
1133         pm_runtime_disable(&pdev->dev);
1134
1135         return 0;
1136 }
1137
1138 #ifdef CONFIG_PM_SLEEP
1139 static int dwc3_suspend(struct device *dev)
1140 {
1141         struct dwc3     *dwc = dev_get_drvdata(dev);
1142         unsigned long   flags;
1143
1144         spin_lock_irqsave(&dwc->lock, flags);
1145
1146         switch (dwc->dr_mode) {
1147         case USB_DR_MODE_PERIPHERAL:
1148         case USB_DR_MODE_OTG:
1149                 dwc3_gadget_suspend(dwc);
1150                 /* FALLTHROUGH */
1151         case USB_DR_MODE_HOST:
1152         default:
1153                 dwc3_event_buffers_cleanup(dwc);
1154                 break;
1155         }
1156
1157         dwc->gctl = dwc3_readl(dwc->regs, DWC3_GCTL);
1158         spin_unlock_irqrestore(&dwc->lock, flags);
1159
1160         usb_phy_shutdown(dwc->usb3_phy);
1161         usb_phy_shutdown(dwc->usb2_phy);
1162         phy_exit(dwc->usb2_generic_phy);
1163         phy_exit(dwc->usb3_generic_phy);
1164
1165         pinctrl_pm_select_sleep_state(dev);
1166
1167         return 0;
1168 }
1169
1170 static int dwc3_resume(struct device *dev)
1171 {
1172         struct dwc3     *dwc = dev_get_drvdata(dev);
1173         unsigned long   flags;
1174         int             ret;
1175
1176         pinctrl_pm_select_default_state(dev);
1177
1178         usb_phy_init(dwc->usb3_phy);
1179         usb_phy_init(dwc->usb2_phy);
1180         ret = phy_init(dwc->usb2_generic_phy);
1181         if (ret < 0)
1182                 return ret;
1183
1184         ret = phy_init(dwc->usb3_generic_phy);
1185         if (ret < 0)
1186                 goto err_usb2phy_init;
1187
1188         spin_lock_irqsave(&dwc->lock, flags);
1189
1190         dwc3_event_buffers_setup(dwc);
1191         dwc3_writel(dwc->regs, DWC3_GCTL, dwc->gctl);
1192
1193         switch (dwc->dr_mode) {
1194         case USB_DR_MODE_PERIPHERAL:
1195         case USB_DR_MODE_OTG:
1196                 dwc3_gadget_resume(dwc);
1197                 /* FALLTHROUGH */
1198         case USB_DR_MODE_HOST:
1199         default:
1200                 /* do nothing */
1201                 break;
1202         }
1203
1204         spin_unlock_irqrestore(&dwc->lock, flags);
1205
1206         pm_runtime_disable(dev);
1207         pm_runtime_set_active(dev);
1208         pm_runtime_enable(dev);
1209
1210         return 0;
1211
1212 err_usb2phy_init:
1213         phy_exit(dwc->usb2_generic_phy);
1214
1215         return ret;
1216 }
1217
1218 static const struct dev_pm_ops dwc3_dev_pm_ops = {
1219         SET_SYSTEM_SLEEP_PM_OPS(dwc3_suspend, dwc3_resume)
1220 };
1221
1222 #define DWC3_PM_OPS     &(dwc3_dev_pm_ops)
1223 #else
1224 #define DWC3_PM_OPS     NULL
1225 #endif
1226
1227 #ifdef CONFIG_OF
1228 static const struct of_device_id of_dwc3_match[] = {
1229         {
1230                 .compatible = "snps,dwc3"
1231         },
1232         {
1233                 .compatible = "synopsys,dwc3"
1234         },
1235         { },
1236 };
1237 MODULE_DEVICE_TABLE(of, of_dwc3_match);
1238 #endif
1239
1240 #ifdef CONFIG_ACPI
1241
1242 #define ACPI_ID_INTEL_BSW       "808622B7"
1243
1244 static const struct acpi_device_id dwc3_acpi_match[] = {
1245         { ACPI_ID_INTEL_BSW, 0 },
1246         { },
1247 };
1248 MODULE_DEVICE_TABLE(acpi, dwc3_acpi_match);
1249 #endif
1250
1251 static struct platform_driver dwc3_driver = {
1252         .probe          = dwc3_probe,
1253         .remove         = dwc3_remove,
1254         .driver         = {
1255                 .name   = "dwc3",
1256                 .of_match_table = of_match_ptr(of_dwc3_match),
1257                 .acpi_match_table = ACPI_PTR(dwc3_acpi_match),
1258                 .pm     = DWC3_PM_OPS,
1259         },
1260 };
1261
1262 module_platform_driver(dwc3_driver);
1263
1264 MODULE_ALIAS("platform:dwc3");
1265 MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
1266 MODULE_LICENSE("GPL v2");
1267 MODULE_DESCRIPTION("DesignWare USB3 DRD Controller Driver");