2 * Rockchip USB2.0 PHY with Innosilicon IP block driver
4 * Copyright (C) 2016 Fuzhou Rockchip Electronics Co., Ltd
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
17 #include <linux/clk.h>
18 #include <linux/clk-provider.h>
19 #include <linux/delay.h>
20 #include <linux/extcon.h>
21 #include <linux/interrupt.h>
23 #include <linux/gpio/consumer.h>
24 #include <linux/jiffies.h>
25 #include <linux/kernel.h>
26 #include <linux/module.h>
27 #include <linux/mutex.h>
29 #include <linux/of_address.h>
30 #include <linux/of_irq.h>
31 #include <linux/of_platform.h>
32 #include <linux/phy/phy.h>
33 #include <linux/platform_device.h>
34 #include <linux/power_supply.h>
35 #include <linux/regmap.h>
36 #include <linux/mfd/syscon.h>
37 #include <linux/usb/of.h>
38 #include <linux/usb/otg.h>
39 #include <linux/wakelock.h>
41 #define BIT_WRITEABLE_SHIFT 16
42 #define SCHEDULE_DELAY (60 * HZ)
43 #define OTG_SCHEDULE_DELAY (2 * HZ)
45 struct rockchip_usb2phy;
47 enum rockchip_usb2phy_port_id {
53 enum rockchip_usb2phy_host_state {
54 PHY_STATE_HS_ONLINE = 0,
55 PHY_STATE_DISCONNECT = 1,
56 PHY_STATE_CONNECT = 2,
57 PHY_STATE_FS_LS_ONLINE = 4,
61 * Different states involved in USB charger detection.
62 * USB_CHG_STATE_UNDEFINED USB charger is not connected or detection
63 * process is not yet started.
64 * USB_CHG_STATE_WAIT_FOR_DCD Waiting for Data pins contact.
65 * USB_CHG_STATE_DCD_DONE Data pin contact is detected.
66 * USB_CHG_STATE_PRIMARY_DONE Primary detection is completed (Detects
67 * between SDP and DCP/CDP).
68 * USB_CHG_STATE_SECONDARY_DONE Secondary detection is completed (Detects
69 * between DCP and CDP).
70 * USB_CHG_STATE_DETECTED USB charger type is determined.
73 USB_CHG_STATE_UNDEFINED = 0,
74 USB_CHG_STATE_WAIT_FOR_DCD,
75 USB_CHG_STATE_DCD_DONE,
76 USB_CHG_STATE_PRIMARY_DONE,
77 USB_CHG_STATE_SECONDARY_DONE,
78 USB_CHG_STATE_DETECTED,
81 static const unsigned int rockchip_usb2phy_extcon_cable[] = {
95 unsigned int bitstart;
101 * struct rockchip_chg_det_reg: usb charger detect registers
102 * @cp_det: charging port detected successfully.
103 * @dcp_det: dedicated charging port detected successfully.
104 * @dp_det: assert data pin connect successfully.
105 * @idm_sink_en: open dm sink curren.
106 * @idp_sink_en: open dp sink current.
107 * @idp_src_en: open dm source current.
108 * @rdm_pdwn_en: open dm pull down resistor.
109 * @vdm_src_en: open dm voltage source.
110 * @vdp_src_en: open dp voltage source.
111 * @opmode: utmi operational mode.
113 struct rockchip_chg_det_reg {
114 struct usb2phy_reg cp_det;
115 struct usb2phy_reg dcp_det;
116 struct usb2phy_reg dp_det;
117 struct usb2phy_reg idm_sink_en;
118 struct usb2phy_reg idp_sink_en;
119 struct usb2phy_reg idp_src_en;
120 struct usb2phy_reg rdm_pdwn_en;
121 struct usb2phy_reg vdm_src_en;
122 struct usb2phy_reg vdp_src_en;
123 struct usb2phy_reg opmode;
127 * struct rockchip_usb2phy_port_cfg: usb-phy port configuration.
128 * @phy_sus: phy suspend register.
129 * @bvalid_det_en: vbus valid rise detection enable register.
130 * @bvalid_det_st: vbus valid rise detection status register.
131 * @bvalid_det_clr: vbus valid rise detection clear register.
132 * @ls_det_en: linestate detection enable register.
133 * @ls_det_st: linestate detection state register.
134 * @ls_det_clr: linestate detection clear register.
135 * @idfall_det_en: id fall detection enable register.
136 * @idfall_det_st: id fall detection state register.
137 * @idfall_det_clr: id fall detection clear register.
138 * @idrise_det_en: id rise detection enable register.
139 * @idrise_det_st: id rise detection state register.
140 * @idrise_det_clr: id rise detection clear register.
141 * @utmi_avalid: utmi vbus avalid status register.
142 * @utmi_bvalid: utmi vbus bvalid status register.
143 * @utmi_iddig: otg port id pin status register.
144 * @utmi_ls: utmi linestate state register.
145 * @utmi_hstdet: utmi host disconnect register.
147 struct rockchip_usb2phy_port_cfg {
148 struct usb2phy_reg phy_sus;
149 struct usb2phy_reg bvalid_det_en;
150 struct usb2phy_reg bvalid_det_st;
151 struct usb2phy_reg bvalid_det_clr;
152 struct usb2phy_reg ls_det_en;
153 struct usb2phy_reg ls_det_st;
154 struct usb2phy_reg ls_det_clr;
155 struct usb2phy_reg idfall_det_en;
156 struct usb2phy_reg idfall_det_st;
157 struct usb2phy_reg idfall_det_clr;
158 struct usb2phy_reg idrise_det_en;
159 struct usb2phy_reg idrise_det_st;
160 struct usb2phy_reg idrise_det_clr;
161 struct usb2phy_reg utmi_avalid;
162 struct usb2phy_reg utmi_bvalid;
163 struct usb2phy_reg utmi_iddig;
164 struct usb2phy_reg utmi_ls;
165 struct usb2phy_reg utmi_hstdet;
169 * struct rockchip_usb2phy_cfg: usb-phy configuration.
170 * @reg: the address offset of grf for usb-phy config.
171 * @num_ports: specify how many ports that the phy has.
172 * @phy_tuning: phy default parameters tunning.
173 * @clkout_ctl: keep on/turn off output clk of phy.
174 * @chg_det: charger detection registers.
176 struct rockchip_usb2phy_cfg {
178 unsigned int num_ports;
179 int (*phy_tuning)(struct rockchip_usb2phy *);
180 struct usb2phy_reg clkout_ctl;
181 const struct rockchip_usb2phy_port_cfg port_cfgs[USB2PHY_NUM_PORTS];
182 const struct rockchip_chg_det_reg chg_det;
186 * struct rockchip_usb2phy_port: usb-phy port data.
187 * @port_id: flag for otg port or host port.
188 * @perip_connected: flag for periphyeral connect status.
189 * @suspended: phy suspended flag.
190 * @utmi_avalid: utmi avalid status usage flag.
191 * true - use avalid to get vbus status
192 * flase - use bvalid to get vbus status
193 * @vbus_attached: otg device vbus status.
194 * @bvalid_irq: IRQ number assigned for vbus valid rise detection.
195 * @ls_irq: IRQ number assigned for linestate detection.
196 * @id_irq: IRQ number assigned for id fall or rise detection.
197 * @mutex: for register updating in sm_work.
198 * @chg_work: charge detect work.
199 * @otg_sm_work: OTG state machine work.
200 * @sm_work: HOST state machine work.
201 * @phy_cfg: port register configuration, assigned by driver data.
202 * @event_nb: hold event notification callback.
203 * @wakelock: wake lock struct to prevent system suspend
204 * when USB is active.
205 * @state: define OTG enumeration states before device reset.
206 * @mode: the dr_mode of the controller.
208 struct rockchip_usb2phy_port {
210 unsigned int port_id;
211 bool perip_connected;
219 struct delayed_work chg_work;
220 struct delayed_work otg_sm_work;
221 struct delayed_work sm_work;
222 const struct rockchip_usb2phy_port_cfg *port_cfg;
223 struct notifier_block event_nb;
224 struct wake_lock wakelock;
225 enum usb_otg_state state;
226 enum usb_dr_mode mode;
230 * struct rockchip_usb2phy: usb2.0 phy driver data.
231 * @grf: General Register Files regmap.
232 * @clk: clock struct of phy input clk.
233 * @clk480m: clock struct of phy output clk.
234 * @clk_hw: clock struct of phy output clk management.
235 * @chg_state: states involved in USB charger detection.
236 * @chg_type: USB charger types.
237 * @dcd_retries: The retry count used to track Data contact
239 * @edev_self: represent the source of extcon.
240 * @edev: extcon device for notification registration
241 * @phy_cfg: phy register configuration, assigned by driver data.
242 * @ports: phy port instance.
244 struct rockchip_usb2phy {
249 struct clk_hw clk480m_hw;
250 enum usb_chg_state chg_state;
251 enum power_supply_type chg_type;
255 struct extcon_dev *edev;
256 const struct rockchip_usb2phy_cfg *phy_cfg;
257 struct rockchip_usb2phy_port ports[USB2PHY_NUM_PORTS];
260 static inline int property_enable(struct rockchip_usb2phy *rphy,
261 const struct usb2phy_reg *reg, bool en)
263 unsigned int val, mask, tmp;
265 tmp = en ? reg->enable : reg->disable;
266 mask = GENMASK(reg->bitend, reg->bitstart);
267 val = (tmp << reg->bitstart) | (mask << BIT_WRITEABLE_SHIFT);
269 return regmap_write(rphy->grf, reg->offset, val);
272 static inline bool property_enabled(struct rockchip_usb2phy *rphy,
273 const struct usb2phy_reg *reg)
276 unsigned int tmp, orig;
277 unsigned int mask = GENMASK(reg->bitend, reg->bitstart);
279 ret = regmap_read(rphy->grf, reg->offset, &orig);
283 tmp = (orig & mask) >> reg->bitstart;
284 return tmp == reg->enable;
287 static int rockchip_usb2phy_clk480m_enable(struct clk_hw *hw)
289 struct rockchip_usb2phy *rphy =
290 container_of(hw, struct rockchip_usb2phy, clk480m_hw);
293 /* turn on 480m clk output if it is off */
294 if (!property_enabled(rphy, &rphy->phy_cfg->clkout_ctl)) {
295 ret = property_enable(rphy, &rphy->phy_cfg->clkout_ctl, true);
299 /* waitting for the clk become stable */
306 static void rockchip_usb2phy_clk480m_disable(struct clk_hw *hw)
308 struct rockchip_usb2phy *rphy =
309 container_of(hw, struct rockchip_usb2phy, clk480m_hw);
311 /* turn off 480m clk output */
312 property_enable(rphy, &rphy->phy_cfg->clkout_ctl, false);
315 static int rockchip_usb2phy_clk480m_enabled(struct clk_hw *hw)
317 struct rockchip_usb2phy *rphy =
318 container_of(hw, struct rockchip_usb2phy, clk480m_hw);
320 return property_enabled(rphy, &rphy->phy_cfg->clkout_ctl);
324 rockchip_usb2phy_clk480m_recalc_rate(struct clk_hw *hw,
325 unsigned long parent_rate)
330 static const struct clk_ops rockchip_usb2phy_clkout_ops = {
331 .enable = rockchip_usb2phy_clk480m_enable,
332 .disable = rockchip_usb2phy_clk480m_disable,
333 .is_enabled = rockchip_usb2phy_clk480m_enabled,
334 .recalc_rate = rockchip_usb2phy_clk480m_recalc_rate,
337 static void rockchip_usb2phy_clk480m_unregister(void *data)
339 struct rockchip_usb2phy *rphy = data;
341 of_clk_del_provider(rphy->dev->of_node);
342 clk_unregister(rphy->clk480m);
346 rockchip_usb2phy_clk480m_register(struct rockchip_usb2phy *rphy)
348 struct device_node *node = rphy->dev->of_node;
349 struct clk_init_data init;
350 const char *clk_name;
354 init.name = "clk_usbphy_480m";
355 init.ops = &rockchip_usb2phy_clkout_ops;
357 /* optional override of the clockname */
358 of_property_read_string(node, "clock-output-names", &init.name);
361 clk_name = __clk_get_name(rphy->clk);
362 init.parent_names = &clk_name;
363 init.num_parents = 1;
365 init.parent_names = NULL;
366 init.num_parents = 0;
369 rphy->clk480m_hw.init = &init;
371 /* register the clock */
372 rphy->clk480m = clk_register(rphy->dev, &rphy->clk480m_hw);
373 if (IS_ERR(rphy->clk480m)) {
374 ret = PTR_ERR(rphy->clk480m);
378 ret = of_clk_add_provider(node, of_clk_src_simple_get, rphy->clk480m);
380 goto err_clk_provider;
382 ret = devm_add_action(rphy->dev, rockchip_usb2phy_clk480m_unregister,
385 goto err_unreg_action;
390 of_clk_del_provider(node);
392 clk_unregister(rphy->clk480m);
397 static int rockchip_usb2phy_extcon_register(struct rockchip_usb2phy *rphy)
400 struct device_node *node = rphy->dev->of_node;
401 struct extcon_dev *edev;
403 if (of_property_read_bool(node, "extcon")) {
404 edev = extcon_get_edev_by_phandle(rphy->dev, 0);
406 if (PTR_ERR(edev) != -EPROBE_DEFER)
407 dev_err(rphy->dev, "Invalid or missing extcon\n");
408 return PTR_ERR(edev);
411 /* Initialize extcon device */
412 edev = devm_extcon_dev_allocate(rphy->dev,
413 rockchip_usb2phy_extcon_cable);
418 ret = devm_extcon_dev_register(rphy->dev, edev);
420 dev_err(rphy->dev, "failed to register extcon device\n");
424 rphy->edev_self = true;
432 static int rockchip_usb2phy_init(struct phy *phy)
434 struct rockchip_usb2phy_port *rport = phy_get_drvdata(phy);
435 struct rockchip_usb2phy *rphy = dev_get_drvdata(phy->dev.parent);
438 mutex_lock(&rport->mutex);
440 if (rport->port_id == USB2PHY_PORT_OTG) {
441 if (rport->mode != USB_DR_MODE_HOST) {
442 /* clear bvalid status and enable bvalid detect irq */
443 ret = property_enable(rphy,
450 ret = property_enable(rphy,
457 if (rphy->edev_self) {
458 ret = property_enable(rphy,
465 ret = property_enable(rphy,
472 ret = property_enable(rphy,
479 ret = property_enable(rphy,
487 schedule_delayed_work(&rport->otg_sm_work,
490 /* If OTG works in host only mode, do nothing. */
491 dev_dbg(&rport->phy->dev, "mode %d\n", rport->mode);
493 } else if (rport->port_id == USB2PHY_PORT_HOST) {
494 /* clear linestate and enable linestate detect irq */
495 ret = property_enable(rphy, &rport->port_cfg->ls_det_clr, true);
499 ret = property_enable(rphy, &rport->port_cfg->ls_det_en, true);
503 schedule_delayed_work(&rport->sm_work, SCHEDULE_DELAY);
507 mutex_unlock(&rport->mutex);
511 static int rockchip_usb2phy_power_on(struct phy *phy)
513 struct rockchip_usb2phy_port *rport = phy_get_drvdata(phy);
514 struct rockchip_usb2phy *rphy = dev_get_drvdata(phy->dev.parent);
517 dev_dbg(&rport->phy->dev, "port power on\n");
519 if (!rport->suspended)
522 ret = clk_prepare_enable(rphy->clk480m);
526 ret = property_enable(rphy, &rport->port_cfg->phy_sus, false);
530 rport->suspended = false;
534 static int rockchip_usb2phy_power_off(struct phy *phy)
536 struct rockchip_usb2phy_port *rport = phy_get_drvdata(phy);
537 struct rockchip_usb2phy *rphy = dev_get_drvdata(phy->dev.parent);
540 dev_dbg(&rport->phy->dev, "port power off\n");
542 if (rport->suspended)
545 ret = property_enable(rphy, &rport->port_cfg->phy_sus, true);
549 rport->suspended = true;
550 clk_disable_unprepare(rphy->clk480m);
555 static int rockchip_usb2phy_exit(struct phy *phy)
557 struct rockchip_usb2phy_port *rport = phy_get_drvdata(phy);
559 if (rport->port_id == USB2PHY_PORT_OTG &&
560 rport->mode != USB_DR_MODE_HOST)
561 cancel_delayed_work_sync(&rport->chg_work);
562 else if (rport->port_id == USB2PHY_PORT_HOST)
563 cancel_delayed_work_sync(&rport->sm_work);
568 static const struct phy_ops rockchip_usb2phy_ops = {
569 .init = rockchip_usb2phy_init,
570 .exit = rockchip_usb2phy_exit,
571 .power_on = rockchip_usb2phy_power_on,
572 .power_off = rockchip_usb2phy_power_off,
573 .owner = THIS_MODULE,
576 static void rockchip_usb2phy_otg_sm_work(struct work_struct *work)
578 struct rockchip_usb2phy_port *rport =
579 container_of(work, struct rockchip_usb2phy_port,
581 struct rockchip_usb2phy *rphy = dev_get_drvdata(rport->phy->dev.parent);
582 static unsigned int cable;
586 if (rport->utmi_avalid)
587 rport->vbus_attached =
588 property_enabled(rphy, &rport->port_cfg->utmi_avalid);
590 rport->vbus_attached =
591 property_enabled(rphy, &rport->port_cfg->utmi_bvalid);
594 delay = OTG_SCHEDULE_DELAY;
596 dev_dbg(&rport->phy->dev, "%s otg sm work\n",
597 usb_otg_state_string(rport->state));
599 switch (rport->state) {
600 case OTG_STATE_UNDEFINED:
601 rport->state = OTG_STATE_B_IDLE;
602 if (!rport->vbus_attached)
603 rockchip_usb2phy_power_off(rport->phy);
605 case OTG_STATE_B_IDLE:
606 if (extcon_get_cable_state_(rphy->edev, EXTCON_USB_HOST) > 0 ||
607 extcon_get_cable_state_(rphy->edev,
608 EXTCON_USB_VBUS_EN) > 0) {
609 dev_dbg(&rport->phy->dev, "usb otg host connect\n");
610 rport->state = OTG_STATE_A_HOST;
611 rockchip_usb2phy_power_on(rport->phy);
613 } else if (rport->vbus_attached) {
614 dev_dbg(&rport->phy->dev, "vbus_attach\n");
615 switch (rphy->chg_state) {
616 case USB_CHG_STATE_UNDEFINED:
617 schedule_delayed_work(&rport->chg_work, 0);
619 case USB_CHG_STATE_DETECTED:
620 switch (rphy->chg_type) {
621 case POWER_SUPPLY_TYPE_USB:
622 dev_dbg(&rport->phy->dev,
623 "sdp cable is connecetd\n");
624 wake_lock(&rport->wakelock);
625 cable = EXTCON_CHG_USB_SDP;
626 rockchip_usb2phy_power_on(rport->phy);
627 rport->state = OTG_STATE_B_PERIPHERAL;
628 rport->perip_connected = true;
631 case POWER_SUPPLY_TYPE_USB_DCP:
632 dev_dbg(&rport->phy->dev,
633 "dcp cable is connecetd\n");
634 cable = EXTCON_CHG_USB_DCP;
635 rockchip_usb2phy_power_off(rport->phy);
638 case POWER_SUPPLY_TYPE_USB_CDP:
639 dev_dbg(&rport->phy->dev,
640 "cdp cable is connecetd\n");
641 wake_lock(&rport->wakelock);
642 cable = EXTCON_CHG_USB_CDP;
643 rockchip_usb2phy_power_on(rport->phy);
644 rport->state = OTG_STATE_B_PERIPHERAL;
645 rport->perip_connected = true;
648 case POWER_SUPPLY_TYPE_USB_FLOATING:
649 dev_dbg(&rport->phy->dev,
650 "floating cable is connecetd\n");
651 cable = EXTCON_CHG_USB_SLOW;
652 rockchip_usb2phy_power_off(rport->phy);
663 rphy->chg_state = USB_CHG_STATE_UNDEFINED;
664 rphy->chg_type = POWER_SUPPLY_TYPE_UNKNOWN;
667 case OTG_STATE_B_PERIPHERAL:
668 if (!rport->vbus_attached) {
669 dev_dbg(&rport->phy->dev, "usb disconnect\n");
670 rphy->chg_state = USB_CHG_STATE_UNDEFINED;
671 rphy->chg_type = POWER_SUPPLY_TYPE_UNKNOWN;
672 rport->state = OTG_STATE_B_IDLE;
673 rport->perip_connected = false;
675 rockchip_usb2phy_power_off(rport->phy);
676 wake_unlock(&rport->wakelock);
681 case OTG_STATE_A_HOST:
682 if (extcon_get_cable_state_(rphy->edev, EXTCON_USB_HOST) == 0) {
683 dev_dbg(&rport->phy->dev, "usb otg host disconnect\n");
684 rport->state = OTG_STATE_B_IDLE;
685 rockchip_usb2phy_power_off(rport->phy);
692 if (extcon_get_state(rphy->edev, cable) != rport->vbus_attached)
693 extcon_set_cable_state_(rphy->edev,
694 cable, rport->vbus_attached);
696 if (rphy->edev_self &&
697 (extcon_get_state(rphy->edev, EXTCON_USB) !=
698 rport->perip_connected))
699 extcon_set_cable_state_(rphy->edev,
701 rport->perip_connected);
704 schedule_delayed_work(&rport->otg_sm_work, delay);
707 static const char *chg_to_string(enum power_supply_type chg_type)
710 case POWER_SUPPLY_TYPE_USB:
711 return "USB_SDP_CHARGER";
712 case POWER_SUPPLY_TYPE_USB_DCP:
713 return "USB_DCP_CHARGER";
714 case POWER_SUPPLY_TYPE_USB_CDP:
715 return "USB_CDP_CHARGER";
716 case POWER_SUPPLY_TYPE_USB_FLOATING:
717 return "USB_FLOATING_CHARGER";
719 return "INVALID_CHARGER";
723 static void rockchip_chg_enable_dcd(struct rockchip_usb2phy *rphy,
726 property_enable(rphy, &rphy->phy_cfg->chg_det.rdm_pdwn_en, en);
727 property_enable(rphy, &rphy->phy_cfg->chg_det.idp_src_en, en);
730 static void rockchip_chg_enable_primary_det(struct rockchip_usb2phy *rphy,
733 property_enable(rphy, &rphy->phy_cfg->chg_det.vdp_src_en, en);
734 property_enable(rphy, &rphy->phy_cfg->chg_det.idm_sink_en, en);
737 static void rockchip_chg_enable_secondary_det(struct rockchip_usb2phy *rphy,
740 property_enable(rphy, &rphy->phy_cfg->chg_det.vdm_src_en, en);
741 property_enable(rphy, &rphy->phy_cfg->chg_det.idp_sink_en, en);
744 #define CHG_DCD_POLL_TIME (100 * HZ / 1000)
745 #define CHG_DCD_MAX_RETRIES 6
746 #define CHG_PRIMARY_DET_TIME (40 * HZ / 1000)
747 #define CHG_SECONDARY_DET_TIME (40 * HZ / 1000)
748 static void rockchip_chg_detect_work(struct work_struct *work)
750 struct rockchip_usb2phy_port *rport =
751 container_of(work, struct rockchip_usb2phy_port, chg_work.work);
752 struct rockchip_usb2phy *rphy = dev_get_drvdata(rport->phy->dev.parent);
753 bool is_dcd, tmout, vout;
756 dev_dbg(&rport->phy->dev, "chg detection work state = %d\n",
758 switch (rphy->chg_state) {
759 case USB_CHG_STATE_UNDEFINED:
760 if (!rport->suspended)
761 rockchip_usb2phy_power_off(rport->phy);
762 /* put the controller in non-driving mode */
763 property_enable(rphy, &rphy->phy_cfg->chg_det.opmode, false);
764 /* Start DCD processing stage 1 */
765 rockchip_chg_enable_dcd(rphy, true);
766 rphy->chg_state = USB_CHG_STATE_WAIT_FOR_DCD;
767 rphy->dcd_retries = 0;
768 rphy->primary_retries = 0;
769 delay = CHG_DCD_POLL_TIME;
771 case USB_CHG_STATE_WAIT_FOR_DCD:
772 /* get data contact detection status */
773 is_dcd = property_enabled(rphy, &rphy->phy_cfg->chg_det.dp_det);
774 tmout = ++rphy->dcd_retries == CHG_DCD_MAX_RETRIES;
776 if (is_dcd || tmout) {
778 /* Turn off DCD circuitry */
779 rockchip_chg_enable_dcd(rphy, false);
780 /* Voltage Source on DP, Probe on DM */
781 rockchip_chg_enable_primary_det(rphy, true);
782 delay = CHG_PRIMARY_DET_TIME;
783 rphy->chg_state = USB_CHG_STATE_DCD_DONE;
786 delay = CHG_DCD_POLL_TIME;
789 case USB_CHG_STATE_DCD_DONE:
790 vout = property_enabled(rphy, &rphy->phy_cfg->chg_det.cp_det);
791 rockchip_chg_enable_primary_det(rphy, false);
793 /* Voltage Source on DM, Probe on DP */
794 rockchip_chg_enable_secondary_det(rphy, true);
795 delay = CHG_SECONDARY_DET_TIME;
796 rphy->chg_state = USB_CHG_STATE_PRIMARY_DONE;
799 /* floating charger found */
800 rphy->chg_type = POWER_SUPPLY_TYPE_USB_FLOATING;
801 rphy->chg_state = USB_CHG_STATE_DETECTED;
804 if (rphy->primary_retries < 2) {
805 /* Turn off DCD circuitry */
806 rockchip_chg_enable_dcd(rphy, false);
807 /* Voltage Source on DP, Probe on DM */
808 rockchip_chg_enable_primary_det(rphy,
810 delay = CHG_PRIMARY_DET_TIME;
812 USB_CHG_STATE_DCD_DONE;
813 rphy->primary_retries++;
814 /* break USB_CHG_STATE_DCD_DONE */
817 rphy->chg_type = POWER_SUPPLY_TYPE_USB;
818 rphy->chg_state = USB_CHG_STATE_DETECTED;
823 case USB_CHG_STATE_PRIMARY_DONE:
824 vout = property_enabled(rphy, &rphy->phy_cfg->chg_det.dcp_det);
825 /* Turn off voltage source */
826 rockchip_chg_enable_secondary_det(rphy, false);
828 rphy->chg_type = POWER_SUPPLY_TYPE_USB_DCP;
830 rphy->chg_type = POWER_SUPPLY_TYPE_USB_CDP;
832 case USB_CHG_STATE_SECONDARY_DONE:
833 rphy->chg_state = USB_CHG_STATE_DETECTED;
836 case USB_CHG_STATE_DETECTED:
837 /* put the controller in normal mode */
838 property_enable(rphy, &rphy->phy_cfg->chg_det.opmode, true);
839 rockchip_usb2phy_otg_sm_work(&rport->otg_sm_work.work);
840 dev_info(&rport->phy->dev, "charger = %s\n",
841 chg_to_string(rphy->chg_type));
847 schedule_delayed_work(&rport->chg_work, delay);
851 * The function manage host-phy port state and suspend/resume phy port
854 * we rely on utmi_linestate and utmi_hostdisconnect to identify whether
855 * devices is disconnect or not. Besides, we do not need care it is FS/LS
856 * disconnected or HS disconnected, actually, we just only need get the
857 * device is disconnected at last through rearm the delayed work,
858 * to suspend the phy port in _PHY_STATE_DISCONNECT_ case.
860 * NOTE: It may invoke *phy_powr_off or *phy_power_on which will invoke
861 * some clk related APIs, so do not invoke it from interrupt context directly.
863 static void rockchip_usb2phy_sm_work(struct work_struct *work)
865 struct rockchip_usb2phy_port *rport =
866 container_of(work, struct rockchip_usb2phy_port, sm_work.work);
867 struct rockchip_usb2phy *rphy = dev_get_drvdata(rport->phy->dev.parent);
868 unsigned int sh = rport->port_cfg->utmi_hstdet.bitend -
869 rport->port_cfg->utmi_hstdet.bitstart + 1;
870 unsigned int ul, uhd, state;
871 unsigned int ul_mask, uhd_mask;
874 mutex_lock(&rport->mutex);
876 ret = regmap_read(rphy->grf, rport->port_cfg->utmi_ls.offset, &ul);
880 ret = regmap_read(rphy->grf, rport->port_cfg->utmi_hstdet.offset,
885 uhd_mask = GENMASK(rport->port_cfg->utmi_hstdet.bitend,
886 rport->port_cfg->utmi_hstdet.bitstart);
887 ul_mask = GENMASK(rport->port_cfg->utmi_ls.bitend,
888 rport->port_cfg->utmi_ls.bitstart);
890 /* stitch on utmi_ls and utmi_hstdet as phy state */
891 state = ((uhd & uhd_mask) >> rport->port_cfg->utmi_hstdet.bitstart) |
892 (((ul & ul_mask) >> rport->port_cfg->utmi_ls.bitstart) << sh);
895 case PHY_STATE_HS_ONLINE:
896 dev_dbg(&rport->phy->dev, "HS online\n");
898 case PHY_STATE_FS_LS_ONLINE:
900 * For FS/LS device, the online state share with connect state
901 * from utmi_ls and utmi_hstdet register, so we distinguish
902 * them via suspended flag.
904 * Plus, there are two cases, one is D- Line pull-up, and D+
905 * line pull-down, the state is 4; another is D+ line pull-up,
906 * and D- line pull-down, the state is 2.
908 if (!rport->suspended) {
909 /* D- line pull-up, D+ line pull-down */
910 dev_dbg(&rport->phy->dev, "FS/LS online\n");
914 case PHY_STATE_CONNECT:
915 if (rport->suspended) {
916 dev_dbg(&rport->phy->dev, "Connected\n");
917 rockchip_usb2phy_power_on(rport->phy);
918 rport->suspended = false;
920 /* D+ line pull-up, D- line pull-down */
921 dev_dbg(&rport->phy->dev, "FS/LS online\n");
924 case PHY_STATE_DISCONNECT:
925 if (!rport->suspended) {
926 dev_dbg(&rport->phy->dev, "Disconnected\n");
927 rockchip_usb2phy_power_off(rport->phy);
928 rport->suspended = true;
932 * activate the linestate detection to get the next device
935 property_enable(rphy, &rport->port_cfg->ls_det_clr, true);
936 property_enable(rphy, &rport->port_cfg->ls_det_en, true);
939 * we don't need to rearm the delayed work when the phy port
942 mutex_unlock(&rport->mutex);
945 dev_dbg(&rport->phy->dev, "unknown phy state\n");
950 mutex_unlock(&rport->mutex);
951 schedule_delayed_work(&rport->sm_work, SCHEDULE_DELAY);
954 static irqreturn_t rockchip_usb2phy_linestate_irq(int irq, void *data)
956 struct rockchip_usb2phy_port *rport = data;
957 struct rockchip_usb2phy *rphy = dev_get_drvdata(rport->phy->dev.parent);
959 if (!property_enabled(rphy, &rport->port_cfg->ls_det_st))
962 mutex_lock(&rport->mutex);
964 /* disable linestate detect irq and clear its status */
965 property_enable(rphy, &rport->port_cfg->ls_det_en, false);
966 property_enable(rphy, &rport->port_cfg->ls_det_clr, true);
968 mutex_unlock(&rport->mutex);
971 * In this case for host phy port, a new device is plugged in,
972 * meanwhile, if the phy port is suspended, we need rearm the work to
973 * resume it and mange its states; otherwise, we do nothing about that.
975 if (rport->suspended && rport->port_id == USB2PHY_PORT_HOST)
976 rockchip_usb2phy_sm_work(&rport->sm_work.work);
981 static irqreturn_t rockchip_usb2phy_bvalid_irq(int irq, void *data)
983 struct rockchip_usb2phy_port *rport = data;
984 struct rockchip_usb2phy *rphy = dev_get_drvdata(rport->phy->dev.parent);
986 if (!property_enabled(rphy, &rport->port_cfg->bvalid_det_st))
989 mutex_lock(&rport->mutex);
991 /* clear bvalid detect irq pending status */
992 property_enable(rphy, &rport->port_cfg->bvalid_det_clr, true);
994 mutex_unlock(&rport->mutex);
996 rockchip_usb2phy_otg_sm_work(&rport->otg_sm_work.work);
1001 static irqreturn_t rockchip_usb2phy_id_irq(int irq, void *data)
1003 struct rockchip_usb2phy_port *rport = data;
1004 struct rockchip_usb2phy *rphy = dev_get_drvdata(rport->phy->dev.parent);
1006 if (!property_enabled(rphy, &rport->port_cfg->idfall_det_st) &&
1007 !property_enabled(rphy, &rport->port_cfg->idrise_det_st))
1010 mutex_lock(&rport->mutex);
1012 /* clear id fall or rise detect irq pending status */
1013 if (property_enabled(rphy, &rport->port_cfg->idfall_det_st)) {
1014 property_enable(rphy, &rport->port_cfg->idfall_det_clr,
1016 extcon_set_state(rphy->edev, EXTCON_USB_HOST, true);
1017 extcon_set_state(rphy->edev, EXTCON_USB_VBUS_EN, true);
1018 } else if (property_enabled(rphy, &rport->port_cfg->idrise_det_st)) {
1019 property_enable(rphy, &rport->port_cfg->idrise_det_clr,
1021 extcon_set_state(rphy->edev, EXTCON_USB_HOST, false);
1022 extcon_set_state(rphy->edev, EXTCON_USB_VBUS_EN, false);
1025 extcon_sync(rphy->edev, EXTCON_USB_HOST);
1026 extcon_sync(rphy->edev, EXTCON_USB_VBUS_EN);
1028 mutex_unlock(&rport->mutex);
1033 static int rockchip_usb2phy_host_port_init(struct rockchip_usb2phy *rphy,
1034 struct rockchip_usb2phy_port *rport,
1035 struct device_node *child_np)
1039 rport->port_id = USB2PHY_PORT_HOST;
1040 rport->port_cfg = &rphy->phy_cfg->port_cfgs[USB2PHY_PORT_HOST];
1041 rport->suspended = true;
1043 mutex_init(&rport->mutex);
1044 INIT_DELAYED_WORK(&rport->sm_work, rockchip_usb2phy_sm_work);
1046 rport->ls_irq = of_irq_get_byname(child_np, "linestate");
1047 if (rport->ls_irq < 0) {
1048 dev_err(rphy->dev, "no linestate irq provided\n");
1049 return rport->ls_irq;
1052 ret = devm_request_threaded_irq(rphy->dev, rport->ls_irq, NULL,
1053 rockchip_usb2phy_linestate_irq,
1055 "rockchip_usb2phy", rport);
1057 dev_err(rphy->dev, "failed to request linestate irq handle\n");
1064 static int rockchip_otg_event(struct notifier_block *nb,
1065 unsigned long event, void *ptr)
1067 struct rockchip_usb2phy_port *rport =
1068 container_of(nb, struct rockchip_usb2phy_port, event_nb);
1070 schedule_delayed_work(&rport->otg_sm_work, OTG_SCHEDULE_DELAY);
1075 static int rockchip_usb2phy_otg_port_init(struct rockchip_usb2phy *rphy,
1076 struct rockchip_usb2phy_port *rport,
1077 struct device_node *child_np)
1082 rport->port_id = USB2PHY_PORT_OTG;
1083 rport->port_cfg = &rphy->phy_cfg->port_cfgs[USB2PHY_PORT_OTG];
1084 rport->state = OTG_STATE_UNDEFINED;
1087 * set suspended flag to true, but actually don't
1088 * put phy in suspend mode, it aims to enable usb
1089 * phy and clock in power_on() called by usb controller
1090 * driver during probe.
1092 rport->suspended = true;
1093 rport->vbus_attached = false;
1094 rport->perip_connected = false;
1096 mutex_init(&rport->mutex);
1098 rport->mode = of_usb_get_dr_mode_by_phy(child_np, -1);
1099 if (rport->mode == USB_DR_MODE_HOST)
1102 wake_lock_init(&rport->wakelock, WAKE_LOCK_SUSPEND, "rockchip_otg");
1103 INIT_DELAYED_WORK(&rport->chg_work, rockchip_chg_detect_work);
1104 INIT_DELAYED_WORK(&rport->otg_sm_work, rockchip_usb2phy_otg_sm_work);
1106 rport->utmi_avalid =
1107 of_property_read_bool(child_np, "rockchip,utmi-avalid");
1109 rport->bvalid_irq = of_irq_get_byname(child_np, "otg-bvalid");
1110 if (rport->bvalid_irq < 0) {
1111 dev_err(rphy->dev, "no vbus valid irq provided\n");
1112 return rport->bvalid_irq;
1115 ret = devm_request_threaded_irq(rphy->dev, rport->bvalid_irq, NULL,
1116 rockchip_usb2phy_bvalid_irq,
1118 "rockchip_usb2phy_bvalid", rport);
1120 dev_err(rphy->dev, "failed to request otg-bvalid irq handle\n");
1124 if (rphy->edev_self) {
1125 rport->id_irq = of_irq_get_byname(child_np, "otg-id");
1126 if (rport->id_irq < 0) {
1127 dev_err(rphy->dev, "no otg id irq provided\n");
1128 return rport->id_irq;
1131 ret = devm_request_threaded_irq(rphy->dev, rport->id_irq, NULL,
1132 rockchip_usb2phy_id_irq,
1134 "rockchip_usb2phy_id", rport);
1136 dev_err(rphy->dev, "failed to request otg-id irq handle\n");
1140 iddig = property_enabled(rphy, &rport->port_cfg->utmi_iddig);
1142 extcon_set_state(rphy->edev, EXTCON_USB, false);
1143 extcon_set_state(rphy->edev, EXTCON_USB_HOST, true);
1144 extcon_set_state(rphy->edev, EXTCON_USB_VBUS_EN, true);
1146 extcon_set_state(rphy->edev, EXTCON_USB_HOST, false);
1147 extcon_set_state(rphy->edev, EXTCON_USB_VBUS_EN, false);
1151 if (!IS_ERR(rphy->edev)) {
1152 rport->event_nb.notifier_call = rockchip_otg_event;
1154 ret = extcon_register_notifier(rphy->edev, EXTCON_USB_HOST,
1157 dev_err(rphy->dev, "register USB HOST notifier failed\n");
1165 static int rockchip_usb2phy_probe(struct platform_device *pdev)
1167 struct device *dev = &pdev->dev;
1168 struct device_node *np = dev->of_node;
1169 struct device_node *child_np;
1170 struct phy_provider *provider;
1171 struct rockchip_usb2phy *rphy;
1172 const struct rockchip_usb2phy_cfg *phy_cfgs;
1173 const struct of_device_id *match;
1177 rphy = devm_kzalloc(dev, sizeof(*rphy), GFP_KERNEL);
1181 match = of_match_device(dev->driver->of_match_table, dev);
1182 if (!match || !match->data) {
1183 dev_err(dev, "phy configs are not assigned!\n");
1187 if (!dev->parent || !dev->parent->of_node)
1190 rphy->grf = syscon_node_to_regmap(dev->parent->of_node);
1191 if (IS_ERR(rphy->grf))
1192 return PTR_ERR(rphy->grf);
1194 if (of_property_read_u32(np, "reg", ®)) {
1195 dev_err(dev, "the reg property is not assigned in %s node\n",
1201 phy_cfgs = match->data;
1202 rphy->chg_state = USB_CHG_STATE_UNDEFINED;
1203 rphy->chg_type = POWER_SUPPLY_TYPE_UNKNOWN;
1204 rphy->edev_self = false;
1205 platform_set_drvdata(pdev, rphy);
1207 ret = rockchip_usb2phy_extcon_register(rphy);
1211 /* find out a proper config which can be matched with dt. */
1213 while (phy_cfgs[index].reg) {
1214 if (phy_cfgs[index].reg == reg) {
1215 rphy->phy_cfg = &phy_cfgs[index];
1222 if (!rphy->phy_cfg) {
1223 dev_err(dev, "no phy-config can be matched with %s node\n",
1228 rphy->clk = of_clk_get_by_name(np, "phyclk");
1229 if (!IS_ERR(rphy->clk)) {
1230 clk_prepare_enable(rphy->clk);
1232 dev_info(&pdev->dev, "no phyclk specified\n");
1236 ret = rockchip_usb2phy_clk480m_register(rphy);
1238 dev_err(dev, "failed to register 480m output clock\n");
1242 if (rphy->phy_cfg->phy_tuning) {
1243 ret = rphy->phy_cfg->phy_tuning(rphy);
1249 for_each_available_child_of_node(np, child_np) {
1250 struct rockchip_usb2phy_port *rport = &rphy->ports[index];
1253 /* This driver aims to support both otg-port and host-port */
1254 if (of_node_cmp(child_np->name, "host-port") &&
1255 of_node_cmp(child_np->name, "otg-port"))
1258 phy = devm_phy_create(dev, child_np, &rockchip_usb2phy_ops);
1260 dev_err(dev, "failed to create phy\n");
1266 phy_set_drvdata(rport->phy, rport);
1268 /* initialize otg/host port separately */
1269 if (!of_node_cmp(child_np->name, "host-port")) {
1270 ret = rockchip_usb2phy_host_port_init(rphy, rport,
1275 ret = rockchip_usb2phy_otg_port_init(rphy, rport,
1282 /* to prevent out of boundary */
1283 if (++index >= rphy->phy_cfg->num_ports)
1287 provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
1288 return PTR_ERR_OR_ZERO(provider);
1291 of_node_put(child_np);
1294 clk_disable_unprepare(rphy->clk);
1300 static int rk3366_usb2phy_tuning(struct rockchip_usb2phy *rphy)
1302 unsigned int open_pre_emphasize = 0xffff851f;
1303 unsigned int eye_height_tuning = 0xffff68c8;
1304 unsigned int compensation_tuning = 0xffff026e;
1307 /* open HS pre-emphasize to expand HS slew rate for each port. */
1308 ret |= regmap_write(rphy->grf, 0x0780, open_pre_emphasize);
1309 ret |= regmap_write(rphy->grf, 0x079c, eye_height_tuning);
1310 ret |= regmap_write(rphy->grf, 0x07b0, open_pre_emphasize);
1311 ret |= regmap_write(rphy->grf, 0x07cc, eye_height_tuning);
1313 /* compensate default tuning reference relate to ODT and etc. */
1314 ret |= regmap_write(rphy->grf, 0x078c, compensation_tuning);
1319 static const struct rockchip_usb2phy_cfg rk3366_phy_cfgs[] = {
1323 .phy_tuning = rk3366_usb2phy_tuning,
1324 .clkout_ctl = { 0x0724, 15, 15, 1, 0 },
1326 [USB2PHY_PORT_HOST] = {
1327 .phy_sus = { 0x0728, 15, 0, 0, 0x1d1 },
1328 .ls_det_en = { 0x0680, 4, 4, 0, 1 },
1329 .ls_det_st = { 0x0690, 4, 4, 0, 1 },
1330 .ls_det_clr = { 0x06a0, 4, 4, 0, 1 },
1331 .utmi_ls = { 0x049c, 14, 13, 0, 1 },
1332 .utmi_hstdet = { 0x049c, 12, 12, 0, 1 }
1339 static const struct rockchip_usb2phy_cfg rk3399_phy_cfgs[] = {
1343 .clkout_ctl = { 0xe450, 4, 4, 1, 0 },
1345 [USB2PHY_PORT_OTG] = {
1346 .phy_sus = { 0xe454, 15, 0, 0x1452, 0x15d1 },
1347 .bvalid_det_en = { 0xe3c0, 3, 3, 0, 1 },
1348 .bvalid_det_st = { 0xe3e0, 3, 3, 0, 1 },
1349 .bvalid_det_clr = { 0xe3d0, 3, 3, 0, 1 },
1350 .idfall_det_en = { 0xe3c0, 5, 5, 0, 1 },
1351 .idfall_det_st = { 0xe3e0, 5, 5, 0, 1 },
1352 .idfall_det_clr = { 0xe3d0, 5, 5, 0, 1 },
1353 .idrise_det_en = { 0xe3c0, 4, 4, 0, 1 },
1354 .idrise_det_st = { 0xe3e0, 4, 4, 0, 1 },
1355 .idrise_det_clr = { 0xe3d0, 4, 4, 0, 1 },
1356 .utmi_avalid = { 0xe2ac, 7, 7, 0, 1 },
1357 .utmi_bvalid = { 0xe2ac, 12, 12, 0, 1 },
1358 .utmi_iddig = { 0xe2ac, 8, 8, 0, 1 },
1360 [USB2PHY_PORT_HOST] = {
1361 .phy_sus = { 0xe458, 1, 0, 0x2, 0x1 },
1362 .ls_det_en = { 0xe3c0, 6, 6, 0, 1 },
1363 .ls_det_st = { 0xe3e0, 6, 6, 0, 1 },
1364 .ls_det_clr = { 0xe3d0, 6, 6, 0, 1 },
1365 .utmi_ls = { 0xe2ac, 22, 21, 0, 1 },
1366 .utmi_hstdet = { 0xe2ac, 23, 23, 0, 1 }
1370 .opmode = { 0xe454, 3, 0, 5, 1 },
1371 .cp_det = { 0xe2ac, 2, 2, 0, 1 },
1372 .dcp_det = { 0xe2ac, 1, 1, 0, 1 },
1373 .dp_det = { 0xe2ac, 0, 0, 0, 1 },
1374 .idm_sink_en = { 0xe450, 8, 8, 0, 1 },
1375 .idp_sink_en = { 0xe450, 7, 7, 0, 1 },
1376 .idp_src_en = { 0xe450, 9, 9, 0, 1 },
1377 .rdm_pdwn_en = { 0xe450, 10, 10, 0, 1 },
1378 .vdm_src_en = { 0xe450, 12, 12, 0, 1 },
1379 .vdp_src_en = { 0xe450, 11, 11, 0, 1 },
1385 .clkout_ctl = { 0xe460, 4, 4, 1, 0 },
1387 [USB2PHY_PORT_OTG] = {
1388 .phy_sus = { 0xe464, 15, 0, 0x1452, 0x15d1 },
1389 .bvalid_det_en = { 0xe3c0, 8, 8, 0, 1 },
1390 .bvalid_det_st = { 0xe3e0, 8, 8, 0, 1 },
1391 .bvalid_det_clr = { 0xe3d0, 8, 8, 0, 1 },
1392 .idfall_det_en = { 0xe3c0, 10, 10, 0, 1 },
1393 .idfall_det_st = { 0xe3e0, 10, 10, 0, 1 },
1394 .idfall_det_clr = { 0xe3d0, 10, 10, 0, 1 },
1395 .idrise_det_en = { 0xe3c0, 9, 9, 0, 1 },
1396 .idrise_det_st = { 0xe3e0, 9, 9, 0, 1 },
1397 .idrise_det_clr = { 0xe3d0, 9, 9, 0, 1 },
1398 .utmi_avalid = { 0xe2ac, 10, 10, 0, 1 },
1399 .utmi_bvalid = { 0xe2ac, 16, 16, 0, 1 },
1400 .utmi_iddig = { 0xe2ac, 11, 11, 0, 1 },
1402 [USB2PHY_PORT_HOST] = {
1403 .phy_sus = { 0xe468, 1, 0, 0x2, 0x1 },
1404 .ls_det_en = { 0xe3c0, 11, 11, 0, 1 },
1405 .ls_det_st = { 0xe3e0, 11, 11, 0, 1 },
1406 .ls_det_clr = { 0xe3d0, 11, 11, 0, 1 },
1407 .utmi_ls = { 0xe2ac, 26, 25, 0, 1 },
1408 .utmi_hstdet = { 0xe2ac, 27, 27, 0, 1 }
1415 static const struct of_device_id rockchip_usb2phy_dt_match[] = {
1416 { .compatible = "rockchip,rk3366-usb2phy", .data = &rk3366_phy_cfgs },
1417 { .compatible = "rockchip,rk3399-usb2phy", .data = &rk3399_phy_cfgs },
1420 MODULE_DEVICE_TABLE(of, rockchip_usb2phy_dt_match);
1422 static struct platform_driver rockchip_usb2phy_driver = {
1423 .probe = rockchip_usb2phy_probe,
1425 .name = "rockchip-usb2phy",
1426 .of_match_table = rockchip_usb2phy_dt_match,
1429 module_platform_driver(rockchip_usb2phy_driver);
1431 MODULE_AUTHOR("Frank Wang <frank.wang@rock-chips.com>");
1432 MODULE_DESCRIPTION("Rockchip USB2.0 PHY driver");
1433 MODULE_LICENSE("GPL v2");