2 * Rockchip AXI PCIe host controller driver
4 * Copyright (c) 2016 Rockchip, Inc.
6 * Author: Shawn Lin <shawn.lin@rock-chips.com>
7 * Wenrui Li <wenrui.li@rock-chips.com>
9 * Bits taken from Synopsys Designware Host controller driver and
10 * ARM PCI Host generic driver.
12 * This program is free software: you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation, either version 2 of the License, or
15 * (at your option) any later version.
18 #include <linux/clk.h>
19 #include <linux/delay.h>
20 #include <linux/gpio/consumer.h>
21 #include <linux/init.h>
22 #include <linux/interrupt.h>
23 #include <linux/irq.h>
24 #include <linux/irqchip/chained_irq.h>
25 #include <linux/irqdomain.h>
26 #include <linux/kernel.h>
27 #include <linux/mfd/syscon.h>
28 #include <linux/of_address.h>
29 #include <linux/of_device.h>
30 #include <linux/of_pci.h>
31 #include <linux/of_platform.h>
32 #include <linux/of_irq.h>
33 #include <linux/pci.h>
34 #include <linux/pci_ids.h>
35 #include <linux/phy/phy.h>
36 #include <linux/platform_device.h>
37 #include <linux/reset.h>
38 #include <linux/regmap.h>
40 #define PCIE_CLIENT_BASE 0x0
41 #define PCIE_RC_CONFIG_NORMAL_BASE 0x800000
42 #define PCIE_RC_CONFIG_BASE 0xa00000
43 #define PCIE_RC_CONFIG_LCSR 0xd0
44 #define PCIE_RC_CONFIG_LCSR_LBMIE BIT(10)
45 #define PCIE_RC_CONFIG_LCSR_LABIE BIT(11)
46 #define PCIE_RC_CONFIG_LCSR_LBMS BIT(30)
47 #define PCIE_RC_CONFIG_LCSR_LAMS BIT(31)
48 #define PCIE_CORE_CTRL_MGMT_BASE 0x900000
49 #define PCIE_CORE_AXI_CONF_BASE 0xc00000
50 #define PCIE_CORE_AXI_INBOUND_BASE 0xc00800
51 #define PCIE_CLIENT_BASIC_STATUS1 0x48
52 #define PCIE_CLIENT_INT_MASK 0x4c
53 #define PCIE_CLIENT_INT_STATUS 0x50
54 #define PCIE_CLIENT_INT_LEGACY_DONE BIT(15)
55 #define PCIE_CLIENT_INT_MSG BIT(14)
56 #define PCIE_CLIENT_INT_HOT_RST BIT(13)
57 #define PCIE_CLIENT_INT_DPA BIT(12)
58 #define PCIE_CLIENT_INT_FATAL_ERR BIT(11)
59 #define PCIE_CLIENT_INT_NFATAL_ERR BIT(10)
60 #define PCIE_CLIENT_INT_CORR_ERR BIT(9)
61 #define PCIE_CLIENT_INT_INTD BIT(8)
62 #define PCIE_CLIENT_INT_INTC BIT(7)
63 #define PCIE_CLIENT_INT_INTB BIT(6)
64 #define PCIE_CLIENT_INT_INTA BIT(5)
65 #define PCIE_CLIENT_INT_LOCAL BIT(4)
66 #define PCIE_CLIENT_INT_UDMA BIT(3)
67 #define PCIE_CLIENT_INT_PHY BIT(2)
68 #define PCIE_CLIENT_INT_HOT_PLUG BIT(1)
69 #define PCIE_CLIENT_INT_PWR_STCG BIT(0)
70 #define PCIE_RC_CONFIG_RID_CCR 0x8
71 #define PCIE_RC_CONFIG_LCS 0xd0
72 #define PCIE_RC_BAR_CONF 0x300
73 #define PCIE_CORE_OB_REGION_ADDR1 0x4
74 #define PCIE_CORE_OB_REGION_DESC0 0x8
75 #define PCIE_CORE_OB_REGION_DESC1 0xc
76 #define PCIE_CORE_OB_REGION_ADDR0_NUM_BITS 0x3f
77 #define PCIE_CORE_OB_REGION_ADDR0_LO_ADDR 0xffffff00
78 #define PCIE_CORE_IB_REGION_ADDR0_NUM_BITS 0x3f
79 #define PCIE_CORE_IB_REGION_ADDR0_LO_ADDR 0xffffff00
80 #define PCIE_RP_IB_ADDR_TRANS 0x4
81 #define PCIE_CORE_INT_MASK 0x900210
82 #define PCIE_CORE_INT_STATUS 0x90020c
83 #define PCIE_CORE_INT_PRFPE BIT(0)
84 #define PCIE_CORE_INT_CRFPE BIT(1)
85 #define PCIE_CORE_INT_RRPE BIT(2)
86 #define PCIE_CORE_INT_PRFO BIT(3)
87 #define PCIE_CORE_INT_CRFO BIT(4)
88 #define PCIE_CORE_INT_RT BIT(5)
89 #define PCIE_CORE_INT_RTR BIT(6)
90 #define PCIE_CORE_INT_PE BIT(7)
91 #define PCIE_CORE_INT_MTR BIT(8)
92 #define PCIE_CORE_INT_UCR BIT(9)
93 #define PCIE_CORE_INT_FCE BIT(10)
94 #define PCIE_CORE_INT_CT BIT(11)
95 #define PCIE_CORE_INT_UTC BIT(18)
96 #define PCIE_CORE_INT_MMVC BIT(19)
98 /* Size of one AXI Region (not Region 0) */
99 #define AXI_REGION_SIZE BIT(20)
100 /* Size of Region 0, equal to sum of sizes of other regions */
101 #define AXI_REGION_0_SIZE (32 * (0x1 << 20))
102 #define OB_REG_SIZE_SHIFT 5
103 #define IB_ROOT_PORT_REG_SIZE_SHIFT 3
104 #define AXI_WRAPPER_IO_WRITE 0x6
105 #define AXI_WRAPPER_MEM_WRITE 0x2
107 #define MAX_AXI_IB_ROOTPORT_REGION_NUM 3
108 #define MIN_AXI_ADDR_BITS_PASSED 8
109 #define ROCKCHIP_VENDOR_ID 0x1d87
110 #define PCIE_ECAM_BUS(x) (((x) & 0xff) << 20)
111 #define PCIE_ECAM_DEV(x) (((x) & 0x1f) << 15)
112 #define PCIE_ECAM_FUNC(x) (((x) & 0x7) << 12)
113 #define PCIE_ECAM_REG(x) (((x) & 0xfff) << 0)
114 #define PCIE_ECAM_ADDR(bus, dev, func, reg) \
115 (PCIE_ECAM_BUS(bus) | PCIE_ECAM_DEV(dev) | \
116 PCIE_ECAM_FUNC(func) | PCIE_ECAM_REG(reg))
119 * The higher 16-bit of this register is used for write protection
120 * only if BIT(x + 16) set to 1 the BIT(x) can be written.
122 #define HIWORD_UPDATE(val, mask, shift) \
123 ((val) << (shift) | (mask) << ((shift) + 16))
125 #define RC_REGION_0_ADDR_TRANS_H 0x00000000
126 #define RC_REGION_0_ADDR_TRANS_L 0x00000000
127 #define RC_REGION_0_PASS_BITS (25 - 1)
128 #define RC_REGION_1_ADDR_TRANS_H 0x00000000
129 #define RC_REGION_1_ADDR_TRANS_L 0x00400000
130 #define RC_REGION_1_PASS_BITS (20 - 1)
131 #define MAX_AXI_WRAPPER_REGION_NUM 33
132 #define PCIE_CORE_LCSR_RETRAIN_LINK BIT(5)
133 #define PCIE_CLIENT_CONF_ENABLE BIT(0)
134 #define PCIE_CLIENT_CONF_ENABLE_SHIFT 0
135 #define PCIE_CLIENT_CONF_ENABLE_MASK 0x1
136 #define PCIE_CLIENT_LINK_TRAIN_ENABLE 1
137 #define PCIE_CLIENT_LINK_TRAIN_SHIFT 1
138 #define PCIE_CLIENT_LINK_TRAIN_MASK 0x1
139 #define PCIE_CLIENT_ARI_ENABLE BIT(0)
140 #define PCIE_CLIENT_ARI_ENABLE_SHIFT 3
141 #define PCIE_CLIENT_ARI_ENABLE_MASK 0x1
142 #define PCIE_CLIENT_CONF_LANE_NUM(x) (x / 2)
143 #define PCIE_CLIENT_CONF_LANE_NUM_SHIFT 4
144 #define PCIE_CLIENT_CONF_LANE_NUM_MASK 0x3
145 #define PCIE_CLIENT_MODE_RC BIT(0)
146 #define PCIE_CLIENT_MODE_SHIFT 6
147 #define PCIE_CLIENT_MODE_MASK 0x1
148 #define PCIE_CLIENT_GEN_SEL_2 1
149 #define PCIE_CLIENT_GEN_SEL_1 0
150 #define PCIE_CLIENT_GEN_SEL_SHIFT 7
151 #define PCIE_CLIENT_GEN_SEL_MASK 0x1
152 #define PCIE_CLIENT_LINK_STATUS_UP 0x3
153 #define PCIE_CLIENT_LINK_STATUS_SHIFT 20
154 #define PCIE_CLIENT_LINK_STATUS_MASK 0x3
155 #define PCIE_CORE_PL_CONF_SPEED_2_5G 0x0
156 #define PCIE_CORE_PL_CONF_SPEED_5G 0x1
157 #define PCIE_CORE_PL_CONF_SPEED_8G 0x2
158 #define PCIE_CORE_PL_CONF_SPEED_SHIFT 3
159 #define PCIE_CORE_PL_CONF_SPEED_MASK 0x3
160 #define PCIE_CORE_PL_CONF_LANE_SHIFT 1
161 #define PCIE_CORE_PL_CONF_LANE_MASK 0x3
162 #define PCIE_CORE_RC_CONF_SCC_SHIFT 16
164 #define ROCKCHIP_PCIE_RPIFR1_INTR_MASK GENMASK(8, 5)
165 #define ROCKCHIP_PCIE_RPIFR1_INTR_SHIFT 5
167 #define PCIE_CORE_INT \
168 (PCIE_CORE_INT_PRFPE | PCIE_CORE_INT_CRFPE | \
169 PCIE_CORE_INT_RRPE | PCIE_CORE_INT_CRFO | \
170 PCIE_CORE_INT_RT | PCIE_CORE_INT_RTR | \
171 PCIE_CORE_INT_PE | PCIE_CORE_INT_MTR | \
172 PCIE_CORE_INT_UCR | PCIE_CORE_INT_FCE | \
173 PCIE_CORE_INT_CT | PCIE_CORE_INT_UTC | \
176 #define PCIE_CLIENT_INT_SUBSYSTEM \
177 (PCIE_CLIENT_INT_PWR_STCG | PCIE_CLIENT_INT_HOT_PLUG | \
178 PCIE_CLIENT_INT_PHY | PCIE_CLIENT_INT_UDMA | \
179 PCIE_CLIENT_INT_LOCAL)
181 #define PCIE_CLIENT_INT_LEGACY \
182 (PCIE_CLIENT_INT_INTA | PCIE_CLIENT_INT_INTB | \
183 PCIE_CLIENT_INT_INTC | PCIE_CLIENT_INT_INTD)
185 #define PCIE_CLIENT_INT_CLI \
186 (PCIE_CLIENT_INT_CORR_ERR | PCIE_CLIENT_INT_NFATAL_ERR | \
187 PCIE_CLIENT_INT_FATAL_ERR | PCIE_CLIENT_INT_DPA | \
188 PCIE_CLIENT_INT_HOT_RST | PCIE_CLIENT_INT_MSG | \
189 PCIE_CLIENT_INT_LEGACY_DONE | PCIE_CLIENT_INT_LEGACY | \
192 struct rockchip_pcie_port {
193 void __iomem *reg_base;
194 void __iomem *apb_base;
196 struct reset_control *core_rst;
197 struct reset_control *mgmt_rst;
198 struct reset_control *mgmt_sticky_rst;
199 struct reset_control *pipe_rst;
200 struct clk *aclk_pcie;
201 struct clk *aclk_perf_pcie;
202 struct clk *hclk_pcie;
203 struct clk *clk_pcie_pm;
204 struct regulator *vpcie3v3; /* 3.3V power supply */
205 struct regulator *vpcie1v8; /* 1.8V power supply */
206 struct regulator *vpcie0v9; /* 0.9V power supply */
207 struct gpio_desc *ep_gpio;
211 struct irq_domain *irq_domain;
214 static inline u32 pcie_read(struct rockchip_pcie_port *port, u32 reg)
216 return readl(port->apb_base + reg);
219 static inline void pcie_write(struct rockchip_pcie_port *port, u32 val, u32 reg)
221 writel(val, port->apb_base + reg);
224 static void rockchip_pcie_enable_bw_int(struct rockchip_pcie_port *port)
228 status = pcie_read(port, PCIE_RC_CONFIG_BASE + PCIE_RC_CONFIG_LCSR);
229 status |= (PCIE_RC_CONFIG_LCSR_LBMIE | PCIE_RC_CONFIG_LCSR_LABIE);
230 pcie_write(port, status, PCIE_RC_CONFIG_BASE + PCIE_RC_CONFIG_LCSR);
233 static void rockchip_pcie_clr_bw_int(struct rockchip_pcie_port *port)
237 status = pcie_read(port, PCIE_RC_CONFIG_BASE + PCIE_RC_CONFIG_LCSR);
238 status |= (PCIE_RC_CONFIG_LCSR_LBMS | PCIE_RC_CONFIG_LCSR_LAMS);
239 pcie_write(port, status, PCIE_RC_CONFIG_BASE + PCIE_RC_CONFIG_LCSR);
242 static int rockchip_pcie_valid_config(struct rockchip_pcie_port *pp,
243 struct pci_bus *bus, int dev)
245 /* access only one slot on each root port */
246 if (bus->number == pp->root_bus_nr && dev > 0)
250 * do not read more than one device on the bus directly attached
251 * to RC's downstream side.
253 if (bus->primary == pp->root_bus_nr && dev > 0)
259 static int rockchip_pcie_rd_own_conf(struct rockchip_pcie_port *pp,
263 void __iomem *addr = pp->apb_base + PCIE_RC_CONFIG_BASE + where;
265 if (!IS_ALIGNED((uintptr_t)addr, size)) {
267 return PCIBIOS_BAD_REGISTER_NUMBER;
272 } else if (size == 2) {
274 } else if (size == 1) {
278 return PCIBIOS_BAD_REGISTER_NUMBER;
280 return PCIBIOS_SUCCESSFUL;
283 static int rockchip_pcie_wr_own_conf(struct rockchip_pcie_port *pp,
284 int where, int size, u32 val)
286 u32 mask, tmp, offset;
288 offset = (where & (~0x3));
291 writel(val, pp->apb_base + PCIE_RC_CONFIG_BASE + offset);
292 return PCIBIOS_SUCCESSFUL;
295 mask = ~(((1 << (size * 8)) - 1) << ((where & 0x3) * 8));
297 tmp = readl(pp->apb_base + PCIE_RC_CONFIG_BASE + offset) & mask;
298 tmp |= val << ((where & 0x3) * 8);
299 writel(tmp, pp->apb_base + PCIE_RC_CONFIG_BASE + offset);
301 return PCIBIOS_SUCCESSFUL;
304 static int rockchip_pcie_rd_other_conf(struct rockchip_pcie_port *pp,
305 struct pci_bus *bus, u32 devfn,
306 int where, int size, u32 *val)
310 busdev = PCIE_ECAM_ADDR(bus->number, PCI_SLOT(devfn),
311 PCI_FUNC(devfn), where);
313 if (!IS_ALIGNED(busdev, size)) {
315 return PCIBIOS_BAD_REGISTER_NUMBER;
319 *val = readl(pp->reg_base + busdev);
320 } else if (size == 2) {
321 *val = readw(pp->reg_base + busdev);
322 } else if (size == 1) {
323 *val = readb(pp->reg_base + busdev);
326 return PCIBIOS_BAD_REGISTER_NUMBER;
328 return PCIBIOS_SUCCESSFUL;
331 static int rockchip_pcie_wr_other_conf(struct rockchip_pcie_port *pp,
332 struct pci_bus *bus, u32 devfn,
333 int where, int size, u32 val)
337 busdev = PCIE_ECAM_ADDR(bus->number, PCI_SLOT(devfn),
338 PCI_FUNC(devfn), where);
339 if (!IS_ALIGNED(busdev, size))
340 return PCIBIOS_BAD_REGISTER_NUMBER;
343 writel(val, pp->reg_base + busdev);
345 writew(val, pp->reg_base + busdev);
347 writeb(val, pp->reg_base + busdev);
349 return PCIBIOS_BAD_REGISTER_NUMBER;
351 return PCIBIOS_SUCCESSFUL;
354 static int rockchip_pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
357 struct rockchip_pcie_port *pp = bus->sysdata;
359 if (!rockchip_pcie_valid_config(pp, bus, PCI_SLOT(devfn))) {
361 return PCIBIOS_DEVICE_NOT_FOUND;
364 if (bus->number == pp->root_bus_nr)
365 return rockchip_pcie_rd_own_conf(pp, where, size, val);
367 return rockchip_pcie_rd_other_conf(pp, bus, devfn, where, size, val);
371 static int rockchip_pcie_wr_conf(struct pci_bus *bus, u32 devfn,
372 int where, int size, u32 val)
374 struct rockchip_pcie_port *pp = bus->sysdata;
376 if (!rockchip_pcie_valid_config(pp, bus, PCI_SLOT(devfn)))
377 return PCIBIOS_DEVICE_NOT_FOUND;
379 if (bus->number == pp->root_bus_nr)
380 return rockchip_pcie_wr_own_conf(pp, where, size, val);
382 return rockchip_pcie_wr_other_conf(pp, bus, devfn, where, size, val);
385 static struct pci_ops rockchip_pcie_ops = {
386 .read = rockchip_pcie_rd_conf,
387 .write = rockchip_pcie_wr_conf,
391 * rockchip_pcie_init_port - Initialize hardware
392 * @port: PCIe port information
394 static int rockchip_pcie_init_port(struct rockchip_pcie_port *port)
398 unsigned long timeout;
400 gpiod_set_value(port->ep_gpio, 0);
402 err = phy_init(port->phy);
404 dev_err(port->dev, "fail to init phy, err %d\n", err);
408 err = reset_control_assert(port->core_rst);
410 dev_err(port->dev, "assert core_rst err %d\n", err);
414 err = reset_control_assert(port->mgmt_rst);
416 dev_err(port->dev, "assert mgmt_rst err %d\n", err);
420 err = reset_control_assert(port->mgmt_sticky_rst);
422 dev_err(port->dev, "assert mgmt_sticky_rst err %d\n", err);
426 err = reset_control_assert(port->pipe_rst);
428 dev_err(port->dev, "assert pipe_rst err %d\n", err);
433 HIWORD_UPDATE(PCIE_CLIENT_CONF_ENABLE,
434 PCIE_CLIENT_CONF_ENABLE_MASK,
435 PCIE_CLIENT_CONF_ENABLE_SHIFT) |
436 HIWORD_UPDATE(PCIE_CLIENT_CONF_LANE_NUM(port->lanes),
437 PCIE_CLIENT_CONF_LANE_NUM_MASK,
438 PCIE_CLIENT_CONF_LANE_NUM_SHIFT) |
439 HIWORD_UPDATE(PCIE_CLIENT_MODE_RC,
440 PCIE_CLIENT_MODE_MASK,
441 PCIE_CLIENT_MODE_SHIFT) |
442 HIWORD_UPDATE(PCIE_CLIENT_ARI_ENABLE,
443 PCIE_CLIENT_ARI_ENABLE_MASK,
444 PCIE_CLIENT_ARI_ENABLE_SHIFT) |
445 HIWORD_UPDATE(PCIE_CLIENT_GEN_SEL_2,
446 PCIE_CLIENT_GEN_SEL_MASK,
447 PCIE_CLIENT_GEN_SEL_SHIFT),
450 err = phy_power_on(port->phy);
452 dev_err(port->dev, "fail to power on phy, err %d\n", err);
456 err = reset_control_deassert(port->core_rst);
458 dev_err(port->dev, "deassert core_rst err %d\n", err);
462 err = reset_control_deassert(port->mgmt_rst);
464 dev_err(port->dev, "deassert mgmt_rst err %d\n", err);
468 err = reset_control_deassert(port->mgmt_sticky_rst);
470 dev_err(port->dev, "deassert mgmt_sticky_rst err %d\n", err);
474 err = reset_control_deassert(port->pipe_rst);
476 dev_err(port->dev, "deassert pipe_rst err %d\n", err);
480 /* Enable Gen1 training */
482 HIWORD_UPDATE(PCIE_CLIENT_LINK_TRAIN_ENABLE,
483 PCIE_CLIENT_LINK_TRAIN_MASK,
484 PCIE_CLIENT_LINK_TRAIN_SHIFT),
487 gpiod_set_value(port->ep_gpio, 1);
489 /* 500ms timeout value should be enough for Gen1/2 training */
490 timeout = jiffies + msecs_to_jiffies(500);
493 status = pcie_read(port, PCIE_CLIENT_BASIC_STATUS1);
494 if (((status >> PCIE_CLIENT_LINK_STATUS_SHIFT) &
495 PCIE_CLIENT_LINK_STATUS_MASK) ==
496 PCIE_CLIENT_LINK_STATUS_UP) {
497 dev_dbg(port->dev, "PCIe link training gen1 pass!\n");
503 if (!time_before(jiffies, timeout)) {
510 /* Double check gen1 training */
512 status = pcie_read(port, PCIE_CLIENT_BASIC_STATUS1);
513 err = (((status >> PCIE_CLIENT_LINK_STATUS_SHIFT) &
514 PCIE_CLIENT_LINK_STATUS_MASK) ==
515 PCIE_CLIENT_LINK_STATUS_UP) ? 0 : -ETIMEDOUT;
517 dev_err(port->dev, "PCIe link training gen1 timeout!\n");
523 * Enable retrain for gen2. This should be configured only after
526 status = pcie_read(port,
527 PCIE_RC_CONFIG_LCS + PCIE_RC_CONFIG_BASE);
528 status |= PCIE_CORE_LCSR_RETRAIN_LINK;
529 pcie_write(port, status,
530 PCIE_RC_CONFIG_LCS + PCIE_RC_CONFIG_BASE);
532 timeout = jiffies + msecs_to_jiffies(500);
534 status = pcie_read(port, PCIE_CORE_CTRL_MGMT_BASE);
535 if (((status >> PCIE_CORE_PL_CONF_SPEED_SHIFT) &
536 PCIE_CORE_PL_CONF_SPEED_MASK) ==
537 PCIE_CORE_PL_CONF_SPEED_5G) {
538 dev_dbg(port->dev, "PCIe link training gen2 pass!\n");
544 if (!time_before(jiffies, timeout)) {
550 /* Double check gen2 training */
552 status = pcie_read(port, PCIE_CORE_CTRL_MGMT_BASE);
553 err = (((status >> PCIE_CORE_PL_CONF_SPEED_SHIFT) &
554 PCIE_CORE_PL_CONF_SPEED_MASK) ==
555 PCIE_CORE_PL_CONF_SPEED_5G) ? 0 : -ETIMEDOUT;
557 dev_dbg(port->dev, "PCIe link training gen2 timeout, fall back to gen1!\n");
560 /* Check the final link width from negotiated lane counter from MGMT */
561 status = pcie_read(port, PCIE_CORE_CTRL_MGMT_BASE);
562 status = 0x1 << ((status >> PCIE_CORE_PL_CONF_LANE_SHIFT) &
563 PCIE_CORE_PL_CONF_LANE_MASK);
564 dev_dbg(port->dev, "current link width is x%d\n", status);
566 pcie_write(port, ROCKCHIP_VENDOR_ID, PCIE_RC_CONFIG_BASE);
567 pcie_write(port, PCI_CLASS_BRIDGE_PCI << PCIE_CORE_RC_CONF_SCC_SHIFT,
568 PCIE_RC_CONFIG_BASE + PCIE_RC_CONFIG_RID_CCR);
569 pcie_write(port, 0x0, PCIE_CORE_CTRL_MGMT_BASE + PCIE_RC_BAR_CONF);
571 pcie_write(port, (RC_REGION_0_ADDR_TRANS_L + RC_REGION_0_PASS_BITS),
572 PCIE_CORE_AXI_CONF_BASE);
573 pcie_write(port, RC_REGION_0_ADDR_TRANS_H,
574 PCIE_CORE_AXI_CONF_BASE + PCIE_CORE_OB_REGION_ADDR1);
575 pcie_write(port, 0x0080000a,
576 PCIE_CORE_AXI_CONF_BASE + PCIE_CORE_OB_REGION_DESC0);
577 pcie_write(port, 0x0,
578 PCIE_CORE_AXI_CONF_BASE + PCIE_CORE_OB_REGION_DESC1);
583 static irqreturn_t rockchip_pcie_subsys_irq_handler(int irq, void *arg)
585 struct rockchip_pcie_port *pp = arg;
589 reg = pcie_read(pp, PCIE_CLIENT_INT_STATUS);
590 if (reg & PCIE_CLIENT_INT_LOCAL) {
591 dev_dbg(pp->dev, "local interrupt received\n");
592 sub_reg = pcie_read(pp, PCIE_CORE_INT_STATUS);
593 if (sub_reg & PCIE_CORE_INT_PRFPE)
594 dev_dbg(pp->dev, "parity error detected while reading from the PNP receive FIFO RAM\n");
596 if (sub_reg & PCIE_CORE_INT_CRFPE)
597 dev_dbg(pp->dev, "parity error detected while reading from the Completion Receive FIFO RAM\n");
599 if (sub_reg & PCIE_CORE_INT_RRPE)
600 dev_dbg(pp->dev, "parity error detected while reading from replay buffer RAM\n");
602 if (sub_reg & PCIE_CORE_INT_PRFO)
603 dev_dbg(pp->dev, "overflow occurred in the PNP receive FIFO\n");
605 if (sub_reg & PCIE_CORE_INT_CRFO)
606 dev_dbg(pp->dev, "overflow occurred in the completion receive FIFO\n");
608 if (sub_reg & PCIE_CORE_INT_RT)
609 dev_dbg(pp->dev, "replay timer timed out\n");
611 if (sub_reg & PCIE_CORE_INT_RTR)
612 dev_dbg(pp->dev, "replay timer rolled over after 4 transmissions of the same TLP\n");
614 if (sub_reg & PCIE_CORE_INT_PE)
615 dev_dbg(pp->dev, "phy error detected on receive side\n");
617 if (sub_reg & PCIE_CORE_INT_MTR)
618 dev_dbg(pp->dev, "malformed TLP received from the link\n");
620 if (sub_reg & PCIE_CORE_INT_UCR)
621 dev_dbg(pp->dev, "malformed TLP received from the link\n");
623 if (sub_reg & PCIE_CORE_INT_FCE)
624 dev_dbg(pp->dev, "an error was observed in the flow control advertisements from the other side\n");
626 if (sub_reg & PCIE_CORE_INT_CT)
627 dev_dbg(pp->dev, "a request timed out waiting for completion\n");
629 if (sub_reg & PCIE_CORE_INT_UTC)
630 dev_dbg(pp->dev, "unmapped TC error\n");
632 if (sub_reg & PCIE_CORE_INT_MMVC)
633 dev_dbg(pp->dev, "MSI mask register changes\n");
635 pcie_write(pp, sub_reg, PCIE_CORE_INT_STATUS);
636 } else if (reg & PCIE_CLIENT_INT_PHY) {
637 dev_dbg(pp->dev, "phy link changes\n");
638 rockchip_pcie_clr_bw_int(pp);
641 pcie_write(pp, reg & PCIE_CLIENT_INT_LOCAL, PCIE_CLIENT_INT_STATUS);
646 static irqreturn_t rockchip_pcie_client_irq_handler(int irq, void *arg)
648 struct rockchip_pcie_port *pp = arg;
651 reg = pcie_read(pp, PCIE_CLIENT_INT_STATUS);
652 if (reg & PCIE_CLIENT_INT_LEGACY_DONE)
653 dev_dbg(pp->dev, "legacy done interrupt received\n");
655 if (reg & PCIE_CLIENT_INT_MSG)
656 dev_dbg(pp->dev, "message done interrupt received\n");
658 if (reg & PCIE_CLIENT_INT_HOT_RST)
659 dev_dbg(pp->dev, "hot reset interrupt received\n");
661 if (reg & PCIE_CLIENT_INT_DPA)
662 dev_dbg(pp->dev, "dpa interrupt received\n");
664 if (reg & PCIE_CLIENT_INT_FATAL_ERR)
665 dev_dbg(pp->dev, "fatal error interrupt received\n");
667 if (reg & PCIE_CLIENT_INT_NFATAL_ERR)
668 dev_dbg(pp->dev, "no fatal error interrupt received\n");
670 if (reg & PCIE_CLIENT_INT_CORR_ERR)
671 dev_dbg(pp->dev, "correctable error interrupt received\n");
673 if (reg & PCIE_CLIENT_INT_PHY)
674 dev_dbg(pp->dev, "phy interrupt received\n");
676 pcie_write(pp, reg & (PCIE_CLIENT_INT_LEGACY_DONE |
677 PCIE_CLIENT_INT_MSG | PCIE_CLIENT_INT_HOT_RST |
678 PCIE_CLIENT_INT_DPA | PCIE_CLIENT_INT_FATAL_ERR |
679 PCIE_CLIENT_INT_NFATAL_ERR |
680 PCIE_CLIENT_INT_CORR_ERR),
681 PCIE_CLIENT_INT_STATUS |
682 PCIE_CLIENT_INT_PHY);
686 static void rockchip_pcie_legacy_int_handler(struct irq_desc *desc)
688 struct irq_chip *chip = irq_desc_get_chip(desc);
689 struct rockchip_pcie_port *port;
694 chained_irq_enter(chip, desc);
695 port = irq_desc_get_handler_data(desc);
697 reg = pcie_read(port, PCIE_CLIENT_INT_STATUS);
698 reg = (reg & ROCKCHIP_PCIE_RPIFR1_INTR_MASK) >>
699 ROCKCHIP_PCIE_RPIFR1_INTR_SHIFT;
702 hwirq = ffs(reg) - 1;
705 virq = irq_find_mapping(port->irq_domain, hwirq);
707 generic_handle_irq(virq);
709 dev_err(port->dev, "unexpected IRQ, INT%d\n", hwirq);
712 chained_irq_exit(chip, desc);
717 * rockchip_pcie_parse_dt - Parse Device Tree
718 * @port: PCIe port information
720 * Return: '0' on success and error value on failure
722 static int rockchip_pcie_parse_dt(struct rockchip_pcie_port *port)
724 struct device *dev = port->dev;
725 struct platform_device *pdev = to_platform_device(dev);
726 struct device_node *node = dev->of_node;
727 struct resource *regs;
731 regs = platform_get_resource_byname(pdev,
735 dev_err(dev, "missing axi-base property\n");
739 port->reg_base = devm_ioremap_resource(dev, regs);
740 if (IS_ERR(port->reg_base))
741 return PTR_ERR(port->reg_base);
743 regs = platform_get_resource_byname(pdev,
747 dev_err(dev, "missing apb-base property\n");
751 port->apb_base = devm_ioremap_resource(dev, regs);
752 if (IS_ERR(port->apb_base))
753 return PTR_ERR(port->apb_base);
755 port->phy = devm_phy_get(dev, "pcie-phy");
756 if (IS_ERR(port->phy)) {
757 if (PTR_ERR(port->phy) != -EPROBE_DEFER)
758 dev_err(dev, "missing phy\n");
759 return PTR_ERR(port->phy);
763 err = of_property_read_u32(node, "num-lanes", &port->lanes);
764 if (!err && ((port->lanes == 0) ||
765 (port->lanes == 3) ||
766 (port->lanes > 4))) {
767 dev_warn(dev, "invalid num-lanes, default use one lane\n");
771 port->core_rst = devm_reset_control_get(dev, "core");
772 if (IS_ERR(port->core_rst)) {
773 if (PTR_ERR(port->core_rst) != -EPROBE_DEFER)
774 dev_err(dev, "missing core rst property in node\n");
775 return PTR_ERR(port->core_rst);
778 port->mgmt_rst = devm_reset_control_get(dev, "mgmt");
779 if (IS_ERR(port->mgmt_rst)) {
780 if (PTR_ERR(port->mgmt_rst) != -EPROBE_DEFER)
781 dev_err(dev, "missing mgmt rst property in node\n");
782 return PTR_ERR(port->mgmt_rst);
785 port->mgmt_sticky_rst = devm_reset_control_get(dev, "mgmt-sticky");
786 if (IS_ERR(port->mgmt_sticky_rst)) {
787 if (PTR_ERR(port->mgmt_sticky_rst) != -EPROBE_DEFER)
788 dev_err(dev, "missing mgmt-sticky rst property in node\n");
789 return PTR_ERR(port->mgmt_sticky_rst);
792 port->pipe_rst = devm_reset_control_get(dev, "pipe");
793 if (IS_ERR(port->pipe_rst)) {
794 if (PTR_ERR(port->pipe_rst) != -EPROBE_DEFER)
795 dev_err(dev, "missing pipe rst property in node\n");
796 return PTR_ERR(port->pipe_rst);
799 port->ep_gpio = devm_gpiod_get(dev, "ep", GPIOD_OUT_HIGH);
800 if (IS_ERR(port->ep_gpio)) {
801 dev_err(dev, "missing ep-gpios property in node\n");
802 return PTR_ERR(port->ep_gpio);
805 port->aclk_pcie = devm_clk_get(dev, "aclk");
806 if (IS_ERR(port->aclk_pcie)) {
807 dev_err(dev, "aclk clock not found\n");
808 return PTR_ERR(port->aclk_pcie);
811 port->aclk_perf_pcie = devm_clk_get(dev, "aclk-perf");
812 if (IS_ERR(port->aclk_perf_pcie)) {
813 dev_err(dev, "aclk_perf clock not found\n");
814 return PTR_ERR(port->aclk_perf_pcie);
817 port->hclk_pcie = devm_clk_get(dev, "hclk");
818 if (IS_ERR(port->hclk_pcie)) {
819 dev_err(dev, "hclk clock not found\n");
820 return PTR_ERR(port->hclk_pcie);
823 port->clk_pcie_pm = devm_clk_get(dev, "pm");
824 if (IS_ERR(port->clk_pcie_pm)) {
825 dev_err(dev, "pm clock not found\n");
826 return PTR_ERR(port->clk_pcie_pm);
829 irq = platform_get_irq_byname(pdev, "sys");
831 dev_err(dev, "missing sys IRQ resource\n");
835 err = devm_request_irq(dev, irq, rockchip_pcie_subsys_irq_handler,
836 IRQF_SHARED, "pcie-sys", port);
838 dev_err(dev, "failed to request PCIe subsystem IRQ\n");
842 irq = platform_get_irq_byname(pdev, "legacy");
844 dev_err(dev, "missing legacy IRQ resource\n");
848 irq_set_chained_handler_and_data(irq,
849 rockchip_pcie_legacy_int_handler,
852 irq = platform_get_irq_byname(pdev, "client");
854 dev_err(dev, "missing client IRQ resource\n");
858 err = devm_request_irq(dev, irq, rockchip_pcie_client_irq_handler,
859 IRQF_SHARED, "pcie-client", port);
861 dev_err(dev, "failed to request PCIe client IRQ\n");
865 port->vpcie3v3 = devm_regulator_get_optional(dev, "vpcie3v3");
866 if (IS_ERR(port->vpcie3v3)) {
867 if (PTR_ERR(port->vpcie3v3) == -EPROBE_DEFER)
868 return -EPROBE_DEFER;
869 dev_info(dev, "no vpcie3v3 regulator found\n");
872 port->vpcie1v8 = devm_regulator_get_optional(dev, "vpcie1v8");
873 if (IS_ERR(port->vpcie1v8)) {
874 if (PTR_ERR(port->vpcie1v8) == -EPROBE_DEFER)
875 return -EPROBE_DEFER;
876 dev_info(dev, "no vpcie1v8 regulator found\n");
879 port->vpcie0v9 = devm_regulator_get_optional(dev, "vpcie0v9");
880 if (IS_ERR(port->vpcie0v9)) {
881 if (PTR_ERR(port->vpcie0v9) == -EPROBE_DEFER)
882 return -EPROBE_DEFER;
883 dev_info(dev, "no vpcie0v9 regulator found\n");
889 static int rockchip_pcie_set_vpcie(struct rockchip_pcie_port *port)
893 if (!IS_ERR(port->vpcie3v3)) {
894 err = regulator_enable(port->vpcie3v3);
896 dev_err(port->dev, "fail to enable vpcie3v3 regulator\n");
901 if (!IS_ERR(port->vpcie1v8)) {
902 err = regulator_enable(port->vpcie1v8);
904 dev_err(port->dev, "fail to enable vpcie1v8 regulator\n");
905 goto err_disable_3v3;
909 if (!IS_ERR(port->vpcie0v9)) {
910 err = regulator_enable(port->vpcie0v9);
912 dev_err(port->dev, "fail to enable vpcie0v9 regulator\n");
913 goto err_disable_1v8;
920 if (!IS_ERR(port->vpcie1v8))
921 regulator_disable(port->vpcie1v8);
923 if (!IS_ERR(port->vpcie3v3))
924 regulator_disable(port->vpcie3v3);
929 static void rockchip_pcie_enable_interrupts(struct rockchip_pcie_port *port)
931 pcie_write(port, (PCIE_CLIENT_INT_CLI << 16) &
932 (~PCIE_CLIENT_INT_CLI), PCIE_CLIENT_INT_MASK);
933 pcie_write(port, (u32)(~PCIE_CORE_INT), PCIE_CORE_INT_MASK);
935 rockchip_pcie_enable_bw_int(port);
938 static int rockchip_pcie_intx_map(struct irq_domain *domain, unsigned int irq,
939 irq_hw_number_t hwirq)
941 irq_set_chip_and_handler(irq, &dummy_irq_chip, handle_simple_irq);
942 irq_set_chip_data(irq, domain->host_data);
947 static const struct irq_domain_ops intx_domain_ops = {
948 .map = rockchip_pcie_intx_map,
951 static int rockchip_pcie_init_irq_domain(struct rockchip_pcie_port *pp)
953 struct device *dev = pp->dev;
954 struct device_node *intc = of_get_next_child(dev->of_node, NULL);
957 dev_err(dev, "missing child interrupt-controller node\n");
961 pp->irq_domain = irq_domain_add_linear(intc, 4, &intx_domain_ops, pp);
962 if (!pp->irq_domain) {
963 dev_err(dev, "failed to get a INTx IRQ domain\n");
970 static int rockchip_pcie_prog_ob_atu(struct rockchip_pcie_port *pp,
971 int region_no, int type, u8 num_pass_bits,
972 u32 lower_addr, u32 upper_addr)
977 void __iomem *aw_base;
979 if (region_no >= MAX_AXI_WRAPPER_REGION_NUM)
981 if ((num_pass_bits + 1) < 8)
983 if (num_pass_bits > 63)
985 if (region_no == 0) {
986 if (AXI_REGION_0_SIZE < (2ULL << num_pass_bits))
989 if (region_no != 0) {
990 if (AXI_REGION_SIZE < (2ULL << num_pass_bits))
994 aw_base = pp->apb_base + PCIE_CORE_AXI_CONF_BASE;
995 aw_base += (region_no << OB_REG_SIZE_SHIFT);
997 ob_addr_0 = num_pass_bits & PCIE_CORE_OB_REGION_ADDR0_NUM_BITS;
998 ob_addr_0 |= lower_addr & PCIE_CORE_OB_REGION_ADDR0_LO_ADDR;
999 ob_addr_1 = upper_addr;
1000 ob_desc_0 = (1 << 23 | type);
1002 writel(ob_addr_0, aw_base);
1003 writel(ob_addr_1, aw_base + PCIE_CORE_OB_REGION_ADDR1);
1004 writel(ob_desc_0, aw_base + PCIE_CORE_OB_REGION_DESC0);
1005 writel(0, aw_base + PCIE_CORE_OB_REGION_DESC1);
1010 static int rockchip_pcie_prog_ib_atu(struct rockchip_pcie_port *pp,
1011 int region_no, u8 num_pass_bits,
1012 u32 lower_addr, u32 upper_addr)
1016 void __iomem *aw_base;
1018 if (region_no > MAX_AXI_IB_ROOTPORT_REGION_NUM)
1020 if ((num_pass_bits + 1) < MIN_AXI_ADDR_BITS_PASSED)
1022 if (num_pass_bits > 63)
1025 aw_base = pp->apb_base + PCIE_CORE_AXI_INBOUND_BASE;
1026 aw_base += (region_no << IB_ROOT_PORT_REG_SIZE_SHIFT);
1028 ib_addr_0 = num_pass_bits & PCIE_CORE_IB_REGION_ADDR0_NUM_BITS;
1029 ib_addr_0 |= (lower_addr << 8) & PCIE_CORE_IB_REGION_ADDR0_LO_ADDR;
1030 ib_addr_1 = upper_addr;
1032 writel(ib_addr_0, aw_base);
1033 writel(ib_addr_1, aw_base + PCIE_RP_IB_ADDR_TRANS);
1038 static int rockchip_pcie_probe(struct platform_device *pdev)
1040 struct rockchip_pcie_port *port;
1041 struct device *dev = &pdev->dev;
1042 struct pci_bus *bus, *child;
1043 struct resource_entry *win;
1044 resource_size_t io_base;
1045 struct resource *busn = NULL;
1046 struct resource *mem;
1047 struct resource *io;
1048 phys_addr_t io_bus_addr = 0;
1050 phys_addr_t mem_bus_addr = 0;
1061 port = devm_kzalloc(dev, sizeof(*port), GFP_KERNEL);
1067 err = rockchip_pcie_parse_dt(port);
1071 err = clk_prepare_enable(port->aclk_pcie);
1073 dev_err(dev, "unable to enable aclk_pcie clock\n");
1077 err = clk_prepare_enable(port->aclk_perf_pcie);
1079 dev_err(dev, "unable to enable aclk_perf_pcie clock\n");
1080 goto err_aclk_perf_pcie;
1083 err = clk_prepare_enable(port->hclk_pcie);
1085 dev_err(dev, "unable to enable hclk_pcie clock\n");
1089 err = clk_prepare_enable(port->clk_pcie_pm);
1091 dev_err(dev, "unable to enable hclk_pcie clock\n");
1095 err = rockchip_pcie_set_vpcie(port);
1097 dev_err(port->dev, "failed to set vpcie regulator\n");
1101 err = rockchip_pcie_init_port(port);
1105 platform_set_drvdata(pdev, port);
1107 rockchip_pcie_enable_interrupts(port);
1109 err = rockchip_pcie_init_irq_domain(port);
1113 err = of_pci_get_host_bridge_resources(dev->of_node, 0, 0xff,
1118 err = devm_request_pci_bus_resources(dev, &res);
1122 /* Get the I/O and memory ranges from DT */
1123 resource_list_for_each_entry(win, &res) {
1124 switch (resource_type(win->res)) {
1128 io_size = resource_size(io);
1129 io_bus_addr = io->start - win->offset;
1130 err = pci_remap_iospace(io, io_base);
1132 dev_warn(port->dev, "error %d: failed to map resource %pR\n",
1137 case IORESOURCE_MEM:
1140 mem_size = resource_size(mem);
1141 mem_bus_addr = mem->start - win->offset;
1143 case IORESOURCE_BUS:
1152 for (reg_no = 0; reg_no < (mem_size >> 20); reg_no++) {
1153 err = rockchip_pcie_prog_ob_atu(port, reg_no + 1,
1154 AXI_WRAPPER_MEM_WRITE,
1160 dev_err(dev, "program RC mem outbound ATU failed\n");
1165 err = rockchip_pcie_prog_ib_atu(port, 2, 32 - 1, 0x0, 0);
1167 dev_err(dev, "program RC mem inbound ATU failed\n");
1171 offset = mem_size >> 20;
1174 for (reg_no = 0; reg_no < (io_size >> 20); reg_no++) {
1175 err = rockchip_pcie_prog_ob_atu(port,
1176 reg_no + 1 + offset,
1177 AXI_WRAPPER_IO_WRITE,
1183 dev_err(dev, "program RC io outbound ATU failed\n");
1189 port->root_bus_nr = busn->start;
1191 bus = pci_scan_root_bus(&pdev->dev, 0, &rockchip_pcie_ops, port, &res);
1198 pci_bus_size_bridges(bus);
1199 pci_bus_assign_resources(bus);
1200 list_for_each_entry(child, &bus->children, node)
1201 pcie_bus_configure_settings(child);
1203 pci_bus_add_devices(bus);
1205 dev_warn(dev, "only 32-bit config accesses supported; smaller writes may corrupt adjacent RW1C fields\n");
1210 if (!IS_ERR(port->vpcie3v3))
1211 regulator_disable(port->vpcie3v3);
1212 if (!IS_ERR(port->vpcie1v8))
1213 regulator_disable(port->vpcie1v8);
1214 if (!IS_ERR(port->vpcie0v9))
1215 regulator_disable(port->vpcie0v9);
1217 clk_disable_unprepare(port->clk_pcie_pm);
1219 clk_disable_unprepare(port->hclk_pcie);
1221 clk_disable_unprepare(port->aclk_perf_pcie);
1223 clk_disable_unprepare(port->aclk_pcie);
1228 static const struct of_device_id rockchip_pcie_of_match[] = {
1229 { .compatible = "rockchip,rk3399-pcie", },
1233 static struct platform_driver rockchip_pcie_driver = {
1235 .name = "rockchip-pcie",
1236 .of_match_table = rockchip_pcie_of_match,
1238 .probe = rockchip_pcie_probe,
1241 builtin_platform_driver(rockchip_pcie_driver);