2 * linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver
4 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or (at
9 * your option) any later version.
11 * Thanks to the following companies for their support:
13 * - JMicron (hardware and technical support)
16 #include <linux/delay.h>
17 #include <linux/highmem.h>
19 #include <linux/dma-mapping.h>
20 #include <linux/slab.h>
21 #include <linux/scatterlist.h>
22 #include <linux/regulator/consumer.h>
24 #include <linux/leds.h>
26 #include <linux/mmc/host.h>
27 #include <linux/mmc/card.h>
31 #define DRIVER_NAME "sdhci"
33 #define DBG(f, x...) \
34 pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x)
36 #if defined(CONFIG_LEDS_CLASS) || (defined(CONFIG_LEDS_CLASS_MODULE) && \
37 defined(CONFIG_MMC_SDHCI_MODULE))
38 #define SDHCI_USE_LEDS_CLASS
41 static unsigned int debug_quirks = 0;
43 static void sdhci_prepare_data(struct sdhci_host *, struct mmc_data *);
44 static void sdhci_finish_data(struct sdhci_host *);
46 static void sdhci_send_command(struct sdhci_host *, struct mmc_command *);
47 static void sdhci_finish_command(struct sdhci_host *);
49 static void sdhci_dumpregs(struct sdhci_host *host)
51 printk(KERN_DEBUG DRIVER_NAME ": ============== REGISTER DUMP ==============\n");
53 printk(KERN_DEBUG DRIVER_NAME ": Sys addr: 0x%08x | Version: 0x%08x\n",
54 sdhci_readl(host, SDHCI_DMA_ADDRESS),
55 sdhci_readw(host, SDHCI_HOST_VERSION));
56 printk(KERN_DEBUG DRIVER_NAME ": Blk size: 0x%08x | Blk cnt: 0x%08x\n",
57 sdhci_readw(host, SDHCI_BLOCK_SIZE),
58 sdhci_readw(host, SDHCI_BLOCK_COUNT));
59 printk(KERN_DEBUG DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n",
60 sdhci_readl(host, SDHCI_ARGUMENT),
61 sdhci_readw(host, SDHCI_TRANSFER_MODE));
62 printk(KERN_DEBUG DRIVER_NAME ": Present: 0x%08x | Host ctl: 0x%08x\n",
63 sdhci_readl(host, SDHCI_PRESENT_STATE),
64 sdhci_readb(host, SDHCI_HOST_CONTROL));
65 printk(KERN_DEBUG DRIVER_NAME ": Power: 0x%08x | Blk gap: 0x%08x\n",
66 sdhci_readb(host, SDHCI_POWER_CONTROL),
67 sdhci_readb(host, SDHCI_BLOCK_GAP_CONTROL));
68 printk(KERN_DEBUG DRIVER_NAME ": Wake-up: 0x%08x | Clock: 0x%08x\n",
69 sdhci_readb(host, SDHCI_WAKE_UP_CONTROL),
70 sdhci_readw(host, SDHCI_CLOCK_CONTROL));
71 printk(KERN_DEBUG DRIVER_NAME ": Timeout: 0x%08x | Int stat: 0x%08x\n",
72 sdhci_readb(host, SDHCI_TIMEOUT_CONTROL),
73 sdhci_readl(host, SDHCI_INT_STATUS));
74 printk(KERN_DEBUG DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n",
75 sdhci_readl(host, SDHCI_INT_ENABLE),
76 sdhci_readl(host, SDHCI_SIGNAL_ENABLE));
77 printk(KERN_DEBUG DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n",
78 sdhci_readw(host, SDHCI_ACMD12_ERR),
79 sdhci_readw(host, SDHCI_SLOT_INT_STATUS));
80 printk(KERN_DEBUG DRIVER_NAME ": Caps: 0x%08x | Max curr: 0x%08x\n",
81 sdhci_readl(host, SDHCI_CAPABILITIES),
82 sdhci_readl(host, SDHCI_MAX_CURRENT));
84 if (host->flags & SDHCI_USE_ADMA)
85 printk(KERN_DEBUG DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x\n",
86 readl(host->ioaddr + SDHCI_ADMA_ERROR),
87 readl(host->ioaddr + SDHCI_ADMA_ADDRESS));
89 printk(KERN_DEBUG DRIVER_NAME ": ===========================================\n");
92 /*****************************************************************************\
94 * Low level functions *
96 \*****************************************************************************/
98 static void sdhci_clear_set_irqs(struct sdhci_host *host, u32 clear, u32 set)
102 ier = sdhci_readl(host, SDHCI_INT_ENABLE);
105 sdhci_writel(host, ier, SDHCI_INT_ENABLE);
106 sdhci_writel(host, ier, SDHCI_SIGNAL_ENABLE);
109 static void sdhci_unmask_irqs(struct sdhci_host *host, u32 irqs)
111 sdhci_clear_set_irqs(host, 0, irqs);
114 static void sdhci_mask_irqs(struct sdhci_host *host, u32 irqs)
116 sdhci_clear_set_irqs(host, irqs, 0);
119 static void sdhci_set_card_detection(struct sdhci_host *host, bool enable)
121 u32 irqs = SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT;
123 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
127 sdhci_unmask_irqs(host, irqs);
129 sdhci_mask_irqs(host, irqs);
132 static void sdhci_enable_card_detection(struct sdhci_host *host)
134 sdhci_set_card_detection(host, true);
137 static void sdhci_disable_card_detection(struct sdhci_host *host)
139 sdhci_set_card_detection(host, false);
142 static void sdhci_reset(struct sdhci_host *host, u8 mask)
144 unsigned long timeout;
145 u32 uninitialized_var(ier);
147 if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
148 if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) &
153 if (host->quirks & SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET)
154 ier = sdhci_readl(host, SDHCI_INT_ENABLE);
156 sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
158 if (mask & SDHCI_RESET_ALL)
161 /* Wait max 100 ms */
164 /* hw clears the bit when it's done */
165 while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) {
167 printk(KERN_ERR "%s: Reset 0x%x never completed.\n",
168 mmc_hostname(host->mmc), (int)mask);
169 sdhci_dumpregs(host);
176 if (host->quirks & SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET)
177 sdhci_clear_set_irqs(host, SDHCI_INT_ALL_MASK, ier);
180 static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios);
182 static void sdhci_init(struct sdhci_host *host, int soft)
185 sdhci_reset(host, SDHCI_RESET_CMD|SDHCI_RESET_DATA);
187 sdhci_reset(host, SDHCI_RESET_ALL);
189 sdhci_clear_set_irqs(host, SDHCI_INT_ALL_MASK,
190 SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
191 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX |
192 SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT |
193 SDHCI_INT_DATA_END | SDHCI_INT_RESPONSE);
196 /* force clock reconfiguration */
198 sdhci_set_ios(host->mmc, &host->mmc->ios);
202 static void sdhci_reinit(struct sdhci_host *host)
205 sdhci_enable_card_detection(host);
208 static void sdhci_activate_led(struct sdhci_host *host)
212 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
213 ctrl |= SDHCI_CTRL_LED;
214 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
217 static void sdhci_deactivate_led(struct sdhci_host *host)
221 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
222 ctrl &= ~SDHCI_CTRL_LED;
223 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
226 #ifdef SDHCI_USE_LEDS_CLASS
227 static void sdhci_led_control(struct led_classdev *led,
228 enum led_brightness brightness)
230 struct sdhci_host *host = container_of(led, struct sdhci_host, led);
233 spin_lock_irqsave(&host->lock, flags);
235 if (brightness == LED_OFF)
236 sdhci_deactivate_led(host);
238 sdhci_activate_led(host);
240 spin_unlock_irqrestore(&host->lock, flags);
244 /*****************************************************************************\
248 \*****************************************************************************/
250 static void sdhci_read_block_pio(struct sdhci_host *host)
253 size_t blksize, len, chunk;
254 u32 uninitialized_var(scratch);
257 DBG("PIO reading\n");
259 blksize = host->data->blksz;
262 local_irq_save(flags);
265 if (!sg_miter_next(&host->sg_miter))
268 len = min(host->sg_miter.length, blksize);
271 host->sg_miter.consumed = len;
273 buf = host->sg_miter.addr;
277 scratch = sdhci_readl(host, SDHCI_BUFFER);
281 *buf = scratch & 0xFF;
290 sg_miter_stop(&host->sg_miter);
292 local_irq_restore(flags);
295 static void sdhci_write_block_pio(struct sdhci_host *host)
298 size_t blksize, len, chunk;
302 DBG("PIO writing\n");
304 blksize = host->data->blksz;
308 local_irq_save(flags);
311 if (!sg_miter_next(&host->sg_miter))
314 len = min(host->sg_miter.length, blksize);
317 host->sg_miter.consumed = len;
319 buf = host->sg_miter.addr;
322 scratch |= (u32)*buf << (chunk * 8);
328 if ((chunk == 4) || ((len == 0) && (blksize == 0))) {
329 sdhci_writel(host, scratch, SDHCI_BUFFER);
336 sg_miter_stop(&host->sg_miter);
338 local_irq_restore(flags);
341 static void sdhci_transfer_pio(struct sdhci_host *host)
347 if (host->blocks == 0)
350 if (host->data->flags & MMC_DATA_READ)
351 mask = SDHCI_DATA_AVAILABLE;
353 mask = SDHCI_SPACE_AVAILABLE;
356 * Some controllers (JMicron JMB38x) mess up the buffer bits
357 * for transfers < 4 bytes. As long as it is just one block,
358 * we can ignore the bits.
360 if ((host->quirks & SDHCI_QUIRK_BROKEN_SMALL_PIO) &&
361 (host->data->blocks == 1))
364 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
365 if (host->quirks & SDHCI_QUIRK_PIO_NEEDS_DELAY)
368 if (host->data->flags & MMC_DATA_READ)
369 sdhci_read_block_pio(host);
371 sdhci_write_block_pio(host);
374 if (host->blocks == 0)
378 DBG("PIO transfer complete.\n");
381 static char *sdhci_kmap_atomic(struct scatterlist *sg, unsigned long *flags)
383 local_irq_save(*flags);
384 return kmap_atomic(sg_page(sg), KM_BIO_SRC_IRQ) + sg->offset;
387 static void sdhci_kunmap_atomic(void *buffer, unsigned long *flags)
389 kunmap_atomic(buffer, KM_BIO_SRC_IRQ);
390 local_irq_restore(*flags);
393 static void sdhci_set_adma_desc(u8 *desc, u32 addr, int len, unsigned cmd)
395 __le32 *dataddr = (__le32 __force *)(desc + 4);
396 __le16 *cmdlen = (__le16 __force *)desc;
398 /* SDHCI specification says ADMA descriptors should be 4 byte
399 * aligned, so using 16 or 32bit operations should be safe. */
401 cmdlen[0] = cpu_to_le16(cmd);
402 cmdlen[1] = cpu_to_le16(len);
404 dataddr[0] = cpu_to_le32(addr);
407 static int sdhci_adma_table_pre(struct sdhci_host *host,
408 struct mmc_data *data)
415 dma_addr_t align_addr;
418 struct scatterlist *sg;
424 * The spec does not specify endianness of descriptor table.
425 * We currently guess that it is LE.
428 if (data->flags & MMC_DATA_READ)
429 direction = DMA_FROM_DEVICE;
431 direction = DMA_TO_DEVICE;
434 * The ADMA descriptor table is mapped further down as we
435 * need to fill it with data first.
438 host->align_addr = dma_map_single(mmc_dev(host->mmc),
439 host->align_buffer, 128 * 4, direction);
440 if (dma_mapping_error(mmc_dev(host->mmc), host->align_addr))
442 BUG_ON(host->align_addr & 0x3);
444 host->sg_count = dma_map_sg(mmc_dev(host->mmc),
445 data->sg, data->sg_len, direction);
446 if (host->sg_count == 0)
449 desc = host->adma_desc;
450 align = host->align_buffer;
452 align_addr = host->align_addr;
454 for_each_sg(data->sg, sg, host->sg_count, i) {
455 addr = sg_dma_address(sg);
456 len = sg_dma_len(sg);
459 * The SDHCI specification states that ADMA
460 * addresses must be 32-bit aligned. If they
461 * aren't, then we use a bounce buffer for
462 * the (up to three) bytes that screw up the
465 offset = (4 - (addr & 0x3)) & 0x3;
467 if (data->flags & MMC_DATA_WRITE) {
468 buffer = sdhci_kmap_atomic(sg, &flags);
469 WARN_ON(((long)buffer & PAGE_MASK) > (PAGE_SIZE - 3));
470 memcpy(align, buffer, offset);
471 sdhci_kunmap_atomic(buffer, &flags);
475 sdhci_set_adma_desc(desc, align_addr, offset, 0x21);
477 BUG_ON(offset > 65536);
491 sdhci_set_adma_desc(desc, addr, len, 0x21);
495 * If this triggers then we have a calculation bug
498 WARN_ON((desc - host->adma_desc) > (128 * 2 + 1) * 4);
501 if (host->quirks & SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC) {
503 * Mark the last descriptor as the terminating descriptor
505 if (desc != host->adma_desc) {
507 desc[0] |= 0x2; /* end */
511 * Add a terminating entry.
514 /* nop, end, valid */
515 sdhci_set_adma_desc(desc, 0, 0, 0x3);
519 * Resync align buffer as we might have changed it.
521 if (data->flags & MMC_DATA_WRITE) {
522 dma_sync_single_for_device(mmc_dev(host->mmc),
523 host->align_addr, 128 * 4, direction);
526 host->adma_addr = dma_map_single(mmc_dev(host->mmc),
527 host->adma_desc, (128 * 2 + 1) * 4, DMA_TO_DEVICE);
528 if (dma_mapping_error(mmc_dev(host->mmc), host->adma_addr))
530 BUG_ON(host->adma_addr & 0x3);
535 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
536 data->sg_len, direction);
538 dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
544 static void sdhci_adma_table_post(struct sdhci_host *host,
545 struct mmc_data *data)
549 struct scatterlist *sg;
555 if (data->flags & MMC_DATA_READ)
556 direction = DMA_FROM_DEVICE;
558 direction = DMA_TO_DEVICE;
560 dma_unmap_single(mmc_dev(host->mmc), host->adma_addr,
561 (128 * 2 + 1) * 4, DMA_TO_DEVICE);
563 dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
566 if (data->flags & MMC_DATA_READ) {
567 dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg,
568 data->sg_len, direction);
570 align = host->align_buffer;
572 for_each_sg(data->sg, sg, host->sg_count, i) {
573 if (sg_dma_address(sg) & 0x3) {
574 size = 4 - (sg_dma_address(sg) & 0x3);
576 buffer = sdhci_kmap_atomic(sg, &flags);
577 WARN_ON(((long)buffer & PAGE_MASK) > (PAGE_SIZE - 3));
578 memcpy(buffer, align, size);
579 sdhci_kunmap_atomic(buffer, &flags);
586 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
587 data->sg_len, direction);
590 static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_data *data)
593 unsigned target_timeout, current_timeout;
596 * If the host controller provides us with an incorrect timeout
597 * value, just skip the check and use 0xE. The hardware may take
598 * longer to time out, but that's much better than having a too-short
601 if (host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL)
605 target_timeout = data->timeout_ns / 1000 +
606 data->timeout_clks / host->clock;
608 if (host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)
609 host->timeout_clk = host->clock / 1000;
612 * Figure out needed cycles.
613 * We do this in steps in order to fit inside a 32 bit int.
614 * The first step is the minimum timeout, which will have a
615 * minimum resolution of 6 bits:
616 * (1) 2^13*1000 > 2^22,
617 * (2) host->timeout_clk < 2^16
622 current_timeout = (1 << 13) * 1000 / host->timeout_clk;
623 while (current_timeout < target_timeout) {
625 current_timeout <<= 1;
631 printk(KERN_WARNING "%s: Too large timeout requested!\n",
632 mmc_hostname(host->mmc));
639 static void sdhci_set_transfer_irqs(struct sdhci_host *host)
641 u32 pio_irqs = SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL;
642 u32 dma_irqs = SDHCI_INT_DMA_END | SDHCI_INT_ADMA_ERROR;
644 if (host->flags & SDHCI_REQ_USE_DMA)
645 sdhci_clear_set_irqs(host, pio_irqs, dma_irqs);
647 sdhci_clear_set_irqs(host, dma_irqs, pio_irqs);
650 static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_data *data)
662 BUG_ON(data->blksz * data->blocks > 524288);
663 BUG_ON(data->blksz > host->mmc->max_blk_size);
664 BUG_ON(data->blocks > 65535);
667 host->data_early = 0;
669 count = sdhci_calc_timeout(host, data);
670 sdhci_writeb(host, count, SDHCI_TIMEOUT_CONTROL);
672 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))
673 host->flags |= SDHCI_REQ_USE_DMA;
676 * FIXME: This doesn't account for merging when mapping the
679 if (host->flags & SDHCI_REQ_USE_DMA) {
681 struct scatterlist *sg;
684 if (host->flags & SDHCI_USE_ADMA) {
685 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
688 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE)
692 if (unlikely(broken)) {
693 for_each_sg(data->sg, sg, data->sg_len, i) {
694 if (sg->length & 0x3) {
695 DBG("Reverting to PIO because of "
696 "transfer size (%d)\n",
698 host->flags &= ~SDHCI_REQ_USE_DMA;
706 * The assumption here being that alignment is the same after
707 * translation to device address space.
709 if (host->flags & SDHCI_REQ_USE_DMA) {
711 struct scatterlist *sg;
714 if (host->flags & SDHCI_USE_ADMA) {
716 * As we use 3 byte chunks to work around
717 * alignment problems, we need to check this
720 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
723 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR)
727 if (unlikely(broken)) {
728 for_each_sg(data->sg, sg, data->sg_len, i) {
729 if (sg->offset & 0x3) {
730 DBG("Reverting to PIO because of "
732 host->flags &= ~SDHCI_REQ_USE_DMA;
739 if (host->flags & SDHCI_REQ_USE_DMA) {
740 if (host->flags & SDHCI_USE_ADMA) {
741 ret = sdhci_adma_table_pre(host, data);
744 * This only happens when someone fed
745 * us an invalid request.
748 host->flags &= ~SDHCI_REQ_USE_DMA;
750 sdhci_writel(host, host->adma_addr,
756 sg_cnt = dma_map_sg(mmc_dev(host->mmc),
757 data->sg, data->sg_len,
758 (data->flags & MMC_DATA_READ) ?
763 * This only happens when someone fed
764 * us an invalid request.
767 host->flags &= ~SDHCI_REQ_USE_DMA;
769 WARN_ON(sg_cnt != 1);
770 sdhci_writel(host, sg_dma_address(data->sg),
777 * Always adjust the DMA selection as some controllers
778 * (e.g. JMicron) can't do PIO properly when the selection
781 if (host->version >= SDHCI_SPEC_200) {
782 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
783 ctrl &= ~SDHCI_CTRL_DMA_MASK;
784 if ((host->flags & SDHCI_REQ_USE_DMA) &&
785 (host->flags & SDHCI_USE_ADMA))
786 ctrl |= SDHCI_CTRL_ADMA32;
788 ctrl |= SDHCI_CTRL_SDMA;
789 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
792 if (!(host->flags & SDHCI_REQ_USE_DMA)) {
795 flags = SG_MITER_ATOMIC;
796 if (host->data->flags & MMC_DATA_READ)
797 flags |= SG_MITER_TO_SG;
799 flags |= SG_MITER_FROM_SG;
800 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
801 host->blocks = data->blocks;
804 sdhci_set_transfer_irqs(host);
806 /* We do not handle DMA boundaries, so set it to max (512 KiB) */
807 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, data->blksz), SDHCI_BLOCK_SIZE);
808 sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
811 static void sdhci_set_transfer_mode(struct sdhci_host *host,
812 struct mmc_data *data)
819 WARN_ON(!host->data);
821 mode = SDHCI_TRNS_BLK_CNT_EN;
822 if (data->blocks > 1) {
823 if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12)
824 mode |= SDHCI_TRNS_MULTI | SDHCI_TRNS_ACMD12;
826 mode |= SDHCI_TRNS_MULTI;
828 if (data->flags & MMC_DATA_READ)
829 mode |= SDHCI_TRNS_READ;
830 if (host->flags & SDHCI_REQ_USE_DMA)
831 mode |= SDHCI_TRNS_DMA;
833 sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
836 static void sdhci_finish_data(struct sdhci_host *host)
838 struct mmc_data *data;
845 if (host->flags & SDHCI_REQ_USE_DMA) {
846 if (host->flags & SDHCI_USE_ADMA)
847 sdhci_adma_table_post(host, data);
849 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
850 data->sg_len, (data->flags & MMC_DATA_READ) ?
851 DMA_FROM_DEVICE : DMA_TO_DEVICE);
856 * The specification states that the block count register must
857 * be updated, but it does not specify at what point in the
858 * data flow. That makes the register entirely useless to read
859 * back so we have to assume that nothing made it to the card
860 * in the event of an error.
863 data->bytes_xfered = 0;
865 data->bytes_xfered = data->blksz * data->blocks;
869 * The controller needs a reset of internal state machines
870 * upon error conditions.
873 sdhci_reset(host, SDHCI_RESET_CMD);
874 sdhci_reset(host, SDHCI_RESET_DATA);
877 sdhci_send_command(host, data->stop);
879 tasklet_schedule(&host->finish_tasklet);
882 static void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
886 unsigned long timeout;
893 mask = SDHCI_CMD_INHIBIT;
894 if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY))
895 mask |= SDHCI_DATA_INHIBIT;
897 /* We shouldn't wait for data inihibit for stop commands, even
898 though they might use busy signaling */
899 if (host->mrq->data && (cmd == host->mrq->data->stop))
900 mask &= ~SDHCI_DATA_INHIBIT;
902 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
904 printk(KERN_ERR "%s: Controller never released "
905 "inhibit bit(s).\n", mmc_hostname(host->mmc));
906 sdhci_dumpregs(host);
908 tasklet_schedule(&host->finish_tasklet);
915 mod_timer(&host->timer, jiffies + 10 * HZ);
919 sdhci_prepare_data(host, cmd->data);
921 sdhci_writel(host, cmd->arg, SDHCI_ARGUMENT);
923 sdhci_set_transfer_mode(host, cmd->data);
925 if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
926 printk(KERN_ERR "%s: Unsupported response type!\n",
927 mmc_hostname(host->mmc));
928 cmd->error = -EINVAL;
929 tasklet_schedule(&host->finish_tasklet);
933 if (!(cmd->flags & MMC_RSP_PRESENT))
934 flags = SDHCI_CMD_RESP_NONE;
935 else if (cmd->flags & MMC_RSP_136)
936 flags = SDHCI_CMD_RESP_LONG;
937 else if (cmd->flags & MMC_RSP_BUSY)
938 flags = SDHCI_CMD_RESP_SHORT_BUSY;
940 flags = SDHCI_CMD_RESP_SHORT;
942 if (cmd->flags & MMC_RSP_CRC)
943 flags |= SDHCI_CMD_CRC;
944 if (cmd->flags & MMC_RSP_OPCODE)
945 flags |= SDHCI_CMD_INDEX;
947 flags |= SDHCI_CMD_DATA;
949 sdhci_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND);
952 static void sdhci_finish_command(struct sdhci_host *host)
956 BUG_ON(host->cmd == NULL);
958 if (host->cmd->flags & MMC_RSP_PRESENT) {
959 if (host->cmd->flags & MMC_RSP_136) {
960 /* CRC is stripped so we need to do some shifting. */
961 for (i = 0;i < 4;i++) {
962 host->cmd->resp[i] = sdhci_readl(host,
963 SDHCI_RESPONSE + (3-i)*4) << 8;
965 host->cmd->resp[i] |=
967 SDHCI_RESPONSE + (3-i)*4-1);
970 host->cmd->resp[0] = sdhci_readl(host, SDHCI_RESPONSE);
974 host->cmd->error = 0;
976 if (host->data && host->data_early)
977 sdhci_finish_data(host);
979 if (!host->cmd->data)
980 tasklet_schedule(&host->finish_tasklet);
985 static void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
989 unsigned long timeout;
991 if (clock && clock == host->clock)
994 if (host->ops->set_clock) {
995 host->ops->set_clock(host, clock);
996 if (host->quirks & SDHCI_QUIRK_NONSTANDARD_CLOCK)
1000 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
1005 for (div = 1;div < 256;div *= 2) {
1006 if ((host->max_clk / div) <= clock)
1011 clk = div << SDHCI_DIVIDER_SHIFT;
1012 clk |= SDHCI_CLOCK_INT_EN;
1013 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1015 /* Wait max 20 ms */
1017 while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
1018 & SDHCI_CLOCK_INT_STABLE)) {
1020 printk(KERN_ERR "%s: Internal clock never "
1021 "stabilised.\n", mmc_hostname(host->mmc));
1022 sdhci_dumpregs(host);
1029 clk |= SDHCI_CLOCK_CARD_EN;
1030 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1034 host->clock = clock;
1037 static void sdhci_set_power(struct sdhci_host *host, unsigned short power)
1041 if (power == (unsigned short)-1)
1044 switch (1 << power) {
1045 case MMC_VDD_165_195:
1046 pwr = SDHCI_POWER_180;
1050 pwr = SDHCI_POWER_300;
1054 pwr = SDHCI_POWER_330;
1061 if (host->pwr == pwr)
1067 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1072 * Spec says that we should clear the power reg before setting
1073 * a new value. Some controllers don't seem to like this though.
1075 if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE))
1076 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1079 * At least the Marvell CaFe chip gets confused if we set the voltage
1080 * and set turn on power at the same time, so set the voltage first.
1082 if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER)
1083 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1085 pwr |= SDHCI_POWER_ON;
1087 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1090 * Some controllers need an extra 10ms delay of 10ms before they
1091 * can apply clock after applying power
1093 if (host->quirks & SDHCI_QUIRK_DELAY_AFTER_POWER)
1097 /*****************************************************************************\
1101 \*****************************************************************************/
1103 static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1105 struct sdhci_host *host;
1107 unsigned long flags;
1109 host = mmc_priv(mmc);
1111 spin_lock_irqsave(&host->lock, flags);
1113 WARN_ON(host->mrq != NULL);
1115 #ifndef SDHCI_USE_LEDS_CLASS
1116 sdhci_activate_led(host);
1118 if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12) {
1120 mrq->data->stop = NULL;
1127 /* If polling, assume that the card is always present. */
1128 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
1131 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
1134 if (!present || host->flags & SDHCI_DEVICE_DEAD) {
1135 host->mrq->cmd->error = -ENOMEDIUM;
1136 tasklet_schedule(&host->finish_tasklet);
1138 sdhci_send_command(host, mrq->cmd);
1141 spin_unlock_irqrestore(&host->lock, flags);
1144 static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1146 struct sdhci_host *host;
1147 unsigned long flags;
1150 host = mmc_priv(mmc);
1152 spin_lock_irqsave(&host->lock, flags);
1154 if (host->flags & SDHCI_DEVICE_DEAD)
1158 * Reset the chip on each power off.
1159 * Should clear out any weird states.
1161 if (ios->power_mode == MMC_POWER_OFF) {
1162 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
1166 sdhci_set_clock(host, ios->clock);
1168 if (ios->power_mode == MMC_POWER_OFF)
1169 sdhci_set_power(host, -1);
1171 sdhci_set_power(host, ios->vdd);
1173 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1175 if (ios->bus_width == MMC_BUS_WIDTH_8)
1176 ctrl |= SDHCI_CTRL_8BITBUS;
1178 ctrl &= ~SDHCI_CTRL_8BITBUS;
1180 if (ios->bus_width == MMC_BUS_WIDTH_4)
1181 ctrl |= SDHCI_CTRL_4BITBUS;
1183 if (ios->timing == MMC_TIMING_SD_HS &&
1184 !(host->quirks & SDHCI_QUIRK_NO_HISPD_BIT))
1185 ctrl |= SDHCI_CTRL_HISPD;
1187 ctrl &= ~SDHCI_CTRL_HISPD;
1189 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1192 * Some (ENE) controllers go apeshit on some ios operation,
1193 * signalling timeout and CRC errors even on CMD0. Resetting
1194 * it on each ios seems to solve the problem.
1196 if(host->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS)
1197 sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
1201 spin_unlock_irqrestore(&host->lock, flags);
1204 static int sdhci_get_ro(struct mmc_host *mmc)
1206 struct sdhci_host *host;
1207 unsigned long flags;
1210 host = mmc_priv(mmc);
1212 spin_lock_irqsave(&host->lock, flags);
1214 if (host->flags & SDHCI_DEVICE_DEAD) {
1216 } else if (!(host->quirks & SDHCI_QUIRK_BROKEN_WRITE_PROTECT)) {
1217 present = sdhci_readl(host, SDHCI_PRESENT_STATE);
1218 present = !(present & SDHCI_WRITE_PROTECT);
1219 } else if (host->ops->get_ro) {
1220 present = host->ops->get_ro(host);
1225 spin_unlock_irqrestore(&host->lock, flags);
1227 if (host->quirks & SDHCI_QUIRK_INVERTED_WRITE_PROTECT)
1228 return !!(present & SDHCI_WRITE_PROTECT);
1232 static int sdhci_enable(struct mmc_host *mmc)
1234 struct sdhci_host *host = mmc_priv(mmc);
1236 if (!mmc->card || mmc->card->type == MMC_TYPE_SDIO)
1240 sdhci_set_clock(host, mmc->ios.clock);
1245 static int sdhci_disable(struct mmc_host *mmc, int lazy)
1247 struct sdhci_host *host = mmc_priv(mmc);
1249 if (!mmc->card || mmc->card->type == MMC_TYPE_SDIO)
1252 sdhci_set_clock(host, 0);
1257 static void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable)
1259 struct sdhci_host *host;
1260 unsigned long flags;
1262 host = mmc_priv(mmc);
1264 spin_lock_irqsave(&host->lock, flags);
1266 if (host->flags & SDHCI_DEVICE_DEAD)
1270 sdhci_unmask_irqs(host, SDHCI_INT_CARD_INT);
1272 sdhci_mask_irqs(host, SDHCI_INT_CARD_INT);
1274 if (host->quirks & SDHCI_QUIRK_ENABLE_INTERRUPT_AT_BLOCK_GAP) {
1275 u8 gap_ctrl = readb(host->ioaddr + SDHCI_BLOCK_GAP_CONTROL);
1280 writeb(gap_ctrl, host->ioaddr + SDHCI_BLOCK_GAP_CONTROL);
1286 spin_unlock_irqrestore(&host->lock, flags);
1289 static const struct mmc_host_ops sdhci_ops = {
1290 .request = sdhci_request,
1291 .set_ios = sdhci_set_ios,
1292 .get_ro = sdhci_get_ro,
1293 .enable = sdhci_enable,
1294 .disable = sdhci_disable,
1295 .enable_sdio_irq = sdhci_enable_sdio_irq,
1298 void sdhci_card_detect_callback(struct sdhci_host *host)
1300 unsigned long flags;
1302 spin_lock_irqsave(&host->lock, flags);
1304 if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT)) {
1306 printk(KERN_ERR "%s: Card removed during transfer!\n",
1307 mmc_hostname(host->mmc));
1308 printk(KERN_ERR "%s: Resetting controller.\n",
1309 mmc_hostname(host->mmc));
1311 sdhci_reset(host, SDHCI_RESET_CMD);
1312 sdhci_reset(host, SDHCI_RESET_DATA);
1314 host->mrq->cmd->error = -ENOMEDIUM;
1315 tasklet_schedule(&host->finish_tasklet);
1319 spin_unlock_irqrestore(&host->lock, flags);
1321 mmc_detect_change(host->mmc, msecs_to_jiffies(200));
1323 EXPORT_SYMBOL_GPL(sdhci_card_detect_callback);
1325 /*****************************************************************************\
1329 \*****************************************************************************/
1331 static void sdhci_tasklet_card(unsigned long param)
1333 struct sdhci_host *host;
1335 host = (struct sdhci_host *)param;
1337 sdhci_card_detect_callback(host);
1340 static void sdhci_tasklet_finish(unsigned long param)
1342 struct sdhci_host *host;
1343 unsigned long flags;
1344 struct mmc_request *mrq;
1346 host = (struct sdhci_host*)param;
1348 spin_lock_irqsave(&host->lock, flags);
1350 del_timer(&host->timer);
1355 * The controller needs a reset of internal state machines
1356 * upon error conditions.
1358 if (!(host->flags & SDHCI_DEVICE_DEAD) &&
1360 (mrq->data && (mrq->data->error ||
1361 (mrq->data->stop && mrq->data->stop->error))) ||
1362 (host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST))) {
1364 /* Some controllers need this kick or reset won't work here */
1365 if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET) {
1368 /* This is to force an update */
1369 clock = host->clock;
1371 sdhci_set_clock(host, clock);
1374 /* Spec says we should do both at the same time, but Ricoh
1375 controllers do not like that. */
1376 sdhci_reset(host, SDHCI_RESET_CMD);
1377 sdhci_reset(host, SDHCI_RESET_DATA);
1384 #ifndef SDHCI_USE_LEDS_CLASS
1385 sdhci_deactivate_led(host);
1389 spin_unlock_irqrestore(&host->lock, flags);
1391 mmc_request_done(host->mmc, mrq);
1394 static void sdhci_timeout_timer(unsigned long data)
1396 struct sdhci_host *host;
1397 unsigned long flags;
1399 host = (struct sdhci_host*)data;
1401 spin_lock_irqsave(&host->lock, flags);
1404 printk(KERN_ERR "%s: Timeout waiting for hardware "
1405 "interrupt.\n", mmc_hostname(host->mmc));
1406 sdhci_dumpregs(host);
1409 host->data->error = -ETIMEDOUT;
1410 sdhci_finish_data(host);
1413 host->cmd->error = -ETIMEDOUT;
1415 host->mrq->cmd->error = -ETIMEDOUT;
1417 tasklet_schedule(&host->finish_tasklet);
1422 spin_unlock_irqrestore(&host->lock, flags);
1425 /*****************************************************************************\
1427 * Interrupt handling *
1429 \*****************************************************************************/
1431 static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask)
1433 BUG_ON(intmask == 0);
1436 printk(KERN_ERR "%s: Got command interrupt 0x%08x even "
1437 "though no command operation was in progress.\n",
1438 mmc_hostname(host->mmc), (unsigned)intmask);
1439 sdhci_dumpregs(host);
1443 if (intmask & SDHCI_INT_TIMEOUT)
1444 host->cmd->error = -ETIMEDOUT;
1445 else if (intmask & (SDHCI_INT_CRC | SDHCI_INT_END_BIT |
1447 host->cmd->error = -EILSEQ;
1449 if (host->cmd->error) {
1450 if (intmask & SDHCI_INT_RESPONSE)
1451 tasklet_schedule(&host->finish_tasklet);
1456 * The host can send and interrupt when the busy state has
1457 * ended, allowing us to wait without wasting CPU cycles.
1458 * Unfortunately this is overloaded on the "data complete"
1459 * interrupt, so we need to take some care when handling
1462 * Note: The 1.0 specification is a bit ambiguous about this
1463 * feature so there might be some problems with older
1466 if (host->cmd->flags & MMC_RSP_BUSY) {
1467 if (host->cmd->data)
1468 DBG("Cannot wait for busy signal when also "
1469 "doing a data transfer");
1470 else if (!(host->quirks & SDHCI_QUIRK_NO_BUSY_IRQ))
1473 /* The controller does not support the end-of-busy IRQ,
1474 * fall through and take the SDHCI_INT_RESPONSE */
1477 if (intmask & SDHCI_INT_RESPONSE)
1478 sdhci_finish_command(host);
1482 static void sdhci_show_adma_error(struct sdhci_host *host)
1484 const char *name = mmc_hostname(host->mmc);
1485 u8 *desc = host->adma_desc;
1490 sdhci_dumpregs(host);
1493 dma = (__le32 *)(desc + 4);
1494 len = (__le16 *)(desc + 2);
1497 DBG("%s: %p: DMA 0x%08x, LEN 0x%04x, Attr=0x%02x\n",
1498 name, desc, le32_to_cpu(*dma), le16_to_cpu(*len), attr);
1507 static void sdhci_show_adma_error(struct sdhci_host *host) { }
1510 static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
1512 BUG_ON(intmask == 0);
1516 * The "data complete" interrupt is also used to
1517 * indicate that a busy state has ended. See comment
1518 * above in sdhci_cmd_irq().
1520 if (host->cmd && (host->cmd->flags & MMC_RSP_BUSY)) {
1521 if (intmask & SDHCI_INT_DATA_END) {
1522 sdhci_finish_command(host);
1527 printk(KERN_ERR "%s: Got data interrupt 0x%08x even "
1528 "though no data operation was in progress.\n",
1529 mmc_hostname(host->mmc), (unsigned)intmask);
1530 sdhci_dumpregs(host);
1535 if (intmask & SDHCI_INT_DATA_TIMEOUT)
1536 host->data->error = -ETIMEDOUT;
1537 else if (intmask & (SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_END_BIT))
1538 host->data->error = -EILSEQ;
1539 else if (intmask & SDHCI_INT_ADMA_ERROR) {
1540 printk(KERN_ERR "%s: ADMA error\n", mmc_hostname(host->mmc));
1541 sdhci_show_adma_error(host);
1542 host->data->error = -EIO;
1545 if (host->data->error)
1546 sdhci_finish_data(host);
1548 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
1549 sdhci_transfer_pio(host);
1552 * We currently don't do anything fancy with DMA
1553 * boundaries, but as we can't disable the feature
1554 * we need to at least restart the transfer.
1556 if (intmask & SDHCI_INT_DMA_END)
1557 sdhci_writel(host, sdhci_readl(host, SDHCI_DMA_ADDRESS),
1560 if (intmask & SDHCI_INT_DATA_END) {
1563 * Data managed to finish before the
1564 * command completed. Make sure we do
1565 * things in the proper order.
1567 host->data_early = 1;
1569 sdhci_finish_data(host);
1575 static irqreturn_t sdhci_irq(int irq, void *dev_id)
1578 struct sdhci_host* host = dev_id;
1582 spin_lock(&host->lock);
1584 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
1586 if (!intmask || intmask == 0xffffffff) {
1591 DBG("*** %s got interrupt: 0x%08x\n",
1592 mmc_hostname(host->mmc), intmask);
1594 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
1595 sdhci_writel(host, intmask & (SDHCI_INT_CARD_INSERT |
1596 SDHCI_INT_CARD_REMOVE), SDHCI_INT_STATUS);
1597 tasklet_schedule(&host->card_tasklet);
1600 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE);
1602 if (intmask & SDHCI_INT_CMD_MASK) {
1603 sdhci_writel(host, intmask & SDHCI_INT_CMD_MASK,
1605 sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK);
1608 if (intmask & SDHCI_INT_DATA_MASK) {
1609 sdhci_writel(host, intmask & SDHCI_INT_DATA_MASK,
1611 sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
1614 intmask &= ~(SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK);
1616 intmask &= ~SDHCI_INT_ERROR;
1618 if (intmask & SDHCI_INT_BUS_POWER) {
1619 printk(KERN_ERR "%s: Card is consuming too much power!\n",
1620 mmc_hostname(host->mmc));
1621 sdhci_writel(host, SDHCI_INT_BUS_POWER, SDHCI_INT_STATUS);
1624 intmask &= ~SDHCI_INT_BUS_POWER;
1626 if (intmask & SDHCI_INT_CARD_INT)
1629 intmask &= ~SDHCI_INT_CARD_INT;
1632 printk(KERN_ERR "%s: Unexpected interrupt 0x%08x.\n",
1633 mmc_hostname(host->mmc), intmask);
1634 sdhci_dumpregs(host);
1636 sdhci_writel(host, intmask, SDHCI_INT_STATUS);
1639 result = IRQ_HANDLED;
1643 spin_unlock(&host->lock);
1646 * We have to delay this as it calls back into the driver.
1649 mmc_signal_sdio_irq(host->mmc);
1654 /*****************************************************************************\
1658 \*****************************************************************************/
1662 int sdhci_suspend_host(struct sdhci_host *host, pm_message_t state)
1665 struct mmc_host *mmc = host->mmc;
1667 sdhci_disable_card_detection(host);
1669 if (mmc->card && (mmc->card->type != MMC_TYPE_SDIO))
1670 ret = mmc_suspend_host(host->mmc);
1672 sdhci_mask_irqs(host, SDHCI_INT_ALL_MASK);
1675 ret = regulator_disable(host->vmmc);
1678 disable_irq(host->irq);
1683 EXPORT_SYMBOL_GPL(sdhci_suspend_host);
1685 int sdhci_resume_host(struct sdhci_host *host)
1688 struct mmc_host *mmc = host->mmc;
1691 int ret = regulator_enable(host->vmmc);
1697 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
1698 if (host->ops->enable_dma)
1699 host->ops->enable_dma(host);
1703 enable_irq(host->irq);
1705 sdhci_init(host, (host->mmc->pm_flags & MMC_PM_KEEP_POWER));
1708 if (mmc->card && (mmc->card->type != MMC_TYPE_SDIO))
1709 ret = mmc_resume_host(host->mmc);
1711 sdhci_enable_card_detection(host);
1716 EXPORT_SYMBOL_GPL(sdhci_resume_host);
1718 #endif /* CONFIG_PM */
1720 /*****************************************************************************\
1722 * Device allocation/registration *
1724 \*****************************************************************************/
1726 struct sdhci_host *sdhci_alloc_host(struct device *dev,
1729 struct mmc_host *mmc;
1730 struct sdhci_host *host;
1732 WARN_ON(dev == NULL);
1734 mmc = mmc_alloc_host(sizeof(struct sdhci_host) + priv_size, dev);
1736 return ERR_PTR(-ENOMEM);
1738 host = mmc_priv(mmc);
1744 EXPORT_SYMBOL_GPL(sdhci_alloc_host);
1746 int sdhci_add_host(struct sdhci_host *host)
1748 struct mmc_host *mmc;
1752 WARN_ON(host == NULL);
1759 host->quirks = debug_quirks;
1761 sdhci_reset(host, SDHCI_RESET_ALL);
1763 if (!(host->quirks & SDHCI_QUIRK_NO_VERSION_REG)) {
1764 host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
1765 host->version = (host->version & SDHCI_SPEC_VER_MASK)
1766 >> SDHCI_SPEC_VER_SHIFT;
1769 if (host->version > SDHCI_SPEC_200) {
1770 printk(KERN_ERR "%s: Unknown controller version (%d). "
1771 "You may experience problems.\n", mmc_hostname(mmc),
1775 caps = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ? host->caps :
1776 sdhci_readl(host, SDHCI_CAPABILITIES);
1778 if (host->quirks & SDHCI_QUIRK_FORCE_DMA)
1779 host->flags |= SDHCI_USE_SDMA;
1780 else if (!(caps & SDHCI_CAN_DO_SDMA))
1781 DBG("Controller doesn't have SDMA capability\n");
1783 host->flags |= SDHCI_USE_SDMA;
1785 if ((host->quirks & SDHCI_QUIRK_BROKEN_DMA) &&
1786 (host->flags & SDHCI_USE_SDMA)) {
1787 DBG("Disabling DMA as it is marked broken\n");
1788 host->flags &= ~SDHCI_USE_SDMA;
1791 if ((host->version >= SDHCI_SPEC_200) && (caps & SDHCI_CAN_DO_ADMA2))
1792 host->flags |= SDHCI_USE_ADMA;
1794 if ((host->quirks & SDHCI_QUIRK_BROKEN_ADMA) &&
1795 (host->flags & SDHCI_USE_ADMA)) {
1796 DBG("Disabling ADMA as it is marked broken\n");
1797 host->flags &= ~SDHCI_USE_ADMA;
1800 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
1801 if (host->ops->enable_dma) {
1802 if (host->ops->enable_dma(host)) {
1803 printk(KERN_WARNING "%s: No suitable DMA "
1804 "available. Falling back to PIO.\n",
1807 ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA);
1812 if (host->flags & SDHCI_USE_ADMA) {
1814 * We need to allocate descriptors for all sg entries
1815 * (128) and potentially one alignment transfer for
1816 * each of those entries.
1818 host->adma_desc = kmalloc((128 * 2 + 1) * 4, GFP_KERNEL);
1819 host->align_buffer = kmalloc(128 * 4, GFP_KERNEL);
1820 if (!host->adma_desc || !host->align_buffer) {
1821 kfree(host->adma_desc);
1822 kfree(host->align_buffer);
1823 printk(KERN_WARNING "%s: Unable to allocate ADMA "
1824 "buffers. Falling back to standard DMA.\n",
1826 host->flags &= ~SDHCI_USE_ADMA;
1831 * If we use DMA, then it's up to the caller to set the DMA
1832 * mask, but PIO does not need the hw shim so we set a new
1833 * mask here in that case.
1835 if (!(host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))) {
1836 host->dma_mask = DMA_BIT_MASK(64);
1837 mmc_dev(host->mmc)->dma_mask = &host->dma_mask;
1841 (caps & SDHCI_CLOCK_BASE_MASK) >> SDHCI_CLOCK_BASE_SHIFT;
1842 host->max_clk *= 1000000;
1843 if (host->max_clk == 0 || host->quirks &
1844 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN) {
1845 if (!host->ops->get_max_clock) {
1847 "%s: Hardware doesn't specify base clock "
1848 "frequency.\n", mmc_hostname(mmc));
1851 host->max_clk = host->ops->get_max_clock(host);
1855 (caps & SDHCI_TIMEOUT_CLK_MASK) >> SDHCI_TIMEOUT_CLK_SHIFT;
1856 if (host->timeout_clk == 0) {
1857 if (host->ops->get_timeout_clock) {
1858 host->timeout_clk = host->ops->get_timeout_clock(host);
1859 } else if (!(host->quirks &
1860 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)) {
1862 "%s: Hardware doesn't specify timeout clock "
1863 "frequency.\n", mmc_hostname(mmc));
1867 if (caps & SDHCI_TIMEOUT_CLK_UNIT)
1868 host->timeout_clk *= 1000;
1871 * Set host parameters.
1873 mmc->ops = &sdhci_ops;
1874 if (host->ops->get_min_clock)
1875 mmc->f_min = host->ops->get_min_clock(host);
1877 mmc->f_min = host->max_clk / 256;
1878 mmc->f_max = host->max_clk;
1881 if (host->quirks & SDHCI_QUIRK_8_BIT_DATA)
1882 mmc->caps |= MMC_CAP_8_BIT_DATA;
1884 if (!(host->quirks & SDHCI_QUIRK_FORCE_1_BIT_DATA))
1885 mmc->caps |= MMC_CAP_4_BIT_DATA;
1887 if (!(host->quirks & SDHCI_QUIRK_NO_SDIO_IRQ))
1888 mmc->caps |= MMC_CAP_SDIO_IRQ;
1890 if (caps & SDHCI_CAN_DO_HISPD) {
1891 mmc->caps |= MMC_CAP_SD_HIGHSPEED;
1892 mmc->caps |= MMC_CAP_MMC_HIGHSPEED;
1895 if (host->quirks & SDHCI_QUIRK_FORCE_HIGH_SPEED_MODE)
1896 mmc->caps |= MMC_CAP_FORCE_HS;
1898 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
1899 mmc->caps |= MMC_CAP_NEEDS_POLL;
1901 if (host->quirks & SDHCI_QUIRK_RUNTIME_DISABLE) {
1902 mmc->caps |= MMC_CAP_DISABLE;
1903 mmc_set_disable_delay(mmc, 50);
1906 mmc->caps |= MMC_CAP_ERASE;
1909 if (caps & SDHCI_CAN_VDD_330)
1910 mmc->ocr_avail |= MMC_VDD_32_33|MMC_VDD_33_34;
1911 if (caps & SDHCI_CAN_VDD_300)
1912 mmc->ocr_avail |= MMC_VDD_29_30|MMC_VDD_30_31;
1913 if (caps & SDHCI_CAN_VDD_180)
1914 mmc->ocr_avail |= MMC_VDD_165_195;
1916 if (mmc->ocr_avail == 0) {
1917 printk(KERN_ERR "%s: Hardware doesn't report any "
1918 "support voltages.\n", mmc_hostname(mmc));
1922 spin_lock_init(&host->lock);
1925 * Maximum number of segments. Depends on if the hardware
1926 * can do scatter/gather or not.
1928 if (host->flags & SDHCI_USE_ADMA)
1929 mmc->max_hw_segs = 128;
1930 else if (host->flags & SDHCI_USE_SDMA)
1931 mmc->max_hw_segs = 1;
1933 mmc->max_hw_segs = 128;
1934 mmc->max_phys_segs = 128;
1937 * Maximum number of sectors in one transfer. Limited by DMA boundary
1940 mmc->max_req_size = 524288;
1943 * Maximum segment size. Could be one segment with the maximum number
1944 * of bytes. When doing hardware scatter/gather, each entry cannot
1945 * be larger than 64 KiB though.
1947 if (host->flags & SDHCI_USE_ADMA) {
1948 if (host->quirks & SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC)
1949 mmc->max_seg_size = 0xffff;
1951 mmc->max_seg_size = 65536;
1953 mmc->max_seg_size = mmc->max_req_size;
1957 * Maximum block size. This varies from controller to controller and
1958 * is specified in the capabilities register.
1960 if (host->quirks & SDHCI_QUIRK_FORCE_BLK_SZ_2048) {
1961 mmc->max_blk_size = 2;
1963 mmc->max_blk_size = (caps & SDHCI_MAX_BLOCK_MASK) >>
1964 SDHCI_MAX_BLOCK_SHIFT;
1965 if (mmc->max_blk_size >= 3) {
1966 printk(KERN_WARNING "%s: Invalid maximum block size, "
1967 "assuming 512 bytes\n", mmc_hostname(mmc));
1968 mmc->max_blk_size = 0;
1972 mmc->max_blk_size = 512 << mmc->max_blk_size;
1975 * Maximum block count.
1977 mmc->max_blk_count = (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535;
1982 tasklet_init(&host->card_tasklet,
1983 sdhci_tasklet_card, (unsigned long)host);
1984 tasklet_init(&host->finish_tasklet,
1985 sdhci_tasklet_finish, (unsigned long)host);
1987 setup_timer(&host->timer, sdhci_timeout_timer, (unsigned long)host);
1989 ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED,
1990 mmc_hostname(mmc), host);
1994 host->vmmc = regulator_get(mmc_dev(mmc), "vmmc");
1995 if (IS_ERR(host->vmmc)) {
1996 printk(KERN_INFO "%s: no vmmc regulator found\n", mmc_hostname(mmc));
1999 regulator_enable(host->vmmc);
2002 sdhci_init(host, 0);
2004 #ifdef CONFIG_MMC_DEBUG
2005 sdhci_dumpregs(host);
2008 #ifdef SDHCI_USE_LEDS_CLASS
2009 snprintf(host->led_name, sizeof(host->led_name),
2010 "%s::", mmc_hostname(mmc));
2011 host->led.name = host->led_name;
2012 host->led.brightness = LED_OFF;
2013 host->led.default_trigger = mmc_hostname(mmc);
2014 host->led.brightness_set = sdhci_led_control;
2016 ret = led_classdev_register(mmc_dev(mmc), &host->led);
2025 printk(KERN_INFO "%s: SDHCI controller on %s [%s] using %s\n",
2026 mmc_hostname(mmc), host->hw_name, dev_name(mmc_dev(mmc)),
2027 (host->flags & SDHCI_USE_ADMA) ? "ADMA" :
2028 (host->flags & SDHCI_USE_SDMA) ? "DMA" : "PIO");
2030 sdhci_enable_card_detection(host);
2034 #ifdef SDHCI_USE_LEDS_CLASS
2036 sdhci_reset(host, SDHCI_RESET_ALL);
2037 free_irq(host->irq, host);
2040 tasklet_kill(&host->card_tasklet);
2041 tasklet_kill(&host->finish_tasklet);
2046 EXPORT_SYMBOL_GPL(sdhci_add_host);
2048 void sdhci_remove_host(struct sdhci_host *host, int dead)
2050 unsigned long flags;
2053 spin_lock_irqsave(&host->lock, flags);
2055 host->flags |= SDHCI_DEVICE_DEAD;
2058 printk(KERN_ERR "%s: Controller removed during "
2059 " transfer!\n", mmc_hostname(host->mmc));
2061 host->mrq->cmd->error = -ENOMEDIUM;
2062 tasklet_schedule(&host->finish_tasklet);
2065 spin_unlock_irqrestore(&host->lock, flags);
2068 sdhci_disable_card_detection(host);
2070 mmc_remove_host(host->mmc);
2072 #ifdef SDHCI_USE_LEDS_CLASS
2073 led_classdev_unregister(&host->led);
2077 sdhci_reset(host, SDHCI_RESET_ALL);
2079 free_irq(host->irq, host);
2081 del_timer_sync(&host->timer);
2083 tasklet_kill(&host->card_tasklet);
2084 tasklet_kill(&host->finish_tasklet);
2087 regulator_disable(host->vmmc);
2088 regulator_put(host->vmmc);
2091 kfree(host->adma_desc);
2092 kfree(host->align_buffer);
2094 host->adma_desc = NULL;
2095 host->align_buffer = NULL;
2098 EXPORT_SYMBOL_GPL(sdhci_remove_host);
2100 void sdhci_free_host(struct sdhci_host *host)
2102 mmc_free_host(host->mmc);
2105 EXPORT_SYMBOL_GPL(sdhci_free_host);
2107 /*****************************************************************************\
2109 * Driver init/exit *
2111 \*****************************************************************************/
2113 static int __init sdhci_drv_init(void)
2115 printk(KERN_INFO DRIVER_NAME
2116 ": Secure Digital Host Controller Interface driver\n");
2117 printk(KERN_INFO DRIVER_NAME ": Copyright(c) Pierre Ossman\n");
2122 static void __exit sdhci_drv_exit(void)
2126 module_init(sdhci_drv_init);
2127 module_exit(sdhci_drv_exit);
2129 module_param(debug_quirks, uint, 0444);
2131 MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
2132 MODULE_DESCRIPTION("Secure Digital Host Controller Interface core driver");
2133 MODULE_LICENSE("GPL");
2135 MODULE_PARM_DESC(debug_quirks, "Force certain quirks.");