drivers/mmc/host/sdhci.c

   1 /*
   2  *  linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver
   3  *
   4  *  Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or (at
   9  * your option) any later version.
  10  *
  11  * Thanks to the following companies for their support:
  12  *
  13  *     - JMicron (hardware and technical support)
  14  */
  15
  16 #include <linux/delay.h>
  17 #include <linux/highmem.h>
  18 #include <linux/io.h>
  19 #include <linux/dma-mapping.h>
  20 #include <linux/slab.h>
  21 #include <linux/scatterlist.h>
  22 #include <linux/regulator/consumer.h>
  23
  24 #include <linux/leds.h>
  25
  26 #include <linux/mmc/mmc.h>
  27 #include <linux/mmc/host.h>
  28
  29 #include "sdhci.h"
  30
  31 #define DRIVER_NAME "sdhci"
  32
  33 #define DBG(f, x...) \
  34         pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x)
  35
  36 #if defined(CONFIG_LEDS_CLASS) || (defined(CONFIG_LEDS_CLASS_MODULE) && \
  37         defined(CONFIG_MMC_SDHCI_MODULE))
  38 #define SDHCI_USE_LEDS_CLASS
  39 #endif
  40
  41 #define MAX_TUNING_LOOP 40
  42
  43 static unsigned int debug_quirks = 0;
  44
  45 static void sdhci_finish_data(struct sdhci_host *);
  46
  47 static void sdhci_send_command(struct sdhci_host *, struct mmc_command *);
  48 static void sdhci_finish_command(struct sdhci_host *);
  49 static int sdhci_execute_tuning(struct mmc_host *mmc);
  50 static void sdhci_tuning_timer(unsigned long data);
  51
  52 static void sdhci_dumpregs(struct sdhci_host *host)
  53 {
  54         printk(KERN_DEBUG DRIVER_NAME ": =========== REGISTER DUMP (%s)===========\n",
  55                 mmc_hostname(host->mmc));
  56
  57         printk(KERN_DEBUG DRIVER_NAME ": Sys addr: 0x%08x | Version:  0x%08x\n",
  58                 sdhci_readl(host, SDHCI_DMA_ADDRESS),
  59                 sdhci_readw(host, SDHCI_HOST_VERSION));
  60         printk(KERN_DEBUG DRIVER_NAME ": Blk size: 0x%08x | Blk cnt:  0x%08x\n",
  61                 sdhci_readw(host, SDHCI_BLOCK_SIZE),
  62                 sdhci_readw(host, SDHCI_BLOCK_COUNT));
  63         printk(KERN_DEBUG DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n",
  64                 sdhci_readl(host, SDHCI_ARGUMENT),
  65                 sdhci_readw(host, SDHCI_TRANSFER_MODE));
  66         printk(KERN_DEBUG DRIVER_NAME ": Present:  0x%08x | Host ctl: 0x%08x\n",
  67                 sdhci_readl(host, SDHCI_PRESENT_STATE),
  68                 sdhci_readb(host, SDHCI_HOST_CONTROL));
  69         printk(KERN_DEBUG DRIVER_NAME ": Power:    0x%08x | Blk gap:  0x%08x\n",
  70                 sdhci_readb(host, SDHCI_POWER_CONTROL),
  71                 sdhci_readb(host, SDHCI_BLOCK_GAP_CONTROL));
  72         printk(KERN_DEBUG DRIVER_NAME ": Wake-up:  0x%08x | Clock:    0x%08x\n",
  73                 sdhci_readb(host, SDHCI_WAKE_UP_CONTROL),
  74                 sdhci_readw(host, SDHCI_CLOCK_CONTROL));
  75         printk(KERN_DEBUG DRIVER_NAME ": Timeout:  0x%08x | Int stat: 0x%08x\n",
  76                 sdhci_readb(host, SDHCI_TIMEOUT_CONTROL),
  77                 sdhci_readl(host, SDHCI_INT_STATUS));
  78         printk(KERN_DEBUG DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n",
  79                 sdhci_readl(host, SDHCI_INT_ENABLE),
  80                 sdhci_readl(host, SDHCI_SIGNAL_ENABLE));
  81         printk(KERN_DEBUG DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n",
  82                 sdhci_readw(host, SDHCI_ACMD12_ERR),
  83                 sdhci_readw(host, SDHCI_SLOT_INT_STATUS));
  84         printk(KERN_DEBUG DRIVER_NAME ": Caps:     0x%08x | Caps_1:   0x%08x\n",
  85                 sdhci_readl(host, SDHCI_CAPABILITIES),
  86                 sdhci_readl(host, SDHCI_CAPABILITIES_1));
  87         printk(KERN_DEBUG DRIVER_NAME ": Cmd:      0x%08x | Max curr: 0x%08x\n",
  88                 sdhci_readw(host, SDHCI_COMMAND),
  89                 sdhci_readl(host, SDHCI_MAX_CURRENT));
  90         printk(KERN_DEBUG DRIVER_NAME ": Host ctl2: 0x%08x\n",
  91                 sdhci_readw(host, SDHCI_HOST_CONTROL2));
  92
  93         if (host->flags & SDHCI_USE_ADMA)
  94                 printk(KERN_DEBUG DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x\n",
  95                        readl(host->ioaddr + SDHCI_ADMA_ERROR),
  96                        readl(host->ioaddr + SDHCI_ADMA_ADDRESS));
  97
  98         printk(KERN_DEBUG DRIVER_NAME ": ===========================================\n");
  99 }
 100
 101 /*****************************************************************************\
 102  *                                                                           *
 103  * Low level functions                                                       *
 104  *                                                                           *
 105 \*****************************************************************************/
 106
 107 static void sdhci_clear_set_irqs(struct sdhci_host *host, u32 clear, u32 set)
 108 {
 109         u32 ier;
 110
 111         ier = sdhci_readl(host, SDHCI_INT_ENABLE);
 112         ier &= ~clear;
 113         ier |= set;
 114         sdhci_writel(host, ier, SDHCI_INT_ENABLE);
 115         sdhci_writel(host, ier, SDHCI_SIGNAL_ENABLE);
 116 }
 117
 118 static void sdhci_unmask_irqs(struct sdhci_host *host, u32 irqs)
 119 {
 120         sdhci_clear_set_irqs(host, 0, irqs);
 121 }
 122
 123 static void sdhci_mask_irqs(struct sdhci_host *host, u32 irqs)
 124 {
 125         sdhci_clear_set_irqs(host, irqs, 0);
 126 }
 127
 128 static void sdhci_set_card_detection(struct sdhci_host *host, bool enable)
 129 {
 130         u32 irqs = SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT;
 131
 132         if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
 133                 return;
 134
 135         if (enable)
 136                 sdhci_unmask_irqs(host, irqs);
 137         else
 138                 sdhci_mask_irqs(host, irqs);
 139 }
 140
 141 static void sdhci_enable_card_detection(struct sdhci_host *host)
 142 {
 143         sdhci_set_card_detection(host, true);
 144 }
 145
 146 static void sdhci_disable_card_detection(struct sdhci_host *host)
 147 {
 148         sdhci_set_card_detection(host, false);
 149 }
 150
 151 static void sdhci_reset(struct sdhci_host *host, u8 mask)
 152 {
 153         unsigned long timeout;
 154         u32 uninitialized_var(ier);
 155
 156         if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
 157                 if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) &
 158                         SDHCI_CARD_PRESENT))
 159                         return;
 160         }
 161
 162         if (host->quirks & SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET)
 163                 ier = sdhci_readl(host, SDHCI_INT_ENABLE);
 164
 165         if (host->ops->platform_reset_enter)
 166                 host->ops->platform_reset_enter(host, mask);
 167
 168         sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
 169
 170         if (mask & SDHCI_RESET_ALL)
 171                 host->clock = 0;
 172
 173         /* Wait max 100 ms */
 174         timeout = 100;
 175
 176         /* hw clears the bit when it's done */
 177         while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) {
 178                 if (timeout == 0) {
 179                         printk(KERN_ERR "%s: Reset 0x%x never completed.\n",
 180                                 mmc_hostname(host->mmc), (int)mask);
 181                         sdhci_dumpregs(host);
 182                         return;
 183                 }
 184                 timeout--;
 185                 mdelay(1);
 186         }
 187
 188         if (host->ops->platform_reset_exit)
 189                 host->ops->platform_reset_exit(host, mask);
 190
 191         if (host->quirks & SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET)
 192                 sdhci_clear_set_irqs(host, SDHCI_INT_ALL_MASK, ier);
 193 }
 194
 195 static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios);
 196
 197 static void sdhci_init(struct sdhci_host *host, int soft)
 198 {
 199         if (soft)
 200                 sdhci_reset(host, SDHCI_RESET_CMD|SDHCI_RESET_DATA);
 201         else
 202                 sdhci_reset(host, SDHCI_RESET_ALL);
 203
 204         sdhci_clear_set_irqs(host, SDHCI_INT_ALL_MASK,
 205                 SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
 206                 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX |
 207                 SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT |
 208                 SDHCI_INT_DATA_END | SDHCI_INT_RESPONSE);
 209
 210         if (soft) {
 211                 /* force clock reconfiguration */
 212                 host->clock = 0;
 213                 sdhci_set_ios(host->mmc, &host->mmc->ios);
 214         }
 215 }
 216
 217 static void sdhci_reinit(struct sdhci_host *host)
 218 {
 219         sdhci_init(host, 0);
 220         sdhci_enable_card_detection(host);
 221 }
 222
 223 static void sdhci_activate_led(struct sdhci_host *host)
 224 {
 225         u8 ctrl;
 226
 227         ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
 228         ctrl |= SDHCI_CTRL_LED;
 229         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
 230 }
 231
 232 static void sdhci_deactivate_led(struct sdhci_host *host)
 233 {
 234         u8 ctrl;
 235
 236         ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
 237         ctrl &= ~SDHCI_CTRL_LED;
 238         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
 239 }
 240
 241 #ifdef SDHCI_USE_LEDS_CLASS
 242 static void sdhci_led_control(struct led_classdev *led,
 243         enum led_brightness brightness)
 244 {
 245         struct sdhci_host *host = container_of(led, struct sdhci_host, led);
 246         unsigned long flags;
 247
 248         spin_lock_irqsave(&host->lock, flags);
 249
 250         if (brightness == LED_OFF)
 251                 sdhci_deactivate_led(host);
 252         else
 253                 sdhci_activate_led(host);
 254
 255         spin_unlock_irqrestore(&host->lock, flags);
 256 }
 257 #endif
 258
 259 /*****************************************************************************\
 260  *                                                                           *
 261  * Core functions                                                            *
 262  *                                                                           *
 263 \*****************************************************************************/
 264
 265 static void sdhci_read_block_pio(struct sdhci_host *host)
 266 {
 267         unsigned long flags;
 268         size_t blksize, len, chunk;
 269         u32 uninitialized_var(scratch);
 270         u8 *buf;
 271
 272         DBG("PIO reading\n");
 273
 274         blksize = host->data->blksz;
 275         chunk = 0;
 276
 277         local_irq_save(flags);
 278
 279         while (blksize) {
 280                 if (!sg_miter_next(&host->sg_miter))
 281                         BUG();
 282
 283                 len = min(host->sg_miter.length, blksize);
 284
 285                 blksize -= len;
 286                 host->sg_miter.consumed = len;
 287
 288                 buf = host->sg_miter.addr;
 289
 290                 while (len) {
 291                         if (chunk == 0) {
 292                                 scratch = sdhci_readl(host, SDHCI_BUFFER);
 293                                 chunk = 4;
 294                         }
 295
 296                         *buf = scratch & 0xFF;
 297
 298                         buf++;
 299                         scratch >>= 8;
 300                         chunk--;
 301                         len--;
 302                 }
 303         }
 304
 305         sg_miter_stop(&host->sg_miter);
 306
 307         local_irq_restore(flags);
 308 }
 309
 310 static void sdhci_write_block_pio(struct sdhci_host *host)
 311 {
 312         unsigned long flags;
 313         size_t blksize, len, chunk;
 314         u32 scratch;
 315         u8 *buf;
 316
 317         DBG("PIO writing\n");
 318
 319         blksize = host->data->blksz;
 320         chunk = 0;
 321         scratch = 0;
 322
 323         local_irq_save(flags);
 324
 325         while (blksize) {
 326                 if (!sg_miter_next(&host->sg_miter))
 327                         BUG();
 328
 329                 len = min(host->sg_miter.length, blksize);
 330
 331                 blksize -= len;
 332                 host->sg_miter.consumed = len;
 333
 334                 buf = host->sg_miter.addr;
 335
 336                 while (len) {
 337                         scratch |= (u32)*buf << (chunk * 8);
 338
 339                         buf++;
 340                         chunk++;
 341                         len--;
 342
 343                         if ((chunk == 4) || ((len == 0) && (blksize == 0))) {
 344                                 sdhci_writel(host, scratch, SDHCI_BUFFER);
 345                                 chunk = 0;
 346                                 scratch = 0;
 347                         }
 348                 }
 349         }
 350
 351         sg_miter_stop(&host->sg_miter);
 352
 353         local_irq_restore(flags);
 354 }
 355
 356 static void sdhci_transfer_pio(struct sdhci_host *host)
 357 {
 358         u32 mask;
 359
 360         BUG_ON(!host->data);
 361
 362         if (host->blocks == 0)
 363                 return;
 364
 365         if (host->data->flags & MMC_DATA_READ)
 366                 mask = SDHCI_DATA_AVAILABLE;
 367         else
 368                 mask = SDHCI_SPACE_AVAILABLE;
 369
 370         /*
 371          * Some controllers (JMicron JMB38x) mess up the buffer bits
 372          * for transfers < 4 bytes. As long as it is just one block,
 373          * we can ignore the bits.
 374          */
 375         if ((host->quirks & SDHCI_QUIRK_BROKEN_SMALL_PIO) &&
 376                 (host->data->blocks == 1))
 377                 mask = ~0;
 378
 379         while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
 380                 if (host->quirks & SDHCI_QUIRK_PIO_NEEDS_DELAY)
 381                         udelay(100);
 382
 383                 if (host->data->flags & MMC_DATA_READ)
 384                         sdhci_read_block_pio(host);
 385                 else
 386                         sdhci_write_block_pio(host);
 387
 388                 host->blocks--;
 389                 if (host->blocks == 0)
 390                         break;
 391         }
 392
 393         DBG("PIO transfer complete.\n");
 394 }
 395
 396 static char *sdhci_kmap_atomic(struct scatterlist *sg, unsigned long *flags)
 397 {
 398         local_irq_save(*flags);
 399         return kmap_atomic(sg_page(sg), KM_BIO_SRC_IRQ) + sg->offset;
 400 }
 401
 402 static void sdhci_kunmap_atomic(void *buffer, unsigned long *flags)
 403 {
 404         kunmap_atomic(buffer, KM_BIO_SRC_IRQ);
 405         local_irq_restore(*flags);
 406 }
 407
 408 static void sdhci_set_adma_desc(u8 *desc, u32 addr, int len, unsigned cmd)
 409 {
 410         __le32 *dataddr = (__le32 __force *)(desc + 4);
 411         __le16 *cmdlen = (__le16 __force *)desc;
 412
 413         /* SDHCI specification says ADMA descriptors should be 4 byte
 414          * aligned, so using 16 or 32bit operations should be safe. */
 415
 416         cmdlen[0] = cpu_to_le16(cmd);
 417         cmdlen[1] = cpu_to_le16(len);
 418
 419         dataddr[0] = cpu_to_le32(addr);
 420 }
 421
 422 static int sdhci_adma_table_pre(struct sdhci_host *host,
 423         struct mmc_data *data)
 424 {
 425         int direction;
 426
 427         u8 *desc;
 428         u8 *align;
 429         dma_addr_t addr;
 430         dma_addr_t align_addr;
 431         int len, offset;
 432
 433         struct scatterlist *sg;
 434         int i;
 435         char *buffer;
 436         unsigned long flags;
 437
 438         /*
 439          * The spec does not specify endianness of descriptor table.
 440          * We currently guess that it is LE.
 441          */
 442
 443         if (data->flags & MMC_DATA_READ)
 444                 direction = DMA_FROM_DEVICE;
 445         else
 446                 direction = DMA_TO_DEVICE;
 447
 448         /*
 449          * The ADMA descriptor table is mapped further down as we
 450          * need to fill it with data first.
 451          */
 452
 453         host->align_addr = dma_map_single(mmc_dev(host->mmc),
 454                 host->align_buffer, 128 * 4, direction);
 455         if (dma_mapping_error(mmc_dev(host->mmc), host->align_addr))
 456                 goto fail;
 457         BUG_ON(host->align_addr & 0x3);
 458
 459         host->sg_count = dma_map_sg(mmc_dev(host->mmc),
 460                 data->sg, data->sg_len, direction);
 461         if (host->sg_count == 0)
 462                 goto unmap_align;
 463
 464         desc = host->adma_desc;
 465         align = host->align_buffer;
 466
 467         align_addr = host->align_addr;
 468
 469         for_each_sg(data->sg, sg, host->sg_count, i) {
 470                 addr = sg_dma_address(sg);
 471                 len = sg_dma_len(sg);
 472
 473                 /*
 474                  * The SDHCI specification states that ADMA
 475                  * addresses must be 32-bit aligned. If they
 476                  * aren't, then we use a bounce buffer for
 477                  * the (up to three) bytes that screw up the
 478                  * alignment.
 479                  */
 480                 offset = (4 - (addr & 0x3)) & 0x3;
 481                 if (offset) {
 482                         if (data->flags & MMC_DATA_WRITE) {
 483                                 buffer = sdhci_kmap_atomic(sg, &flags);
 484                                 WARN_ON(((long)buffer & PAGE_MASK) > (PAGE_SIZE - 3));
 485                                 memcpy(align, buffer, offset);
 486                                 sdhci_kunmap_atomic(buffer, &flags);
 487                         }
 488
 489                         /* tran, valid */
 490                         sdhci_set_adma_desc(desc, align_addr, offset, 0x21);
 491
 492                         BUG_ON(offset > 65536);
 493
 494                         align += 4;
 495                         align_addr += 4;
 496
 497                         desc += 8;
 498
 499                         addr += offset;
 500                         len -= offset;
 501                 }
 502
 503                 BUG_ON(len > 65536);
 504
 505                 /* tran, valid */
 506                 sdhci_set_adma_desc(desc, addr, len, 0x21);
 507                 desc += 8;
 508
 509                 /*
 510                  * If this triggers then we have a calculation bug
 511                  * somewhere. :/
 512                  */
 513                 WARN_ON((desc - host->adma_desc) > (128 * 2 + 1) * 4);
 514         }
 515
 516         if (host->quirks & SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC) {
 517                 /*
 518                 * Mark the last descriptor as the terminating descriptor
 519                 */
 520                 if (desc != host->adma_desc) {
 521                         desc -= 8;
 522                         desc[0] |= 0x2; /* end */
 523                 }
 524         } else {
 525                 /*
 526                 * Add a terminating entry.
 527                 */
 528
 529                 /* nop, end, valid */
 530                 sdhci_set_adma_desc(desc, 0, 0, 0x3);
 531         }
 532
 533         /*
 534          * Resync align buffer as we might have changed it.
 535          */
 536         if (data->flags & MMC_DATA_WRITE) {
 537                 dma_sync_single_for_device(mmc_dev(host->mmc),
 538                         host->align_addr, 128 * 4, direction);
 539         }
 540
 541         host->adma_addr = dma_map_single(mmc_dev(host->mmc),
 542                 host->adma_desc, (128 * 2 + 1) * 4, DMA_TO_DEVICE);
 543         if (dma_mapping_error(mmc_dev(host->mmc), host->adma_addr))
 544                 goto unmap_entries;
 545         BUG_ON(host->adma_addr & 0x3);
 546
 547         return 0;
 548
 549 unmap_entries:
 550         dma_unmap_sg(mmc_dev(host->mmc), data->sg,
 551                 data->sg_len, direction);
 552 unmap_align:
 553         dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
 554                 128 * 4, direction);
 555 fail:
 556         return -EINVAL;
 557 }
 558
 559 static void sdhci_adma_table_post(struct sdhci_host *host,
 560         struct mmc_data *data)
 561 {
 562         int direction;
 563
 564         struct scatterlist *sg;
 565         int i, size;
 566         u8 *align;
 567         char *buffer;
 568         unsigned long flags;
 569
 570         if (data->flags & MMC_DATA_READ)
 571                 direction = DMA_FROM_DEVICE;
 572         else
 573                 direction = DMA_TO_DEVICE;
 574
 575         dma_unmap_single(mmc_dev(host->mmc), host->adma_addr,
 576                 (128 * 2 + 1) * 4, DMA_TO_DEVICE);
 577
 578         dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
 579                 128 * 4, direction);
 580
 581         if (data->flags & MMC_DATA_READ) {
 582                 dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg,
 583                         data->sg_len, direction);
 584
 585                 align = host->align_buffer;
 586
 587                 for_each_sg(data->sg, sg, host->sg_count, i) {
 588                         if (sg_dma_address(sg) & 0x3) {
 589                                 size = 4 - (sg_dma_address(sg) & 0x3);
 590
 591                                 buffer = sdhci_kmap_atomic(sg, &flags);
 592                                 WARN_ON(((long)buffer & PAGE_MASK) > (PAGE_SIZE - 3));
 593                                 memcpy(buffer, align, size);
 594                                 sdhci_kunmap_atomic(buffer, &flags);
 595
 596                                 align += 4;
 597                         }
 598                 }
 599         }
 600
 601         dma_unmap_sg(mmc_dev(host->mmc), data->sg,
 602                 data->sg_len, direction);
 603 }
 604
 605 static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_command *cmd)
 606 {
 607         u8 count;
 608         struct mmc_data *data = cmd->data;
 609         unsigned target_timeout, current_timeout;
 610
 611         /*
 612          * If the host controller provides us with an incorrect timeout
 613          * value, just skip the check and use 0xE.  The hardware may take
 614          * longer to time out, but that's much better than having a too-short
 615          * timeout value.
 616          */
 617         if (host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL)
 618                 return 0xE;
 619
 620         /* Unspecified timeout, assume max */
 621         if (!data && !cmd->cmd_timeout_ms)
 622                 return 0xE;
 623
 624         /* timeout in us */
 625         if (!data)
 626                 target_timeout = cmd->cmd_timeout_ms * 1000;
 627         else
 628                 target_timeout = data->timeout_ns / 1000 +
 629                         data->timeout_clks / host->clock;
 630
 631         if (host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)
 632                 host->timeout_clk = host->clock / 1000;
 633
 634         /*
 635          * Figure out needed cycles.
 636          * We do this in steps in order to fit inside a 32 bit int.
 637          * The first step is the minimum timeout, which will have a
 638          * minimum resolution of 6 bits:
 639          * (1) 2^13*1000 > 2^22,
 640          * (2) host->timeout_clk < 2^16
 641          *     =>
 642          *     (1) / (2) > 2^6
 643          */
 644         BUG_ON(!host->timeout_clk);
 645         count = 0;
 646         current_timeout = (1 << 13) * 1000 / host->timeout_clk;
 647         while (current_timeout < target_timeout) {
 648                 count++;
 649                 current_timeout <<= 1;
 650                 if (count >= 0xF)
 651                         break;
 652         }
 653
 654         if (count >= 0xF) {
 655                 printk(KERN_WARNING "%s: Too large timeout requested for CMD%d!\n",
 656                        mmc_hostname(host->mmc), cmd->opcode);
 657                 count = 0xE;
 658         }
 659
 660         return count;
 661 }
 662
 663 static void sdhci_set_transfer_irqs(struct sdhci_host *host)
 664 {
 665         u32 pio_irqs = SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL;
 666         u32 dma_irqs = SDHCI_INT_DMA_END | SDHCI_INT_ADMA_ERROR;
 667
 668         if (host->flags & SDHCI_REQ_USE_DMA)
 669                 sdhci_clear_set_irqs(host, pio_irqs, dma_irqs);
 670         else
 671                 sdhci_clear_set_irqs(host, dma_irqs, pio_irqs);
 672 }
 673
 674 static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd)
 675 {
 676         u8 count;
 677         u8 ctrl;
 678         struct mmc_data *data = cmd->data;
 679         int ret;
 680
 681         WARN_ON(host->data);
 682
 683         if (data || (cmd->flags & MMC_RSP_BUSY)) {
 684                 count = sdhci_calc_timeout(host, cmd);
 685                 sdhci_writeb(host, count, SDHCI_TIMEOUT_CONTROL);
 686         }
 687
 688         if (!data)
 689                 return;
 690
 691         /* Sanity checks */
 692         BUG_ON(data->blksz * data->blocks > 524288);
 693         BUG_ON(data->blksz > host->mmc->max_blk_size);
 694         BUG_ON(data->blocks > 65535);
 695
 696         host->data = data;
 697         host->data_early = 0;
 698         host->data->bytes_xfered = 0;
 699
 700         if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))
 701                 host->flags |= SDHCI_REQ_USE_DMA;
 702
 703         /*
 704          * FIXME: This doesn't account for merging when mapping the
 705          * scatterlist.
 706          */
 707         if (host->flags & SDHCI_REQ_USE_DMA) {
 708                 int broken, i;
 709                 struct scatterlist *sg;
 710
 711                 broken = 0;
 712                 if (host->flags & SDHCI_USE_ADMA) {
 713                         if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
 714                                 broken = 1;
 715                 } else {
 716                         if (host->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE)
 717                                 broken = 1;
 718                 }
 719
 720                 if (unlikely(broken)) {
 721                         for_each_sg(data->sg, sg, data->sg_len, i) {
 722                                 if (sg->length & 0x3) {
 723                                         DBG("Reverting to PIO because of "
 724                                                 "transfer size (%d)\n",
 725                                                 sg->length);
 726                                         host->flags &= ~SDHCI_REQ_USE_DMA;
 727                                         break;
 728                                 }
 729                         }
 730                 }
 731         }
 732
 733         /*
 734          * The assumption here being that alignment is the same after
 735          * translation to device address space.
 736          */
 737         if (host->flags & SDHCI_REQ_USE_DMA) {
 738                 int broken, i;
 739                 struct scatterlist *sg;
 740
 741                 broken = 0;
 742                 if (host->flags & SDHCI_USE_ADMA) {
 743                         /*
 744                          * As we use 3 byte chunks to work around
 745                          * alignment problems, we need to check this
 746                          * quirk.
 747                          */
 748                         if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
 749                                 broken = 1;
 750                 } else {
 751                         if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR)
 752                                 broken = 1;
 753                 }
 754
 755                 if (unlikely(broken)) {
 756                         for_each_sg(data->sg, sg, data->sg_len, i) {
 757                                 if (sg->offset & 0x3) {
 758                                         DBG("Reverting to PIO because of "
 759                                                 "bad alignment\n");
 760                                         host->flags &= ~SDHCI_REQ_USE_DMA;
 761                                         break;
 762                                 }
 763                         }
 764                 }
 765         }
 766
 767         if (host->flags & SDHCI_REQ_USE_DMA) {
 768                 if (host->flags & SDHCI_USE_ADMA) {
 769                         ret = sdhci_adma_table_pre(host, data);
 770                         if (ret) {
 771                                 /*
 772                                  * This only happens when someone fed
 773                                  * us an invalid request.
 774                                  */
 775                                 WARN_ON(1);
 776                                 host->flags &= ~SDHCI_REQ_USE_DMA;
 777                         } else {
 778                                 sdhci_writel(host, host->adma_addr,
 779                                         SDHCI_ADMA_ADDRESS);
 780                         }
 781                 } else {
 782                         int sg_cnt;
 783
 784                         sg_cnt = dma_map_sg(mmc_dev(host->mmc),
 785                                         data->sg, data->sg_len,
 786                                         (data->flags & MMC_DATA_READ) ?
 787                                                 DMA_FROM_DEVICE :
 788                                                 DMA_TO_DEVICE);
 789                         if (sg_cnt == 0) {
 790                                 /*
 791                                  * This only happens when someone fed
 792                                  * us an invalid request.
 793                                  */
 794                                 WARN_ON(1);
 795                                 host->flags &= ~SDHCI_REQ_USE_DMA;
 796                         } else {
 797                                 WARN_ON(sg_cnt != 1);
 798                                 sdhci_writel(host, sg_dma_address(data->sg),
 799                                         SDHCI_DMA_ADDRESS);
 800                         }
 801                 }
 802         }
 803
 804         /*
 805          * Always adjust the DMA selection as some controllers
 806          * (e.g. JMicron) can't do PIO properly when the selection
 807          * is ADMA.
 808          */
 809         if (host->version >= SDHCI_SPEC_200) {
 810                 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
 811                 ctrl &= ~SDHCI_CTRL_DMA_MASK;
 812                 if ((host->flags & SDHCI_REQ_USE_DMA) &&
 813                         (host->flags & SDHCI_USE_ADMA))
 814                         ctrl |= SDHCI_CTRL_ADMA32;
 815                 else
 816                         ctrl |= SDHCI_CTRL_SDMA;
 817                 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
 818         }
 819
 820         if (!(host->flags & SDHCI_REQ_USE_DMA)) {
 821                 int flags;
 822
 823                 flags = SG_MITER_ATOMIC;
 824                 if (host->data->flags & MMC_DATA_READ)
 825                         flags |= SG_MITER_TO_SG;
 826                 else
 827                         flags |= SG_MITER_FROM_SG;
 828                 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
 829                 host->blocks = data->blocks;
 830         }
 831
 832         sdhci_set_transfer_irqs(host);
 833
 834         /* Set the DMA boundary value and block size */
 835         sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
 836                 data->blksz), SDHCI_BLOCK_SIZE);
 837         sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
 838 }
 839
 840 static void sdhci_set_transfer_mode(struct sdhci_host *host,
 841         struct mmc_command *cmd)
 842 {
 843         u16 mode;
 844         struct mmc_data *data = cmd->data;
 845
 846         if (data == NULL)
 847                 return;
 848
 849         WARN_ON(!host->data);
 850
 851         mode = SDHCI_TRNS_BLK_CNT_EN;
 852         if (mmc_op_multi(cmd->opcode) || data->blocks > 1) {
 853                 mode |= SDHCI_TRNS_MULTI;
 854                 /*
 855                  * If we are sending CMD23, CMD12 never gets sent
 856                  * on successful completion (so no Auto-CMD12).
 857                  */
 858                 if (!host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD12))
 859                         mode |= SDHCI_TRNS_AUTO_CMD12;
 860                 else if (host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD23)) {
 861                         mode |= SDHCI_TRNS_AUTO_CMD23;
 862                         sdhci_writel(host, host->mrq->sbc->arg, SDHCI_ARGUMENT2);
 863                 }
 864         }
 865
 866         if (data->flags & MMC_DATA_READ)
 867                 mode |= SDHCI_TRNS_READ;
 868         if (host->flags & SDHCI_REQ_USE_DMA)
 869                 mode |= SDHCI_TRNS_DMA;
 870
 871         sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
 872 }
 873
 874 static void sdhci_finish_data(struct sdhci_host *host)
 875 {
 876         struct mmc_data *data;
 877
 878         BUG_ON(!host->data);
 879
 880         data = host->data;
 881         host->data = NULL;
 882
 883         if (host->flags & SDHCI_REQ_USE_DMA) {
 884                 if (host->flags & SDHCI_USE_ADMA)
 885                         sdhci_adma_table_post(host, data);
 886                 else {
 887                         dma_unmap_sg(mmc_dev(host->mmc), data->sg,
 888                                 data->sg_len, (data->flags & MMC_DATA_READ) ?
 889                                         DMA_FROM_DEVICE : DMA_TO_DEVICE);
 890                 }
 891         }
 892
 893         /*
 894          * The specification states that the block count register must
 895          * be updated, but it does not specify at what point in the
 896          * data flow. That makes the register entirely useless to read
 897          * back so we have to assume that nothing made it to the card
 898          * in the event of an error.
 899          */
 900         if (data->error)
 901                 data->bytes_xfered = 0;
 902         else
 903                 data->bytes_xfered = data->blksz * data->blocks;
 904
 905         /*
 906          * Need to send CMD12 if -
 907          * a) open-ended multiblock transfer (no CMD23)
 908          * b) error in multiblock transfer
 909          */
 910         if (data->stop &&
 911             (data->error ||
 912              !host->mrq->sbc)) {
 913
 914                 /*
 915                  * The controller needs a reset of internal state machines
 916                  * upon error conditions.
 917                  */
 918                 if (data->error) {
 919                         sdhci_reset(host, SDHCI_RESET_CMD);
 920                         sdhci_reset(host, SDHCI_RESET_DATA);
 921                 }
 922
 923                 sdhci_send_command(host, data->stop);
 924         } else
 925                 tasklet_schedule(&host->finish_tasklet);
 926 }
 927
 928 static void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
 929 {
 930         int flags;
 931         u32 mask;
 932         unsigned long timeout;
 933
 934         WARN_ON(host->cmd);
 935
 936         /* Wait max 10 ms */
 937         timeout = 10;
 938
 939         mask = SDHCI_CMD_INHIBIT;
 940         if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY))
 941                 mask |= SDHCI_DATA_INHIBIT;
 942
 943         /* We shouldn't wait for data inihibit for stop commands, even
 944            though they might use busy signaling */
 945         if (host->mrq->data && (cmd == host->mrq->data->stop))
 946                 mask &= ~SDHCI_DATA_INHIBIT;
 947
 948         while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
 949                 if (timeout == 0) {
 950                         printk(KERN_ERR "%s: Controller never released "
 951                                 "inhibit bit(s).\n", mmc_hostname(host->mmc));
 952                         sdhci_dumpregs(host);
 953                         cmd->error = -EIO;
 954                         tasklet_schedule(&host->finish_tasklet);
 955                         return;
 956                 }
 957                 timeout--;
 958                 mdelay(1);
 959         }
 960
 961         mod_timer(&host->timer, jiffies + 10 * HZ);
 962
 963         host->cmd = cmd;
 964
 965         sdhci_prepare_data(host, cmd);
 966
 967         sdhci_writel(host, cmd->arg, SDHCI_ARGUMENT);
 968
 969         sdhci_set_transfer_mode(host, cmd);
 970
 971         if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
 972                 printk(KERN_ERR "%s: Unsupported response type!\n",
 973                         mmc_hostname(host->mmc));
 974                 cmd->error = -EINVAL;
 975                 tasklet_schedule(&host->finish_tasklet);
 976                 return;
 977         }
 978
 979         if (!(cmd->flags & MMC_RSP_PRESENT))
 980                 flags = SDHCI_CMD_RESP_NONE;
 981         else if (cmd->flags & MMC_RSP_136)
 982                 flags = SDHCI_CMD_RESP_LONG;
 983         else if (cmd->flags & MMC_RSP_BUSY)
 984                 flags = SDHCI_CMD_RESP_SHORT_BUSY;
 985         else
 986                 flags = SDHCI_CMD_RESP_SHORT;
 987
 988         if (cmd->flags & MMC_RSP_CRC)
 989                 flags |= SDHCI_CMD_CRC;
 990         if (cmd->flags & MMC_RSP_OPCODE)
 991                 flags |= SDHCI_CMD_INDEX;
 992
 993         /* CMD19 is special in that the Data Present Select should be set */
 994         if (cmd->data || (cmd->opcode == MMC_SEND_TUNING_BLOCK))
 995                 flags |= SDHCI_CMD_DATA;
 996
 997         sdhci_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND);
 998 }
 999
1000 static void sdhci_finish_command(struct sdhci_host *host)
1001 {
1002         int i;
1003
1004         BUG_ON(host->cmd == NULL);
1005
1006         if (host->cmd->flags & MMC_RSP_PRESENT) {
1007                 if (host->cmd->flags & MMC_RSP_136) {
1008                         /* CRC is stripped so we need to do some shifting. */
1009                         for (i = 0;i < 4;i++) {
1010                                 host->cmd->resp[i] = sdhci_readl(host,
1011                                         SDHCI_RESPONSE + (3-i)*4) << 8;
1012                                 if (i != 3)
1013                                         host->cmd->resp[i] |=
1014                                                 sdhci_readb(host,
1015                                                 SDHCI_RESPONSE + (3-i)*4-1);
1016                         }
1017                 } else {
1018                         host->cmd->resp[0] = sdhci_readl(host, SDHCI_RESPONSE);
1019                 }
1020         }
1021
1022         host->cmd->error = 0;
1023
1024         /* Finished CMD23, now send actual command. */
1025         if (host->cmd == host->mrq->sbc) {
1026                 host->cmd = NULL;
1027                 sdhci_send_command(host, host->mrq->cmd);
1028         } else {
1029
1030                 /* Processed actual command. */
1031                 if (host->data && host->data_early)
1032                         sdhci_finish_data(host);
1033
1034                 if (!host->cmd->data)
1035                         tasklet_schedule(&host->finish_tasklet);
1036
1037                 host->cmd = NULL;
1038         }
1039 }
1040
1041 static void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
1042 {
1043         int div = 0; /* Initialized for compiler warning */
1044         u16 clk = 0;
1045         unsigned long timeout;
1046
1047         if (clock && clock == host->clock)
1048                 return;
1049
1050         if (host->ops->set_clock) {
1051                 host->ops->set_clock(host, clock);
1052                 if (host->quirks & SDHCI_QUIRK_NONSTANDARD_CLOCK)
1053                         return;
1054         }
1055
1056         sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
1057
1058         if (clock == 0)
1059                 goto out;
1060
1061         if (host->version >= SDHCI_SPEC_300) {
1062                 /*
1063                  * Check if the Host Controller supports Programmable Clock
1064                  * Mode.
1065                  */
1066                 if (host->clk_mul) {
1067                         u16 ctrl;
1068
1069                         /*
1070                          * We need to figure out whether the Host Driver needs
1071                          * to select Programmable Clock Mode, or the value can
1072                          * be set automatically by the Host Controller based on
1073                          * the Preset Value registers.
1074                          */
1075                         ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1076                         if (!(ctrl & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
1077                                 for (div = 1; div <= 1024; div++) {
1078                                         if (((host->max_clk * host->clk_mul) /
1079                                               div) <= clock)
1080                                                 break;
1081                                 }
1082                                 /*
1083                                  * Set Programmable Clock Mode in the Clock
1084                                  * Control register.
1085                                  */
1086                                 clk = SDHCI_PROG_CLOCK_MODE;
1087                                 div--;
1088                         }
1089                 } else {
1090                         /* Version 3.00 divisors must be a multiple of 2. */
1091                         if (host->max_clk <= clock)
1092                                 div = 1;
1093                         else {
1094                                 for (div = 2; div < SDHCI_MAX_DIV_SPEC_300;
1095                                      div += 2) {
1096                                         if ((host->max_clk / div) <= clock)
1097                                                 break;
1098                                 }
1099                         }
1100                         div >>= 1;
1101                 }
1102         } else {
1103                 /* Version 2.00 divisors must be a power of 2. */
1104                 for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
1105                         if ((host->max_clk / div) <= clock)
1106                                 break;
1107                 }
1108                 div >>= 1;
1109         }
1110
1111         clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
1112         clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
1113                 << SDHCI_DIVIDER_HI_SHIFT;
1114         clk |= SDHCI_CLOCK_INT_EN;
1115         sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1116
1117         /* Wait max 20 ms */
1118         timeout = 20;
1119         while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
1120                 & SDHCI_CLOCK_INT_STABLE)) {
1121                 if (timeout == 0) {
1122                         printk(KERN_ERR "%s: Internal clock never "
1123                                 "stabilised.\n", mmc_hostname(host->mmc));
1124                         sdhci_dumpregs(host);
1125                         return;
1126                 }
1127                 timeout--;
1128                 mdelay(1);
1129         }
1130
1131         clk |= SDHCI_CLOCK_CARD_EN;
1132         sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1133
1134 out:
1135         host->clock = clock;
1136 }
1137
1138 static void sdhci_set_power(struct sdhci_host *host, unsigned short power)
1139 {
1140         u8 pwr = 0;
1141
1142         if (power != (unsigned short)-1) {
1143                 switch (1 << power) {
1144                 case MMC_VDD_165_195:
1145                         pwr = SDHCI_POWER_180;
1146                         break;
1147                 case MMC_VDD_29_30:
1148                 case MMC_VDD_30_31:
1149                         pwr = SDHCI_POWER_300;
1150                         break;
1151                 case MMC_VDD_32_33:
1152                 case MMC_VDD_33_34:
1153                         pwr = SDHCI_POWER_330;
1154                         break;
1155                 default:
1156                         BUG();
1157                 }
1158         }
1159
1160         if (host->pwr == pwr)
1161                 return;
1162
1163         host->pwr = pwr;
1164
1165         if (pwr == 0) {
1166                 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1167                 return;
1168         }
1169
1170         /*
1171          * Spec says that we should clear the power reg before setting
1172          * a new value. Some controllers don't seem to like this though.
1173          */
1174         if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE))
1175                 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1176
1177         /*
1178          * At least the Marvell CaFe chip gets confused if we set the voltage
1179          * and set turn on power at the same time, so set the voltage first.
1180          */
1181         if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER)
1182                 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1183
1184         pwr |= SDHCI_POWER_ON;
1185
1186         sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1187
1188         /*
1189          * Some controllers need an extra 10ms delay of 10ms before they
1190          * can apply clock after applying power
1191          */
1192         if (host->quirks & SDHCI_QUIRK_DELAY_AFTER_POWER)
1193                 mdelay(10);
1194 }
1195
1196 /*****************************************************************************\
1197  *                                                                           *
1198  * MMC callbacks                                                             *
1199  *                                                                           *
1200 \*****************************************************************************/
1201
1202 static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1203 {
1204         struct sdhci_host *host;
1205         bool present;
1206         unsigned long flags;
1207
1208         host = mmc_priv(mmc);
1209
1210         spin_lock_irqsave(&host->lock, flags);
1211
1212         WARN_ON(host->mrq != NULL);
1213
1214 #ifndef SDHCI_USE_LEDS_CLASS
1215         sdhci_activate_led(host);
1216 #endif
1217
1218         /*
1219          * Ensure we don't send the STOP for non-SET_BLOCK_COUNTED
1220          * requests if Auto-CMD12 is enabled.
1221          */
1222         if (!mrq->sbc && (host->flags & SDHCI_AUTO_CMD12)) {
1223                 if (mrq->stop) {
1224                         mrq->data->stop = NULL;
1225                         mrq->stop = NULL;
1226                 }
1227         }
1228
1229         host->mrq = mrq;
1230
1231         /* If polling, assume that the card is always present. */
1232         if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
1233                 present = true;
1234         else
1235                 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
1236                                 SDHCI_CARD_PRESENT;
1237
1238         if (!present || host->flags & SDHCI_DEVICE_DEAD) {
1239                 host->mrq->cmd->error = -ENOMEDIUM;
1240                 tasklet_schedule(&host->finish_tasklet);
1241         } else {
1242                 u32 present_state;
1243
1244                 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
1245                 /*
1246                  * Check if the re-tuning timer has already expired and there
1247                  * is no on-going data transfer. If so, we need to execute
1248                  * tuning procedure before sending command.
1249                  */
1250                 if ((host->flags & SDHCI_NEEDS_RETUNING) &&
1251                     !(present_state & (SDHCI_DOING_WRITE | SDHCI_DOING_READ))) {
1252                         spin_unlock_irqrestore(&host->lock, flags);
1253                         sdhci_execute_tuning(mmc);
1254                         spin_lock_irqsave(&host->lock, flags);
1255
1256                         /* Restore original mmc_request structure */
1257                         host->mrq = mrq;
1258                 }
1259
1260                 if (mrq->sbc && !(host->flags & SDHCI_AUTO_CMD23))
1261                         sdhci_send_command(host, mrq->sbc);
1262                 else
1263                         sdhci_send_command(host, mrq->cmd);
1264         }
1265
1266         mmiowb();
1267         spin_unlock_irqrestore(&host->lock, flags);
1268 }
1269
1270 static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1271 {
1272         struct sdhci_host *host;
1273         unsigned long flags;
1274         u8 ctrl;
1275
1276         host = mmc_priv(mmc);
1277
1278         spin_lock_irqsave(&host->lock, flags);
1279
1280         if (host->flags & SDHCI_DEVICE_DEAD)
1281                 goto out;
1282
1283         /*
1284          * Reset the chip on each power off.
1285          * Should clear out any weird states.
1286          */
1287         if (ios->power_mode == MMC_POWER_OFF) {
1288                 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
1289                 sdhci_reinit(host);
1290         }
1291
1292         sdhci_set_clock(host, ios->clock);
1293
1294         if (ios->power_mode == MMC_POWER_OFF)
1295                 sdhci_set_power(host, -1);
1296         else
1297                 sdhci_set_power(host, ios->vdd);
1298
1299         if (host->ops->platform_send_init_74_clocks)
1300                 host->ops->platform_send_init_74_clocks(host, ios->power_mode);
1301
1302         /*
1303          * If your platform has 8-bit width support but is not a v3 controller,
1304          * or if it requires special setup code, you should implement that in
1305          * platform_8bit_width().
1306          */
1307         if (host->ops->platform_8bit_width)
1308                 host->ops->platform_8bit_width(host, ios->bus_width);
1309         else {
1310                 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1311                 if (ios->bus_width == MMC_BUS_WIDTH_8) {
1312                         ctrl &= ~SDHCI_CTRL_4BITBUS;
1313                         if (host->version >= SDHCI_SPEC_300)
1314                                 ctrl |= SDHCI_CTRL_8BITBUS;
1315                 } else {
1316                         if (host->version >= SDHCI_SPEC_300)
1317                                 ctrl &= ~SDHCI_CTRL_8BITBUS;
1318                         if (ios->bus_width == MMC_BUS_WIDTH_4)
1319                                 ctrl |= SDHCI_CTRL_4BITBUS;
1320                         else
1321                                 ctrl &= ~SDHCI_CTRL_4BITBUS;
1322                 }
1323                 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1324         }
1325
1326         ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1327
1328         if ((ios->timing == MMC_TIMING_SD_HS ||
1329              ios->timing == MMC_TIMING_MMC_HS)
1330             && !(host->quirks & SDHCI_QUIRK_NO_HISPD_BIT))
1331                 ctrl |= SDHCI_CTRL_HISPD;
1332         else
1333                 ctrl &= ~SDHCI_CTRL_HISPD;
1334
1335         if (host->version >= SDHCI_SPEC_300) {
1336                 u16 clk, ctrl_2;
1337                 unsigned int clock;
1338
1339                 /* In case of UHS-I modes, set High Speed Enable */
1340                 if ((ios->timing == MMC_TIMING_UHS_SDR50) ||
1341                     (ios->timing == MMC_TIMING_UHS_SDR104) ||
1342                     (ios->timing == MMC_TIMING_UHS_DDR50) ||
1343                     (ios->timing == MMC_TIMING_UHS_SDR25))
1344                         ctrl |= SDHCI_CTRL_HISPD;
1345
1346                 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1347                 if (!(ctrl_2 & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
1348                         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1349                         /*
1350                          * We only need to set Driver Strength if the
1351                          * preset value enable is not set.
1352                          */
1353                         ctrl_2 &= ~SDHCI_CTRL_DRV_TYPE_MASK;
1354                         if (ios->drv_type == MMC_SET_DRIVER_TYPE_A)
1355                                 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_A;
1356                         else if (ios->drv_type == MMC_SET_DRIVER_TYPE_C)
1357                                 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_C;
1358
1359                         sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1360                 } else {
1361                         /*
1362                          * According to SDHC Spec v3.00, if the Preset Value
1363                          * Enable in the Host Control 2 register is set, we
1364                          * need to reset SD Clock Enable before changing High
1365                          * Speed Enable to avoid generating clock gliches.
1366                          */
1367
1368                         /* Reset SD Clock Enable */
1369                         clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1370                         clk &= ~SDHCI_CLOCK_CARD_EN;
1371                         sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1372
1373                         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1374
1375                         /* Re-enable SD Clock */
1376                         clock = host->clock;
1377                         host->clock = 0;
1378                         sdhci_set_clock(host, clock);
1379                 }
1380
1381
1382                 /* Reset SD Clock Enable */
1383                 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1384                 clk &= ~SDHCI_CLOCK_CARD_EN;
1385                 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1386
1387                 if (host->ops->set_uhs_signaling)
1388                         host->ops->set_uhs_signaling(host, ios->timing);
1389                 else {
1390                         ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1391                         /* Select Bus Speed Mode for host */
1392                         ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
1393                         if (ios->timing == MMC_TIMING_UHS_SDR12)
1394                                 ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
1395                         else if (ios->timing == MMC_TIMING_UHS_SDR25)
1396                                 ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
1397                         else if (ios->timing == MMC_TIMING_UHS_SDR50)
1398                                 ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
1399                         else if (ios->timing == MMC_TIMING_UHS_SDR104)
1400                                 ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
1401                         else if (ios->timing == MMC_TIMING_UHS_DDR50)
1402                                 ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
1403                         sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1404                 }
1405
1406                 /* Re-enable SD Clock */
1407                 clock = host->clock;
1408                 host->clock = 0;
1409                 sdhci_set_clock(host, clock);
1410         } else
1411                 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1412
1413         /*
1414          * Some (ENE) controllers go apeshit on some ios operation,
1415          * signalling timeout and CRC errors even on CMD0. Resetting
1416          * it on each ios seems to solve the problem.
1417          */
1418         if(host->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS)
1419                 sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
1420
1421 out:
1422         mmiowb();
1423         spin_unlock_irqrestore(&host->lock, flags);
1424 }
1425
1426 static int check_ro(struct sdhci_host *host)
1427 {
1428         unsigned long flags;
1429         int is_readonly;
1430
1431         spin_lock_irqsave(&host->lock, flags);
1432
1433         if (host->flags & SDHCI_DEVICE_DEAD)
1434                 is_readonly = 0;
1435         else if (host->ops->get_ro)
1436                 is_readonly = host->ops->get_ro(host);
1437         else
1438                 is_readonly = !(sdhci_readl(host, SDHCI_PRESENT_STATE)
1439                                 & SDHCI_WRITE_PROTECT);
1440
1441         spin_unlock_irqrestore(&host->lock, flags);
1442
1443         /* This quirk needs to be replaced by a callback-function later */
1444         return host->quirks & SDHCI_QUIRK_INVERTED_WRITE_PROTECT ?
1445                 !is_readonly : is_readonly;
1446 }
1447
1448 #define SAMPLE_COUNT    5
1449
1450 static int sdhci_get_ro(struct mmc_host *mmc)
1451 {
1452         struct sdhci_host *host;
1453         int i, ro_count;
1454
1455         host = mmc_priv(mmc);
1456
1457         if (!(host->quirks & SDHCI_QUIRK_UNSTABLE_RO_DETECT))
1458                 return check_ro(host);
1459
1460         ro_count = 0;
1461         for (i = 0; i < SAMPLE_COUNT; i++) {
1462                 if (check_ro(host)) {
1463                         if (++ro_count > SAMPLE_COUNT / 2)
1464                                 return 1;
1465                 }
1466                 msleep(30);
1467         }
1468         return 0;
1469 }
1470
1471 static void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable)
1472 {
1473         struct sdhci_host *host;
1474         unsigned long flags;
1475
1476         host = mmc_priv(mmc);
1477
1478         spin_lock_irqsave(&host->lock, flags);
1479
1480         if (host->flags & SDHCI_DEVICE_DEAD)
1481                 goto out;
1482
1483         if (enable)
1484                 sdhci_unmask_irqs(host, SDHCI_INT_CARD_INT);
1485         else
1486                 sdhci_mask_irqs(host, SDHCI_INT_CARD_INT);
1487 out:
1488         mmiowb();
1489
1490         spin_unlock_irqrestore(&host->lock, flags);
1491 }
1492
1493 static int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
1494         struct mmc_ios *ios)
1495 {
1496         struct sdhci_host *host;
1497         u8 pwr;
1498         u16 clk, ctrl;
1499         u32 present_state;
1500
1501         host = mmc_priv(mmc);
1502
1503         /*
1504          * Signal Voltage Switching is only applicable for Host Controllers
1505          * v3.00 and above.
1506          */
1507         if (host->version < SDHCI_SPEC_300)
1508                 return 0;
1509
1510         /*
1511          * We first check whether the request is to set signalling voltage
1512          * to 3.3V. If so, we change the voltage to 3.3V and return quickly.
1513          */
1514         ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1515         if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330) {
1516                 /* Set 1.8V Signal Enable in the Host Control2 register to 0 */
1517                 ctrl &= ~SDHCI_CTRL_VDD_180;
1518                 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1519
1520                 /* Wait for 5ms */
1521                 usleep_range(5000, 5500);
1522
1523                 /* 3.3V regulator output should be stable within 5 ms */
1524                 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1525                 if (!(ctrl & SDHCI_CTRL_VDD_180))
1526                         return 0;
1527                 else {
1528                         printk(KERN_INFO DRIVER_NAME ": Switching to 3.3V "
1529                                 "signalling voltage failed\n");
1530                         return -EIO;
1531                 }
1532         } else if (!(ctrl & SDHCI_CTRL_VDD_180) &&
1533                   (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180)) {
1534                 /* Stop SDCLK */
1535                 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1536                 clk &= ~SDHCI_CLOCK_CARD_EN;
1537                 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1538
1539                 /* Check whether DAT[3:0] is 0000 */
1540                 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
1541                 if (!((present_state & SDHCI_DATA_LVL_MASK) >>
1542                        SDHCI_DATA_LVL_SHIFT)) {
1543                         /*
1544                          * Enable 1.8V Signal Enable in the Host Control2
1545                          * register
1546                          */
1547                         ctrl |= SDHCI_CTRL_VDD_180;
1548                         sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1549
1550                         /* Wait for 5ms */
1551                         usleep_range(5000, 5500);
1552
1553                         ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1554                         if (ctrl & SDHCI_CTRL_VDD_180) {
1555                                 /* Provide SDCLK again and wait for 1ms*/
1556                                 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1557                                 clk |= SDHCI_CLOCK_CARD_EN;
1558                                 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1559                                 usleep_range(1000, 1500);
1560
1561                                 /*
1562                                  * If DAT[3:0] level is 1111b, then the card
1563                                  * was successfully switched to 1.8V signaling.
1564                                  */
1565                                 present_state = sdhci_readl(host,
1566                                                         SDHCI_PRESENT_STATE);
1567                                 if ((present_state & SDHCI_DATA_LVL_MASK) ==
1568                                      SDHCI_DATA_LVL_MASK)
1569                                         return 0;
1570                         }
1571                 }
1572
1573                 /*
1574                  * If we are here, that means the switch to 1.8V signaling
1575                  * failed. We power cycle the card, and retry initialization
1576                  * sequence by setting S18R to 0.
1577                  */
1578                 pwr = sdhci_readb(host, SDHCI_POWER_CONTROL);
1579                 pwr &= ~SDHCI_POWER_ON;
1580                 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1581
1582                 /* Wait for 1ms as per the spec */
1583                 usleep_range(1000, 1500);
1584                 pwr |= SDHCI_POWER_ON;
1585                 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1586
1587                 printk(KERN_INFO DRIVER_NAME ": Switching to 1.8V signalling "
1588                         "voltage failed, retrying with S18R set to 0\n");
1589                 return -EAGAIN;
1590         } else
1591                 /* No signal voltage switch required */
1592                 return 0;
1593 }
1594
1595 static int sdhci_execute_tuning(struct mmc_host *mmc)
1596 {
1597         struct sdhci_host *host;
1598         u16 ctrl;
1599         u32 ier;
1600         int tuning_loop_counter = MAX_TUNING_LOOP;
1601         unsigned long timeout;
1602         int err = 0;
1603
1604         host = mmc_priv(mmc);
1605
1606         disable_irq(host->irq);
1607         spin_lock(&host->lock);
1608
1609         ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1610
1611         /*
1612          * Host Controller needs tuning only in case of SDR104 mode
1613          * and for SDR50 mode when Use Tuning for SDR50 is set in
1614          * Capabilities register.
1615          */
1616         if (((ctrl & SDHCI_CTRL_UHS_MASK) == SDHCI_CTRL_UHS_SDR104) ||
1617             (((ctrl & SDHCI_CTRL_UHS_MASK) == SDHCI_CTRL_UHS_SDR50) &&
1618             (host->flags & SDHCI_SDR50_NEEDS_TUNING)))
1619                 ctrl |= SDHCI_CTRL_EXEC_TUNING;
1620         else {
1621                 spin_unlock(&host->lock);
1622                 enable_irq(host->irq);
1623                 return 0;
1624         }
1625
1626         sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1627
1628         /*
1629          * As per the Host Controller spec v3.00, tuning command
1630          * generates Buffer Read Ready interrupt, so enable that.
1631          *
1632          * Note: The spec clearly says that when tuning sequence
1633          * is being performed, the controller does not generate
1634          * interrupts other than Buffer Read Ready interrupt. But
1635          * to make sure we don't hit a controller bug, we _only_
1636          * enable Buffer Read Ready interrupt here.
1637          */
1638         ier = sdhci_readl(host, SDHCI_INT_ENABLE);
1639         sdhci_clear_set_irqs(host, ier, SDHCI_INT_DATA_AVAIL);
1640
1641         /*
1642          * Issue CMD19 repeatedly till Execute Tuning is set to 0 or the number
1643          * of loops reaches 40 times or a timeout of 150ms occurs.
1644          */
1645         timeout = 150;
1646         do {
1647                 struct mmc_command cmd = {0};
1648                 struct mmc_request mrq = {0};
1649
1650                 if (!tuning_loop_counter && !timeout)
1651                         break;
1652
1653                 cmd.opcode = MMC_SEND_TUNING_BLOCK;
1654                 cmd.arg = 0;
1655                 cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC;
1656                 cmd.retries = 0;
1657                 cmd.data = NULL;
1658                 cmd.error = 0;
1659
1660                 mrq.cmd = &cmd;
1661                 host->mrq = &mrq;
1662
1663                 /*
1664                  * In response to CMD19, the card sends 64 bytes of tuning
1665                  * block to the Host Controller. So we set the block size
1666                  * to 64 here.
1667                  */
1668                 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64), SDHCI_BLOCK_SIZE);
1669
1670                 /*
1671                  * The tuning block is sent by the card to the host controller.
1672                  * So we set the TRNS_READ bit in the Transfer Mode register.
1673                  * This also takes care of setting DMA Enable and Multi Block
1674                  * Select in the same register to 0.
1675                  */
1676                 sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE);
1677
1678                 sdhci_send_command(host, &cmd);
1679
1680                 host->cmd = NULL;
1681                 host->mrq = NULL;
1682
1683                 spin_unlock(&host->lock);
1684                 enable_irq(host->irq);
1685
1686                 /* Wait for Buffer Read Ready interrupt */
1687                 wait_event_interruptible_timeout(host->buf_ready_int,
1688                                         (host->tuning_done == 1),
1689                                         msecs_to_jiffies(50));
1690                 disable_irq(host->irq);
1691                 spin_lock(&host->lock);
1692
1693                 if (!host->tuning_done) {
1694                         printk(KERN_INFO DRIVER_NAME ": Timeout waiting for "
1695                                 "Buffer Read Ready interrupt during tuning "
1696                                 "procedure, falling back to fixed sampling "
1697                                 "clock\n");
1698                         ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1699                         ctrl &= ~SDHCI_CTRL_TUNED_CLK;
1700                         ctrl &= ~SDHCI_CTRL_EXEC_TUNING;
1701                         sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1702
1703                         err = -EIO;
1704                         goto out;
1705                 }
1706
1707                 host->tuning_done = 0;
1708
1709                 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1710                 tuning_loop_counter--;
1711                 timeout--;
1712                 mdelay(1);
1713         } while (ctrl & SDHCI_CTRL_EXEC_TUNING);
1714
1715         /*
1716          * The Host Driver has exhausted the maximum number of loops allowed,
1717          * so use fixed sampling frequency.
1718          */
1719         if (!tuning_loop_counter || !timeout) {
1720                 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
1721                 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1722         } else {
1723                 if (!(ctrl & SDHCI_CTRL_TUNED_CLK)) {
1724                         printk(KERN_INFO DRIVER_NAME ": Tuning procedure"
1725                                 " failed, falling back to fixed sampling"
1726                                 " clock\n");
1727                         err = -EIO;
1728                 }
1729         }
1730
1731 out:
1732         /*
1733          * If this is the very first time we are here, we start the retuning
1734          * timer. Since only during the first time, SDHCI_NEEDS_RETUNING
1735          * flag won't be set, we check this condition before actually starting
1736          * the timer.
1737          */
1738         if (!(host->flags & SDHCI_NEEDS_RETUNING) && host->tuning_count &&
1739             (host->tuning_mode == SDHCI_TUNING_MODE_1)) {
1740                 mod_timer(&host->tuning_timer, jiffies +
1741                         host->tuning_count * HZ);
1742                 /* Tuning mode 1 limits the maximum data length to 4MB */
1743                 mmc->max_blk_count = (4 * 1024 * 1024) / mmc->max_blk_size;
1744         } else {
1745                 host->flags &= ~SDHCI_NEEDS_RETUNING;
1746                 /* Reload the new initial value for timer */
1747                 if (host->tuning_mode == SDHCI_TUNING_MODE_1)
1748                         mod_timer(&host->tuning_timer, jiffies +
1749                                 host->tuning_count * HZ);
1750         }
1751
1752         /*
1753          * In case tuning fails, host controllers which support re-tuning can
1754          * try tuning again at a later time, when the re-tuning timer expires.
1755          * So for these controllers, we return 0. Since there might be other
1756          * controllers who do not have this capability, we return error for
1757          * them.
1758          */
1759         if (err && host->tuning_count &&
1760             host->tuning_mode == SDHCI_TUNING_MODE_1)
1761                 err = 0;
1762
1763         sdhci_clear_set_irqs(host, SDHCI_INT_DATA_AVAIL, ier);
1764         spin_unlock(&host->lock);
1765         enable_irq(host->irq);
1766
1767         return err;
1768 }
1769
1770 static void sdhci_enable_preset_value(struct mmc_host *mmc, bool enable)
1771 {
1772         struct sdhci_host *host;
1773         u16 ctrl;
1774         unsigned long flags;
1775
1776         host = mmc_priv(mmc);
1777
1778         /* Host Controller v3.00 defines preset value registers */
1779         if (host->version < SDHCI_SPEC_300)
1780                 return;
1781
1782         spin_lock_irqsave(&host->lock, flags);
1783
1784         ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1785
1786         /*
1787          * We only enable or disable Preset Value if they are not already
1788          * enabled or disabled respectively. Otherwise, we bail out.
1789          */
1790         if (enable && !(ctrl & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
1791                 ctrl |= SDHCI_CTRL_PRESET_VAL_ENABLE;
1792                 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1793         } else if (!enable && (ctrl & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
1794                 ctrl &= ~SDHCI_CTRL_PRESET_VAL_ENABLE;
1795                 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1796         }
1797
1798         spin_unlock_irqrestore(&host->lock, flags);
1799 }
1800
1801 static const struct mmc_host_ops sdhci_ops = {
1802         .request        = sdhci_request,
1803         .set_ios        = sdhci_set_ios,
1804         .get_ro         = sdhci_get_ro,
1805         .enable_sdio_irq = sdhci_enable_sdio_irq,
1806         .start_signal_voltage_switch    = sdhci_start_signal_voltage_switch,
1807         .execute_tuning                 = sdhci_execute_tuning,
1808         .enable_preset_value            = sdhci_enable_preset_value,
1809 };
1810
1811 /*****************************************************************************\
1812  *                                                                           *
1813  * Tasklets                                                                  *
1814  *                                                                           *
1815 \*****************************************************************************/
1816
1817 static void sdhci_tasklet_card(unsigned long param)
1818 {
1819         struct sdhci_host *host;
1820         unsigned long flags;
1821
1822         host = (struct sdhci_host*)param;
1823
1824         spin_lock_irqsave(&host->lock, flags);
1825
1826         if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT)) {
1827                 if (host->mrq) {
1828                         printk(KERN_ERR "%s: Card removed during transfer!\n",
1829                                 mmc_hostname(host->mmc));
1830                         printk(KERN_ERR "%s: Resetting controller.\n",
1831                                 mmc_hostname(host->mmc));
1832
1833                         sdhci_reset(host, SDHCI_RESET_CMD);
1834                         sdhci_reset(host, SDHCI_RESET_DATA);
1835
1836                         host->mrq->cmd->error = -ENOMEDIUM;
1837                         tasklet_schedule(&host->finish_tasklet);
1838                 }
1839         }
1840
1841         spin_unlock_irqrestore(&host->lock, flags);
1842
1843         mmc_detect_change(host->mmc, msecs_to_jiffies(200));
1844 }
1845
1846 static void sdhci_tasklet_finish(unsigned long param)
1847 {
1848         struct sdhci_host *host;
1849         unsigned long flags;
1850         struct mmc_request *mrq;
1851
1852         host = (struct sdhci_host*)param;
1853
1854         /*
1855          * If this tasklet gets rescheduled while running, it will
1856          * be run again afterwards but without any active request.
1857          */
1858         if (!host->mrq)
1859                 return;
1860
1861         spin_lock_irqsave(&host->lock, flags);
1862
1863         del_timer(&host->timer);
1864
1865         mrq = host->mrq;
1866
1867         /*
1868          * The controller needs a reset of internal state machines
1869          * upon error conditions.
1870          */
1871         if (!(host->flags & SDHCI_DEVICE_DEAD) &&
1872             ((mrq->cmd && mrq->cmd->error) ||
1873                  (mrq->data && (mrq->data->error ||
1874                   (mrq->data->stop && mrq->data->stop->error))) ||
1875                    (host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST))) {
1876
1877                 /* Some controllers need this kick or reset won't work here */
1878                 if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET) {
1879                         unsigned int clock;
1880
1881                         /* This is to force an update */
1882                         clock = host->clock;
1883                         host->clock = 0;
1884                         sdhci_set_clock(host, clock);
1885                 }
1886
1887                 /* Spec says we should do both at the same time, but Ricoh
1888                    controllers do not like that. */
1889                 sdhci_reset(host, SDHCI_RESET_CMD);
1890                 sdhci_reset(host, SDHCI_RESET_DATA);
1891         }
1892
1893         host->mrq = NULL;
1894         host->cmd = NULL;
1895         host->data = NULL;
1896
1897 #ifndef SDHCI_USE_LEDS_CLASS
1898         sdhci_deactivate_led(host);
1899 #endif
1900
1901         mmiowb();
1902         spin_unlock_irqrestore(&host->lock, flags);
1903
1904         mmc_request_done(host->mmc, mrq);
1905 }
1906
1907 static void sdhci_timeout_timer(unsigned long data)
1908 {
1909         struct sdhci_host *host;
1910         unsigned long flags;
1911
1912         host = (struct sdhci_host*)data;
1913
1914         spin_lock_irqsave(&host->lock, flags);
1915
1916         if (host->mrq) {
1917                 printk(KERN_ERR "%s: Timeout waiting for hardware "
1918                         "interrupt.\n", mmc_hostname(host->mmc));
1919                 sdhci_dumpregs(host);
1920
1921                 if (host->data) {
1922                         host->data->error = -ETIMEDOUT;
1923                         sdhci_finish_data(host);
1924                 } else {
1925                         if (host->cmd)
1926                                 host->cmd->error = -ETIMEDOUT;
1927                         else
1928                                 host->mrq->cmd->error = -ETIMEDOUT;
1929
1930                         tasklet_schedule(&host->finish_tasklet);
1931                 }
1932         }
1933
1934         mmiowb();
1935         spin_unlock_irqrestore(&host->lock, flags);
1936 }
1937
1938 static void sdhci_tuning_timer(unsigned long data)
1939 {
1940         struct sdhci_host *host;
1941         unsigned long flags;
1942
1943         host = (struct sdhci_host *)data;
1944
1945         spin_lock_irqsave(&host->lock, flags);
1946
1947         host->flags |= SDHCI_NEEDS_RETUNING;
1948
1949         spin_unlock_irqrestore(&host->lock, flags);
1950 }
1951
1952 /*****************************************************************************\
1953  *                                                                           *
1954  * Interrupt handling                                                        *
1955  *                                                                           *
1956 \*****************************************************************************/
1957
1958 static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask)
1959 {
1960         BUG_ON(intmask == 0);
1961
1962         if (!host->cmd) {
1963                 printk(KERN_ERR "%s: Got command interrupt 0x%08x even "
1964                         "though no command operation was in progress.\n",
1965                         mmc_hostname(host->mmc), (unsigned)intmask);
1966                 sdhci_dumpregs(host);
1967                 return;
1968         }
1969
1970         if (intmask & SDHCI_INT_TIMEOUT)
1971                 host->cmd->error = -ETIMEDOUT;
1972         else if (intmask & (SDHCI_INT_CRC | SDHCI_INT_END_BIT |
1973                         SDHCI_INT_INDEX))
1974                 host->cmd->error = -EILSEQ;
1975
1976         if (host->cmd->error) {
1977                 tasklet_schedule(&host->finish_tasklet);
1978                 return;
1979         }
1980
1981         /*
1982          * The host can send and interrupt when the busy state has
1983          * ended, allowing us to wait without wasting CPU cycles.
1984          * Unfortunately this is overloaded on the "data complete"
1985          * interrupt, so we need to take some care when handling
1986          * it.
1987          *
1988          * Note: The 1.0 specification is a bit ambiguous about this
1989          *       feature so there might be some problems with older
1990          *       controllers.
1991          */
1992         if (host->cmd->flags & MMC_RSP_BUSY) {
1993                 if (host->cmd->data)
1994                         DBG("Cannot wait for busy signal when also "
1995                                 "doing a data transfer");
1996                 else if (!(host->quirks & SDHCI_QUIRK_NO_BUSY_IRQ))
1997                         return;
1998
1999                 /* The controller does not support the end-of-busy IRQ,
2000                  * fall through and take the SDHCI_INT_RESPONSE */
2001         }
2002
2003         if (intmask & SDHCI_INT_RESPONSE)
2004                 sdhci_finish_command(host);
2005 }
2006
2007 #ifdef CONFIG_MMC_DEBUG
2008 static void sdhci_show_adma_error(struct sdhci_host *host)
2009 {
2010         const char *name = mmc_hostname(host->mmc);
2011         u8 *desc = host->adma_desc;
2012         __le32 *dma;
2013         __le16 *len;
2014         u8 attr;
2015
2016         sdhci_dumpregs(host);
2017
2018         while (true) {
2019                 dma = (__le32 *)(desc + 4);
2020                 len = (__le16 *)(desc + 2);
2021                 attr = *desc;
2022
2023                 DBG("%s: %p: DMA 0x%08x, LEN 0x%04x, Attr=0x%02x\n",
2024                     name, desc, le32_to_cpu(*dma), le16_to_cpu(*len), attr);
2025
2026                 desc += 8;
2027
2028                 if (attr & 2)
2029                         break;
2030         }
2031 }
2032 #else
2033 static void sdhci_show_adma_error(struct sdhci_host *host) { }
2034 #endif
2035
2036 static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
2037 {
2038         BUG_ON(intmask == 0);
2039
2040         /* CMD19 generates _only_ Buffer Read Ready interrupt */
2041         if (intmask & SDHCI_INT_DATA_AVAIL) {
2042                 if (SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND)) ==
2043                     MMC_SEND_TUNING_BLOCK) {
2044                         host->tuning_done = 1;
2045                         wake_up(&host->buf_ready_int);
2046                         return;
2047                 }
2048         }
2049
2050         if (!host->data) {
2051                 /*
2052                  * The "data complete" interrupt is also used to
2053                  * indicate that a busy state has ended. See comment
2054                  * above in sdhci_cmd_irq().
2055                  */
2056                 if (host->cmd && (host->cmd->flags & MMC_RSP_BUSY)) {
2057                         if (intmask & SDHCI_INT_DATA_END) {
2058                                 sdhci_finish_command(host);
2059                                 return;
2060                         }
2061                 }
2062
2063                 printk(KERN_ERR "%s: Got data interrupt 0x%08x even "
2064                         "though no data operation was in progress.\n",
2065                         mmc_hostname(host->mmc), (unsigned)intmask);
2066                 sdhci_dumpregs(host);
2067
2068                 return;
2069         }
2070
2071         if (intmask & SDHCI_INT_DATA_TIMEOUT)
2072                 host->data->error = -ETIMEDOUT;
2073         else if (intmask & SDHCI_INT_DATA_END_BIT)
2074                 host->data->error = -EILSEQ;
2075         else if ((intmask & SDHCI_INT_DATA_CRC) &&
2076                 SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND))
2077                         != MMC_BUS_TEST_R)
2078                 host->data->error = -EILSEQ;
2079         else if (intmask & SDHCI_INT_ADMA_ERROR) {
2080                 printk(KERN_ERR "%s: ADMA error\n", mmc_hostname(host->mmc));
2081                 sdhci_show_adma_error(host);
2082                 host->data->error = -EIO;
2083         }
2084
2085         if (host->data->error)
2086                 sdhci_finish_data(host);
2087         else {
2088                 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
2089                         sdhci_transfer_pio(host);
2090
2091                 /*
2092                  * We currently don't do anything fancy with DMA
2093                  * boundaries, but as we can't disable the feature
2094                  * we need to at least restart the transfer.
2095                  *
2096                  * According to the spec sdhci_readl(host, SDHCI_DMA_ADDRESS)
2097                  * should return a valid address to continue from, but as
2098                  * some controllers are faulty, don't trust them.
2099                  */
2100                 if (intmask & SDHCI_INT_DMA_END) {
2101                         u32 dmastart, dmanow;
2102                         dmastart = sg_dma_address(host->data->sg);
2103                         dmanow = dmastart + host->data->bytes_xfered;
2104                         /*
2105                          * Force update to the next DMA block boundary.
2106                          */
2107                         dmanow = (dmanow &
2108                                 ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) +
2109                                 SDHCI_DEFAULT_BOUNDARY_SIZE;
2110                         host->data->bytes_xfered = dmanow - dmastart;
2111                         DBG("%s: DMA base 0x%08x, transferred 0x%06x bytes,"
2112                                 " next 0x%08x\n",
2113                                 mmc_hostname(host->mmc), dmastart,
2114                                 host->data->bytes_xfered, dmanow);
2115                         sdhci_writel(host, dmanow, SDHCI_DMA_ADDRESS);
2116                 }
2117
2118                 if (intmask & SDHCI_INT_DATA_END) {
2119                         if (host->cmd) {
2120                                 /*
2121                                  * Data managed to finish before the
2122                                  * command completed. Make sure we do
2123                                  * things in the proper order.
2124                                  */
2125                                 host->data_early = 1;
2126                         } else {
2127                                 sdhci_finish_data(host);
2128                         }
2129                 }
2130         }
2131 }
2132
2133 static irqreturn_t sdhci_irq(int irq, void *dev_id)
2134 {
2135         irqreturn_t result;
2136         struct sdhci_host* host = dev_id;
2137         u32 intmask;
2138         int cardint = 0;
2139
2140         spin_lock(&host->lock);
2141
2142         intmask = sdhci_readl(host, SDHCI_INT_STATUS);
2143
2144         if (!intmask || intmask == 0xffffffff) {
2145                 result = IRQ_NONE;
2146                 goto out;
2147         }
2148
2149         DBG("*** %s got interrupt: 0x%08x\n",
2150                 mmc_hostname(host->mmc), intmask);
2151
2152         if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
2153                 sdhci_writel(host, intmask & (SDHCI_INT_CARD_INSERT |
2154                         SDHCI_INT_CARD_REMOVE), SDHCI_INT_STATUS);
2155                 tasklet_schedule(&host->card_tasklet);
2156         }
2157
2158         intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE);
2159
2160         if (intmask & SDHCI_INT_CMD_MASK) {
2161                 sdhci_writel(host, intmask & SDHCI_INT_CMD_MASK,
2162                         SDHCI_INT_STATUS);
2163                 sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK);
2164         }
2165
2166         if (intmask & SDHCI_INT_DATA_MASK) {
2167                 sdhci_writel(host, intmask & SDHCI_INT_DATA_MASK,
2168                         SDHCI_INT_STATUS);
2169                 sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
2170         }
2171
2172         intmask &= ~(SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK);
2173
2174         intmask &= ~SDHCI_INT_ERROR;
2175
2176         if (intmask & SDHCI_INT_BUS_POWER) {
2177                 printk(KERN_ERR "%s: Card is consuming too much power!\n",
2178                         mmc_hostname(host->mmc));
2179                 sdhci_writel(host, SDHCI_INT_BUS_POWER, SDHCI_INT_STATUS);
2180         }
2181
2182         intmask &= ~SDHCI_INT_BUS_POWER;
2183
2184         if (intmask & SDHCI_INT_CARD_INT)
2185                 cardint = 1;
2186
2187         intmask &= ~SDHCI_INT_CARD_INT;
2188
2189         if (intmask) {
2190                 printk(KERN_ERR "%s: Unexpected interrupt 0x%08x.\n",
2191                         mmc_hostname(host->mmc), intmask);
2192                 sdhci_dumpregs(host);
2193
2194                 sdhci_writel(host, intmask, SDHCI_INT_STATUS);
2195         }
2196
2197         result = IRQ_HANDLED;
2198
2199         mmiowb();
2200 out:
2201         spin_unlock(&host->lock);
2202
2203         /*
2204          * We have to delay this as it calls back into the driver.
2205          */
2206         if (cardint)
2207                 mmc_signal_sdio_irq(host->mmc);
2208
2209         return result;
2210 }
2211
2212 /*****************************************************************************\
2213  *                                                                           *
2214  * Suspend/resume                                                            *
2215  *                                                                           *
2216 \*****************************************************************************/
2217
2218 #ifdef CONFIG_PM
2219
2220 int sdhci_suspend_host(struct sdhci_host *host, pm_message_t state)
2221 {
2222         int ret;
2223
2224         sdhci_disable_card_detection(host);
2225
2226         /* Disable tuning since we are suspending */
2227         if (host->version >= SDHCI_SPEC_300 && host->tuning_count &&
2228             host->tuning_mode == SDHCI_TUNING_MODE_1) {
2229                 del_timer_sync(&host->tuning_timer);
2230                 host->flags &= ~SDHCI_NEEDS_RETUNING;
2231         }
2232
2233         ret = mmc_suspend_host(host->mmc);
2234         if (ret)
2235                 return ret;
2236
2237         free_irq(host->irq, host);
2238
2239         if (host->vmmc)
2240                 ret = regulator_disable(host->vmmc);
2241
2242         return ret;
2243 }
2244
2245 EXPORT_SYMBOL_GPL(sdhci_suspend_host);
2246
2247 int sdhci_resume_host(struct sdhci_host *host)
2248 {
2249         int ret;
2250
2251         if (host->vmmc) {
2252                 int ret = regulator_enable(host->vmmc);
2253                 if (ret)
2254                         return ret;
2255         }
2256
2257
2258         if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2259                 if (host->ops->enable_dma)
2260                         host->ops->enable_dma(host);
2261         }
2262
2263         ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED,
2264                           mmc_hostname(host->mmc), host);
2265         if (ret)
2266                 return ret;
2267
2268         sdhci_init(host, (host->mmc->pm_flags & MMC_PM_KEEP_POWER));
2269         mmiowb();
2270
2271         ret = mmc_resume_host(host->mmc);
2272         sdhci_enable_card_detection(host);
2273
2274         /* Set the re-tuning expiration flag */
2275         if ((host->version >= SDHCI_SPEC_300) && host->tuning_count &&
2276             (host->tuning_mode == SDHCI_TUNING_MODE_1))
2277                 host->flags |= SDHCI_NEEDS_RETUNING;
2278
2279         return ret;
2280 }
2281
2282 EXPORT_SYMBOL_GPL(sdhci_resume_host);
2283
2284 void sdhci_enable_irq_wakeups(struct sdhci_host *host)
2285 {
2286         u8 val;
2287         val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
2288         val |= SDHCI_WAKE_ON_INT;
2289         sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
2290 }
2291
2292 EXPORT_SYMBOL_GPL(sdhci_enable_irq_wakeups);
2293
2294 #endif /* CONFIG_PM */
2295
2296 /*****************************************************************************\
2297  *                                                                           *
2298  * Device allocation/registration                                            *
2299  *                                                                           *
2300 \*****************************************************************************/
2301
2302 struct sdhci_host *sdhci_alloc_host(struct device *dev,
2303         size_t priv_size)
2304 {
2305         struct mmc_host *mmc;
2306         struct sdhci_host *host;
2307
2308         WARN_ON(dev == NULL);
2309
2310         mmc = mmc_alloc_host(sizeof(struct sdhci_host) + priv_size, dev);
2311         if (!mmc)
2312                 return ERR_PTR(-ENOMEM);
2313
2314         host = mmc_priv(mmc);
2315         host->mmc = mmc;
2316
2317         return host;
2318 }
2319
2320 EXPORT_SYMBOL_GPL(sdhci_alloc_host);
2321
2322 int sdhci_add_host(struct sdhci_host *host)
2323 {
2324         struct mmc_host *mmc;
2325         u32 caps[2];
2326         u32 max_current_caps;
2327         unsigned int ocr_avail;
2328         int ret;
2329
2330         WARN_ON(host == NULL);
2331         if (host == NULL)
2332                 return -EINVAL;
2333
2334         mmc = host->mmc;
2335
2336         if (debug_quirks)
2337                 host->quirks = debug_quirks;
2338
2339         sdhci_reset(host, SDHCI_RESET_ALL);
2340
2341         host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
2342         host->version = (host->version & SDHCI_SPEC_VER_MASK)
2343                                 >> SDHCI_SPEC_VER_SHIFT;
2344         if (host->version > SDHCI_SPEC_300) {
2345                 printk(KERN_ERR "%s: Unknown controller version (%d). "
2346                         "You may experience problems.\n", mmc_hostname(mmc),
2347                         host->version);
2348         }
2349
2350         caps[0] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ? host->caps :
2351                 sdhci_readl(host, SDHCI_CAPABILITIES);
2352
2353         caps[1] = (host->version >= SDHCI_SPEC_300) ?
2354                 sdhci_readl(host, SDHCI_CAPABILITIES_1) : 0;
2355
2356         if (host->quirks & SDHCI_QUIRK_FORCE_DMA)
2357                 host->flags |= SDHCI_USE_SDMA;
2358         else if (!(caps[0] & SDHCI_CAN_DO_SDMA))
2359                 DBG("Controller doesn't have SDMA capability\n");
2360         else
2361                 host->flags |= SDHCI_USE_SDMA;
2362
2363         if ((host->quirks & SDHCI_QUIRK_BROKEN_DMA) &&
2364                 (host->flags & SDHCI_USE_SDMA)) {
2365                 DBG("Disabling DMA as it is marked broken\n");
2366                 host->flags &= ~SDHCI_USE_SDMA;
2367         }
2368
2369         if ((host->version >= SDHCI_SPEC_200) &&
2370                 (caps[0] & SDHCI_CAN_DO_ADMA2))
2371                 host->flags |= SDHCI_USE_ADMA;
2372
2373         if ((host->quirks & SDHCI_QUIRK_BROKEN_ADMA) &&
2374                 (host->flags & SDHCI_USE_ADMA)) {
2375                 DBG("Disabling ADMA as it is marked broken\n");
2376                 host->flags &= ~SDHCI_USE_ADMA;
2377         }
2378
2379         if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2380                 if (host->ops->enable_dma) {
2381                         if (host->ops->enable_dma(host)) {
2382                                 printk(KERN_WARNING "%s: No suitable DMA "
2383                                         "available. Falling back to PIO.\n",
2384                                         mmc_hostname(mmc));
2385                                 host->flags &=
2386                                         ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA);
2387                         }
2388                 }
2389         }
2390
2391         if (host->flags & SDHCI_USE_ADMA) {
2392                 /*
2393                  * We need to allocate descriptors for all sg entries
2394                  * (128) and potentially one alignment transfer for
2395                  * each of those entries.
2396                  */
2397                 host->adma_desc = kmalloc((128 * 2 + 1) * 4, GFP_KERNEL);
2398                 host->align_buffer = kmalloc(128 * 4, GFP_KERNEL);
2399                 if (!host->adma_desc || !host->align_buffer) {
2400                         kfree(host->adma_desc);
2401                         kfree(host->align_buffer);
2402                         printk(KERN_WARNING "%s: Unable to allocate ADMA "
2403                                 "buffers. Falling back to standard DMA.\n",
2404                                 mmc_hostname(mmc));
2405                         host->flags &= ~SDHCI_USE_ADMA;
2406                 }
2407         }
2408
2409         /*
2410          * If we use DMA, then it's up to the caller to set the DMA
2411          * mask, but PIO does not need the hw shim so we set a new
2412          * mask here in that case.
2413          */
2414         if (!(host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))) {
2415                 host->dma_mask = DMA_BIT_MASK(64);
2416                 mmc_dev(host->mmc)->dma_mask = &host->dma_mask;
2417         }
2418
2419         if (host->version >= SDHCI_SPEC_300)
2420                 host->max_clk = (caps[0] & SDHCI_CLOCK_V3_BASE_MASK)
2421                         >> SDHCI_CLOCK_BASE_SHIFT;
2422         else
2423                 host->max_clk = (caps[0] & SDHCI_CLOCK_BASE_MASK)
2424                         >> SDHCI_CLOCK_BASE_SHIFT;
2425
2426         host->max_clk *= 1000000;
2427         if (host->max_clk == 0 || host->quirks &
2428                         SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN) {
2429                 if (!host->ops->get_max_clock) {
2430                         printk(KERN_ERR
2431                                "%s: Hardware doesn't specify base clock "
2432                                "frequency.\n", mmc_hostname(mmc));
2433                         return -ENODEV;
2434                 }
2435                 host->max_clk = host->ops->get_max_clock(host);
2436         }
2437
2438         host->timeout_clk =
2439                 (caps[0] & SDHCI_TIMEOUT_CLK_MASK) >> SDHCI_TIMEOUT_CLK_SHIFT;
2440         if (host->timeout_clk == 0) {
2441                 if (host->ops->get_timeout_clock) {
2442                         host->timeout_clk = host->ops->get_timeout_clock(host);
2443                 } else if (!(host->quirks &
2444                                 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)) {
2445                         printk(KERN_ERR
2446                                "%s: Hardware doesn't specify timeout clock "
2447                                "frequency.\n", mmc_hostname(mmc));
2448                         return -ENODEV;
2449                 }
2450         }
2451         if (caps[0] & SDHCI_TIMEOUT_CLK_UNIT)
2452                 host->timeout_clk *= 1000;
2453
2454         /*
2455          * In case of Host Controller v3.00, find out whether clock
2456          * multiplier is supported.
2457          */
2458         host->clk_mul = (caps[1] & SDHCI_CLOCK_MUL_MASK) >>
2459                         SDHCI_CLOCK_MUL_SHIFT;
2460
2461         /*
2462          * In case the value in Clock Multiplier is 0, then programmable
2463          * clock mode is not supported, otherwise the actual clock
2464          * multiplier is one more than the value of Clock Multiplier
2465          * in the Capabilities Register.
2466          */
2467         if (host->clk_mul)
2468                 host->clk_mul += 1;
2469
2470         /*
2471          * Set host parameters.
2472          */
2473         mmc->ops = &sdhci_ops;
2474         mmc->f_max = host->max_clk;
2475         if (host->ops->get_min_clock)
2476                 mmc->f_min = host->ops->get_min_clock(host);
2477         else if (host->version >= SDHCI_SPEC_300) {
2478                 if (host->clk_mul) {
2479                         mmc->f_min = (host->max_clk * host->clk_mul) / 1024;
2480                         mmc->f_max = host->max_clk * host->clk_mul;
2481                 } else
2482                         mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_300;
2483         } else
2484                 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_200;
2485
2486         mmc->caps |= MMC_CAP_SDIO_IRQ | MMC_CAP_ERASE | MMC_CAP_CMD23;
2487
2488         if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12)
2489                 host->flags |= SDHCI_AUTO_CMD12;
2490
2491         /* Auto-CMD23 stuff only works in ADMA or PIO. */
2492         if ((host->version >= SDHCI_SPEC_300) &&
2493             ((host->flags & SDHCI_USE_ADMA) ||
2494              !(host->flags & SDHCI_USE_SDMA))) {
2495                 host->flags |= SDHCI_AUTO_CMD23;
2496                 DBG("%s: Auto-CMD23 available\n", mmc_hostname(mmc));
2497         } else {
2498                 DBG("%s: Auto-CMD23 unavailable\n", mmc_hostname(mmc));
2499         }
2500
2501         /*
2502          * A controller may support 8-bit width, but the board itself
2503          * might not have the pins brought out.  Boards that support
2504          * 8-bit width must set "mmc->caps |= MMC_CAP_8_BIT_DATA;" in
2505          * their platform code before calling sdhci_add_host(), and we
2506          * won't assume 8-bit width for hosts without that CAP.
2507          */
2508         if (!(host->quirks & SDHCI_QUIRK_FORCE_1_BIT_DATA))
2509                 mmc->caps |= MMC_CAP_4_BIT_DATA;
2510
2511         if (caps[0] & SDHCI_CAN_DO_HISPD)
2512                 mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
2513
2514         if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) &&
2515             mmc_card_is_removable(mmc))
2516                 mmc->caps |= MMC_CAP_NEEDS_POLL;
2517
2518         /* UHS-I mode(s) supported by the host controller. */
2519         if (host->version >= SDHCI_SPEC_300)
2520                 mmc->caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25;
2521
2522         /* SDR104 supports also implies SDR50 support */
2523         if (caps[1] & SDHCI_SUPPORT_SDR104)
2524                 mmc->caps |= MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50;
2525         else if (caps[1] & SDHCI_SUPPORT_SDR50)
2526                 mmc->caps |= MMC_CAP_UHS_SDR50;
2527
2528         if (caps[1] & SDHCI_SUPPORT_DDR50)
2529                 mmc->caps |= MMC_CAP_UHS_DDR50;
2530
2531         /* Does the host needs tuning for SDR50? */
2532         if (caps[1] & SDHCI_USE_SDR50_TUNING)
2533                 host->flags |= SDHCI_SDR50_NEEDS_TUNING;
2534
2535         /* Driver Type(s) (A, C, D) supported by the host */
2536         if (caps[1] & SDHCI_DRIVER_TYPE_A)
2537                 mmc->caps |= MMC_CAP_DRIVER_TYPE_A;
2538         if (caps[1] & SDHCI_DRIVER_TYPE_C)
2539                 mmc->caps |= MMC_CAP_DRIVER_TYPE_C;
2540         if (caps[1] & SDHCI_DRIVER_TYPE_D)
2541                 mmc->caps |= MMC_CAP_DRIVER_TYPE_D;
2542
2543         /* Initial value for re-tuning timer count */
2544         host->tuning_count = (caps[1] & SDHCI_RETUNING_TIMER_COUNT_MASK) >>
2545                               SDHCI_RETUNING_TIMER_COUNT_SHIFT;
2546
2547         /*
2548          * In case Re-tuning Timer is not disabled, the actual value of
2549          * re-tuning timer will be 2 ^ (n - 1).
2550          */
2551         if (host->tuning_count)
2552                 host->tuning_count = 1 << (host->tuning_count - 1);
2553
2554         /* Re-tuning mode supported by the Host Controller */
2555         host->tuning_mode = (caps[1] & SDHCI_RETUNING_MODE_MASK) >>
2556                              SDHCI_RETUNING_MODE_SHIFT;
2557
2558         ocr_avail = 0;
2559         /*
2560          * According to SD Host Controller spec v3.00, if the Host System
2561          * can afford more than 150mA, Host Driver should set XPC to 1. Also
2562          * the value is meaningful only if Voltage Support in the Capabilities
2563          * register is set. The actual current value is 4 times the register
2564          * value.
2565          */
2566         max_current_caps = sdhci_readl(host, SDHCI_MAX_CURRENT);
2567
2568         if (caps[0] & SDHCI_CAN_VDD_330) {
2569                 int max_current_330;
2570
2571                 ocr_avail |= MMC_VDD_32_33 | MMC_VDD_33_34;
2572
2573                 max_current_330 = ((max_current_caps &
2574                                    SDHCI_MAX_CURRENT_330_MASK) >>
2575                                    SDHCI_MAX_CURRENT_330_SHIFT) *
2576                                    SDHCI_MAX_CURRENT_MULTIPLIER;
2577
2578                 if (max_current_330 > 150)
2579                         mmc->caps |= MMC_CAP_SET_XPC_330;
2580         }
2581         if (caps[0] & SDHCI_CAN_VDD_300) {
2582                 int max_current_300;
2583
2584                 ocr_avail |= MMC_VDD_29_30 | MMC_VDD_30_31;
2585
2586                 max_current_300 = ((max_current_caps &
2587                                    SDHCI_MAX_CURRENT_300_MASK) >>
2588                                    SDHCI_MAX_CURRENT_300_SHIFT) *
2589                                    SDHCI_MAX_CURRENT_MULTIPLIER;
2590
2591                 if (max_current_300 > 150)
2592                         mmc->caps |= MMC_CAP_SET_XPC_300;
2593         }
2594         if (caps[0] & SDHCI_CAN_VDD_180) {
2595                 int max_current_180;
2596
2597                 ocr_avail |= MMC_VDD_165_195;
2598
2599                 max_current_180 = ((max_current_caps &
2600                                    SDHCI_MAX_CURRENT_180_MASK) >>
2601                                    SDHCI_MAX_CURRENT_180_SHIFT) *
2602                                    SDHCI_MAX_CURRENT_MULTIPLIER;
2603
2604                 if (max_current_180 > 150)
2605                         mmc->caps |= MMC_CAP_SET_XPC_180;
2606
2607                 /* Maximum current capabilities of the host at 1.8V */
2608                 if (max_current_180 >= 800)
2609                         mmc->caps |= MMC_CAP_MAX_CURRENT_800;
2610                 else if (max_current_180 >= 600)
2611                         mmc->caps |= MMC_CAP_MAX_CURRENT_600;
2612                 else if (max_current_180 >= 400)
2613                         mmc->caps |= MMC_CAP_MAX_CURRENT_400;
2614                 else
2615                         mmc->caps |= MMC_CAP_MAX_CURRENT_200;
2616         }
2617
2618         mmc->ocr_avail = ocr_avail;
2619         mmc->ocr_avail_sdio = ocr_avail;
2620         if (host->ocr_avail_sdio)
2621                 mmc->ocr_avail_sdio &= host->ocr_avail_sdio;
2622         mmc->ocr_avail_sd = ocr_avail;
2623         if (host->ocr_avail_sd)
2624                 mmc->ocr_avail_sd &= host->ocr_avail_sd;
2625         else /* normal SD controllers don't support 1.8V */
2626                 mmc->ocr_avail_sd &= ~MMC_VDD_165_195;
2627         mmc->ocr_avail_mmc = ocr_avail;
2628         if (host->ocr_avail_mmc)
2629                 mmc->ocr_avail_mmc &= host->ocr_avail_mmc;
2630
2631         if (mmc->ocr_avail == 0) {
2632                 printk(KERN_ERR "%s: Hardware doesn't report any "
2633                         "support voltages.\n", mmc_hostname(mmc));
2634                 return -ENODEV;
2635         }
2636
2637         spin_lock_init(&host->lock);
2638
2639         /*
2640          * Maximum number of segments. Depends on if the hardware
2641          * can do scatter/gather or not.
2642          */
2643         if (host->flags & SDHCI_USE_ADMA)
2644                 mmc->max_segs = 128;
2645         else if (host->flags & SDHCI_USE_SDMA)
2646                 mmc->max_segs = 1;
2647         else /* PIO */
2648                 mmc->max_segs = 128;
2649
2650         /*
2651          * Maximum number of sectors in one transfer. Limited by DMA boundary
2652          * size (512KiB).
2653          */
2654         mmc->max_req_size = 524288;
2655
2656         /*
2657          * Maximum segment size. Could be one segment with the maximum number
2658          * of bytes. When doing hardware scatter/gather, each entry cannot
2659          * be larger than 64 KiB though.
2660          */
2661         if (host->flags & SDHCI_USE_ADMA) {
2662                 if (host->quirks & SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC)
2663                         mmc->max_seg_size = 65535;
2664                 else
2665                         mmc->max_seg_size = 65536;
2666         } else {
2667                 mmc->max_seg_size = mmc->max_req_size;
2668         }
2669
2670         /*
2671          * Maximum block size. This varies from controller to controller and
2672          * is specified in the capabilities register.
2673          */
2674         if (host->quirks & SDHCI_QUIRK_FORCE_BLK_SZ_2048) {
2675                 mmc->max_blk_size = 2;
2676         } else {
2677                 mmc->max_blk_size = (caps[0] & SDHCI_MAX_BLOCK_MASK) >>
2678                                 SDHCI_MAX_BLOCK_SHIFT;
2679                 if (mmc->max_blk_size >= 3) {
2680                         printk(KERN_WARNING "%s: Invalid maximum block size, "
2681                                 "assuming 512 bytes\n", mmc_hostname(mmc));
2682                         mmc->max_blk_size = 0;
2683                 }
2684         }
2685
2686         mmc->max_blk_size = 512 << mmc->max_blk_size;
2687
2688         /*
2689          * Maximum block count.
2690          */
2691         mmc->max_blk_count = (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535;
2692
2693         /*
2694          * Init tasklets.
2695          */
2696         tasklet_init(&host->card_tasklet,
2697                 sdhci_tasklet_card, (unsigned long)host);
2698         tasklet_init(&host->finish_tasklet,
2699                 sdhci_tasklet_finish, (unsigned long)host);
2700
2701         setup_timer(&host->timer, sdhci_timeout_timer, (unsigned long)host);
2702
2703         if (host->version >= SDHCI_SPEC_300) {
2704                 init_waitqueue_head(&host->buf_ready_int);
2705
2706                 /* Initialize re-tuning timer */
2707                 init_timer(&host->tuning_timer);
2708                 host->tuning_timer.data = (unsigned long)host;
2709                 host->tuning_timer.function = sdhci_tuning_timer;
2710         }
2711
2712         ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED,
2713                 mmc_hostname(mmc), host);
2714         if (ret)
2715                 goto untasklet;
2716
2717         host->vmmc = regulator_get(mmc_dev(mmc), "vmmc");
2718         if (IS_ERR(host->vmmc)) {
2719                 printk(KERN_INFO "%s: no vmmc regulator found\n", mmc_hostname(mmc));
2720                 host->vmmc = NULL;
2721         } else {
2722                 regulator_enable(host->vmmc);
2723         }
2724
2725         sdhci_init(host, 0);
2726
2727 #ifdef CONFIG_MMC_DEBUG
2728         sdhci_dumpregs(host);
2729 #endif
2730
2731 #ifdef SDHCI_USE_LEDS_CLASS
2732         snprintf(host->led_name, sizeof(host->led_name),
2733                 "%s::", mmc_hostname(mmc));
2734         host->led.name = host->led_name;
2735         host->led.brightness = LED_OFF;
2736         host->led.default_trigger = mmc_hostname(mmc);
2737         host->led.brightness_set = sdhci_led_control;
2738
2739         ret = led_classdev_register(mmc_dev(mmc), &host->led);
2740         if (ret)
2741                 goto reset;
2742 #endif
2743
2744         mmiowb();
2745
2746         mmc_add_host(mmc);
2747
2748         printk(KERN_INFO "%s: SDHCI controller on %s [%s] using %s\n",
2749                 mmc_hostname(mmc), host->hw_name, dev_name(mmc_dev(mmc)),
2750                 (host->flags & SDHCI_USE_ADMA) ? "ADMA" :
2751                 (host->flags & SDHCI_USE_SDMA) ? "DMA" : "PIO");
2752
2753         sdhci_enable_card_detection(host);
2754
2755         return 0;
2756
2757 #ifdef SDHCI_USE_LEDS_CLASS
2758 reset:
2759         sdhci_reset(host, SDHCI_RESET_ALL);
2760         free_irq(host->irq, host);
2761 #endif
2762 untasklet:
2763         tasklet_kill(&host->card_tasklet);
2764         tasklet_kill(&host->finish_tasklet);
2765
2766         return ret;
2767 }
2768
2769 EXPORT_SYMBOL_GPL(sdhci_add_host);
2770
2771 void sdhci_remove_host(struct sdhci_host *host, int dead)
2772 {
2773         unsigned long flags;
2774
2775         if (dead) {
2776                 spin_lock_irqsave(&host->lock, flags);
2777
2778                 host->flags |= SDHCI_DEVICE_DEAD;
2779
2780                 if (host->mrq) {
2781                         printk(KERN_ERR "%s: Controller removed during "
2782                                 " transfer!\n", mmc_hostname(host->mmc));
2783
2784                         host->mrq->cmd->error = -ENOMEDIUM;
2785                         tasklet_schedule(&host->finish_tasklet);
2786                 }
2787
2788                 spin_unlock_irqrestore(&host->lock, flags);
2789         }
2790
2791         sdhci_disable_card_detection(host);
2792
2793         mmc_remove_host(host->mmc);
2794
2795 #ifdef SDHCI_USE_LEDS_CLASS
2796         led_classdev_unregister(&host->led);
2797 #endif
2798
2799         if (!dead)
2800                 sdhci_reset(host, SDHCI_RESET_ALL);
2801
2802         free_irq(host->irq, host);
2803
2804         del_timer_sync(&host->timer);
2805         if (host->version >= SDHCI_SPEC_300)
2806                 del_timer_sync(&host->tuning_timer);
2807
2808         tasklet_kill(&host->card_tasklet);
2809         tasklet_kill(&host->finish_tasklet);
2810
2811         if (host->vmmc) {
2812                 regulator_disable(host->vmmc);
2813                 regulator_put(host->vmmc);
2814         }
2815
2816         kfree(host->adma_desc);
2817         kfree(host->align_buffer);
2818
2819         host->adma_desc = NULL;
2820         host->align_buffer = NULL;
2821 }
2822
2823 EXPORT_SYMBOL_GPL(sdhci_remove_host);
2824
2825 void sdhci_free_host(struct sdhci_host *host)
2826 {
2827         mmc_free_host(host->mmc);
2828 }
2829
2830 EXPORT_SYMBOL_GPL(sdhci_free_host);
2831
2832 /*****************************************************************************\
2833  *                                                                           *
2834  * Driver init/exit                                                          *
2835  *                                                                           *
2836 \*****************************************************************************/
2837
2838 static int __init sdhci_drv_init(void)
2839 {
2840         printk(KERN_INFO DRIVER_NAME
2841                 ": Secure Digital Host Controller Interface driver\n");
2842         printk(KERN_INFO DRIVER_NAME ": Copyright(c) Pierre Ossman\n");
2843
2844         return 0;
2845 }
2846
2847 static void __exit sdhci_drv_exit(void)
2848 {
2849 }
2850
2851 module_init(sdhci_drv_init);
2852 module_exit(sdhci_drv_exit);
2853
2854 module_param(debug_quirks, uint, 0444);
2855
2856 MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
2857 MODULE_DESCRIPTION("Secure Digital Host Controller Interface core driver");
2858 MODULE_LICENSE("GPL");
2859
2860 MODULE_PARM_DESC(debug_quirks, "Force certain quirks.");