2 * linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver
4 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or (at
9 * your option) any later version.
11 * Thanks to the following companies for their support:
13 * - JMicron (hardware and technical support)
16 #include <linux/delay.h>
17 #include <linux/highmem.h>
19 #include <linux/dma-mapping.h>
20 #include <linux/slab.h>
21 #include <linux/scatterlist.h>
22 #include <linux/regulator/consumer.h>
24 #include <linux/leds.h>
26 #include <linux/mmc/host.h>
30 #define DRIVER_NAME "sdhci"
32 #define DBG(f, x...) \
33 pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x)
35 #if defined(CONFIG_LEDS_CLASS) || (defined(CONFIG_LEDS_CLASS_MODULE) && \
36 defined(CONFIG_MMC_SDHCI_MODULE))
37 #define SDHCI_USE_LEDS_CLASS
40 static unsigned int debug_quirks = 0;
42 static void sdhci_prepare_data(struct sdhci_host *, struct mmc_data *);
43 static void sdhci_finish_data(struct sdhci_host *);
45 static void sdhci_send_command(struct sdhci_host *, struct mmc_command *);
46 static void sdhci_finish_command(struct sdhci_host *);
48 static void sdhci_dumpregs(struct sdhci_host *host)
50 printk(KERN_DEBUG DRIVER_NAME ": ============== REGISTER DUMP ==============\n");
52 printk(KERN_DEBUG DRIVER_NAME ": Sys addr: 0x%08x | Version: 0x%08x\n",
53 sdhci_readl(host, SDHCI_DMA_ADDRESS),
54 sdhci_readw(host, SDHCI_HOST_VERSION));
55 printk(KERN_DEBUG DRIVER_NAME ": Blk size: 0x%08x | Blk cnt: 0x%08x\n",
56 sdhci_readw(host, SDHCI_BLOCK_SIZE),
57 sdhci_readw(host, SDHCI_BLOCK_COUNT));
58 printk(KERN_DEBUG DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n",
59 sdhci_readl(host, SDHCI_ARGUMENT),
60 sdhci_readw(host, SDHCI_TRANSFER_MODE));
61 printk(KERN_DEBUG DRIVER_NAME ": Present: 0x%08x | Host ctl: 0x%08x\n",
62 sdhci_readl(host, SDHCI_PRESENT_STATE),
63 sdhci_readb(host, SDHCI_HOST_CONTROL));
64 printk(KERN_DEBUG DRIVER_NAME ": Power: 0x%08x | Blk gap: 0x%08x\n",
65 sdhci_readb(host, SDHCI_POWER_CONTROL),
66 sdhci_readb(host, SDHCI_BLOCK_GAP_CONTROL));
67 printk(KERN_DEBUG DRIVER_NAME ": Wake-up: 0x%08x | Clock: 0x%08x\n",
68 sdhci_readb(host, SDHCI_WAKE_UP_CONTROL),
69 sdhci_readw(host, SDHCI_CLOCK_CONTROL));
70 printk(KERN_DEBUG DRIVER_NAME ": Timeout: 0x%08x | Int stat: 0x%08x\n",
71 sdhci_readb(host, SDHCI_TIMEOUT_CONTROL),
72 sdhci_readl(host, SDHCI_INT_STATUS));
73 printk(KERN_DEBUG DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n",
74 sdhci_readl(host, SDHCI_INT_ENABLE),
75 sdhci_readl(host, SDHCI_SIGNAL_ENABLE));
76 printk(KERN_DEBUG DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n",
77 sdhci_readw(host, SDHCI_ACMD12_ERR),
78 sdhci_readw(host, SDHCI_SLOT_INT_STATUS));
79 printk(KERN_DEBUG DRIVER_NAME ": Caps: 0x%08x | Max curr: 0x%08x\n",
80 sdhci_readl(host, SDHCI_CAPABILITIES),
81 sdhci_readl(host, SDHCI_MAX_CURRENT));
83 if (host->flags & SDHCI_USE_ADMA)
84 printk(KERN_DEBUG DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x\n",
85 readl(host->ioaddr + SDHCI_ADMA_ERROR),
86 readl(host->ioaddr + SDHCI_ADMA_ADDRESS));
88 printk(KERN_DEBUG DRIVER_NAME ": ===========================================\n");
91 /*****************************************************************************\
93 * Low level functions *
95 \*****************************************************************************/
97 static void sdhci_clear_set_irqs(struct sdhci_host *host, u32 clear, u32 set)
101 ier = sdhci_readl(host, SDHCI_INT_ENABLE);
104 sdhci_writel(host, ier, SDHCI_INT_ENABLE);
105 sdhci_writel(host, ier, SDHCI_SIGNAL_ENABLE);
108 static void sdhci_unmask_irqs(struct sdhci_host *host, u32 irqs)
110 sdhci_clear_set_irqs(host, 0, irqs);
113 static void sdhci_mask_irqs(struct sdhci_host *host, u32 irqs)
115 sdhci_clear_set_irqs(host, irqs, 0);
118 static void sdhci_set_card_detection(struct sdhci_host *host, bool enable)
120 u32 irqs = SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT;
122 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
126 sdhci_unmask_irqs(host, irqs);
128 sdhci_mask_irqs(host, irqs);
131 static void sdhci_enable_card_detection(struct sdhci_host *host)
133 sdhci_set_card_detection(host, true);
136 static void sdhci_disable_card_detection(struct sdhci_host *host)
138 sdhci_set_card_detection(host, false);
141 static void sdhci_reset(struct sdhci_host *host, u8 mask)
143 unsigned long timeout;
144 u32 uninitialized_var(ier);
146 if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
147 if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) &
152 if (host->quirks & SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET)
153 ier = sdhci_readl(host, SDHCI_INT_ENABLE);
155 sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
157 if (mask & SDHCI_RESET_ALL)
160 /* Wait max 100 ms */
163 /* hw clears the bit when it's done */
164 while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) {
166 printk(KERN_ERR "%s: Reset 0x%x never completed.\n",
167 mmc_hostname(host->mmc), (int)mask);
168 sdhci_dumpregs(host);
175 if (host->quirks & SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET)
176 sdhci_clear_set_irqs(host, SDHCI_INT_ALL_MASK, ier);
179 static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios);
181 static void sdhci_init(struct sdhci_host *host, int soft)
184 sdhci_reset(host, SDHCI_RESET_CMD|SDHCI_RESET_DATA);
186 sdhci_reset(host, SDHCI_RESET_ALL);
188 sdhci_clear_set_irqs(host, SDHCI_INT_ALL_MASK,
189 SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
190 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX |
191 SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT |
192 SDHCI_INT_DATA_END | SDHCI_INT_RESPONSE);
195 /* force clock reconfiguration */
197 sdhci_set_ios(host->mmc, &host->mmc->ios);
201 static void sdhci_reinit(struct sdhci_host *host)
204 sdhci_enable_card_detection(host);
207 static void sdhci_activate_led(struct sdhci_host *host)
211 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
212 ctrl |= SDHCI_CTRL_LED;
213 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
216 static void sdhci_deactivate_led(struct sdhci_host *host)
220 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
221 ctrl &= ~SDHCI_CTRL_LED;
222 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
225 #ifdef SDHCI_USE_LEDS_CLASS
226 static void sdhci_led_control(struct led_classdev *led,
227 enum led_brightness brightness)
229 struct sdhci_host *host = container_of(led, struct sdhci_host, led);
232 spin_lock_irqsave(&host->lock, flags);
234 if (brightness == LED_OFF)
235 sdhci_deactivate_led(host);
237 sdhci_activate_led(host);
239 spin_unlock_irqrestore(&host->lock, flags);
243 /*****************************************************************************\
247 \*****************************************************************************/
249 static void sdhci_read_block_pio(struct sdhci_host *host)
252 size_t blksize, len, chunk;
253 u32 uninitialized_var(scratch);
256 DBG("PIO reading\n");
258 blksize = host->data->blksz;
261 local_irq_save(flags);
264 if (!sg_miter_next(&host->sg_miter))
267 len = min(host->sg_miter.length, blksize);
270 host->sg_miter.consumed = len;
272 buf = host->sg_miter.addr;
276 scratch = sdhci_readl(host, SDHCI_BUFFER);
280 *buf = scratch & 0xFF;
289 sg_miter_stop(&host->sg_miter);
291 local_irq_restore(flags);
294 static void sdhci_write_block_pio(struct sdhci_host *host)
297 size_t blksize, len, chunk;
301 DBG("PIO writing\n");
303 blksize = host->data->blksz;
307 local_irq_save(flags);
310 if (!sg_miter_next(&host->sg_miter))
313 len = min(host->sg_miter.length, blksize);
316 host->sg_miter.consumed = len;
318 buf = host->sg_miter.addr;
321 scratch |= (u32)*buf << (chunk * 8);
327 if ((chunk == 4) || ((len == 0) && (blksize == 0))) {
328 sdhci_writel(host, scratch, SDHCI_BUFFER);
335 sg_miter_stop(&host->sg_miter);
337 local_irq_restore(flags);
340 static void sdhci_transfer_pio(struct sdhci_host *host)
346 if (host->blocks == 0)
349 if (host->data->flags & MMC_DATA_READ)
350 mask = SDHCI_DATA_AVAILABLE;
352 mask = SDHCI_SPACE_AVAILABLE;
355 * Some controllers (JMicron JMB38x) mess up the buffer bits
356 * for transfers < 4 bytes. As long as it is just one block,
357 * we can ignore the bits.
359 if ((host->quirks & SDHCI_QUIRK_BROKEN_SMALL_PIO) &&
360 (host->data->blocks == 1))
363 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
364 if (host->quirks & SDHCI_QUIRK_PIO_NEEDS_DELAY)
367 if (host->data->flags & MMC_DATA_READ)
368 sdhci_read_block_pio(host);
370 sdhci_write_block_pio(host);
373 if (host->blocks == 0)
377 DBG("PIO transfer complete.\n");
380 static char *sdhci_kmap_atomic(struct scatterlist *sg, unsigned long *flags)
382 local_irq_save(*flags);
383 return kmap_atomic(sg_page(sg), KM_BIO_SRC_IRQ) + sg->offset;
386 static void sdhci_kunmap_atomic(void *buffer, unsigned long *flags)
388 kunmap_atomic(buffer, KM_BIO_SRC_IRQ);
389 local_irq_restore(*flags);
392 static void sdhci_set_adma_desc(u8 *desc, u32 addr, int len, unsigned cmd)
394 __le32 *dataddr = (__le32 __force *)(desc + 4);
395 __le16 *cmdlen = (__le16 __force *)desc;
397 /* SDHCI specification says ADMA descriptors should be 4 byte
398 * aligned, so using 16 or 32bit operations should be safe. */
400 cmdlen[0] = cpu_to_le16(cmd);
401 cmdlen[1] = cpu_to_le16(len);
403 dataddr[0] = cpu_to_le32(addr);
406 static int sdhci_adma_table_pre(struct sdhci_host *host,
407 struct mmc_data *data)
414 dma_addr_t align_addr;
417 struct scatterlist *sg;
423 * The spec does not specify endianness of descriptor table.
424 * We currently guess that it is LE.
427 if (data->flags & MMC_DATA_READ)
428 direction = DMA_FROM_DEVICE;
430 direction = DMA_TO_DEVICE;
433 * The ADMA descriptor table is mapped further down as we
434 * need to fill it with data first.
437 host->align_addr = dma_map_single(mmc_dev(host->mmc),
438 host->align_buffer, 128 * 4, direction);
439 if (dma_mapping_error(mmc_dev(host->mmc), host->align_addr))
441 BUG_ON(host->align_addr & 0x3);
443 host->sg_count = dma_map_sg(mmc_dev(host->mmc),
444 data->sg, data->sg_len, direction);
445 if (host->sg_count == 0)
448 desc = host->adma_desc;
449 align = host->align_buffer;
451 align_addr = host->align_addr;
453 for_each_sg(data->sg, sg, host->sg_count, i) {
454 addr = sg_dma_address(sg);
455 len = sg_dma_len(sg);
458 * The SDHCI specification states that ADMA
459 * addresses must be 32-bit aligned. If they
460 * aren't, then we use a bounce buffer for
461 * the (up to three) bytes that screw up the
464 offset = (4 - (addr & 0x3)) & 0x3;
466 if (data->flags & MMC_DATA_WRITE) {
467 buffer = sdhci_kmap_atomic(sg, &flags);
468 WARN_ON(((long)buffer & PAGE_MASK) > (PAGE_SIZE - 3));
469 memcpy(align, buffer, offset);
470 sdhci_kunmap_atomic(buffer, &flags);
474 sdhci_set_adma_desc(desc, align_addr, offset, 0x21);
476 BUG_ON(offset > 65536);
490 sdhci_set_adma_desc(desc, addr, len, 0x21);
494 * If this triggers then we have a calculation bug
497 WARN_ON((desc - host->adma_desc) > (128 * 2 + 1) * 4);
500 if (host->quirks & SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC) {
502 * Mark the last descriptor as the terminating descriptor
504 if (desc != host->adma_desc) {
506 desc[0] |= 0x2; /* end */
510 * Add a terminating entry.
513 /* nop, end, valid */
514 sdhci_set_adma_desc(desc, 0, 0, 0x3);
518 * Resync align buffer as we might have changed it.
520 if (data->flags & MMC_DATA_WRITE) {
521 dma_sync_single_for_device(mmc_dev(host->mmc),
522 host->align_addr, 128 * 4, direction);
525 host->adma_addr = dma_map_single(mmc_dev(host->mmc),
526 host->adma_desc, (128 * 2 + 1) * 4, DMA_TO_DEVICE);
527 if (dma_mapping_error(mmc_dev(host->mmc), host->adma_addr))
529 BUG_ON(host->adma_addr & 0x3);
534 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
535 data->sg_len, direction);
537 dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
543 static void sdhci_adma_table_post(struct sdhci_host *host,
544 struct mmc_data *data)
548 struct scatterlist *sg;
554 if (data->flags & MMC_DATA_READ)
555 direction = DMA_FROM_DEVICE;
557 direction = DMA_TO_DEVICE;
559 dma_unmap_single(mmc_dev(host->mmc), host->adma_addr,
560 (128 * 2 + 1) * 4, DMA_TO_DEVICE);
562 dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
565 if (data->flags & MMC_DATA_READ) {
566 dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg,
567 data->sg_len, direction);
569 align = host->align_buffer;
571 for_each_sg(data->sg, sg, host->sg_count, i) {
572 if (sg_dma_address(sg) & 0x3) {
573 size = 4 - (sg_dma_address(sg) & 0x3);
575 buffer = sdhci_kmap_atomic(sg, &flags);
576 WARN_ON(((long)buffer & PAGE_MASK) > (PAGE_SIZE - 3));
577 memcpy(buffer, align, size);
578 sdhci_kunmap_atomic(buffer, &flags);
585 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
586 data->sg_len, direction);
589 static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_data *data)
592 unsigned target_timeout, current_timeout;
595 * If the host controller provides us with an incorrect timeout
596 * value, just skip the check and use 0xE. The hardware may take
597 * longer to time out, but that's much better than having a too-short
600 if (host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL)
604 target_timeout = data->timeout_ns / 1000 +
605 data->timeout_clks / host->clock;
607 if (host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)
608 host->timeout_clk = host->clock / 1000;
611 * Figure out needed cycles.
612 * We do this in steps in order to fit inside a 32 bit int.
613 * The first step is the minimum timeout, which will have a
614 * minimum resolution of 6 bits:
615 * (1) 2^13*1000 > 2^22,
616 * (2) host->timeout_clk < 2^16
621 current_timeout = (1 << 13) * 1000 / host->timeout_clk;
622 while (current_timeout < target_timeout) {
624 current_timeout <<= 1;
630 printk(KERN_WARNING "%s: Too large timeout requested!\n",
631 mmc_hostname(host->mmc));
638 static void sdhci_set_transfer_irqs(struct sdhci_host *host)
640 u32 pio_irqs = SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL;
641 u32 dma_irqs = SDHCI_INT_DMA_END | SDHCI_INT_ADMA_ERROR;
643 if (host->flags & SDHCI_REQ_USE_DMA)
644 sdhci_clear_set_irqs(host, pio_irqs, dma_irqs);
646 sdhci_clear_set_irqs(host, dma_irqs, pio_irqs);
649 static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_data *data)
661 BUG_ON(data->blksz * data->blocks > 524288);
662 BUG_ON(data->blksz > host->mmc->max_blk_size);
663 BUG_ON(data->blocks > 65535);
666 host->data_early = 0;
668 count = sdhci_calc_timeout(host, data);
669 sdhci_writeb(host, count, SDHCI_TIMEOUT_CONTROL);
671 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))
672 host->flags |= SDHCI_REQ_USE_DMA;
675 * FIXME: This doesn't account for merging when mapping the
678 if (host->flags & SDHCI_REQ_USE_DMA) {
680 struct scatterlist *sg;
683 if (host->flags & SDHCI_USE_ADMA) {
684 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
687 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE)
691 if (unlikely(broken)) {
692 for_each_sg(data->sg, sg, data->sg_len, i) {
693 if (sg->length & 0x3) {
694 DBG("Reverting to PIO because of "
695 "transfer size (%d)\n",
697 host->flags &= ~SDHCI_REQ_USE_DMA;
705 * The assumption here being that alignment is the same after
706 * translation to device address space.
708 if (host->flags & SDHCI_REQ_USE_DMA) {
710 struct scatterlist *sg;
713 if (host->flags & SDHCI_USE_ADMA) {
715 * As we use 3 byte chunks to work around
716 * alignment problems, we need to check this
719 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
722 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR)
726 if (unlikely(broken)) {
727 for_each_sg(data->sg, sg, data->sg_len, i) {
728 if (sg->offset & 0x3) {
729 DBG("Reverting to PIO because of "
731 host->flags &= ~SDHCI_REQ_USE_DMA;
738 if (host->flags & SDHCI_REQ_USE_DMA) {
739 if (host->flags & SDHCI_USE_ADMA) {
740 ret = sdhci_adma_table_pre(host, data);
743 * This only happens when someone fed
744 * us an invalid request.
747 host->flags &= ~SDHCI_REQ_USE_DMA;
749 sdhci_writel(host, host->adma_addr,
755 sg_cnt = dma_map_sg(mmc_dev(host->mmc),
756 data->sg, data->sg_len,
757 (data->flags & MMC_DATA_READ) ?
762 * This only happens when someone fed
763 * us an invalid request.
766 host->flags &= ~SDHCI_REQ_USE_DMA;
768 WARN_ON(sg_cnt != 1);
769 sdhci_writel(host, sg_dma_address(data->sg),
776 * Always adjust the DMA selection as some controllers
777 * (e.g. JMicron) can't do PIO properly when the selection
780 if (host->version >= SDHCI_SPEC_200) {
781 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
782 ctrl &= ~SDHCI_CTRL_DMA_MASK;
783 if ((host->flags & SDHCI_REQ_USE_DMA) &&
784 (host->flags & SDHCI_USE_ADMA))
785 ctrl |= SDHCI_CTRL_ADMA32;
787 ctrl |= SDHCI_CTRL_SDMA;
788 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
791 if (!(host->flags & SDHCI_REQ_USE_DMA)) {
794 flags = SG_MITER_ATOMIC;
795 if (host->data->flags & MMC_DATA_READ)
796 flags |= SG_MITER_TO_SG;
798 flags |= SG_MITER_FROM_SG;
799 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
800 host->blocks = data->blocks;
803 sdhci_set_transfer_irqs(host);
805 /* We do not handle DMA boundaries, so set it to max (512 KiB) */
806 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, data->blksz), SDHCI_BLOCK_SIZE);
807 sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
810 static void sdhci_set_transfer_mode(struct sdhci_host *host,
811 struct mmc_data *data)
818 WARN_ON(!host->data);
820 mode = SDHCI_TRNS_BLK_CNT_EN;
821 if (data->blocks > 1) {
822 if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12)
823 mode |= SDHCI_TRNS_MULTI | SDHCI_TRNS_ACMD12;
825 mode |= SDHCI_TRNS_MULTI;
827 if (data->flags & MMC_DATA_READ)
828 mode |= SDHCI_TRNS_READ;
829 if (host->flags & SDHCI_REQ_USE_DMA)
830 mode |= SDHCI_TRNS_DMA;
832 sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
835 static void sdhci_finish_data(struct sdhci_host *host)
837 struct mmc_data *data;
844 if (host->flags & SDHCI_REQ_USE_DMA) {
845 if (host->flags & SDHCI_USE_ADMA)
846 sdhci_adma_table_post(host, data);
848 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
849 data->sg_len, (data->flags & MMC_DATA_READ) ?
850 DMA_FROM_DEVICE : DMA_TO_DEVICE);
855 * The specification states that the block count register must
856 * be updated, but it does not specify at what point in the
857 * data flow. That makes the register entirely useless to read
858 * back so we have to assume that nothing made it to the card
859 * in the event of an error.
862 data->bytes_xfered = 0;
864 data->bytes_xfered = data->blksz * data->blocks;
868 * The controller needs a reset of internal state machines
869 * upon error conditions.
872 sdhci_reset(host, SDHCI_RESET_CMD);
873 sdhci_reset(host, SDHCI_RESET_DATA);
876 sdhci_send_command(host, data->stop);
878 tasklet_schedule(&host->finish_tasklet);
881 static void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
885 unsigned long timeout;
892 mask = SDHCI_CMD_INHIBIT;
893 if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY))
894 mask |= SDHCI_DATA_INHIBIT;
896 /* We shouldn't wait for data inihibit for stop commands, even
897 though they might use busy signaling */
898 if (host->mrq->data && (cmd == host->mrq->data->stop))
899 mask &= ~SDHCI_DATA_INHIBIT;
901 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
903 printk(KERN_ERR "%s: Controller never released "
904 "inhibit bit(s).\n", mmc_hostname(host->mmc));
905 sdhci_dumpregs(host);
907 tasklet_schedule(&host->finish_tasklet);
914 mod_timer(&host->timer, jiffies + 10 * HZ);
918 sdhci_prepare_data(host, cmd->data);
920 sdhci_writel(host, cmd->arg, SDHCI_ARGUMENT);
922 sdhci_set_transfer_mode(host, cmd->data);
924 if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
925 printk(KERN_ERR "%s: Unsupported response type!\n",
926 mmc_hostname(host->mmc));
927 cmd->error = -EINVAL;
928 tasklet_schedule(&host->finish_tasklet);
932 if (!(cmd->flags & MMC_RSP_PRESENT))
933 flags = SDHCI_CMD_RESP_NONE;
934 else if (cmd->flags & MMC_RSP_136)
935 flags = SDHCI_CMD_RESP_LONG;
936 else if (cmd->flags & MMC_RSP_BUSY)
937 flags = SDHCI_CMD_RESP_SHORT_BUSY;
939 flags = SDHCI_CMD_RESP_SHORT;
941 if (cmd->flags & MMC_RSP_CRC)
942 flags |= SDHCI_CMD_CRC;
943 if (cmd->flags & MMC_RSP_OPCODE)
944 flags |= SDHCI_CMD_INDEX;
946 flags |= SDHCI_CMD_DATA;
948 sdhci_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND);
951 static void sdhci_finish_command(struct sdhci_host *host)
955 BUG_ON(host->cmd == NULL);
957 if (host->cmd->flags & MMC_RSP_PRESENT) {
958 if (host->cmd->flags & MMC_RSP_136) {
959 /* CRC is stripped so we need to do some shifting. */
960 for (i = 0;i < 4;i++) {
961 host->cmd->resp[i] = sdhci_readl(host,
962 SDHCI_RESPONSE + (3-i)*4) << 8;
964 host->cmd->resp[i] |=
966 SDHCI_RESPONSE + (3-i)*4-1);
969 host->cmd->resp[0] = sdhci_readl(host, SDHCI_RESPONSE);
973 host->cmd->error = 0;
975 if (host->data && host->data_early)
976 sdhci_finish_data(host);
978 if (!host->cmd->data)
979 tasklet_schedule(&host->finish_tasklet);
984 static void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
988 unsigned long timeout;
990 if (clock == host->clock)
993 if (host->ops->set_clock) {
994 host->ops->set_clock(host, clock);
995 if (host->quirks & SDHCI_QUIRK_NONSTANDARD_CLOCK)
999 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
1004 for (div = 1;div < 256;div *= 2) {
1005 if ((host->max_clk / div) <= clock)
1010 clk = div << SDHCI_DIVIDER_SHIFT;
1011 clk |= SDHCI_CLOCK_INT_EN;
1012 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1014 /* Wait max 20 ms */
1016 while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
1017 & SDHCI_CLOCK_INT_STABLE)) {
1019 printk(KERN_ERR "%s: Internal clock never "
1020 "stabilised.\n", mmc_hostname(host->mmc));
1021 sdhci_dumpregs(host);
1028 clk |= SDHCI_CLOCK_CARD_EN;
1029 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1032 host->clock = clock;
1035 static void sdhci_set_power(struct sdhci_host *host, unsigned short power)
1039 if (power == (unsigned short)-1)
1042 switch (1 << power) {
1043 case MMC_VDD_165_195:
1044 pwr = SDHCI_POWER_180;
1048 pwr = SDHCI_POWER_300;
1052 pwr = SDHCI_POWER_330;
1059 if (host->pwr == pwr)
1065 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1070 * Spec says that we should clear the power reg before setting
1071 * a new value. Some controllers don't seem to like this though.
1073 if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE))
1074 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1077 * At least the Marvell CaFe chip gets confused if we set the voltage
1078 * and set turn on power at the same time, so set the voltage first.
1080 if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER)
1081 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1083 pwr |= SDHCI_POWER_ON;
1085 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1088 * Some controllers need an extra 10ms delay of 10ms before they
1089 * can apply clock after applying power
1091 if (host->quirks & SDHCI_QUIRK_DELAY_AFTER_POWER)
1095 /*****************************************************************************\
1099 \*****************************************************************************/
1101 static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1103 struct sdhci_host *host;
1105 unsigned long flags;
1107 host = mmc_priv(mmc);
1109 spin_lock_irqsave(&host->lock, flags);
1111 WARN_ON(host->mrq != NULL);
1113 #ifndef SDHCI_USE_LEDS_CLASS
1114 sdhci_activate_led(host);
1116 if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12) {
1118 mrq->data->stop = NULL;
1125 /* If polling, assume that the card is always present. */
1126 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
1129 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
1132 if (!present || host->flags & SDHCI_DEVICE_DEAD) {
1133 host->mrq->cmd->error = -ENOMEDIUM;
1134 tasklet_schedule(&host->finish_tasklet);
1136 sdhci_send_command(host, mrq->cmd);
1139 spin_unlock_irqrestore(&host->lock, flags);
1142 static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1144 struct sdhci_host *host;
1145 unsigned long flags;
1148 host = mmc_priv(mmc);
1150 spin_lock_irqsave(&host->lock, flags);
1152 if (host->flags & SDHCI_DEVICE_DEAD)
1156 * Reset the chip on each power off.
1157 * Should clear out any weird states.
1159 if (ios->power_mode == MMC_POWER_OFF) {
1160 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
1164 sdhci_set_clock(host, ios->clock);
1166 if (ios->power_mode == MMC_POWER_OFF)
1167 sdhci_set_power(host, -1);
1169 sdhci_set_power(host, ios->vdd);
1171 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1173 if (ios->bus_width == MMC_BUS_WIDTH_8)
1174 ctrl |= SDHCI_CTRL_8BITBUS;
1176 ctrl &= ~SDHCI_CTRL_8BITBUS;
1178 if (ios->bus_width == MMC_BUS_WIDTH_4)
1179 ctrl |= SDHCI_CTRL_4BITBUS;
1181 ctrl &= ~SDHCI_CTRL_4BITBUS;
1183 if (ios->timing == MMC_TIMING_SD_HS)
1184 ctrl |= SDHCI_CTRL_HISPD;
1186 ctrl &= ~SDHCI_CTRL_HISPD;
1188 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1191 * Some (ENE) controllers go apeshit on some ios operation,
1192 * signalling timeout and CRC errors even on CMD0. Resetting
1193 * it on each ios seems to solve the problem.
1195 if(host->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS)
1196 sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
1200 spin_unlock_irqrestore(&host->lock, flags);
1203 static int sdhci_get_ro(struct mmc_host *mmc)
1205 struct sdhci_host *host;
1206 unsigned long flags;
1209 host = mmc_priv(mmc);
1211 spin_lock_irqsave(&host->lock, flags);
1213 if (host->flags & SDHCI_DEVICE_DEAD)
1216 present = sdhci_readl(host, SDHCI_PRESENT_STATE);
1218 spin_unlock_irqrestore(&host->lock, flags);
1220 if (host->quirks & SDHCI_QUIRK_INVERTED_WRITE_PROTECT)
1221 return !!(present & SDHCI_WRITE_PROTECT);
1222 return !(present & SDHCI_WRITE_PROTECT);
1225 static void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable)
1227 struct sdhci_host *host;
1228 unsigned long flags;
1230 host = mmc_priv(mmc);
1232 spin_lock_irqsave(&host->lock, flags);
1234 if (host->flags & SDHCI_DEVICE_DEAD)
1238 sdhci_unmask_irqs(host, SDHCI_INT_CARD_INT);
1240 sdhci_mask_irqs(host, SDHCI_INT_CARD_INT);
1244 spin_unlock_irqrestore(&host->lock, flags);
1247 static const struct mmc_host_ops sdhci_ops = {
1248 .request = sdhci_request,
1249 .set_ios = sdhci_set_ios,
1250 .get_ro = sdhci_get_ro,
1251 .enable_sdio_irq = sdhci_enable_sdio_irq,
1254 /*****************************************************************************\
1258 \*****************************************************************************/
1260 static void sdhci_tasklet_card(unsigned long param)
1262 struct sdhci_host *host;
1263 unsigned long flags;
1265 host = (struct sdhci_host*)param;
1267 spin_lock_irqsave(&host->lock, flags);
1269 if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT)) {
1271 printk(KERN_ERR "%s: Card removed during transfer!\n",
1272 mmc_hostname(host->mmc));
1273 printk(KERN_ERR "%s: Resetting controller.\n",
1274 mmc_hostname(host->mmc));
1276 sdhci_reset(host, SDHCI_RESET_CMD);
1277 sdhci_reset(host, SDHCI_RESET_DATA);
1279 host->mrq->cmd->error = -ENOMEDIUM;
1280 tasklet_schedule(&host->finish_tasklet);
1284 spin_unlock_irqrestore(&host->lock, flags);
1286 mmc_detect_change(host->mmc, msecs_to_jiffies(200));
1289 static void sdhci_tasklet_finish(unsigned long param)
1291 struct sdhci_host *host;
1292 unsigned long flags;
1293 struct mmc_request *mrq;
1295 host = (struct sdhci_host*)param;
1297 spin_lock_irqsave(&host->lock, flags);
1299 del_timer(&host->timer);
1304 * The controller needs a reset of internal state machines
1305 * upon error conditions.
1307 if (!(host->flags & SDHCI_DEVICE_DEAD) &&
1309 (mrq->data && (mrq->data->error ||
1310 (mrq->data->stop && mrq->data->stop->error))) ||
1311 (host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST))) {
1313 /* Some controllers need this kick or reset won't work here */
1314 if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET) {
1317 /* This is to force an update */
1318 clock = host->clock;
1320 sdhci_set_clock(host, clock);
1323 /* Spec says we should do both at the same time, but Ricoh
1324 controllers do not like that. */
1325 sdhci_reset(host, SDHCI_RESET_CMD);
1326 sdhci_reset(host, SDHCI_RESET_DATA);
1333 #ifndef SDHCI_USE_LEDS_CLASS
1334 sdhci_deactivate_led(host);
1338 spin_unlock_irqrestore(&host->lock, flags);
1340 mmc_request_done(host->mmc, mrq);
1343 static void sdhci_timeout_timer(unsigned long data)
1345 struct sdhci_host *host;
1346 unsigned long flags;
1348 host = (struct sdhci_host*)data;
1350 spin_lock_irqsave(&host->lock, flags);
1353 printk(KERN_ERR "%s: Timeout waiting for hardware "
1354 "interrupt.\n", mmc_hostname(host->mmc));
1355 sdhci_dumpregs(host);
1358 host->data->error = -ETIMEDOUT;
1359 sdhci_finish_data(host);
1362 host->cmd->error = -ETIMEDOUT;
1364 host->mrq->cmd->error = -ETIMEDOUT;
1366 tasklet_schedule(&host->finish_tasklet);
1371 spin_unlock_irqrestore(&host->lock, flags);
1374 /*****************************************************************************\
1376 * Interrupt handling *
1378 \*****************************************************************************/
1380 static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask)
1382 BUG_ON(intmask == 0);
1385 printk(KERN_ERR "%s: Got command interrupt 0x%08x even "
1386 "though no command operation was in progress.\n",
1387 mmc_hostname(host->mmc), (unsigned)intmask);
1388 sdhci_dumpregs(host);
1392 if (intmask & SDHCI_INT_TIMEOUT)
1393 host->cmd->error = -ETIMEDOUT;
1394 else if (intmask & (SDHCI_INT_CRC | SDHCI_INT_END_BIT |
1396 host->cmd->error = -EILSEQ;
1398 if (host->cmd->error) {
1399 tasklet_schedule(&host->finish_tasklet);
1404 * The host can send and interrupt when the busy state has
1405 * ended, allowing us to wait without wasting CPU cycles.
1406 * Unfortunately this is overloaded on the "data complete"
1407 * interrupt, so we need to take some care when handling
1410 * Note: The 1.0 specification is a bit ambiguous about this
1411 * feature so there might be some problems with older
1414 if (host->cmd->flags & MMC_RSP_BUSY) {
1415 if (host->cmd->data)
1416 DBG("Cannot wait for busy signal when also "
1417 "doing a data transfer");
1418 else if (!(host->quirks & SDHCI_QUIRK_NO_BUSY_IRQ))
1421 /* The controller does not support the end-of-busy IRQ,
1422 * fall through and take the SDHCI_INT_RESPONSE */
1425 if (intmask & SDHCI_INT_RESPONSE)
1426 sdhci_finish_command(host);
1430 static void sdhci_show_adma_error(struct sdhci_host *host)
1432 const char *name = mmc_hostname(host->mmc);
1433 u8 *desc = host->adma_desc;
1438 sdhci_dumpregs(host);
1441 dma = (__le32 *)(desc + 4);
1442 len = (__le16 *)(desc + 2);
1445 DBG("%s: %p: DMA 0x%08x, LEN 0x%04x, Attr=0x%02x\n",
1446 name, desc, le32_to_cpu(*dma), le16_to_cpu(*len), attr);
1455 static void sdhci_show_adma_error(struct sdhci_host *host) { }
1458 static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
1460 BUG_ON(intmask == 0);
1464 * The "data complete" interrupt is also used to
1465 * indicate that a busy state has ended. See comment
1466 * above in sdhci_cmd_irq().
1468 if (host->cmd && (host->cmd->flags & MMC_RSP_BUSY)) {
1469 if (intmask & SDHCI_INT_DATA_END) {
1470 sdhci_finish_command(host);
1475 printk(KERN_ERR "%s: Got data interrupt 0x%08x even "
1476 "though no data operation was in progress.\n",
1477 mmc_hostname(host->mmc), (unsigned)intmask);
1478 sdhci_dumpregs(host);
1483 if (intmask & SDHCI_INT_DATA_TIMEOUT)
1484 host->data->error = -ETIMEDOUT;
1485 else if (intmask & (SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_END_BIT))
1486 host->data->error = -EILSEQ;
1487 else if (intmask & SDHCI_INT_ADMA_ERROR) {
1488 printk(KERN_ERR "%s: ADMA error\n", mmc_hostname(host->mmc));
1489 sdhci_show_adma_error(host);
1490 host->data->error = -EIO;
1493 if (host->data->error)
1494 sdhci_finish_data(host);
1496 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
1497 sdhci_transfer_pio(host);
1500 * We currently don't do anything fancy with DMA
1501 * boundaries, but as we can't disable the feature
1502 * we need to at least restart the transfer.
1504 if (intmask & SDHCI_INT_DMA_END)
1505 sdhci_writel(host, sdhci_readl(host, SDHCI_DMA_ADDRESS),
1508 if (intmask & SDHCI_INT_DATA_END) {
1511 * Data managed to finish before the
1512 * command completed. Make sure we do
1513 * things in the proper order.
1515 host->data_early = 1;
1517 sdhci_finish_data(host);
1523 static irqreturn_t sdhci_irq(int irq, void *dev_id)
1526 struct sdhci_host* host = dev_id;
1530 spin_lock(&host->lock);
1532 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
1534 if (!intmask || intmask == 0xffffffff) {
1539 DBG("*** %s got interrupt: 0x%08x\n",
1540 mmc_hostname(host->mmc), intmask);
1542 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
1543 sdhci_writel(host, intmask & (SDHCI_INT_CARD_INSERT |
1544 SDHCI_INT_CARD_REMOVE), SDHCI_INT_STATUS);
1545 tasklet_schedule(&host->card_tasklet);
1548 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE);
1550 if (intmask & SDHCI_INT_CMD_MASK) {
1551 sdhci_writel(host, intmask & SDHCI_INT_CMD_MASK,
1553 sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK);
1556 if (intmask & SDHCI_INT_DATA_MASK) {
1557 sdhci_writel(host, intmask & SDHCI_INT_DATA_MASK,
1559 sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
1562 intmask &= ~(SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK);
1564 intmask &= ~SDHCI_INT_ERROR;
1566 if (intmask & SDHCI_INT_BUS_POWER) {
1567 printk(KERN_ERR "%s: Card is consuming too much power!\n",
1568 mmc_hostname(host->mmc));
1569 sdhci_writel(host, SDHCI_INT_BUS_POWER, SDHCI_INT_STATUS);
1572 intmask &= ~SDHCI_INT_BUS_POWER;
1574 if (intmask & SDHCI_INT_CARD_INT)
1577 intmask &= ~SDHCI_INT_CARD_INT;
1580 printk(KERN_ERR "%s: Unexpected interrupt 0x%08x.\n",
1581 mmc_hostname(host->mmc), intmask);
1582 sdhci_dumpregs(host);
1584 sdhci_writel(host, intmask, SDHCI_INT_STATUS);
1587 result = IRQ_HANDLED;
1591 spin_unlock(&host->lock);
1594 * We have to delay this as it calls back into the driver.
1597 mmc_signal_sdio_irq(host->mmc);
1602 /*****************************************************************************\
1606 \*****************************************************************************/
1610 int sdhci_suspend_host(struct sdhci_host *host, pm_message_t state)
1614 sdhci_disable_card_detection(host);
1616 ret = mmc_suspend_host(host->mmc);
1620 free_irq(host->irq, host);
1623 ret = regulator_disable(host->vmmc);
1628 EXPORT_SYMBOL_GPL(sdhci_suspend_host);
1630 int sdhci_resume_host(struct sdhci_host *host)
1635 int ret = regulator_enable(host->vmmc);
1641 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
1642 if (host->ops->enable_dma)
1643 host->ops->enable_dma(host);
1646 ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED,
1647 mmc_hostname(host->mmc), host);
1651 sdhci_init(host, (host->mmc->pm_flags & MMC_PM_KEEP_POWER));
1654 ret = mmc_resume_host(host->mmc);
1655 sdhci_enable_card_detection(host);
1660 EXPORT_SYMBOL_GPL(sdhci_resume_host);
1662 #endif /* CONFIG_PM */
1664 /*****************************************************************************\
1666 * Device allocation/registration *
1668 \*****************************************************************************/
1670 struct sdhci_host *sdhci_alloc_host(struct device *dev,
1673 struct mmc_host *mmc;
1674 struct sdhci_host *host;
1676 WARN_ON(dev == NULL);
1678 mmc = mmc_alloc_host(sizeof(struct sdhci_host) + priv_size, dev);
1680 return ERR_PTR(-ENOMEM);
1682 host = mmc_priv(mmc);
1688 EXPORT_SYMBOL_GPL(sdhci_alloc_host);
1690 int sdhci_add_host(struct sdhci_host *host)
1692 struct mmc_host *mmc;
1696 WARN_ON(host == NULL);
1703 host->quirks = debug_quirks;
1705 sdhci_reset(host, SDHCI_RESET_ALL);
1707 host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
1708 host->version = (host->version & SDHCI_SPEC_VER_MASK)
1709 >> SDHCI_SPEC_VER_SHIFT;
1710 if (host->version > SDHCI_SPEC_200) {
1711 printk(KERN_ERR "%s: Unknown controller version (%d). "
1712 "You may experience problems.\n", mmc_hostname(mmc),
1716 caps = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ? host->caps :
1717 sdhci_readl(host, SDHCI_CAPABILITIES);
1719 if (host->quirks & SDHCI_QUIRK_FORCE_DMA)
1720 host->flags |= SDHCI_USE_SDMA;
1721 else if (!(caps & SDHCI_CAN_DO_SDMA))
1722 DBG("Controller doesn't have SDMA capability\n");
1724 host->flags |= SDHCI_USE_SDMA;
1726 if ((host->quirks & SDHCI_QUIRK_BROKEN_DMA) &&
1727 (host->flags & SDHCI_USE_SDMA)) {
1728 DBG("Disabling DMA as it is marked broken\n");
1729 host->flags &= ~SDHCI_USE_SDMA;
1732 if ((host->version >= SDHCI_SPEC_200) && (caps & SDHCI_CAN_DO_ADMA2))
1733 host->flags |= SDHCI_USE_ADMA;
1735 if ((host->quirks & SDHCI_QUIRK_BROKEN_ADMA) &&
1736 (host->flags & SDHCI_USE_ADMA)) {
1737 DBG("Disabling ADMA as it is marked broken\n");
1738 host->flags &= ~SDHCI_USE_ADMA;
1741 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
1742 if (host->ops->enable_dma) {
1743 if (host->ops->enable_dma(host)) {
1744 printk(KERN_WARNING "%s: No suitable DMA "
1745 "available. Falling back to PIO.\n",
1748 ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA);
1753 if (host->flags & SDHCI_USE_ADMA) {
1755 * We need to allocate descriptors for all sg entries
1756 * (128) and potentially one alignment transfer for
1757 * each of those entries.
1759 host->adma_desc = kmalloc((128 * 2 + 1) * 4, GFP_KERNEL);
1760 host->align_buffer = kmalloc(128 * 4, GFP_KERNEL);
1761 if (!host->adma_desc || !host->align_buffer) {
1762 kfree(host->adma_desc);
1763 kfree(host->align_buffer);
1764 printk(KERN_WARNING "%s: Unable to allocate ADMA "
1765 "buffers. Falling back to standard DMA.\n",
1767 host->flags &= ~SDHCI_USE_ADMA;
1772 * If we use DMA, then it's up to the caller to set the DMA
1773 * mask, but PIO does not need the hw shim so we set a new
1774 * mask here in that case.
1776 if (!(host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))) {
1777 host->dma_mask = DMA_BIT_MASK(64);
1778 mmc_dev(host->mmc)->dma_mask = &host->dma_mask;
1782 (caps & SDHCI_CLOCK_BASE_MASK) >> SDHCI_CLOCK_BASE_SHIFT;
1783 host->max_clk *= 1000000;
1784 if (host->max_clk == 0 || host->quirks &
1785 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN) {
1786 if (!host->ops->get_max_clock) {
1788 "%s: Hardware doesn't specify base clock "
1789 "frequency.\n", mmc_hostname(mmc));
1792 host->max_clk = host->ops->get_max_clock(host);
1796 (caps & SDHCI_TIMEOUT_CLK_MASK) >> SDHCI_TIMEOUT_CLK_SHIFT;
1797 if (host->timeout_clk == 0) {
1798 if (host->ops->get_timeout_clock) {
1799 host->timeout_clk = host->ops->get_timeout_clock(host);
1800 } else if (!(host->quirks &
1801 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)) {
1803 "%s: Hardware doesn't specify timeout clock "
1804 "frequency.\n", mmc_hostname(mmc));
1808 if (caps & SDHCI_TIMEOUT_CLK_UNIT)
1809 host->timeout_clk *= 1000;
1812 * Set host parameters.
1814 mmc->ops = &sdhci_ops;
1815 if (host->ops->get_min_clock)
1816 mmc->f_min = host->ops->get_min_clock(host);
1818 mmc->f_min = host->max_clk / 256;
1819 mmc->f_max = host->max_clk;
1820 mmc->caps |= MMC_CAP_SDIO_IRQ;
1822 if (!(host->quirks & SDHCI_QUIRK_FORCE_1_BIT_DATA))
1823 mmc->caps |= MMC_CAP_4_BIT_DATA;
1825 if (caps & SDHCI_CAN_DO_HISPD)
1826 mmc->caps |= MMC_CAP_SD_HIGHSPEED;
1828 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
1829 mmc->caps |= MMC_CAP_NEEDS_POLL;
1832 if (caps & SDHCI_CAN_VDD_330)
1833 mmc->ocr_avail |= MMC_VDD_32_33|MMC_VDD_33_34;
1834 if (caps & SDHCI_CAN_VDD_300)
1835 mmc->ocr_avail |= MMC_VDD_29_30|MMC_VDD_30_31;
1836 if (caps & SDHCI_CAN_VDD_180)
1837 mmc->ocr_avail |= MMC_VDD_165_195;
1839 if (mmc->ocr_avail == 0) {
1840 printk(KERN_ERR "%s: Hardware doesn't report any "
1841 "support voltages.\n", mmc_hostname(mmc));
1845 spin_lock_init(&host->lock);
1848 * Maximum number of segments. Depends on if the hardware
1849 * can do scatter/gather or not.
1851 if (host->flags & SDHCI_USE_ADMA)
1852 mmc->max_hw_segs = 128;
1853 else if (host->flags & SDHCI_USE_SDMA)
1854 mmc->max_hw_segs = 1;
1856 mmc->max_hw_segs = 128;
1857 mmc->max_phys_segs = 128;
1860 * Maximum number of sectors in one transfer. Limited by DMA boundary
1863 mmc->max_req_size = 524288;
1866 * Maximum segment size. Could be one segment with the maximum number
1867 * of bytes. When doing hardware scatter/gather, each entry cannot
1868 * be larger than 64 KiB though.
1870 if (host->flags & SDHCI_USE_ADMA)
1871 mmc->max_seg_size = 65536;
1873 mmc->max_seg_size = mmc->max_req_size;
1876 * Maximum block size. This varies from controller to controller and
1877 * is specified in the capabilities register.
1879 if (host->quirks & SDHCI_QUIRK_FORCE_BLK_SZ_2048) {
1880 mmc->max_blk_size = 2;
1882 mmc->max_blk_size = (caps & SDHCI_MAX_BLOCK_MASK) >>
1883 SDHCI_MAX_BLOCK_SHIFT;
1884 if (mmc->max_blk_size >= 3) {
1885 printk(KERN_WARNING "%s: Invalid maximum block size, "
1886 "assuming 512 bytes\n", mmc_hostname(mmc));
1887 mmc->max_blk_size = 0;
1891 mmc->max_blk_size = 512 << mmc->max_blk_size;
1894 * Maximum block count.
1896 mmc->max_blk_count = (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535;
1901 tasklet_init(&host->card_tasklet,
1902 sdhci_tasklet_card, (unsigned long)host);
1903 tasklet_init(&host->finish_tasklet,
1904 sdhci_tasklet_finish, (unsigned long)host);
1906 setup_timer(&host->timer, sdhci_timeout_timer, (unsigned long)host);
1908 ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED,
1909 mmc_hostname(mmc), host);
1913 host->vmmc = regulator_get(mmc_dev(mmc), "vmmc");
1914 if (IS_ERR(host->vmmc)) {
1915 printk(KERN_INFO "%s: no vmmc regulator found\n", mmc_hostname(mmc));
1918 regulator_enable(host->vmmc);
1921 sdhci_init(host, 0);
1923 #ifdef CONFIG_MMC_DEBUG
1924 sdhci_dumpregs(host);
1927 #ifdef SDHCI_USE_LEDS_CLASS
1928 snprintf(host->led_name, sizeof(host->led_name),
1929 "%s::", mmc_hostname(mmc));
1930 host->led.name = host->led_name;
1931 host->led.brightness = LED_OFF;
1932 host->led.default_trigger = mmc_hostname(mmc);
1933 host->led.brightness_set = sdhci_led_control;
1935 ret = led_classdev_register(mmc_dev(mmc), &host->led);
1944 printk(KERN_INFO "%s: SDHCI controller on %s [%s] using %s\n",
1945 mmc_hostname(mmc), host->hw_name, dev_name(mmc_dev(mmc)),
1946 (host->flags & SDHCI_USE_ADMA) ? "ADMA" :
1947 (host->flags & SDHCI_USE_SDMA) ? "DMA" : "PIO");
1949 sdhci_enable_card_detection(host);
1953 #ifdef SDHCI_USE_LEDS_CLASS
1955 sdhci_reset(host, SDHCI_RESET_ALL);
1956 free_irq(host->irq, host);
1959 tasklet_kill(&host->card_tasklet);
1960 tasklet_kill(&host->finish_tasklet);
1965 EXPORT_SYMBOL_GPL(sdhci_add_host);
1967 void sdhci_remove_host(struct sdhci_host *host, int dead)
1969 unsigned long flags;
1972 spin_lock_irqsave(&host->lock, flags);
1974 host->flags |= SDHCI_DEVICE_DEAD;
1977 printk(KERN_ERR "%s: Controller removed during "
1978 " transfer!\n", mmc_hostname(host->mmc));
1980 host->mrq->cmd->error = -ENOMEDIUM;
1981 tasklet_schedule(&host->finish_tasklet);
1984 spin_unlock_irqrestore(&host->lock, flags);
1987 sdhci_disable_card_detection(host);
1989 mmc_remove_host(host->mmc);
1991 #ifdef SDHCI_USE_LEDS_CLASS
1992 led_classdev_unregister(&host->led);
1996 sdhci_reset(host, SDHCI_RESET_ALL);
1998 free_irq(host->irq, host);
2000 del_timer_sync(&host->timer);
2002 tasklet_kill(&host->card_tasklet);
2003 tasklet_kill(&host->finish_tasklet);
2006 regulator_disable(host->vmmc);
2007 regulator_put(host->vmmc);
2010 kfree(host->adma_desc);
2011 kfree(host->align_buffer);
2013 host->adma_desc = NULL;
2014 host->align_buffer = NULL;
2017 EXPORT_SYMBOL_GPL(sdhci_remove_host);
2019 void sdhci_free_host(struct sdhci_host *host)
2021 mmc_free_host(host->mmc);
2024 EXPORT_SYMBOL_GPL(sdhci_free_host);
2026 /*****************************************************************************\
2028 * Driver init/exit *
2030 \*****************************************************************************/
2032 static int __init sdhci_drv_init(void)
2034 printk(KERN_INFO DRIVER_NAME
2035 ": Secure Digital Host Controller Interface driver\n");
2036 printk(KERN_INFO DRIVER_NAME ": Copyright(c) Pierre Ossman\n");
2041 static void __exit sdhci_drv_exit(void)
2045 module_init(sdhci_drv_init);
2046 module_exit(sdhci_drv_exit);
2048 module_param(debug_quirks, uint, 0444);
2050 MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
2051 MODULE_DESCRIPTION("Secure Digital Host Controller Interface core driver");
2052 MODULE_LICENSE("GPL");
2054 MODULE_PARM_DESC(debug_quirks, "Force certain quirks.");