drivers/mmc/host/sdhci.c

   1 /*
   2  *  linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver
   3  *
   4  *  Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or (at
   9  * your option) any later version.
  10  *
  11  * Thanks to the following companies for their support:
  12  *
  13  *     - JMicron (hardware and technical support)
  14  */
  15
  16 #include <linux/delay.h>
  17 #include <linux/highmem.h>
  18 #include <linux/io.h>
  19 #include <linux/dma-mapping.h>
  20 #include <linux/slab.h>
  21 #include <linux/scatterlist.h>
  22 #include <linux/regulator/consumer.h>
  23
  24 #include <linux/leds.h>
  25
  26 #include <linux/mmc/host.h>
  27 #include <linux/mmc/card.h>
  28
  29 #include "sdhci.h"
  30
  31 #define DRIVER_NAME "sdhci"
  32
  33 #define DBG(f, x...) \
  34         pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x)
  35
  36 #if defined(CONFIG_LEDS_CLASS) || (defined(CONFIG_LEDS_CLASS_MODULE) && \
  37         defined(CONFIG_MMC_SDHCI_MODULE))
  38 #define SDHCI_USE_LEDS_CLASS
  39 #endif
  40
  41 static unsigned int debug_quirks = 0;
  42
  43 static void sdhci_prepare_data(struct sdhci_host *, struct mmc_data *);
  44 static void sdhci_finish_data(struct sdhci_host *);
  45
  46 static void sdhci_send_command(struct sdhci_host *, struct mmc_command *);
  47 static void sdhci_finish_command(struct sdhci_host *);
  48
  49 static void sdhci_dumpregs(struct sdhci_host *host)
  50 {
  51         printk(KERN_DEBUG DRIVER_NAME ": ============== REGISTER DUMP ==============\n");
  52
  53         printk(KERN_DEBUG DRIVER_NAME ": Sys addr: 0x%08x | Version:  0x%08x\n",
  54                 sdhci_readl(host, SDHCI_DMA_ADDRESS),
  55                 sdhci_readw(host, SDHCI_HOST_VERSION));
  56         printk(KERN_DEBUG DRIVER_NAME ": Blk size: 0x%08x | Blk cnt:  0x%08x\n",
  57                 sdhci_readw(host, SDHCI_BLOCK_SIZE),
  58                 sdhci_readw(host, SDHCI_BLOCK_COUNT));
  59         printk(KERN_DEBUG DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n",
  60                 sdhci_readl(host, SDHCI_ARGUMENT),
  61                 sdhci_readw(host, SDHCI_TRANSFER_MODE));
  62         printk(KERN_DEBUG DRIVER_NAME ": Present:  0x%08x | Host ctl: 0x%08x\n",
  63                 sdhci_readl(host, SDHCI_PRESENT_STATE),
  64                 sdhci_readb(host, SDHCI_HOST_CONTROL));
  65         printk(KERN_DEBUG DRIVER_NAME ": Power:    0x%08x | Blk gap:  0x%08x\n",
  66                 sdhci_readb(host, SDHCI_POWER_CONTROL),
  67                 sdhci_readb(host, SDHCI_BLOCK_GAP_CONTROL));
  68         printk(KERN_DEBUG DRIVER_NAME ": Wake-up:  0x%08x | Clock:    0x%08x\n",
  69                 sdhci_readb(host, SDHCI_WAKE_UP_CONTROL),
  70                 sdhci_readw(host, SDHCI_CLOCK_CONTROL));
  71         printk(KERN_DEBUG DRIVER_NAME ": Timeout:  0x%08x | Int stat: 0x%08x\n",
  72                 sdhci_readb(host, SDHCI_TIMEOUT_CONTROL),
  73                 sdhci_readl(host, SDHCI_INT_STATUS));
  74         printk(KERN_DEBUG DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n",
  75                 sdhci_readl(host, SDHCI_INT_ENABLE),
  76                 sdhci_readl(host, SDHCI_SIGNAL_ENABLE));
  77         printk(KERN_DEBUG DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n",
  78                 sdhci_readw(host, SDHCI_ACMD12_ERR),
  79                 sdhci_readw(host, SDHCI_SLOT_INT_STATUS));
  80         printk(KERN_DEBUG DRIVER_NAME ": Caps:     0x%08x | Max curr: 0x%08x\n",
  81                 sdhci_readl(host, SDHCI_CAPABILITIES),
  82                 sdhci_readl(host, SDHCI_MAX_CURRENT));
  83
  84         if (host->flags & SDHCI_USE_ADMA)
  85                 printk(KERN_DEBUG DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x\n",
  86                        readl(host->ioaddr + SDHCI_ADMA_ERROR),
  87                        readl(host->ioaddr + SDHCI_ADMA_ADDRESS));
  88
  89         printk(KERN_DEBUG DRIVER_NAME ": ===========================================\n");
  90 }
  91
  92 /*****************************************************************************\
  93  *                                                                           *
  94  * Low level functions                                                       *
  95  *                                                                           *
  96 \*****************************************************************************/
  97
  98 static void sdhci_clear_set_irqs(struct sdhci_host *host, u32 clear, u32 set)
  99 {
 100         u32 ier;
 101
 102         ier = sdhci_readl(host, SDHCI_INT_ENABLE);
 103         ier &= ~clear;
 104         ier |= set;
 105         sdhci_writel(host, ier, SDHCI_INT_ENABLE);
 106         sdhci_writel(host, ier, SDHCI_SIGNAL_ENABLE);
 107 }
 108
 109 static void sdhci_unmask_irqs(struct sdhci_host *host, u32 irqs)
 110 {
 111         sdhci_clear_set_irqs(host, 0, irqs);
 112 }
 113
 114 static void sdhci_mask_irqs(struct sdhci_host *host, u32 irqs)
 115 {
 116         sdhci_clear_set_irqs(host, irqs, 0);
 117 }
 118
 119 static void sdhci_set_card_detection(struct sdhci_host *host, bool enable)
 120 {
 121         u32 irqs = SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT;
 122
 123         if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
 124                 return;
 125
 126         if (enable)
 127                 sdhci_unmask_irqs(host, irqs);
 128         else
 129                 sdhci_mask_irqs(host, irqs);
 130 }
 131
 132 static void sdhci_enable_card_detection(struct sdhci_host *host)
 133 {
 134         sdhci_set_card_detection(host, true);
 135 }
 136
 137 static void sdhci_disable_card_detection(struct sdhci_host *host)
 138 {
 139         sdhci_set_card_detection(host, false);
 140 }
 141
 142 static void sdhci_reset(struct sdhci_host *host, u8 mask)
 143 {
 144         unsigned long timeout;
 145         u32 uninitialized_var(ier);
 146
 147         if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
 148                 if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) &
 149                         SDHCI_CARD_PRESENT))
 150                         return;
 151         }
 152
 153         if (host->quirks & SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET)
 154                 ier = sdhci_readl(host, SDHCI_INT_ENABLE);
 155
 156         sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
 157
 158         if (mask & SDHCI_RESET_ALL)
 159                 host->clock = 0;
 160
 161         /* Wait max 100 ms */
 162         timeout = 100;
 163
 164         /* hw clears the bit when it's done */
 165         while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) {
 166                 if (timeout == 0) {
 167                         printk(KERN_ERR "%s: Reset 0x%x never completed.\n",
 168                                 mmc_hostname(host->mmc), (int)mask);
 169                         sdhci_dumpregs(host);
 170                         return;
 171                 }
 172                 timeout--;
 173                 mdelay(1);
 174         }
 175
 176         if (host->quirks & SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET)
 177                 sdhci_clear_set_irqs(host, SDHCI_INT_ALL_MASK, ier);
 178 }
 179
 180 static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios);
 181
 182 static void sdhci_init(struct sdhci_host *host, int soft)
 183 {
 184         if (soft)
 185                 sdhci_reset(host, SDHCI_RESET_CMD|SDHCI_RESET_DATA);
 186         else
 187                 sdhci_reset(host, SDHCI_RESET_ALL);
 188
 189         sdhci_clear_set_irqs(host, SDHCI_INT_ALL_MASK,
 190                 SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
 191                 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX |
 192                 SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT |
 193                 SDHCI_INT_DATA_END | SDHCI_INT_RESPONSE);
 194
 195         if (soft) {
 196                 /* force clock reconfiguration */
 197                 host->clock = 0;
 198                 sdhci_set_ios(host->mmc, &host->mmc->ios);
 199         }
 200 }
 201
 202 static void sdhci_reinit(struct sdhci_host *host)
 203 {
 204         sdhci_init(host, 0);
 205         sdhci_enable_card_detection(host);
 206 }
 207
 208 static void sdhci_activate_led(struct sdhci_host *host)
 209 {
 210         u8 ctrl;
 211
 212         ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
 213         ctrl |= SDHCI_CTRL_LED;
 214         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
 215 }
 216
 217 static void sdhci_deactivate_led(struct sdhci_host *host)
 218 {
 219         u8 ctrl;
 220
 221         ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
 222         ctrl &= ~SDHCI_CTRL_LED;
 223         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
 224 }
 225
 226 #ifdef SDHCI_USE_LEDS_CLASS
 227 static void sdhci_led_control(struct led_classdev *led,
 228         enum led_brightness brightness)
 229 {
 230         struct sdhci_host *host = container_of(led, struct sdhci_host, led);
 231         unsigned long flags;
 232
 233         spin_lock_irqsave(&host->lock, flags);
 234
 235         if (brightness == LED_OFF)
 236                 sdhci_deactivate_led(host);
 237         else
 238                 sdhci_activate_led(host);
 239
 240         spin_unlock_irqrestore(&host->lock, flags);
 241 }
 242 #endif
 243
 244 /*****************************************************************************\
 245  *                                                                           *
 246  * Core functions                                                            *
 247  *                                                                           *
 248 \*****************************************************************************/
 249
 250 static void sdhci_read_block_pio(struct sdhci_host *host)
 251 {
 252         unsigned long flags;
 253         size_t blksize, len, chunk;
 254         u32 uninitialized_var(scratch);
 255         u8 *buf;
 256
 257         DBG("PIO reading\n");
 258
 259         blksize = host->data->blksz;
 260         chunk = 0;
 261
 262         local_irq_save(flags);
 263
 264         while (blksize) {
 265                 if (!sg_miter_next(&host->sg_miter))
 266                         BUG();
 267
 268                 len = min(host->sg_miter.length, blksize);
 269
 270                 blksize -= len;
 271                 host->sg_miter.consumed = len;
 272
 273                 buf = host->sg_miter.addr;
 274
 275                 while (len) {
 276                         if (chunk == 0) {
 277                                 scratch = sdhci_readl(host, SDHCI_BUFFER);
 278                                 chunk = 4;
 279                         }
 280
 281                         *buf = scratch & 0xFF;
 282
 283                         buf++;
 284                         scratch >>= 8;
 285                         chunk--;
 286                         len--;
 287                 }
 288         }
 289
 290         sg_miter_stop(&host->sg_miter);
 291
 292         local_irq_restore(flags);
 293 }
 294
 295 static void sdhci_write_block_pio(struct sdhci_host *host)
 296 {
 297         unsigned long flags;
 298         size_t blksize, len, chunk;
 299         u32 scratch;
 300         u8 *buf;
 301
 302         DBG("PIO writing\n");
 303
 304         blksize = host->data->blksz;
 305         chunk = 0;
 306         scratch = 0;
 307
 308         local_irq_save(flags);
 309
 310         while (blksize) {
 311                 if (!sg_miter_next(&host->sg_miter))
 312                         BUG();
 313
 314                 len = min(host->sg_miter.length, blksize);
 315
 316                 blksize -= len;
 317                 host->sg_miter.consumed = len;
 318
 319                 buf = host->sg_miter.addr;
 320
 321                 while (len) {
 322                         scratch |= (u32)*buf << (chunk * 8);
 323
 324                         buf++;
 325                         chunk++;
 326                         len--;
 327
 328                         if ((chunk == 4) || ((len == 0) && (blksize == 0))) {
 329                                 sdhci_writel(host, scratch, SDHCI_BUFFER);
 330                                 chunk = 0;
 331                                 scratch = 0;
 332                         }
 333                 }
 334         }
 335
 336         sg_miter_stop(&host->sg_miter);
 337
 338         local_irq_restore(flags);
 339 }
 340
 341 static void sdhci_transfer_pio(struct sdhci_host *host)
 342 {
 343         u32 mask;
 344
 345         BUG_ON(!host->data);
 346
 347         if (host->blocks == 0)
 348                 return;
 349
 350         if (host->data->flags & MMC_DATA_READ)
 351                 mask = SDHCI_DATA_AVAILABLE;
 352         else
 353                 mask = SDHCI_SPACE_AVAILABLE;
 354
 355         /*
 356          * Some controllers (JMicron JMB38x) mess up the buffer bits
 357          * for transfers < 4 bytes. As long as it is just one block,
 358          * we can ignore the bits.
 359          */
 360         if ((host->quirks & SDHCI_QUIRK_BROKEN_SMALL_PIO) &&
 361                 (host->data->blocks == 1))
 362                 mask = ~0;
 363
 364         while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
 365                 if (host->quirks & SDHCI_QUIRK_PIO_NEEDS_DELAY)
 366                         udelay(100);
 367
 368                 if (host->data->flags & MMC_DATA_READ)
 369                         sdhci_read_block_pio(host);
 370                 else
 371                         sdhci_write_block_pio(host);
 372
 373                 host->blocks--;
 374                 if (host->blocks == 0)
 375                         break;
 376         }
 377
 378         DBG("PIO transfer complete.\n");
 379 }
 380
 381 static char *sdhci_kmap_atomic(struct scatterlist *sg, unsigned long *flags)
 382 {
 383         local_irq_save(*flags);
 384         return kmap_atomic(sg_page(sg), KM_BIO_SRC_IRQ) + sg->offset;
 385 }
 386
 387 static void sdhci_kunmap_atomic(void *buffer, unsigned long *flags)
 388 {
 389         kunmap_atomic(buffer, KM_BIO_SRC_IRQ);
 390         local_irq_restore(*flags);
 391 }
 392
 393 static void sdhci_set_adma_desc(u8 *desc, u32 addr, int len, unsigned cmd)
 394 {
 395         __le32 *dataddr = (__le32 __force *)(desc + 4);
 396         __le16 *cmdlen = (__le16 __force *)desc;
 397
 398         /* SDHCI specification says ADMA descriptors should be 4 byte
 399          * aligned, so using 16 or 32bit operations should be safe. */
 400
 401         cmdlen[0] = cpu_to_le16(cmd);
 402         cmdlen[1] = cpu_to_le16(len);
 403
 404         dataddr[0] = cpu_to_le32(addr);
 405 }
 406
 407 static int sdhci_adma_table_pre(struct sdhci_host *host,
 408         struct mmc_data *data)
 409 {
 410         int direction;
 411
 412         u8 *desc;
 413         u8 *align;
 414         dma_addr_t addr;
 415         dma_addr_t align_addr;
 416         int len, offset;
 417
 418         struct scatterlist *sg;
 419         int i;
 420         char *buffer;
 421         unsigned long flags;
 422
 423         /*
 424          * The spec does not specify endianness of descriptor table.
 425          * We currently guess that it is LE.
 426          */
 427
 428         if (data->flags & MMC_DATA_READ)
 429                 direction = DMA_FROM_DEVICE;
 430         else
 431                 direction = DMA_TO_DEVICE;
 432
 433         /*
 434          * The ADMA descriptor table is mapped further down as we
 435          * need to fill it with data first.
 436          */
 437
 438         host->align_addr = dma_map_single(mmc_dev(host->mmc),
 439                 host->align_buffer, 128 * 4, direction);
 440         if (dma_mapping_error(mmc_dev(host->mmc), host->align_addr))
 441                 goto fail;
 442         BUG_ON(host->align_addr & 0x3);
 443
 444         host->sg_count = dma_map_sg(mmc_dev(host->mmc),
 445                 data->sg, data->sg_len, direction);
 446         if (host->sg_count == 0)
 447                 goto unmap_align;
 448
 449         desc = host->adma_desc;
 450         align = host->align_buffer;
 451
 452         align_addr = host->align_addr;
 453
 454         for_each_sg(data->sg, sg, host->sg_count, i) {
 455                 addr = sg_dma_address(sg);
 456                 len = sg_dma_len(sg);
 457
 458                 /*
 459                  * The SDHCI specification states that ADMA
 460                  * addresses must be 32-bit aligned. If they
 461                  * aren't, then we use a bounce buffer for
 462                  * the (up to three) bytes that screw up the
 463                  * alignment.
 464                  */
 465                 offset = (4 - (addr & 0x3)) & 0x3;
 466                 if (offset) {
 467                         if (data->flags & MMC_DATA_WRITE) {
 468                                 buffer = sdhci_kmap_atomic(sg, &flags);
 469                                 WARN_ON(((long)buffer & PAGE_MASK) > (PAGE_SIZE - 3));
 470                                 memcpy(align, buffer, offset);
 471                                 sdhci_kunmap_atomic(buffer, &flags);
 472                         }
 473
 474                         /* tran, valid */
 475                         sdhci_set_adma_desc(desc, align_addr, offset, 0x21);
 476
 477                         BUG_ON(offset > 65536);
 478
 479                         align += 4;
 480                         align_addr += 4;
 481
 482                         desc += 8;
 483
 484                         addr += offset;
 485                         len -= offset;
 486                 }
 487
 488                 BUG_ON(len > 65536);
 489
 490                 /* tran, valid */
 491                 sdhci_set_adma_desc(desc, addr, len, 0x21);
 492                 desc += 8;
 493
 494                 /*
 495                  * If this triggers then we have a calculation bug
 496                  * somewhere. :/
 497                  */
 498                 WARN_ON((desc - host->adma_desc) > (128 * 2 + 1) * 4);
 499         }
 500
 501         if (host->quirks & SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC) {
 502                 /*
 503                 * Mark the last descriptor as the terminating descriptor
 504                 */
 505                 if (desc != host->adma_desc) {
 506                         desc -= 8;
 507                         desc[0] |= 0x2; /* end */
 508                 }
 509         } else {
 510                 /*
 511                 * Add a terminating entry.
 512                 */
 513
 514                 /* nop, end, valid */
 515                 sdhci_set_adma_desc(desc, 0, 0, 0x3);
 516         }
 517
 518         /*
 519          * Resync align buffer as we might have changed it.
 520          */
 521         if (data->flags & MMC_DATA_WRITE) {
 522                 dma_sync_single_for_device(mmc_dev(host->mmc),
 523                         host->align_addr, 128 * 4, direction);
 524         }
 525
 526         host->adma_addr = dma_map_single(mmc_dev(host->mmc),
 527                 host->adma_desc, (128 * 2 + 1) * 4, DMA_TO_DEVICE);
 528         if (dma_mapping_error(mmc_dev(host->mmc), host->adma_addr))
 529                 goto unmap_entries;
 530         BUG_ON(host->adma_addr & 0x3);
 531
 532         return 0;
 533
 534 unmap_entries:
 535         dma_unmap_sg(mmc_dev(host->mmc), data->sg,
 536                 data->sg_len, direction);
 537 unmap_align:
 538         dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
 539                 128 * 4, direction);
 540 fail:
 541         return -EINVAL;
 542 }
 543
 544 static void sdhci_adma_table_post(struct sdhci_host *host,
 545         struct mmc_data *data)
 546 {
 547         int direction;
 548
 549         struct scatterlist *sg;
 550         int i, size;
 551         u8 *align;
 552         char *buffer;
 553         unsigned long flags;
 554
 555         if (data->flags & MMC_DATA_READ)
 556                 direction = DMA_FROM_DEVICE;
 557         else
 558                 direction = DMA_TO_DEVICE;
 559
 560         dma_unmap_single(mmc_dev(host->mmc), host->adma_addr,
 561                 (128 * 2 + 1) * 4, DMA_TO_DEVICE);
 562
 563         dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
 564                 128 * 4, direction);
 565
 566         if (data->flags & MMC_DATA_READ) {
 567                 dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg,
 568                         data->sg_len, direction);
 569
 570                 align = host->align_buffer;
 571
 572                 for_each_sg(data->sg, sg, host->sg_count, i) {
 573                         if (sg_dma_address(sg) & 0x3) {
 574                                 size = 4 - (sg_dma_address(sg) & 0x3);
 575
 576                                 buffer = sdhci_kmap_atomic(sg, &flags);
 577                                 WARN_ON(((long)buffer & PAGE_MASK) > (PAGE_SIZE - 3));
 578                                 memcpy(buffer, align, size);
 579                                 sdhci_kunmap_atomic(buffer, &flags);
 580
 581                                 align += 4;
 582                         }
 583                 }
 584         }
 585
 586         dma_unmap_sg(mmc_dev(host->mmc), data->sg,
 587                 data->sg_len, direction);
 588 }
 589
 590 static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_data *data)
 591 {
 592         u8 count;
 593         unsigned target_timeout, current_timeout;
 594
 595         /*
 596          * If the host controller provides us with an incorrect timeout
 597          * value, just skip the check and use 0xE.  The hardware may take
 598          * longer to time out, but that's much better than having a too-short
 599          * timeout value.
 600          */
 601         if (host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL)
 602                 return 0xE;
 603
 604         /* timeout in us */
 605         target_timeout = data->timeout_ns / 1000 +
 606                 data->timeout_clks / host->clock;
 607
 608         if (host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)
 609                 host->timeout_clk = host->clock / 1000;
 610
 611         /*
 612          * Figure out needed cycles.
 613          * We do this in steps in order to fit inside a 32 bit int.
 614          * The first step is the minimum timeout, which will have a
 615          * minimum resolution of 6 bits:
 616          * (1) 2^13*1000 > 2^22,
 617          * (2) host->timeout_clk < 2^16
 618          *     =>
 619          *     (1) / (2) > 2^6
 620          */
 621         count = 0;
 622         current_timeout = (1 << 13) * 1000 / host->timeout_clk;
 623         while (current_timeout < target_timeout) {
 624                 count++;
 625                 current_timeout <<= 1;
 626                 if (count >= 0xF)
 627                         break;
 628         }
 629
 630         if (count >= 0xF) {
 631                 printk(KERN_WARNING "%s: Too large timeout requested!\n",
 632                         mmc_hostname(host->mmc));
 633                 count = 0xE;
 634         }
 635
 636         return count;
 637 }
 638
 639 static void sdhci_set_transfer_irqs(struct sdhci_host *host)
 640 {
 641         u32 pio_irqs = SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL;
 642         u32 dma_irqs = SDHCI_INT_DMA_END | SDHCI_INT_ADMA_ERROR;
 643
 644         if (host->flags & SDHCI_REQ_USE_DMA)
 645                 sdhci_clear_set_irqs(host, pio_irqs, dma_irqs);
 646         else
 647                 sdhci_clear_set_irqs(host, dma_irqs, pio_irqs);
 648 }
 649
 650 static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_data *data)
 651 {
 652         u8 count;
 653         u8 ctrl;
 654         int ret;
 655
 656         WARN_ON(host->data);
 657
 658         if (data == NULL)
 659                 return;
 660
 661         /* Sanity checks */
 662         BUG_ON(data->blksz * data->blocks > 524288);
 663         BUG_ON(data->blksz > host->mmc->max_blk_size);
 664         BUG_ON(data->blocks > 65535);
 665
 666         host->data = data;
 667         host->data_early = 0;
 668
 669         count = sdhci_calc_timeout(host, data);
 670         sdhci_writeb(host, count, SDHCI_TIMEOUT_CONTROL);
 671
 672         if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))
 673                 host->flags |= SDHCI_REQ_USE_DMA;
 674
 675         /*
 676          * FIXME: This doesn't account for merging when mapping the
 677          * scatterlist.
 678          */
 679         if (host->flags & SDHCI_REQ_USE_DMA) {
 680                 int broken, i;
 681                 struct scatterlist *sg;
 682
 683                 broken = 0;
 684                 if (host->flags & SDHCI_USE_ADMA) {
 685                         if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
 686                                 broken = 1;
 687                 } else {
 688                         if (host->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE)
 689                                 broken = 1;
 690                 }
 691
 692                 if (unlikely(broken)) {
 693                         for_each_sg(data->sg, sg, data->sg_len, i) {
 694                                 if (sg->length & 0x3) {
 695                                         DBG("Reverting to PIO because of "
 696                                                 "transfer size (%d)\n",
 697                                                 sg->length);
 698                                         host->flags &= ~SDHCI_REQ_USE_DMA;
 699                                         break;
 700                                 }
 701                         }
 702                 }
 703         }
 704
 705         /*
 706          * The assumption here being that alignment is the same after
 707          * translation to device address space.
 708          */
 709         if (host->flags & SDHCI_REQ_USE_DMA) {
 710                 int broken, i;
 711                 struct scatterlist *sg;
 712
 713                 broken = 0;
 714                 if (host->flags & SDHCI_USE_ADMA) {
 715                         /*
 716                          * As we use 3 byte chunks to work around
 717                          * alignment problems, we need to check this
 718                          * quirk.
 719                          */
 720                         if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
 721                                 broken = 1;
 722                 } else {
 723                         if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR)
 724                                 broken = 1;
 725                 }
 726
 727                 if (unlikely(broken)) {
 728                         for_each_sg(data->sg, sg, data->sg_len, i) {
 729                                 if (sg->offset & 0x3) {
 730                                         DBG("Reverting to PIO because of "
 731                                                 "bad alignment\n");
 732                                         host->flags &= ~SDHCI_REQ_USE_DMA;
 733                                         break;
 734                                 }
 735                         }
 736                 }
 737         }
 738
 739         if (host->flags & SDHCI_REQ_USE_DMA) {
 740                 if (host->flags & SDHCI_USE_ADMA) {
 741                         ret = sdhci_adma_table_pre(host, data);
 742                         if (ret) {
 743                                 /*
 744                                  * This only happens when someone fed
 745                                  * us an invalid request.
 746                                  */
 747                                 WARN_ON(1);
 748                                 host->flags &= ~SDHCI_REQ_USE_DMA;
 749                         } else {
 750                                 sdhci_writel(host, host->adma_addr,
 751                                         SDHCI_ADMA_ADDRESS);
 752                         }
 753                 } else {
 754                         int sg_cnt;
 755
 756                         sg_cnt = dma_map_sg(mmc_dev(host->mmc),
 757                                         data->sg, data->sg_len,
 758                                         (data->flags & MMC_DATA_READ) ?
 759                                                 DMA_FROM_DEVICE :
 760                                                 DMA_TO_DEVICE);
 761                         if (sg_cnt == 0) {
 762                                 /*
 763                                  * This only happens when someone fed
 764                                  * us an invalid request.
 765                                  */
 766                                 WARN_ON(1);
 767                                 host->flags &= ~SDHCI_REQ_USE_DMA;
 768                         } else {
 769                                 WARN_ON(sg_cnt != 1);
 770                                 sdhci_writel(host, sg_dma_address(data->sg),
 771                                         SDHCI_DMA_ADDRESS);
 772                         }
 773                 }
 774         }
 775
 776         /*
 777          * Always adjust the DMA selection as some controllers
 778          * (e.g. JMicron) can't do PIO properly when the selection
 779          * is ADMA.
 780          */
 781         if (host->version >= SDHCI_SPEC_200) {
 782                 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
 783                 ctrl &= ~SDHCI_CTRL_DMA_MASK;
 784                 if ((host->flags & SDHCI_REQ_USE_DMA) &&
 785                         (host->flags & SDHCI_USE_ADMA))
 786                         ctrl |= SDHCI_CTRL_ADMA32;
 787                 else
 788                         ctrl |= SDHCI_CTRL_SDMA;
 789                 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
 790         }
 791
 792         if (!(host->flags & SDHCI_REQ_USE_DMA)) {
 793                 int flags;
 794
 795                 flags = SG_MITER_ATOMIC;
 796                 if (host->data->flags & MMC_DATA_READ)
 797                         flags |= SG_MITER_TO_SG;
 798                 else
 799                         flags |= SG_MITER_FROM_SG;
 800                 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
 801                 host->blocks = data->blocks;
 802         }
 803
 804         sdhci_set_transfer_irqs(host);
 805
 806         /* We do not handle DMA boundaries, so set it to max (512 KiB) */
 807         sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, data->blksz), SDHCI_BLOCK_SIZE);
 808         sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
 809 }
 810
 811 static void sdhci_set_transfer_mode(struct sdhci_host *host,
 812         struct mmc_data *data)
 813 {
 814         u16 mode;
 815
 816         if (data == NULL)
 817                 return;
 818
 819         WARN_ON(!host->data);
 820
 821         mode = SDHCI_TRNS_BLK_CNT_EN;
 822         if (data->blocks > 1) {
 823                 if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12)
 824                         mode |= SDHCI_TRNS_MULTI | SDHCI_TRNS_ACMD12;
 825                 else
 826                         mode |= SDHCI_TRNS_MULTI;
 827         }
 828         if (data->flags & MMC_DATA_READ)
 829                 mode |= SDHCI_TRNS_READ;
 830         if (host->flags & SDHCI_REQ_USE_DMA)
 831                 mode |= SDHCI_TRNS_DMA;
 832
 833         sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
 834 }
 835
 836 static void sdhci_finish_data(struct sdhci_host *host)
 837 {
 838         struct mmc_data *data;
 839
 840         BUG_ON(!host->data);
 841
 842         data = host->data;
 843         host->data = NULL;
 844
 845         if (host->flags & SDHCI_REQ_USE_DMA) {
 846                 if (host->flags & SDHCI_USE_ADMA)
 847                         sdhci_adma_table_post(host, data);
 848                 else {
 849                         dma_unmap_sg(mmc_dev(host->mmc), data->sg,
 850                                 data->sg_len, (data->flags & MMC_DATA_READ) ?
 851                                         DMA_FROM_DEVICE : DMA_TO_DEVICE);
 852                 }
 853         }
 854
 855         /*
 856          * The specification states that the block count register must
 857          * be updated, but it does not specify at what point in the
 858          * data flow. That makes the register entirely useless to read
 859          * back so we have to assume that nothing made it to the card
 860          * in the event of an error.
 861          */
 862         if (data->error)
 863                 data->bytes_xfered = 0;
 864         else
 865                 data->bytes_xfered = data->blksz * data->blocks;
 866
 867         if (data->stop) {
 868                 /*
 869                  * The controller needs a reset of internal state machines
 870                  * upon error conditions.
 871                  */
 872                 if (data->error) {
 873                         sdhci_reset(host, SDHCI_RESET_CMD);
 874                         sdhci_reset(host, SDHCI_RESET_DATA);
 875                 }
 876
 877                 sdhci_send_command(host, data->stop);
 878         } else
 879                 tasklet_schedule(&host->finish_tasklet);
 880 }
 881
 882 static void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
 883 {
 884         int flags;
 885         u32 mask;
 886         unsigned long timeout;
 887
 888         WARN_ON(host->cmd);
 889
 890         /* Wait max 10 ms */
 891         timeout = 10;
 892
 893         mask = SDHCI_CMD_INHIBIT;
 894         if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY))
 895                 mask |= SDHCI_DATA_INHIBIT;
 896
 897         /* We shouldn't wait for data inihibit for stop commands, even
 898            though they might use busy signaling */
 899         if (host->mrq->data && (cmd == host->mrq->data->stop))
 900                 mask &= ~SDHCI_DATA_INHIBIT;
 901
 902         while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
 903                 if (timeout == 0) {
 904                         printk(KERN_ERR "%s: Controller never released "
 905                                 "inhibit bit(s).\n", mmc_hostname(host->mmc));
 906                         sdhci_dumpregs(host);
 907                         cmd->error = -EIO;
 908                         tasklet_schedule(&host->finish_tasklet);
 909                         return;
 910                 }
 911                 timeout--;
 912                 mdelay(1);
 913         }
 914
 915         mod_timer(&host->timer, jiffies + 10 * HZ);
 916
 917         host->cmd = cmd;
 918
 919         sdhci_prepare_data(host, cmd->data);
 920
 921         sdhci_writel(host, cmd->arg, SDHCI_ARGUMENT);
 922
 923         sdhci_set_transfer_mode(host, cmd->data);
 924
 925         if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
 926                 printk(KERN_ERR "%s: Unsupported response type!\n",
 927                         mmc_hostname(host->mmc));
 928                 cmd->error = -EINVAL;
 929                 tasklet_schedule(&host->finish_tasklet);
 930                 return;
 931         }
 932
 933         if (!(cmd->flags & MMC_RSP_PRESENT))
 934                 flags = SDHCI_CMD_RESP_NONE;
 935         else if (cmd->flags & MMC_RSP_136)
 936                 flags = SDHCI_CMD_RESP_LONG;
 937         else if (cmd->flags & MMC_RSP_BUSY)
 938                 flags = SDHCI_CMD_RESP_SHORT_BUSY;
 939         else
 940                 flags = SDHCI_CMD_RESP_SHORT;
 941
 942         if (cmd->flags & MMC_RSP_CRC)
 943                 flags |= SDHCI_CMD_CRC;
 944         if (cmd->flags & MMC_RSP_OPCODE)
 945                 flags |= SDHCI_CMD_INDEX;
 946         if (cmd->data)
 947                 flags |= SDHCI_CMD_DATA;
 948
 949         sdhci_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND);
 950 }
 951
 952 static void sdhci_finish_command(struct sdhci_host *host)
 953 {
 954         int i;
 955
 956         BUG_ON(host->cmd == NULL);
 957
 958         if (host->cmd->flags & MMC_RSP_PRESENT) {
 959                 if (host->cmd->flags & MMC_RSP_136) {
 960                         /* CRC is stripped so we need to do some shifting. */
 961                         for (i = 0;i < 4;i++) {
 962                                 host->cmd->resp[i] = sdhci_readl(host,
 963                                         SDHCI_RESPONSE + (3-i)*4) << 8;
 964                                 if (i != 3)
 965                                         host->cmd->resp[i] |=
 966                                                 sdhci_readb(host,
 967                                                 SDHCI_RESPONSE + (3-i)*4-1);
 968                         }
 969                 } else {
 970                         host->cmd->resp[0] = sdhci_readl(host, SDHCI_RESPONSE);
 971                 }
 972         }
 973
 974         host->cmd->error = 0;
 975
 976         if (host->data && host->data_early)
 977                 sdhci_finish_data(host);
 978
 979         if (!host->cmd->data)
 980                 tasklet_schedule(&host->finish_tasklet);
 981
 982         host->cmd = NULL;
 983 }
 984
 985 static void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
 986 {
 987         int div;
 988         u16 clk;
 989         unsigned long timeout;
 990
 991         if (clock && clock == host->clock)
 992                 return;
 993
 994         if (host->ops->set_clock) {
 995                 host->ops->set_clock(host, clock);
 996                 if (host->quirks & SDHCI_QUIRK_NONSTANDARD_CLOCK)
 997                         return;
 998         }
 999
1000         sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
1001
1002         if (clock == 0)
1003                 goto out;
1004
1005         for (div = 1;div < 256;div *= 2) {
1006                 if ((host->max_clk / div) <= clock)
1007                         break;
1008         }
1009         div >>= 1;
1010
1011         clk = div << SDHCI_DIVIDER_SHIFT;
1012         clk |= SDHCI_CLOCK_INT_EN;
1013         sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1014
1015         /* Wait max 20 ms */
1016         timeout = 20;
1017         while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
1018                 & SDHCI_CLOCK_INT_STABLE)) {
1019                 if (timeout == 0) {
1020                         printk(KERN_ERR "%s: Internal clock never "
1021                                 "stabilised.\n", mmc_hostname(host->mmc));
1022                         sdhci_dumpregs(host);
1023                         return;
1024                 }
1025                 timeout--;
1026                 mdelay(1);
1027         }
1028
1029         clk |= SDHCI_CLOCK_CARD_EN;
1030         sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1031
1032 out:
1033
1034         host->clock = clock;
1035 }
1036
1037 static void sdhci_set_power(struct sdhci_host *host, unsigned short power)
1038 {
1039         u8 pwr;
1040
1041         if (power == (unsigned short)-1)
1042                 pwr = 0;
1043         else {
1044                 switch (1 << power) {
1045                 case MMC_VDD_165_195:
1046                         pwr = SDHCI_POWER_180;
1047                         break;
1048                 case MMC_VDD_29_30:
1049                 case MMC_VDD_30_31:
1050                         pwr = SDHCI_POWER_300;
1051                         break;
1052                 case MMC_VDD_32_33:
1053                 case MMC_VDD_33_34:
1054                         pwr = SDHCI_POWER_330;
1055                         break;
1056                 default:
1057                         BUG();
1058                 }
1059         }
1060
1061         if (host->pwr == pwr)
1062                 return;
1063
1064         host->pwr = pwr;
1065
1066         if (pwr == 0) {
1067                 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1068                 return;
1069         }
1070
1071         /*
1072          * Spec says that we should clear the power reg before setting
1073          * a new value. Some controllers don't seem to like this though.
1074          */
1075         if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE))
1076                 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1077
1078         /*
1079          * At least the Marvell CaFe chip gets confused if we set the voltage
1080          * and set turn on power at the same time, so set the voltage first.
1081          */
1082         if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER)
1083                 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1084
1085         pwr |= SDHCI_POWER_ON;
1086
1087         sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1088
1089         /*
1090          * Some controllers need an extra 10ms delay of 10ms before they
1091          * can apply clock after applying power
1092          */
1093         if (host->quirks & SDHCI_QUIRK_DELAY_AFTER_POWER)
1094                 mdelay(10);
1095 }
1096
1097 /*****************************************************************************\
1098  *                                                                           *
1099  * MMC callbacks                                                             *
1100  *                                                                           *
1101 \*****************************************************************************/
1102
1103 static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1104 {
1105         struct sdhci_host *host;
1106         bool present;
1107         unsigned long flags;
1108
1109         host = mmc_priv(mmc);
1110
1111         spin_lock_irqsave(&host->lock, flags);
1112
1113         WARN_ON(host->mrq != NULL);
1114
1115 #ifndef SDHCI_USE_LEDS_CLASS
1116         sdhci_activate_led(host);
1117 #endif
1118         if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12) {
1119                 if (mrq->stop) {
1120                         mrq->data->stop = NULL;
1121                         mrq->stop = NULL;
1122                 }
1123         }
1124
1125         host->mrq = mrq;
1126
1127         /* If polling, assume that the card is always present. */
1128         if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
1129                 present = true;
1130         else
1131                 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
1132                                 SDHCI_CARD_PRESENT;
1133
1134         if (!present || host->flags & SDHCI_DEVICE_DEAD) {
1135                 host->mrq->cmd->error = -ENOMEDIUM;
1136                 tasklet_schedule(&host->finish_tasklet);
1137         } else
1138                 sdhci_send_command(host, mrq->cmd);
1139
1140         mmiowb();
1141         spin_unlock_irqrestore(&host->lock, flags);
1142 }
1143
1144 static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1145 {
1146         struct sdhci_host *host;
1147         unsigned long flags;
1148         u8 ctrl;
1149
1150         host = mmc_priv(mmc);
1151
1152         spin_lock_irqsave(&host->lock, flags);
1153
1154         if (host->flags & SDHCI_DEVICE_DEAD)
1155                 goto out;
1156
1157         /*
1158          * Reset the chip on each power off.
1159          * Should clear out any weird states.
1160          */
1161         if (ios->power_mode == MMC_POWER_OFF) {
1162                 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
1163                 sdhci_reinit(host);
1164         }
1165
1166         sdhci_set_clock(host, ios->clock);
1167
1168         if (ios->power_mode == MMC_POWER_OFF)
1169                 sdhci_set_power(host, -1);
1170         else
1171                 sdhci_set_power(host, ios->vdd);
1172
1173         ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1174
1175         if (ios->bus_width == MMC_BUS_WIDTH_8)
1176                 ctrl |= SDHCI_CTRL_8BITBUS;
1177         else
1178                 ctrl &= ~SDHCI_CTRL_8BITBUS;
1179
1180         if (ios->bus_width == MMC_BUS_WIDTH_4)
1181                 ctrl |= SDHCI_CTRL_4BITBUS;
1182
1183         if (ios->timing == MMC_TIMING_SD_HS &&
1184             !(host->quirks & SDHCI_QUIRK_NO_HISPD_BIT))
1185                 ctrl |= SDHCI_CTRL_HISPD;
1186         else
1187                 ctrl &= ~SDHCI_CTRL_HISPD;
1188
1189         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1190
1191         /*
1192          * Some (ENE) controllers go apeshit on some ios operation,
1193          * signalling timeout and CRC errors even on CMD0. Resetting
1194          * it on each ios seems to solve the problem.
1195          */
1196         if(host->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS)
1197                 sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
1198
1199 out:
1200         mmiowb();
1201         spin_unlock_irqrestore(&host->lock, flags);
1202 }
1203
1204 static int sdhci_get_ro(struct mmc_host *mmc)
1205 {
1206         struct sdhci_host *host;
1207         unsigned long flags;
1208         int present;
1209
1210         host = mmc_priv(mmc);
1211
1212         spin_lock_irqsave(&host->lock, flags);
1213
1214         if (host->flags & SDHCI_DEVICE_DEAD) {
1215                 present = 0;
1216         } else if (!(host->quirks & SDHCI_QUIRK_BROKEN_WRITE_PROTECT)) {
1217                 present = sdhci_readl(host, SDHCI_PRESENT_STATE);
1218                 present = !(present & SDHCI_WRITE_PROTECT);
1219         } else if (host->ops->get_ro) {
1220                 present = host->ops->get_ro(host);
1221         } else {
1222                 present = 0;
1223         }
1224
1225         spin_unlock_irqrestore(&host->lock, flags);
1226
1227         if (host->quirks & SDHCI_QUIRK_INVERTED_WRITE_PROTECT)
1228                 return !!(present & SDHCI_WRITE_PROTECT);
1229         return present;
1230 }
1231
1232 static void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable)
1233 {
1234         struct sdhci_host *host;
1235         unsigned long flags;
1236
1237         host = mmc_priv(mmc);
1238
1239         spin_lock_irqsave(&host->lock, flags);
1240
1241         if (host->flags & SDHCI_DEVICE_DEAD)
1242                 goto out;
1243
1244         if (enable)
1245                 sdhci_unmask_irqs(host, SDHCI_INT_CARD_INT);
1246         else
1247                 sdhci_mask_irqs(host, SDHCI_INT_CARD_INT);
1248
1249         if (host->quirks & SDHCI_QUIRK_ENABLE_INTERRUPT_AT_BLOCK_GAP) {
1250                 u8 gap_ctrl = readb(host->ioaddr + SDHCI_BLOCK_GAP_CONTROL);
1251                 if (enable)
1252                         gap_ctrl |= 0x8;
1253                 else
1254                         gap_ctrl &= ~0x8;
1255                 writeb(gap_ctrl, host->ioaddr + SDHCI_BLOCK_GAP_CONTROL);
1256         }
1257
1258 out:
1259         mmiowb();
1260
1261         spin_unlock_irqrestore(&host->lock, flags);
1262 }
1263
1264 static const struct mmc_host_ops sdhci_ops = {
1265         .request        = sdhci_request,
1266         .set_ios        = sdhci_set_ios,
1267         .get_ro         = sdhci_get_ro,
1268         .enable_sdio_irq = sdhci_enable_sdio_irq,
1269 };
1270
1271 void sdhci_card_detect_callback(struct sdhci_host *host)
1272 {
1273         unsigned long flags;
1274
1275         spin_lock_irqsave(&host->lock, flags);
1276
1277         if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT)) {
1278                 if (host->mrq) {
1279                         printk(KERN_ERR "%s: Card removed during transfer!\n",
1280                                 mmc_hostname(host->mmc));
1281                         printk(KERN_ERR "%s: Resetting controller.\n",
1282                                 mmc_hostname(host->mmc));
1283
1284                         sdhci_reset(host, SDHCI_RESET_CMD);
1285                         sdhci_reset(host, SDHCI_RESET_DATA);
1286
1287                         host->mrq->cmd->error = -ENOMEDIUM;
1288                         tasklet_schedule(&host->finish_tasklet);
1289                 }
1290         }
1291
1292         spin_unlock_irqrestore(&host->lock, flags);
1293
1294         mmc_detect_change(host->mmc, msecs_to_jiffies(200));
1295 }
1296 EXPORT_SYMBOL_GPL(sdhci_card_detect_callback);
1297
1298 /*****************************************************************************\
1299  *                                                                           *
1300  * Tasklets                                                                  *
1301  *                                                                           *
1302 \*****************************************************************************/
1303
1304 static void sdhci_tasklet_card(unsigned long param)
1305 {
1306         struct sdhci_host *host;
1307
1308         host = (struct sdhci_host *)param;
1309
1310         sdhci_card_detect_callback(host);
1311 }
1312
1313 static void sdhci_tasklet_finish(unsigned long param)
1314 {
1315         struct sdhci_host *host;
1316         unsigned long flags;
1317         struct mmc_request *mrq;
1318
1319         host = (struct sdhci_host*)param;
1320
1321         spin_lock_irqsave(&host->lock, flags);
1322
1323         del_timer(&host->timer);
1324
1325         mrq = host->mrq;
1326
1327         /*
1328          * The controller needs a reset of internal state machines
1329          * upon error conditions.
1330          */
1331         if (!(host->flags & SDHCI_DEVICE_DEAD) &&
1332                 (mrq->cmd->error ||
1333                  (mrq->data && (mrq->data->error ||
1334                   (mrq->data->stop && mrq->data->stop->error))) ||
1335                    (host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST))) {
1336
1337                 /* Some controllers need this kick or reset won't work here */
1338                 if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET) {
1339                         unsigned int clock;
1340
1341                         /* This is to force an update */
1342                         clock = host->clock;
1343                         host->clock = 0;
1344                         sdhci_set_clock(host, clock);
1345                 }
1346
1347                 /* Spec says we should do both at the same time, but Ricoh
1348                    controllers do not like that. */
1349                 sdhci_reset(host, SDHCI_RESET_CMD);
1350                 sdhci_reset(host, SDHCI_RESET_DATA);
1351         }
1352
1353         host->mrq = NULL;
1354         host->cmd = NULL;
1355         host->data = NULL;
1356
1357 #ifndef SDHCI_USE_LEDS_CLASS
1358         sdhci_deactivate_led(host);
1359 #endif
1360
1361         mmiowb();
1362         spin_unlock_irqrestore(&host->lock, flags);
1363
1364         mmc_request_done(host->mmc, mrq);
1365 }
1366
1367 static void sdhci_timeout_timer(unsigned long data)
1368 {
1369         struct sdhci_host *host;
1370         unsigned long flags;
1371
1372         host = (struct sdhci_host*)data;
1373
1374         spin_lock_irqsave(&host->lock, flags);
1375
1376         if (host->mrq) {
1377                 printk(KERN_ERR "%s: Timeout waiting for hardware "
1378                         "interrupt.\n", mmc_hostname(host->mmc));
1379                 sdhci_dumpregs(host);
1380
1381                 if (host->data) {
1382                         host->data->error = -ETIMEDOUT;
1383                         sdhci_finish_data(host);
1384                 } else {
1385                         if (host->cmd)
1386                                 host->cmd->error = -ETIMEDOUT;
1387                         else
1388                                 host->mrq->cmd->error = -ETIMEDOUT;
1389
1390                         tasklet_schedule(&host->finish_tasklet);
1391                 }
1392         }
1393
1394         mmiowb();
1395         spin_unlock_irqrestore(&host->lock, flags);
1396 }
1397
1398 /*****************************************************************************\
1399  *                                                                           *
1400  * Interrupt handling                                                        *
1401  *                                                                           *
1402 \*****************************************************************************/
1403
1404 static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask)
1405 {
1406         BUG_ON(intmask == 0);
1407
1408         if (!host->cmd) {
1409                 printk(KERN_ERR "%s: Got command interrupt 0x%08x even "
1410                         "though no command operation was in progress.\n",
1411                         mmc_hostname(host->mmc), (unsigned)intmask);
1412                 sdhci_dumpregs(host);
1413                 return;
1414         }
1415
1416         if (intmask & SDHCI_INT_TIMEOUT)
1417                 host->cmd->error = -ETIMEDOUT;
1418         else if (intmask & (SDHCI_INT_CRC | SDHCI_INT_END_BIT |
1419                         SDHCI_INT_INDEX))
1420                 host->cmd->error = -EILSEQ;
1421
1422         if (host->cmd->error) {
1423                 if (intmask & SDHCI_INT_RESPONSE)
1424                         tasklet_schedule(&host->finish_tasklet);
1425                 return;
1426         }
1427
1428         /*
1429          * The host can send and interrupt when the busy state has
1430          * ended, allowing us to wait without wasting CPU cycles.
1431          * Unfortunately this is overloaded on the "data complete"
1432          * interrupt, so we need to take some care when handling
1433          * it.
1434          *
1435          * Note: The 1.0 specification is a bit ambiguous about this
1436          *       feature so there might be some problems with older
1437          *       controllers.
1438          */
1439         if (host->cmd->flags & MMC_RSP_BUSY) {
1440                 if (host->cmd->data)
1441                         DBG("Cannot wait for busy signal when also "
1442                                 "doing a data transfer");
1443                 else if (!(host->quirks & SDHCI_QUIRK_NO_BUSY_IRQ))
1444                         return;
1445
1446                 /* The controller does not support the end-of-busy IRQ,
1447                  * fall through and take the SDHCI_INT_RESPONSE */
1448         }
1449
1450         if (intmask & SDHCI_INT_RESPONSE)
1451                 sdhci_finish_command(host);
1452 }
1453
1454 #ifdef DEBUG
1455 static void sdhci_show_adma_error(struct sdhci_host *host)
1456 {
1457         const char *name = mmc_hostname(host->mmc);
1458         u8 *desc = host->adma_desc;
1459         __le32 *dma;
1460         __le16 *len;
1461         u8 attr;
1462
1463         sdhci_dumpregs(host);
1464
1465         while (true) {
1466                 dma = (__le32 *)(desc + 4);
1467                 len = (__le16 *)(desc + 2);
1468                 attr = *desc;
1469
1470                 DBG("%s: %p: DMA 0x%08x, LEN 0x%04x, Attr=0x%02x\n",
1471                     name, desc, le32_to_cpu(*dma), le16_to_cpu(*len), attr);
1472
1473                 desc += 8;
1474
1475                 if (attr & 2)
1476                         break;
1477         }
1478 }
1479 #else
1480 static void sdhci_show_adma_error(struct sdhci_host *host) { }
1481 #endif
1482
1483 static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
1484 {
1485         BUG_ON(intmask == 0);
1486
1487         if (!host->data) {
1488                 /*
1489                  * The "data complete" interrupt is also used to
1490                  * indicate that a busy state has ended. See comment
1491                  * above in sdhci_cmd_irq().
1492                  */
1493                 if (host->cmd && (host->cmd->flags & MMC_RSP_BUSY)) {
1494                         if (intmask & SDHCI_INT_DATA_END) {
1495                                 sdhci_finish_command(host);
1496                                 return;
1497                         }
1498                 }
1499
1500                 printk(KERN_ERR "%s: Got data interrupt 0x%08x even "
1501                         "though no data operation was in progress.\n",
1502                         mmc_hostname(host->mmc), (unsigned)intmask);
1503                 sdhci_dumpregs(host);
1504
1505                 return;
1506         }
1507
1508         if (intmask & SDHCI_INT_DATA_TIMEOUT)
1509                 host->data->error = -ETIMEDOUT;
1510         else if (intmask & (SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_END_BIT))
1511                 host->data->error = -EILSEQ;
1512         else if (intmask & SDHCI_INT_ADMA_ERROR) {
1513                 printk(KERN_ERR "%s: ADMA error\n", mmc_hostname(host->mmc));
1514                 sdhci_show_adma_error(host);
1515                 host->data->error = -EIO;
1516         }
1517
1518         if (host->data->error)
1519                 sdhci_finish_data(host);
1520         else {
1521                 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
1522                         sdhci_transfer_pio(host);
1523
1524                 /*
1525                  * We currently don't do anything fancy with DMA
1526                  * boundaries, but as we can't disable the feature
1527                  * we need to at least restart the transfer.
1528                  */
1529                 if (intmask & SDHCI_INT_DMA_END)
1530                         sdhci_writel(host, sdhci_readl(host, SDHCI_DMA_ADDRESS),
1531                                 SDHCI_DMA_ADDRESS);
1532
1533                 if (intmask & SDHCI_INT_DATA_END) {
1534                         if (host->cmd) {
1535                                 /*
1536                                  * Data managed to finish before the
1537                                  * command completed. Make sure we do
1538                                  * things in the proper order.
1539                                  */
1540                                 host->data_early = 1;
1541                         } else {
1542                                 sdhci_finish_data(host);
1543                         }
1544                 }
1545         }
1546 }
1547
1548 static irqreturn_t sdhci_irq(int irq, void *dev_id)
1549 {
1550         irqreturn_t result;
1551         struct sdhci_host* host = dev_id;
1552         u32 intmask;
1553         int cardint = 0;
1554
1555         spin_lock(&host->lock);
1556
1557         intmask = sdhci_readl(host, SDHCI_INT_STATUS);
1558
1559         if (!intmask || intmask == 0xffffffff) {
1560                 result = IRQ_NONE;
1561                 goto out;
1562         }
1563
1564         DBG("*** %s got interrupt: 0x%08x\n",
1565                 mmc_hostname(host->mmc), intmask);
1566
1567         if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
1568                 sdhci_writel(host, intmask & (SDHCI_INT_CARD_INSERT |
1569                         SDHCI_INT_CARD_REMOVE), SDHCI_INT_STATUS);
1570                 tasklet_schedule(&host->card_tasklet);
1571         }
1572
1573         intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE);
1574
1575         if (intmask & SDHCI_INT_CMD_MASK) {
1576                 sdhci_writel(host, intmask & SDHCI_INT_CMD_MASK,
1577                         SDHCI_INT_STATUS);
1578                 sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK);
1579         }
1580
1581         if (intmask & SDHCI_INT_DATA_MASK) {
1582                 sdhci_writel(host, intmask & SDHCI_INT_DATA_MASK,
1583                         SDHCI_INT_STATUS);
1584                 sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
1585         }
1586
1587         intmask &= ~(SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK);
1588
1589         intmask &= ~SDHCI_INT_ERROR;
1590
1591         if (intmask & SDHCI_INT_BUS_POWER) {
1592                 printk(KERN_ERR "%s: Card is consuming too much power!\n",
1593                         mmc_hostname(host->mmc));
1594                 sdhci_writel(host, SDHCI_INT_BUS_POWER, SDHCI_INT_STATUS);
1595         }
1596
1597         intmask &= ~SDHCI_INT_BUS_POWER;
1598
1599         if (intmask & SDHCI_INT_CARD_INT)
1600                 cardint = 1;
1601
1602         intmask &= ~SDHCI_INT_CARD_INT;
1603
1604         if (intmask) {
1605                 printk(KERN_ERR "%s: Unexpected interrupt 0x%08x.\n",
1606                         mmc_hostname(host->mmc), intmask);
1607                 sdhci_dumpregs(host);
1608
1609                 sdhci_writel(host, intmask, SDHCI_INT_STATUS);
1610         }
1611
1612         result = IRQ_HANDLED;
1613
1614         mmiowb();
1615 out:
1616         spin_unlock(&host->lock);
1617
1618         /*
1619          * We have to delay this as it calls back into the driver.
1620          */
1621         if (cardint)
1622                 mmc_signal_sdio_irq(host->mmc);
1623
1624         return result;
1625 }
1626
1627 /*****************************************************************************\
1628  *                                                                           *
1629  * Suspend/resume                                                            *
1630  *                                                                           *
1631 \*****************************************************************************/
1632
1633 #ifdef CONFIG_PM
1634
1635 int sdhci_suspend_host(struct sdhci_host *host, pm_message_t state)
1636 {
1637         int ret = 0;
1638         struct mmc_host *mmc = host->mmc;
1639
1640         sdhci_disable_card_detection(host);
1641
1642         if (mmc->card && (mmc->card->type != MMC_TYPE_SDIO))
1643                 ret = mmc_suspend_host(host->mmc);
1644
1645         sdhci_mask_irqs(host, SDHCI_INT_ALL_MASK);
1646
1647         if (host->vmmc)
1648                 ret = regulator_disable(host->vmmc);
1649
1650         if (host->irq)
1651                 disable_irq(host->irq);
1652
1653         return ret;
1654 }
1655
1656 EXPORT_SYMBOL_GPL(sdhci_suspend_host);
1657
1658 int sdhci_resume_host(struct sdhci_host *host)
1659 {
1660         int ret = 0;
1661         struct mmc_host *mmc = host->mmc;
1662
1663         if (host->vmmc) {
1664                 int ret = regulator_enable(host->vmmc);
1665                 if (ret)
1666                         return ret;
1667         }
1668
1669
1670         if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
1671                 if (host->ops->enable_dma)
1672                         host->ops->enable_dma(host);
1673         }
1674
1675         if (host->irq)
1676                 enable_irq(host->irq);
1677
1678         sdhci_init(host, (host->mmc->pm_flags & MMC_PM_KEEP_POWER));
1679         mmiowb();
1680
1681         if (mmc->card && (mmc->card->type != MMC_TYPE_SDIO))
1682                 ret = mmc_resume_host(host->mmc);
1683
1684         sdhci_enable_card_detection(host);
1685
1686         return ret;
1687 }
1688
1689 EXPORT_SYMBOL_GPL(sdhci_resume_host);
1690
1691 #endif /* CONFIG_PM */
1692
1693 /*****************************************************************************\
1694  *                                                                           *
1695  * Device allocation/registration                                            *
1696  *                                                                           *
1697 \*****************************************************************************/
1698
1699 struct sdhci_host *sdhci_alloc_host(struct device *dev,
1700         size_t priv_size)
1701 {
1702         struct mmc_host *mmc;
1703         struct sdhci_host *host;
1704
1705         WARN_ON(dev == NULL);
1706
1707         mmc = mmc_alloc_host(sizeof(struct sdhci_host) + priv_size, dev);
1708         if (!mmc)
1709                 return ERR_PTR(-ENOMEM);
1710
1711         host = mmc_priv(mmc);
1712         host->mmc = mmc;
1713
1714         return host;
1715 }
1716
1717 EXPORT_SYMBOL_GPL(sdhci_alloc_host);
1718
1719 int sdhci_add_host(struct sdhci_host *host)
1720 {
1721         struct mmc_host *mmc;
1722         unsigned int caps;
1723         int ret;
1724
1725         WARN_ON(host == NULL);
1726         if (host == NULL)
1727                 return -EINVAL;
1728
1729         mmc = host->mmc;
1730
1731         if (debug_quirks)
1732                 host->quirks = debug_quirks;
1733
1734         sdhci_reset(host, SDHCI_RESET_ALL);
1735
1736         if (!(host->quirks & SDHCI_QUIRK_NO_VERSION_REG)) {
1737                 host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
1738                 host->version = (host->version & SDHCI_SPEC_VER_MASK)
1739                                         >> SDHCI_SPEC_VER_SHIFT;
1740         }
1741
1742         if (host->version > SDHCI_SPEC_200) {
1743                 printk(KERN_ERR "%s: Unknown controller version (%d). "
1744                         "You may experience problems.\n", mmc_hostname(mmc),
1745                         host->version);
1746         }
1747
1748         caps = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ? host->caps :
1749                 sdhci_readl(host, SDHCI_CAPABILITIES);
1750
1751         if (host->quirks & SDHCI_QUIRK_FORCE_DMA)
1752                 host->flags |= SDHCI_USE_SDMA;
1753         else if (!(caps & SDHCI_CAN_DO_SDMA))
1754                 DBG("Controller doesn't have SDMA capability\n");
1755         else
1756                 host->flags |= SDHCI_USE_SDMA;
1757
1758         if ((host->quirks & SDHCI_QUIRK_BROKEN_DMA) &&
1759                 (host->flags & SDHCI_USE_SDMA)) {
1760                 DBG("Disabling DMA as it is marked broken\n");
1761                 host->flags &= ~SDHCI_USE_SDMA;
1762         }
1763
1764         if ((host->version >= SDHCI_SPEC_200) && (caps & SDHCI_CAN_DO_ADMA2))
1765                 host->flags |= SDHCI_USE_ADMA;
1766
1767         if ((host->quirks & SDHCI_QUIRK_BROKEN_ADMA) &&
1768                 (host->flags & SDHCI_USE_ADMA)) {
1769                 DBG("Disabling ADMA as it is marked broken\n");
1770                 host->flags &= ~SDHCI_USE_ADMA;
1771         }
1772
1773         if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
1774                 if (host->ops->enable_dma) {
1775                         if (host->ops->enable_dma(host)) {
1776                                 printk(KERN_WARNING "%s: No suitable DMA "
1777                                         "available. Falling back to PIO.\n",
1778                                         mmc_hostname(mmc));
1779                                 host->flags &=
1780                                         ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA);
1781                         }
1782                 }
1783         }
1784
1785         if (host->flags & SDHCI_USE_ADMA) {
1786                 /*
1787                  * We need to allocate descriptors for all sg entries
1788                  * (128) and potentially one alignment transfer for
1789                  * each of those entries.
1790                  */
1791                 host->adma_desc = kmalloc((128 * 2 + 1) * 4, GFP_KERNEL);
1792                 host->align_buffer = kmalloc(128 * 4, GFP_KERNEL);
1793                 if (!host->adma_desc || !host->align_buffer) {
1794                         kfree(host->adma_desc);
1795                         kfree(host->align_buffer);
1796                         printk(KERN_WARNING "%s: Unable to allocate ADMA "
1797                                 "buffers. Falling back to standard DMA.\n",
1798                                 mmc_hostname(mmc));
1799                         host->flags &= ~SDHCI_USE_ADMA;
1800                 }
1801         }
1802
1803         /*
1804          * If we use DMA, then it's up to the caller to set the DMA
1805          * mask, but PIO does not need the hw shim so we set a new
1806          * mask here in that case.
1807          */
1808         if (!(host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))) {
1809                 host->dma_mask = DMA_BIT_MASK(64);
1810                 mmc_dev(host->mmc)->dma_mask = &host->dma_mask;
1811         }
1812
1813         host->max_clk =
1814                 (caps & SDHCI_CLOCK_BASE_MASK) >> SDHCI_CLOCK_BASE_SHIFT;
1815         host->max_clk *= 1000000;
1816         if (host->max_clk == 0 || host->quirks &
1817                         SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN) {
1818                 if (!host->ops->get_max_clock) {
1819                         printk(KERN_ERR
1820                                "%s: Hardware doesn't specify base clock "
1821                                "frequency.\n", mmc_hostname(mmc));
1822                         return -ENODEV;
1823                 }
1824                 host->max_clk = host->ops->get_max_clock(host);
1825         }
1826
1827         host->timeout_clk =
1828                 (caps & SDHCI_TIMEOUT_CLK_MASK) >> SDHCI_TIMEOUT_CLK_SHIFT;
1829         if (host->timeout_clk == 0) {
1830                 if (host->ops->get_timeout_clock) {
1831                         host->timeout_clk = host->ops->get_timeout_clock(host);
1832                 } else if (!(host->quirks &
1833                                 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)) {
1834                         printk(KERN_ERR
1835                                "%s: Hardware doesn't specify timeout clock "
1836                                "frequency.\n", mmc_hostname(mmc));
1837                         return -ENODEV;
1838                 }
1839         }
1840         if (caps & SDHCI_TIMEOUT_CLK_UNIT)
1841                 host->timeout_clk *= 1000;
1842
1843         /*
1844          * Set host parameters.
1845          */
1846         mmc->ops = &sdhci_ops;
1847         if (host->ops->get_min_clock)
1848                 mmc->f_min = host->ops->get_min_clock(host);
1849         else
1850                 mmc->f_min = host->max_clk / 256;
1851         mmc->f_max = host->max_clk;
1852         mmc->caps = 0;
1853
1854         if (host->quirks & SDHCI_QUIRK_8_BIT_DATA)
1855                 mmc->caps |= MMC_CAP_8_BIT_DATA;
1856
1857         if (!(host->quirks & SDHCI_QUIRK_FORCE_1_BIT_DATA))
1858                 mmc->caps |= MMC_CAP_4_BIT_DATA;
1859
1860         if (!(host->quirks & SDHCI_QUIRK_NO_SDIO_IRQ))
1861                 mmc->caps |= MMC_CAP_SDIO_IRQ;
1862
1863         if (caps & SDHCI_CAN_DO_HISPD) {
1864                 mmc->caps |= MMC_CAP_SD_HIGHSPEED;
1865                 mmc->caps |= MMC_CAP_MMC_HIGHSPEED;
1866         }
1867
1868         if (host->quirks & SDHCI_QUIRK_FORCE_HIGH_SPEED_MODE)
1869                 mmc->caps |= MMC_CAP_FORCE_HS;
1870
1871         if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
1872                 mmc->caps |= MMC_CAP_NEEDS_POLL;
1873
1874         mmc->caps |= MMC_CAP_ERASE;
1875
1876         mmc->ocr_avail = 0;
1877         if (caps & SDHCI_CAN_VDD_330)
1878                 mmc->ocr_avail |= MMC_VDD_32_33|MMC_VDD_33_34;
1879         if (caps & SDHCI_CAN_VDD_300)
1880                 mmc->ocr_avail |= MMC_VDD_29_30|MMC_VDD_30_31;
1881         if (caps & SDHCI_CAN_VDD_180)
1882                 mmc->ocr_avail |= MMC_VDD_165_195;
1883
1884         if (mmc->ocr_avail == 0) {
1885                 printk(KERN_ERR "%s: Hardware doesn't report any "
1886                         "support voltages.\n", mmc_hostname(mmc));
1887                 return -ENODEV;
1888         }
1889
1890         spin_lock_init(&host->lock);
1891
1892         /*
1893          * Maximum number of segments. Depends on if the hardware
1894          * can do scatter/gather or not.
1895          */
1896         if (host->flags & SDHCI_USE_ADMA)
1897                 mmc->max_hw_segs = 128;
1898         else if (host->flags & SDHCI_USE_SDMA)
1899                 mmc->max_hw_segs = 1;
1900         else /* PIO */
1901                 mmc->max_hw_segs = 128;
1902         mmc->max_phys_segs = 128;
1903
1904         /*
1905          * Maximum number of sectors in one transfer. Limited by DMA boundary
1906          * size (512KiB).
1907          */
1908         mmc->max_req_size = 524288;
1909
1910         /*
1911          * Maximum segment size. Could be one segment with the maximum number
1912          * of bytes. When doing hardware scatter/gather, each entry cannot
1913          * be larger than 64 KiB though.
1914          */
1915         if (host->flags & SDHCI_USE_ADMA) {
1916                 if (host->quirks & SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC)
1917                         mmc->max_seg_size = 0xffff;
1918                 else
1919                         mmc->max_seg_size = 65536;
1920         } else {
1921                 mmc->max_seg_size = mmc->max_req_size;
1922         }
1923
1924         /*
1925          * Maximum block size. This varies from controller to controller and
1926          * is specified in the capabilities register.
1927          */
1928         if (host->quirks & SDHCI_QUIRK_FORCE_BLK_SZ_2048) {
1929                 mmc->max_blk_size = 2;
1930         } else {
1931                 mmc->max_blk_size = (caps & SDHCI_MAX_BLOCK_MASK) >>
1932                                 SDHCI_MAX_BLOCK_SHIFT;
1933                 if (mmc->max_blk_size >= 3) {
1934                         printk(KERN_WARNING "%s: Invalid maximum block size, "
1935                                 "assuming 512 bytes\n", mmc_hostname(mmc));
1936                         mmc->max_blk_size = 0;
1937                 }
1938         }
1939
1940         mmc->max_blk_size = 512 << mmc->max_blk_size;
1941
1942         /*
1943          * Maximum block count.
1944          */
1945         mmc->max_blk_count = (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535;
1946
1947         /*
1948          * Init tasklets.
1949          */
1950         tasklet_init(&host->card_tasklet,
1951                 sdhci_tasklet_card, (unsigned long)host);
1952         tasklet_init(&host->finish_tasklet,
1953                 sdhci_tasklet_finish, (unsigned long)host);
1954
1955         setup_timer(&host->timer, sdhci_timeout_timer, (unsigned long)host);
1956
1957         ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED,
1958                 mmc_hostname(mmc), host);
1959         if (ret)
1960                 goto untasklet;
1961
1962         host->vmmc = regulator_get(mmc_dev(mmc), "vmmc");
1963         if (IS_ERR(host->vmmc)) {
1964                 printk(KERN_INFO "%s: no vmmc regulator found\n", mmc_hostname(mmc));
1965                 host->vmmc = NULL;
1966         } else {
1967                 regulator_enable(host->vmmc);
1968         }
1969
1970         sdhci_init(host, 0);
1971
1972 #ifdef CONFIG_MMC_DEBUG
1973         sdhci_dumpregs(host);
1974 #endif
1975
1976 #ifdef SDHCI_USE_LEDS_CLASS
1977         snprintf(host->led_name, sizeof(host->led_name),
1978                 "%s::", mmc_hostname(mmc));
1979         host->led.name = host->led_name;
1980         host->led.brightness = LED_OFF;
1981         host->led.default_trigger = mmc_hostname(mmc);
1982         host->led.brightness_set = sdhci_led_control;
1983
1984         ret = led_classdev_register(mmc_dev(mmc), &host->led);
1985         if (ret)
1986                 goto reset;
1987 #endif
1988
1989         mmiowb();
1990
1991         mmc_add_host(mmc);
1992
1993         printk(KERN_INFO "%s: SDHCI controller on %s [%s] using %s\n",
1994                 mmc_hostname(mmc), host->hw_name, dev_name(mmc_dev(mmc)),
1995                 (host->flags & SDHCI_USE_ADMA) ? "ADMA" :
1996                 (host->flags & SDHCI_USE_SDMA) ? "DMA" : "PIO");
1997
1998         sdhci_enable_card_detection(host);
1999
2000         return 0;
2001
2002 #ifdef SDHCI_USE_LEDS_CLASS
2003 reset:
2004         sdhci_reset(host, SDHCI_RESET_ALL);
2005         free_irq(host->irq, host);
2006 #endif
2007 untasklet:
2008         tasklet_kill(&host->card_tasklet);
2009         tasklet_kill(&host->finish_tasklet);
2010
2011         return ret;
2012 }
2013
2014 EXPORT_SYMBOL_GPL(sdhci_add_host);
2015
2016 void sdhci_remove_host(struct sdhci_host *host, int dead)
2017 {
2018         unsigned long flags;
2019
2020         if (dead) {
2021                 spin_lock_irqsave(&host->lock, flags);
2022
2023                 host->flags |= SDHCI_DEVICE_DEAD;
2024
2025                 if (host->mrq) {
2026                         printk(KERN_ERR "%s: Controller removed during "
2027                                 " transfer!\n", mmc_hostname(host->mmc));
2028
2029                         host->mrq->cmd->error = -ENOMEDIUM;
2030                         tasklet_schedule(&host->finish_tasklet);
2031                 }
2032
2033                 spin_unlock_irqrestore(&host->lock, flags);
2034         }
2035
2036         sdhci_disable_card_detection(host);
2037
2038         mmc_remove_host(host->mmc);
2039
2040 #ifdef SDHCI_USE_LEDS_CLASS
2041         led_classdev_unregister(&host->led);
2042 #endif
2043
2044         if (!dead)
2045                 sdhci_reset(host, SDHCI_RESET_ALL);
2046
2047         free_irq(host->irq, host);
2048
2049         del_timer_sync(&host->timer);
2050
2051         tasklet_kill(&host->card_tasklet);
2052         tasklet_kill(&host->finish_tasklet);
2053
2054         if (host->vmmc) {
2055                 regulator_disable(host->vmmc);
2056                 regulator_put(host->vmmc);
2057         }
2058
2059         kfree(host->adma_desc);
2060         kfree(host->align_buffer);
2061
2062         host->adma_desc = NULL;
2063         host->align_buffer = NULL;
2064 }
2065
2066 EXPORT_SYMBOL_GPL(sdhci_remove_host);
2067
2068 void sdhci_free_host(struct sdhci_host *host)
2069 {
2070         mmc_free_host(host->mmc);
2071 }
2072
2073 EXPORT_SYMBOL_GPL(sdhci_free_host);
2074
2075 /*****************************************************************************\
2076  *                                                                           *
2077  * Driver init/exit                                                          *
2078  *                                                                           *
2079 \*****************************************************************************/
2080
2081 static int __init sdhci_drv_init(void)
2082 {
2083         printk(KERN_INFO DRIVER_NAME
2084                 ": Secure Digital Host Controller Interface driver\n");
2085         printk(KERN_INFO DRIVER_NAME ": Copyright(c) Pierre Ossman\n");
2086
2087         return 0;
2088 }
2089
2090 static void __exit sdhci_drv_exit(void)
2091 {
2092 }
2093
2094 module_init(sdhci_drv_init);
2095 module_exit(sdhci_drv_exit);
2096
2097 module_param(debug_quirks, uint, 0444);
2098
2099 MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
2100 MODULE_DESCRIPTION("Secure Digital Host Controller Interface core driver");
2101 MODULE_LICENSE("GPL");
2102
2103 MODULE_PARM_DESC(debug_quirks, "Force certain quirks.");