drivers/gpu/drm/rockchip/rockchip_drm_vop.c

   1 /*
   2  * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
   3  * Author:Mark Yao <mark.yao@rock-chips.com>
   4  *
   5  * This software is licensed under the terms of the GNU General Public
   6  * License version 2, as published by the Free Software Foundation, and
   7  * may be copied, distributed, and modified under those terms.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  */
  14
  15 #include <drm/drm.h>
  16 #include <drm/drmP.h>
  17 #include <drm/drm_atomic.h>
  18 #include <drm/drm_crtc.h>
  19 #include <drm/drm_crtc_helper.h>
  20 #include <drm/drm_plane_helper.h>
  21
  22 #include <linux/kernel.h>
  23 #include <linux/module.h>
  24 #include <linux/platform_device.h>
  25 #include <linux/clk.h>
  26 #include <linux/of.h>
  27 #include <linux/of_device.h>
  28 #include <linux/pm_runtime.h>
  29 #include <linux/component.h>
  30
  31 #include <linux/reset.h>
  32 #include <linux/delay.h>
  33 #include <linux/sort.h>
  34
  35 #include "rockchip_drm_drv.h"
  36 #include "rockchip_drm_gem.h"
  37 #include "rockchip_drm_fb.h"
  38 #include "rockchip_drm_vop.h"
  39
  40 #define VOP_REG_SUPPORT(vop, reg) \
  41                 (!reg.major || (reg.major == VOP_MAJOR(vop->data->version) && \
  42                 reg.begin_minor <= VOP_MINOR(vop->data->version) && \
  43                 reg.end_minor >= VOP_MINOR(vop->data->version) && \
  44                 reg.mask))
  45
  46 #define VOP_WIN_SUPPORT(vop, win, name) \
  47                 VOP_REG_SUPPORT(vop, win->phy->name)
  48
  49 #define VOP_CTRL_SUPPORT(vop, win, name) \
  50                 VOP_REG_SUPPORT(vop, vop->data->ctrl->name)
  51
  52 #define VOP_INTR_SUPPORT(vop, win, name) \
  53                 VOP_REG_SUPPORT(vop, vop->data->intr->name)
  54
  55 #define __REG_SET(x, off, mask, shift, v, write_mask, relaxed) \
  56                 vop_mask_write(x, off, mask, shift, v, write_mask, relaxed)
  57
  58 #define _REG_SET(vop, name, off, reg, mask, v, relaxed) \
  59         do { \
  60                 if (VOP_REG_SUPPORT(vop, reg)) \
  61                         __REG_SET(vop, off + reg.offset, mask, reg.shift, \
  62                                   v, reg.write_mask, relaxed); \
  63                 else \
  64                         dev_dbg(vop->dev, "Warning: not support "#name"\n"); \
  65         } while(0)
  66
  67 #define REG_SET(x, name, off, reg, v, relaxed) \
  68                 _REG_SET(x, name, off, reg, reg.mask, v, relaxed)
  69 #define REG_SET_MASK(x, name, off, reg, mask, v, relaxed) \
  70                 _REG_SET(x, name, off, reg, reg.mask & mask, v, relaxed)
  71
  72 #define VOP_WIN_SET(x, win, name, v) \
  73                 REG_SET(x, name, win->offset, VOP_WIN_NAME(win, name), v, true)
  74 #define VOP_SCL_SET(x, win, name, v) \
  75                 REG_SET(x, name, win->offset, win->phy->scl->name, v, true)
  76 #define VOP_SCL_SET_EXT(x, win, name, v) \
  77                 REG_SET(x, name, win->offset, win->phy->scl->ext->name, v, true)
  78
  79 #define VOP_CTRL_SET(x, name, v) \
  80                 REG_SET(x, name, 0, (x)->data->ctrl->name, v, false)
  81
  82 #define VOP_INTR_GET(vop, name) \
  83                 vop_read_reg(vop, 0, &vop->data->ctrl->name)
  84
  85 #define VOP_INTR_SET(vop, name, mask, v) \
  86                 REG_SET_MASK(vop, name, 0, vop->data->intr->name, \
  87                              mask, v, false)
  88
  89 #define VOP_INTR_SET_TYPE(vop, name, type, v) \
  90         do { \
  91                 int i, reg = 0, mask = 0; \
  92                 for (i = 0; i < vop->data->intr->nintrs; i++) { \
  93                         if (vop->data->intr->intrs[i] & type) { \
  94                                 reg |= (v) << i; \
  95                                 mask |= 1 << i; \
  96                         } \
  97                 } \
  98                 VOP_INTR_SET(vop, name, mask, reg); \
  99         } while (0)
 100 #define VOP_INTR_GET_TYPE(vop, name, type) \
 101                 vop_get_intr_type(vop, &vop->data->intr->name, type)
 102
 103 #define VOP_CTRL_GET(x, name) \
 104                 vop_read_reg(x, 0, vop->data->ctrl->name)
 105
 106 #define VOP_WIN_GET(x, win, name) \
 107                 vop_read_reg(x, win->offset, &VOP_WIN_NAME(win, name))
 108
 109 #define VOP_WIN_NAME(win, name) \
 110                 (vop_get_win_phy(win, &win->phy->name)->name)
 111
 112 #define VOP_WIN_GET_YRGBADDR(vop, win) \
 113                 vop_readl(vop, win->offset + VOP_WIN_NAME(win, yrgb_mst).offset)
 114
 115 #define to_vop(x) container_of(x, struct vop, crtc)
 116 #define to_vop_win(x) container_of(x, struct vop_win, base)
 117 #define to_vop_plane_state(x) container_of(x, struct vop_plane_state, base)
 118
 119 struct vop_zpos {
 120         int win_id;
 121         int zpos;
 122 };
 123
 124 struct vop_plane_state {
 125         struct drm_plane_state base;
 126         int format;
 127         int zpos;
 128         struct drm_rect src;
 129         struct drm_rect dest;
 130         dma_addr_t yrgb_mst;
 131         bool enable;
 132 };
 133
 134 struct vop_win {
 135         struct vop_win *parent;
 136         struct drm_plane base;
 137
 138         int win_id;
 139         int area_id;
 140         uint32_t offset;
 141         enum drm_plane_type type;
 142         const struct vop_win_phy *phy;
 143         const uint32_t *data_formats;
 144         uint32_t nformats;
 145         struct vop *vop;
 146
 147         struct drm_property *rotation_prop;
 148         struct vop_plane_state state;
 149 };
 150
 151 struct vop {
 152         struct drm_crtc crtc;
 153         struct device *dev;
 154         struct drm_device *drm_dev;
 155         struct drm_property *plane_zpos_prop;
 156         bool is_enabled;
 157
 158         /* mutex vsync_ work */
 159         struct mutex vsync_mutex;
 160         bool vsync_work_pending;
 161         struct completion dsp_hold_completion;
 162         struct completion wait_update_complete;
 163         struct drm_pending_vblank_event *event;
 164
 165         const struct vop_data *data;
 166         int num_wins;
 167
 168         uint32_t *regsbak;
 169         void __iomem *regs;
 170
 171         /* physical map length of vop register */
 172         uint32_t len;
 173
 174         /* one time only one process allowed to config the register */
 175         spinlock_t reg_lock;
 176         /* lock vop irq reg */
 177         spinlock_t irq_lock;
 178
 179         unsigned int irq;
 180
 181         /* vop AHP clk */
 182         struct clk *hclk;
 183         /* vop dclk */
 184         struct clk *dclk;
 185         /* vop share memory frequency */
 186         struct clk *aclk;
 187
 188         /* vop dclk reset */
 189         struct reset_control *dclk_rst;
 190
 191         struct vop_win win[];
 192 };
 193
 194 static inline void vop_writel(struct vop *vop, uint32_t offset, uint32_t v)
 195 {
 196         writel(v, vop->regs + offset);
 197         vop->regsbak[offset >> 2] = v;
 198 }
 199
 200 static inline uint32_t vop_readl(struct vop *vop, uint32_t offset)
 201 {
 202         return readl(vop->regs + offset);
 203 }
 204
 205 static inline uint32_t vop_read_reg(struct vop *vop, uint32_t base,
 206                                     const struct vop_reg *reg)
 207 {
 208         return (vop_readl(vop, base + reg->offset) >> reg->shift) & reg->mask;
 209 }
 210
 211 static inline void vop_mask_write(struct vop *vop, uint32_t offset,
 212                                   uint32_t mask, uint32_t shift, uint32_t v,
 213                                   bool write_mask, bool relaxed)
 214 {
 215         if (!mask)
 216                 return;
 217
 218         if (write_mask) {
 219                 v = ((v & mask) << shift) | (mask << (shift + 16));
 220         } else {
 221                 uint32_t cached_val = vop->regsbak[offset >> 2];
 222
 223                 v = (cached_val & ~(mask << shift)) | ((v & mask) << shift);
 224                 vop->regsbak[offset >> 2] = v;
 225         }
 226
 227         if (relaxed)
 228                 writel_relaxed(v, vop->regs + offset);
 229         else
 230                 writel(v, vop->regs + offset);
 231 }
 232
 233 static inline const struct vop_win_phy *
 234 vop_get_win_phy(struct vop_win *win, const struct vop_reg *reg)
 235 {
 236         if (!reg->mask && win->parent)
 237                 return win->parent->phy;
 238
 239         return win->phy;
 240 }
 241
 242 static inline uint32_t vop_get_intr_type(struct vop *vop,
 243                                          const struct vop_reg *reg, int type)
 244 {
 245         uint32_t i, ret = 0;
 246         uint32_t regs = vop_read_reg(vop, 0, reg);
 247
 248         for (i = 0; i < vop->data->intr->nintrs; i++) {
 249                 if ((type & vop->data->intr->intrs[i]) && (regs & 1 << i))
 250                         ret |= vop->data->intr->intrs[i];
 251         }
 252
 253         return ret;
 254 }
 255
 256 static inline void vop_cfg_done(struct vop *vop)
 257 {
 258         VOP_CTRL_SET(vop, cfg_done, 1);
 259 }
 260
 261 static bool has_rb_swapped(uint32_t format)
 262 {
 263         switch (format) {
 264         case DRM_FORMAT_XBGR8888:
 265         case DRM_FORMAT_ABGR8888:
 266         case DRM_FORMAT_BGR888:
 267         case DRM_FORMAT_BGR565:
 268                 return true;
 269         default:
 270                 return false;
 271         }
 272 }
 273
 274 static enum vop_data_format vop_convert_format(uint32_t format)
 275 {
 276         switch (format) {
 277         case DRM_FORMAT_XRGB8888:
 278         case DRM_FORMAT_ARGB8888:
 279         case DRM_FORMAT_XBGR8888:
 280         case DRM_FORMAT_ABGR8888:
 281                 return VOP_FMT_ARGB8888;
 282         case DRM_FORMAT_RGB888:
 283         case DRM_FORMAT_BGR888:
 284                 return VOP_FMT_RGB888;
 285         case DRM_FORMAT_RGB565:
 286         case DRM_FORMAT_BGR565:
 287                 return VOP_FMT_RGB565;
 288         case DRM_FORMAT_NV12:
 289                 return VOP_FMT_YUV420SP;
 290         case DRM_FORMAT_NV16:
 291                 return VOP_FMT_YUV422SP;
 292         case DRM_FORMAT_NV24:
 293                 return VOP_FMT_YUV444SP;
 294         default:
 295                 DRM_ERROR("unsupport format[%08x]\n", format);
 296                 return -EINVAL;
 297         }
 298 }
 299
 300 static bool is_yuv_support(uint32_t format)
 301 {
 302         switch (format) {
 303         case DRM_FORMAT_NV12:
 304         case DRM_FORMAT_NV16:
 305         case DRM_FORMAT_NV24:
 306                 return true;
 307         default:
 308                 return false;
 309         }
 310 }
 311
 312 static bool is_alpha_support(uint32_t format)
 313 {
 314         switch (format) {
 315         case DRM_FORMAT_ARGB8888:
 316         case DRM_FORMAT_ABGR8888:
 317                 return true;
 318         default:
 319                 return false;
 320         }
 321 }
 322
 323 static uint16_t scl_vop_cal_scale(enum scale_mode mode, uint32_t src,
 324                                   uint32_t dst, bool is_horizontal,
 325                                   int vsu_mode, int *vskiplines)
 326 {
 327         uint16_t val = 1 << SCL_FT_DEFAULT_FIXPOINT_SHIFT;
 328
 329         if (is_horizontal) {
 330                 if (mode == SCALE_UP)
 331                         val = GET_SCL_FT_BIC(src, dst);
 332                 else if (mode == SCALE_DOWN)
 333                         val = GET_SCL_FT_BILI_DN(src, dst);
 334         } else {
 335                 if (mode == SCALE_UP) {
 336                         if (vsu_mode == SCALE_UP_BIL)
 337                                 val = GET_SCL_FT_BILI_UP(src, dst);
 338                         else
 339                                 val = GET_SCL_FT_BIC(src, dst);
 340                 } else if (mode == SCALE_DOWN) {
 341                         if (vskiplines) {
 342                                 *vskiplines = scl_get_vskiplines(src, dst);
 343                                 val = scl_get_bili_dn_vskip(src, dst,
 344                                                             *vskiplines);
 345                         } else {
 346                                 val = GET_SCL_FT_BILI_DN(src, dst);
 347                         }
 348                 }
 349         }
 350
 351         return val;
 352 }
 353
 354 static void scl_vop_cal_scl_fac(struct vop *vop, struct vop_win *win,
 355                                 uint32_t src_w, uint32_t src_h, uint32_t dst_w,
 356                                 uint32_t dst_h, uint32_t pixel_format)
 357 {
 358         uint16_t yrgb_hor_scl_mode, yrgb_ver_scl_mode;
 359         uint16_t cbcr_hor_scl_mode = SCALE_NONE;
 360         uint16_t cbcr_ver_scl_mode = SCALE_NONE;
 361         int hsub = drm_format_horz_chroma_subsampling(pixel_format);
 362         int vsub = drm_format_vert_chroma_subsampling(pixel_format);
 363         bool is_yuv = is_yuv_support(pixel_format);
 364         uint16_t cbcr_src_w = src_w / hsub;
 365         uint16_t cbcr_src_h = src_h / vsub;
 366         uint16_t vsu_mode;
 367         uint16_t lb_mode;
 368         uint32_t val;
 369         int vskiplines = 0;
 370
 371         if (!win->phy->scl)
 372                 return;
 373
 374         if (dst_w > 3840) {
 375                 DRM_ERROR("Maximum destination width (3840) exceeded\n");
 376                 return;
 377         }
 378
 379         if (!win->phy->scl->ext) {
 380                 VOP_SCL_SET(vop, win, scale_yrgb_x,
 381                             scl_cal_scale2(src_w, dst_w));
 382                 VOP_SCL_SET(vop, win, scale_yrgb_y,
 383                             scl_cal_scale2(src_h, dst_h));
 384                 if (is_yuv) {
 385                         VOP_SCL_SET(vop, win, scale_cbcr_x,
 386                                     scl_cal_scale2(cbcr_src_w, dst_w));
 387                         VOP_SCL_SET(vop, win, scale_cbcr_y,
 388                                     scl_cal_scale2(cbcr_src_h, dst_h));
 389                 }
 390                 return;
 391         }
 392
 393         yrgb_hor_scl_mode = scl_get_scl_mode(src_w, dst_w);
 394         yrgb_ver_scl_mode = scl_get_scl_mode(src_h, dst_h);
 395
 396         if (is_yuv) {
 397                 cbcr_hor_scl_mode = scl_get_scl_mode(cbcr_src_w, dst_w);
 398                 cbcr_ver_scl_mode = scl_get_scl_mode(cbcr_src_h, dst_h);
 399                 if (cbcr_hor_scl_mode == SCALE_DOWN)
 400                         lb_mode = scl_vop_cal_lb_mode(dst_w, true);
 401                 else
 402                         lb_mode = scl_vop_cal_lb_mode(cbcr_src_w, true);
 403         } else {
 404                 if (yrgb_hor_scl_mode == SCALE_DOWN)
 405                         lb_mode = scl_vop_cal_lb_mode(dst_w, false);
 406                 else
 407                         lb_mode = scl_vop_cal_lb_mode(src_w, false);
 408         }
 409
 410         VOP_SCL_SET_EXT(vop, win, lb_mode, lb_mode);
 411         if (lb_mode == LB_RGB_3840X2) {
 412                 if (yrgb_ver_scl_mode != SCALE_NONE) {
 413                         DRM_ERROR("ERROR : not allow yrgb ver scale\n");
 414                         return;
 415                 }
 416                 if (cbcr_ver_scl_mode != SCALE_NONE) {
 417                         DRM_ERROR("ERROR : not allow cbcr ver scale\n");
 418                         return;
 419                 }
 420                 vsu_mode = SCALE_UP_BIL;
 421         } else if (lb_mode == LB_RGB_2560X4) {
 422                 vsu_mode = SCALE_UP_BIL;
 423         } else {
 424                 vsu_mode = SCALE_UP_BIC;
 425         }
 426
 427         val = scl_vop_cal_scale(yrgb_hor_scl_mode, src_w, dst_w,
 428                                 true, 0, NULL);
 429         VOP_SCL_SET(vop, win, scale_yrgb_x, val);
 430         val = scl_vop_cal_scale(yrgb_ver_scl_mode, src_h, dst_h,
 431                                 false, vsu_mode, &vskiplines);
 432         VOP_SCL_SET(vop, win, scale_yrgb_y, val);
 433
 434         VOP_SCL_SET_EXT(vop, win, vsd_yrgb_gt4, vskiplines == 4);
 435         VOP_SCL_SET_EXT(vop, win, vsd_yrgb_gt2, vskiplines == 2);
 436
 437         VOP_SCL_SET_EXT(vop, win, yrgb_hor_scl_mode, yrgb_hor_scl_mode);
 438         VOP_SCL_SET_EXT(vop, win, yrgb_ver_scl_mode, yrgb_ver_scl_mode);
 439         VOP_SCL_SET_EXT(vop, win, yrgb_hsd_mode, SCALE_DOWN_BIL);
 440         VOP_SCL_SET_EXT(vop, win, yrgb_vsd_mode, SCALE_DOWN_BIL);
 441         VOP_SCL_SET_EXT(vop, win, yrgb_vsu_mode, vsu_mode);
 442         if (is_yuv) {
 443                 val = scl_vop_cal_scale(cbcr_hor_scl_mode, cbcr_src_w,
 444                                         dst_w, true, 0, NULL);
 445                 VOP_SCL_SET(vop, win, scale_cbcr_x, val);
 446                 val = scl_vop_cal_scale(cbcr_ver_scl_mode, cbcr_src_h,
 447                                         dst_h, false, vsu_mode, &vskiplines);
 448                 VOP_SCL_SET(vop, win, scale_cbcr_y, val);
 449
 450                 VOP_SCL_SET_EXT(vop, win, vsd_cbcr_gt4, vskiplines == 4);
 451                 VOP_SCL_SET_EXT(vop, win, vsd_cbcr_gt2, vskiplines == 2);
 452                 VOP_SCL_SET_EXT(vop, win, cbcr_hor_scl_mode, cbcr_hor_scl_mode);
 453                 VOP_SCL_SET_EXT(vop, win, cbcr_ver_scl_mode, cbcr_ver_scl_mode);
 454                 VOP_SCL_SET_EXT(vop, win, cbcr_hsd_mode, SCALE_DOWN_BIL);
 455                 VOP_SCL_SET_EXT(vop, win, cbcr_vsd_mode, SCALE_DOWN_BIL);
 456                 VOP_SCL_SET_EXT(vop, win, cbcr_vsu_mode, vsu_mode);
 457         }
 458 }
 459
 460 static void vop_dsp_hold_valid_irq_enable(struct vop *vop)
 461 {
 462         unsigned long flags;
 463
 464         if (WARN_ON(!vop->is_enabled))
 465                 return;
 466
 467         spin_lock_irqsave(&vop->irq_lock, flags);
 468
 469         VOP_INTR_SET_TYPE(vop, enable, DSP_HOLD_VALID_INTR, 1);
 470
 471         spin_unlock_irqrestore(&vop->irq_lock, flags);
 472 }
 473
 474 static void vop_dsp_hold_valid_irq_disable(struct vop *vop)
 475 {
 476         unsigned long flags;
 477
 478         if (WARN_ON(!vop->is_enabled))
 479                 return;
 480
 481         spin_lock_irqsave(&vop->irq_lock, flags);
 482
 483         VOP_INTR_SET_TYPE(vop, enable, DSP_HOLD_VALID_INTR, 0);
 484
 485         spin_unlock_irqrestore(&vop->irq_lock, flags);
 486 }
 487
 488 static void vop_enable(struct drm_crtc *crtc)
 489 {
 490         struct vop *vop = to_vop(crtc);
 491         int ret, i;
 492
 493         if (vop->is_enabled)
 494                 return;
 495
 496         ret = clk_prepare_enable(vop->hclk);
 497         if (ret < 0) {
 498                 dev_err(vop->dev, "failed to enable hclk - %d\n", ret);
 499                 return;
 500         }
 501
 502         ret = clk_prepare_enable(vop->dclk);
 503         if (ret < 0) {
 504                 dev_err(vop->dev, "failed to enable dclk - %d\n", ret);
 505                 goto err_disable_hclk;
 506         }
 507
 508         ret = clk_prepare_enable(vop->aclk);
 509         if (ret < 0) {
 510                 dev_err(vop->dev, "failed to enable aclk - %d\n", ret);
 511                 goto err_disable_dclk;
 512         }
 513
 514         ret = pm_runtime_get_sync(vop->dev);
 515         if (ret < 0) {
 516                 dev_err(vop->dev, "failed to get pm runtime: %d\n", ret);
 517                 return;
 518         }
 519
 520         /*
 521          * Slave iommu shares power, irq and clock with vop.  It was associated
 522          * automatically with this master device via common driver code.
 523          * Now that we have enabled the clock we attach it to the shared drm
 524          * mapping.
 525          */
 526         ret = rockchip_drm_dma_attach_device(vop->drm_dev, vop->dev);
 527         if (ret) {
 528                 dev_err(vop->dev, "failed to attach dma mapping, %d\n", ret);
 529                 goto err_disable_aclk;
 530         }
 531
 532         memcpy(vop->regsbak, vop->regs, vop->len);
 533
 534         VOP_CTRL_SET(vop, global_regdone_en, 1);
 535
 536         for (i = 0; i < vop->num_wins; i++) {
 537                 struct vop_win *win = &vop->win[i];
 538
 539                 VOP_WIN_SET(vop, win, gate, 1);
 540         }
 541
 542         /*
 543          * At here, vop clock & iommu is enable, R/W vop regs would be safe.
 544          */
 545         vop->is_enabled = true;
 546
 547         spin_lock(&vop->reg_lock);
 548
 549         VOP_CTRL_SET(vop, standby, 0);
 550
 551         spin_unlock(&vop->reg_lock);
 552
 553         enable_irq(vop->irq);
 554
 555         drm_crtc_vblank_on(crtc);
 556
 557         return;
 558
 559 err_disable_aclk:
 560         clk_disable_unprepare(vop->aclk);
 561 err_disable_dclk:
 562         clk_disable_unprepare(vop->dclk);
 563 err_disable_hclk:
 564         clk_disable_unprepare(vop->hclk);
 565 }
 566
 567 static void vop_crtc_disable(struct drm_crtc *crtc)
 568 {
 569         struct vop *vop = to_vop(crtc);
 570         int i;
 571
 572         if (!vop->is_enabled)
 573                 return;
 574
 575         /*
 576          * We need to make sure that all windows are disabled before we
 577          * disable that crtc. Otherwise we might try to scan from a destroyed
 578          * buffer later.
 579          */
 580         for (i = 0; i < vop->num_wins; i++) {
 581                 struct vop_win *win = &vop->win[i];
 582
 583                 spin_lock(&vop->reg_lock);
 584                 VOP_WIN_SET(vop, win, enable, 0);
 585                 spin_unlock(&vop->reg_lock);
 586         }
 587         vop_cfg_done(vop);
 588
 589         drm_crtc_vblank_off(crtc);
 590
 591         /*
 592          * Vop standby will take effect at end of current frame,
 593          * if dsp hold valid irq happen, it means standby complete.
 594          *
 595          * we must wait standby complete when we want to disable aclk,
 596          * if not, memory bus maybe dead.
 597          */
 598         reinit_completion(&vop->dsp_hold_completion);
 599         vop_dsp_hold_valid_irq_enable(vop);
 600
 601         spin_lock(&vop->reg_lock);
 602
 603         VOP_CTRL_SET(vop, standby, 1);
 604
 605         spin_unlock(&vop->reg_lock);
 606
 607         wait_for_completion(&vop->dsp_hold_completion);
 608
 609         vop_dsp_hold_valid_irq_disable(vop);
 610
 611         disable_irq(vop->irq);
 612
 613         vop->is_enabled = false;
 614
 615         /*
 616          * vop standby complete, so iommu detach is safe.
 617          */
 618         rockchip_drm_dma_detach_device(vop->drm_dev, vop->dev);
 619
 620         pm_runtime_put(vop->dev);
 621         clk_disable_unprepare(vop->dclk);
 622         clk_disable_unprepare(vop->aclk);
 623         clk_disable_unprepare(vop->hclk);
 624 }
 625
 626 static void vop_plane_destroy(struct drm_plane *plane)
 627 {
 628         drm_plane_cleanup(plane);
 629 }
 630
 631 static int vop_plane_prepare_fb(struct drm_plane *plane,
 632                                 const struct drm_plane_state *new_state)
 633 {
 634         if (plane->state->fb)
 635                 drm_framebuffer_reference(plane->state->fb);
 636
 637         return 0;
 638 }
 639
 640 static void vop_plane_cleanup_fb(struct drm_plane *plane,
 641                                  const struct drm_plane_state *old_state)
 642 {
 643         if (old_state->fb)
 644                 drm_framebuffer_unreference(old_state->fb);
 645 }
 646
 647 static int vop_plane_atomic_check(struct drm_plane *plane,
 648                            struct drm_plane_state *state)
 649 {
 650         struct drm_crtc *crtc = state->crtc;
 651         struct drm_framebuffer *fb = state->fb;
 652         struct vop_win *win = to_vop_win(plane);
 653         struct vop_plane_state *vop_plane_state = to_vop_plane_state(state);
 654         struct drm_crtc_state *crtc_state;
 655         bool visible;
 656         int ret;
 657         struct drm_rect *dest = &vop_plane_state->dest;
 658         struct drm_rect *src = &vop_plane_state->src;
 659         struct drm_rect clip;
 660         int min_scale = win->phy->scl ? FRAC_16_16(1, 8) :
 661                                         DRM_PLANE_HELPER_NO_SCALING;
 662         int max_scale = win->phy->scl ? FRAC_16_16(8, 1) :
 663                                         DRM_PLANE_HELPER_NO_SCALING;
 664
 665         crtc = crtc ? crtc : plane->state->crtc;
 666         /*
 667          * Both crtc or plane->state->crtc can be null.
 668          */
 669         if (!crtc || !fb)
 670                 goto out_disable;
 671
 672         crtc_state = drm_atomic_get_crtc_state(state->state, crtc);
 673         if (IS_ERR(crtc_state))
 674                 return PTR_ERR(crtc_state);
 675
 676         src->x1 = state->src_x;
 677         src->y1 = state->src_y;
 678         src->x2 = state->src_x + state->src_w;
 679         src->y2 = state->src_y + state->src_h;
 680         dest->x1 = state->crtc_x;
 681         dest->y1 = state->crtc_y;
 682         dest->x2 = state->crtc_x + state->crtc_w;
 683         dest->y2 = state->crtc_y + state->crtc_h;
 684
 685         clip.x1 = 0;
 686         clip.y1 = 0;
 687         clip.x2 = crtc_state->mode.hdisplay;
 688         clip.y2 = crtc_state->mode.vdisplay;
 689
 690         ret = drm_plane_helper_check_update(plane, crtc, state->fb,
 691                                             src, dest, &clip,
 692                                             min_scale,
 693                                             max_scale,
 694                                             true, true, &visible);
 695         if (ret)
 696                 return ret;
 697
 698         if (!visible)
 699                 goto out_disable;
 700
 701         vop_plane_state->format = vop_convert_format(fb->pixel_format);
 702         if (vop_plane_state->format < 0)
 703                 return vop_plane_state->format;
 704
 705         /*
 706          * Src.x1 can be odd when do clip, but yuv plane start point
 707          * need align with 2 pixel.
 708          */
 709         if (is_yuv_support(fb->pixel_format) && ((src->x1 >> 16) % 2))
 710                 return -EINVAL;
 711
 712         vop_plane_state->enable = true;
 713
 714         return 0;
 715
 716 out_disable:
 717         vop_plane_state->enable = false;
 718         return 0;
 719 }
 720
 721 static void vop_plane_atomic_disable(struct drm_plane *plane,
 722                                      struct drm_plane_state *old_state)
 723 {
 724         struct vop_plane_state *vop_plane_state = to_vop_plane_state(old_state);
 725         struct vop_win *win = to_vop_win(plane);
 726         struct vop *vop = to_vop(old_state->crtc);
 727
 728         if (!old_state->crtc)
 729                 return;
 730
 731         spin_lock(&vop->reg_lock);
 732
 733         VOP_WIN_SET(vop, win, enable, 0);
 734
 735         spin_unlock(&vop->reg_lock);
 736
 737         vop_plane_state->enable = false;
 738 }
 739
 740 static void vop_plane_atomic_update(struct drm_plane *plane,
 741                 struct drm_plane_state *old_state)
 742 {
 743         struct drm_plane_state *state = plane->state;
 744         struct drm_crtc *crtc = state->crtc;
 745         struct vop_win *win = to_vop_win(plane);
 746         struct vop_plane_state *vop_plane_state = to_vop_plane_state(state);
 747         struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc->state);
 748         struct vop *vop = to_vop(state->crtc);
 749         struct drm_framebuffer *fb = state->fb;
 750         unsigned int actual_w, actual_h;
 751         unsigned int dsp_stx, dsp_sty;
 752         uint32_t act_info, dsp_info, dsp_st;
 753         struct drm_rect *src = &vop_plane_state->src;
 754         struct drm_rect *dest = &vop_plane_state->dest;
 755         struct drm_gem_object *obj, *uv_obj;
 756         struct rockchip_gem_object *rk_obj, *rk_uv_obj;
 757         unsigned long offset;
 758         dma_addr_t dma_addr;
 759         int ymirror, xmirror;
 760         uint32_t val;
 761         bool rb_swap;
 762
 763         /*
 764          * can't update plane when vop is disabled.
 765          */
 766         if (!crtc)
 767                 return;
 768
 769         if (WARN_ON(!vop->is_enabled))
 770                 return;
 771
 772         if (!vop_plane_state->enable) {
 773                 vop_plane_atomic_disable(plane, old_state);
 774                 return;
 775         }
 776
 777         obj = rockchip_fb_get_gem_obj(fb, 0);
 778         rk_obj = to_rockchip_obj(obj);
 779
 780         actual_w = drm_rect_width(src) >> 16;
 781         actual_h = drm_rect_height(src) >> 16;
 782         act_info = (actual_h - 1) << 16 | ((actual_w - 1) & 0xffff);
 783
 784         dsp_info = (drm_rect_height(dest) - 1) << 16;
 785         dsp_info |= (drm_rect_width(dest) - 1) & 0xffff;
 786
 787         dsp_stx = dest->x1 + crtc->mode.htotal - crtc->mode.hsync_start;
 788         dsp_sty = dest->y1 + crtc->mode.vtotal - crtc->mode.vsync_start;
 789         dsp_st = dsp_sty << 16 | (dsp_stx & 0xffff);
 790
 791         offset = (src->x1 >> 16) * drm_format_plane_cpp(fb->pixel_format, 0);
 792         if (state->rotation & BIT(DRM_REFLECT_Y))
 793                 offset += ((src->y2 >> 16) - 1) * fb->pitches[0];
 794         else
 795                 offset += (src->y1 >> 16) * fb->pitches[0];
 796         vop_plane_state->yrgb_mst = rk_obj->dma_addr + offset + fb->offsets[0];
 797
 798         ymirror = !!(state->rotation & BIT(DRM_REFLECT_Y));
 799         xmirror = !!(state->rotation & BIT(DRM_REFLECT_X));
 800
 801         spin_lock(&vop->reg_lock);
 802
 803         VOP_WIN_SET(vop, win, xmirror, xmirror);
 804         VOP_WIN_SET(vop, win, ymirror, ymirror);
 805         VOP_WIN_SET(vop, win, format, vop_plane_state->format);
 806         VOP_WIN_SET(vop, win, yrgb_vir, fb->pitches[0] >> 2);
 807         VOP_WIN_SET(vop, win, yrgb_mst, vop_plane_state->yrgb_mst);
 808         if (is_yuv_support(fb->pixel_format)) {
 809                 int hsub = drm_format_horz_chroma_subsampling(fb->pixel_format);
 810                 int vsub = drm_format_vert_chroma_subsampling(fb->pixel_format);
 811                 int bpp = drm_format_plane_cpp(fb->pixel_format, 1);
 812
 813                 uv_obj = rockchip_fb_get_gem_obj(fb, 1);
 814                 rk_uv_obj = to_rockchip_obj(uv_obj);
 815
 816                 offset = (src->x1 >> 16) * bpp / hsub;
 817                 offset += (src->y1 >> 16) * fb->pitches[1] / vsub;
 818
 819                 dma_addr = rk_uv_obj->dma_addr + offset + fb->offsets[1];
 820                 VOP_WIN_SET(vop, win, uv_vir, fb->pitches[1] >> 2);
 821                 VOP_WIN_SET(vop, win, uv_mst, dma_addr);
 822         }
 823
 824         scl_vop_cal_scl_fac(vop, win, actual_w, actual_h,
 825                             drm_rect_width(dest), drm_rect_height(dest),
 826                             fb->pixel_format);
 827
 828         VOP_WIN_SET(vop, win, act_info, act_info);
 829         VOP_WIN_SET(vop, win, dsp_info, dsp_info);
 830         VOP_WIN_SET(vop, win, dsp_st, dsp_st);
 831
 832         rb_swap = has_rb_swapped(fb->pixel_format);
 833         VOP_WIN_SET(vop, win, rb_swap, rb_swap);
 834
 835         if (is_alpha_support(fb->pixel_format) &&
 836             (s->dsp_layer_sel & 0x3) != win->win_id) {
 837                 VOP_WIN_SET(vop, win, dst_alpha_ctl,
 838                             DST_FACTOR_M0(ALPHA_SRC_INVERSE));
 839                 val = SRC_ALPHA_EN(1) | SRC_COLOR_M0(ALPHA_SRC_PRE_MUL) |
 840                         SRC_ALPHA_M0(ALPHA_STRAIGHT) |
 841                         SRC_BLEND_M0(ALPHA_PER_PIX) |
 842                         SRC_ALPHA_CAL_M0(ALPHA_NO_SATURATION) |
 843                         SRC_FACTOR_M0(ALPHA_ONE);
 844                 VOP_WIN_SET(vop, win, src_alpha_ctl, val);
 845                 VOP_WIN_SET(vop, win, alpha_mode, 1);
 846                 VOP_WIN_SET(vop, win, alpha_en, 1);
 847         } else {
 848                 VOP_WIN_SET(vop, win, src_alpha_ctl, SRC_ALPHA_EN(0));
 849                 VOP_WIN_SET(vop, win, alpha_en, 0);
 850         }
 851
 852         VOP_WIN_SET(vop, win, enable, 1);
 853         spin_unlock(&vop->reg_lock);
 854 }
 855
 856 static const struct drm_plane_helper_funcs plane_helper_funcs = {
 857         .prepare_fb = vop_plane_prepare_fb,
 858         .cleanup_fb = vop_plane_cleanup_fb,
 859         .atomic_check = vop_plane_atomic_check,
 860         .atomic_update = vop_plane_atomic_update,
 861         .atomic_disable = vop_plane_atomic_disable,
 862 };
 863
 864 void vop_atomic_plane_reset(struct drm_plane *plane)
 865 {
 866         struct vop_win *win = to_vop_win(plane);
 867         struct vop_plane_state *vop_plane_state =
 868                                         to_vop_plane_state(plane->state);
 869
 870         if (plane->state && plane->state->fb)
 871                 drm_framebuffer_unreference(plane->state->fb);
 872
 873         kfree(vop_plane_state);
 874         vop_plane_state = kzalloc(sizeof(*vop_plane_state), GFP_KERNEL);
 875         if (!vop_plane_state)
 876                 return;
 877
 878         vop_plane_state->zpos = win->win_id;
 879         plane->state = &vop_plane_state->base;
 880         plane->state->plane = plane;
 881 }
 882
 883 struct drm_plane_state *
 884 vop_atomic_plane_duplicate_state(struct drm_plane *plane)
 885 {
 886         struct vop_plane_state *old_vop_plane_state;
 887         struct vop_plane_state *vop_plane_state;
 888
 889         if (WARN_ON(!plane->state))
 890                 return NULL;
 891
 892         old_vop_plane_state = to_vop_plane_state(plane->state);
 893         vop_plane_state = kmemdup(old_vop_plane_state,
 894                                   sizeof(*vop_plane_state), GFP_KERNEL);
 895         if (!vop_plane_state)
 896                 return NULL;
 897
 898         __drm_atomic_helper_plane_duplicate_state(plane,
 899                                                   &vop_plane_state->base);
 900
 901         return &vop_plane_state->base;
 902 }
 903
 904 static void vop_atomic_plane_destroy_state(struct drm_plane *plane,
 905                                            struct drm_plane_state *state)
 906 {
 907         struct vop_plane_state *vop_state = to_vop_plane_state(state);
 908
 909         __drm_atomic_helper_plane_destroy_state(plane, state);
 910
 911         kfree(vop_state);
 912 }
 913
 914 static int vop_atomic_plane_set_property(struct drm_plane *plane,
 915                                          struct drm_plane_state *state,
 916                                          struct drm_property *property,
 917                                          uint64_t val)
 918 {
 919         struct vop_win *win = to_vop_win(plane);
 920         struct vop_plane_state *plane_state = to_vop_plane_state(state);
 921
 922         if (property == win->vop->plane_zpos_prop) {
 923                 plane_state->zpos = val;
 924                 return 0;
 925         }
 926
 927         if (property == win->rotation_prop) {
 928                 state->rotation = val;
 929                 return 0;
 930         }
 931
 932         DRM_ERROR("failed to set vop plane property\n");
 933         return -EINVAL;
 934 }
 935
 936 static int vop_atomic_plane_get_property(struct drm_plane *plane,
 937                                          const struct drm_plane_state *state,
 938                                          struct drm_property *property,
 939                                          uint64_t *val)
 940 {
 941         struct vop_win *win = to_vop_win(plane);
 942         struct vop_plane_state *plane_state = to_vop_plane_state(state);
 943
 944         if (property == win->vop->plane_zpos_prop) {
 945                 *val = plane_state->zpos;
 946                 return 0;
 947         }
 948
 949         if (property == win->rotation_prop) {
 950                 *val = state->rotation;
 951                 return 0;
 952         }
 953
 954         DRM_ERROR("failed to get vop plane property\n");
 955         return -EINVAL;
 956 }
 957
 958 static const struct drm_plane_funcs vop_plane_funcs = {
 959         .update_plane   = drm_atomic_helper_update_plane,
 960         .disable_plane  = drm_atomic_helper_disable_plane,
 961         .destroy = vop_plane_destroy,
 962         .reset = vop_atomic_plane_reset,
 963         .atomic_duplicate_state = vop_atomic_plane_duplicate_state,
 964         .atomic_destroy_state = vop_atomic_plane_destroy_state,
 965         .atomic_set_property = vop_atomic_plane_set_property,
 966         .atomic_get_property = vop_atomic_plane_get_property,
 967 };
 968
 969 static int vop_crtc_enable_vblank(struct drm_crtc *crtc)
 970 {
 971         struct vop *vop = to_vop(crtc);
 972         unsigned long flags;
 973
 974         if (WARN_ON(!vop->is_enabled))
 975                 return -EPERM;
 976
 977         spin_lock_irqsave(&vop->irq_lock, flags);
 978
 979         VOP_INTR_SET_TYPE(vop, enable, FS_INTR, 1);
 980
 981         spin_unlock_irqrestore(&vop->irq_lock, flags);
 982
 983         return 0;
 984 }
 985
 986 static void vop_crtc_disable_vblank(struct drm_crtc *crtc)
 987 {
 988         struct vop *vop = to_vop(crtc);
 989         unsigned long flags;
 990
 991         if (WARN_ON(!vop->is_enabled))
 992                 return;
 993
 994         spin_lock_irqsave(&vop->irq_lock, flags);
 995
 996         VOP_INTR_SET_TYPE(vop, enable, FS_INTR, 0);
 997
 998         spin_unlock_irqrestore(&vop->irq_lock, flags);
 999 }
1000
1001 static void vop_crtc_wait_for_update(struct drm_crtc *crtc)
1002 {
1003         struct vop *vop = to_vop(crtc);
1004
1005         reinit_completion(&vop->wait_update_complete);
1006         WARN_ON(!wait_for_completion_timeout(&vop->wait_update_complete, 100));
1007 }
1008
1009 static void vop_crtc_cancel_pending_vblank(struct drm_crtc *crtc,
1010                                            struct drm_file *file_priv)
1011 {
1012         struct drm_device *drm = crtc->dev;
1013         struct vop *vop = to_vop(crtc);
1014         struct drm_pending_vblank_event *e;
1015         unsigned long flags;
1016
1017         spin_lock_irqsave(&drm->event_lock, flags);
1018         e = vop->event;
1019         if (e && e->base.file_priv == file_priv) {
1020                 vop->event = NULL;
1021
1022                 e->base.destroy(&e->base);
1023                 file_priv->event_space += sizeof(e->event);
1024         }
1025         spin_unlock_irqrestore(&drm->event_lock, flags);
1026 }
1027
1028 static const struct rockchip_crtc_funcs private_crtc_funcs = {
1029         .enable_vblank = vop_crtc_enable_vblank,
1030         .disable_vblank = vop_crtc_disable_vblank,
1031         .wait_for_update = vop_crtc_wait_for_update,
1032         .cancel_pending_vblank = vop_crtc_cancel_pending_vblank,
1033 };
1034
1035 static bool vop_crtc_mode_fixup(struct drm_crtc *crtc,
1036                                 const struct drm_display_mode *mode,
1037                                 struct drm_display_mode *adjusted_mode)
1038 {
1039         struct vop *vop = to_vop(crtc);
1040
1041         adjusted_mode->clock =
1042                 clk_round_rate(vop->dclk, mode->clock * 1000) / 1000;
1043
1044         return true;
1045 }
1046
1047 static void vop_crtc_enable(struct drm_crtc *crtc)
1048 {
1049         struct vop *vop = to_vop(crtc);
1050         const struct vop_data *vop_data = vop->data;
1051         struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc->state);
1052         struct drm_display_mode *adjusted_mode = &crtc->state->adjusted_mode;
1053         u16 hsync_len = adjusted_mode->hsync_end - adjusted_mode->hsync_start;
1054         u16 hdisplay = adjusted_mode->hdisplay;
1055         u16 htotal = adjusted_mode->htotal;
1056         u16 hact_st = adjusted_mode->htotal - adjusted_mode->hsync_start;
1057         u16 hact_end = hact_st + hdisplay;
1058         u16 vdisplay = adjusted_mode->vdisplay;
1059         u16 vtotal = adjusted_mode->vtotal;
1060         u16 vsync_len = adjusted_mode->vsync_end - adjusted_mode->vsync_start;
1061         u16 vact_st = adjusted_mode->vtotal - adjusted_mode->vsync_start;
1062         u16 vact_end = vact_st + vdisplay;
1063         uint32_t val;
1064
1065         vop_enable(crtc);
1066         /*
1067          * If dclk rate is zero, mean that scanout is stop,
1068          * we don't need wait any more.
1069          */
1070         if (clk_get_rate(vop->dclk)) {
1071                 /*
1072                  * Rk3288 vop timing register is immediately, when configure
1073                  * display timing on display time, may cause tearing.
1074                  *
1075                  * Vop standby will take effect at end of current frame,
1076                  * if dsp hold valid irq happen, it means standby complete.
1077                  *
1078                  * mode set:
1079                  *    standby and wait complete --> |----
1080                  *                                  | display time
1081                  *                                  |----
1082                  *                                  |---> dsp hold irq
1083                  *     configure display timing --> |
1084                  *         standby exit             |
1085                  *                                  | new frame start.
1086                  */
1087
1088                 reinit_completion(&vop->dsp_hold_completion);
1089                 vop_dsp_hold_valid_irq_enable(vop);
1090
1091                 spin_lock(&vop->reg_lock);
1092
1093                 VOP_CTRL_SET(vop, standby, 1);
1094
1095                 spin_unlock(&vop->reg_lock);
1096
1097                 wait_for_completion(&vop->dsp_hold_completion);
1098
1099                 vop_dsp_hold_valid_irq_disable(vop);
1100         }
1101
1102         val = 0x8;
1103         val |= (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC) ? 0 : 1;
1104         val |= (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC) ? 0 : (1 << 1);
1105         VOP_CTRL_SET(vop, pin_pol, val);
1106         switch (s->output_type) {
1107         case DRM_MODE_CONNECTOR_LVDS:
1108                 VOP_CTRL_SET(vop, rgb_en, 1);
1109                 VOP_CTRL_SET(vop, rgb_pin_pol, val);
1110                 break;
1111         case DRM_MODE_CONNECTOR_eDP:
1112                 VOP_CTRL_SET(vop, edp_en, 1);
1113                 VOP_CTRL_SET(vop, edp_pin_pol, val);
1114                 break;
1115         case DRM_MODE_CONNECTOR_HDMIA:
1116                 VOP_CTRL_SET(vop, hdmi_en, 1);
1117                 VOP_CTRL_SET(vop, hdmi_pin_pol, val);
1118                 break;
1119         case DRM_MODE_CONNECTOR_DSI:
1120                 VOP_CTRL_SET(vop, mipi_en, 1);
1121                 VOP_CTRL_SET(vop, mipi_pin_pol, val);
1122                 break;
1123         default:
1124                 DRM_ERROR("unsupport connector_type[%d]\n", s->output_type);
1125         }
1126
1127         if (s->output_mode == ROCKCHIP_OUT_MODE_AAAA &&
1128             !(vop_data->feature & VOP_FEATURE_OUTPUT_10BIT))
1129                 s->output_mode = ROCKCHIP_OUT_MODE_P888;
1130
1131         VOP_CTRL_SET(vop, out_mode, s->output_mode);
1132
1133         VOP_CTRL_SET(vop, htotal_pw, (htotal << 16) | hsync_len);
1134         val = hact_st << 16;
1135         val |= hact_end;
1136         VOP_CTRL_SET(vop, hact_st_end, val);
1137         VOP_CTRL_SET(vop, hpost_st_end, val);
1138
1139         VOP_CTRL_SET(vop, vtotal_pw, (vtotal << 16) | vsync_len);
1140         val = vact_st << 16;
1141         val |= vact_end;
1142         VOP_CTRL_SET(vop, vact_st_end, val);
1143         VOP_CTRL_SET(vop, vpost_st_end, val);
1144
1145         clk_set_rate(vop->dclk, adjusted_mode->clock * 1000);
1146
1147         VOP_CTRL_SET(vop, standby, 0);
1148 }
1149
1150 static int vop_zpos_cmp(const void *a, const void *b)
1151 {
1152         struct vop_zpos *pa = (struct vop_zpos *)a;
1153         struct vop_zpos *pb = (struct vop_zpos *)b;
1154
1155         return pa->zpos - pb->zpos;
1156 }
1157
1158 static int vop_crtc_atomic_check(struct drm_crtc *crtc,
1159                                  struct drm_crtc_state *crtc_state)
1160 {
1161         struct drm_atomic_state *state = crtc_state->state;
1162         struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state);
1163         struct vop *vop = to_vop(crtc);
1164         const struct vop_data *vop_data = vop->data;
1165         struct drm_plane *plane;
1166         struct drm_plane_state *pstate;
1167         struct vop_plane_state *plane_state;
1168         struct vop_zpos *pzpos;
1169         int dsp_layer_sel = 0;
1170         int i, j, cnt = 0, ret = 0;
1171
1172         pzpos = kmalloc_array(vop_data->win_size, sizeof(*pzpos), GFP_KERNEL);
1173         if (!pzpos)
1174                 return -ENOMEM;
1175
1176         for (i = 0; i < vop_data->win_size; i++) {
1177                 const struct vop_win_data *win_data = &vop_data->win[i];
1178                 struct vop_win *win;
1179
1180                 if (!win_data->phy)
1181                         continue;
1182
1183                 for (j = 0; j < vop->num_wins; j++) {
1184                         win = &vop->win[j];
1185
1186                         if (win->win_id == i && !win->area_id)
1187                                 break;
1188                 }
1189                 if (WARN_ON(j >= vop->num_wins)) {
1190                         ret = -EINVAL;
1191                         goto err_free_pzpos;
1192                 }
1193
1194                 plane = &win->base;
1195                 pstate = state->plane_states[drm_plane_index(plane)];
1196                 /*
1197                  * plane might not have changed, in which case take
1198                  * current state:
1199                  */
1200                 if (!pstate)
1201                         pstate = plane->state;
1202                 plane_state = to_vop_plane_state(pstate);
1203                 pzpos[cnt].zpos = plane_state->zpos;
1204                 pzpos[cnt++].win_id = win->win_id;
1205         }
1206
1207         sort(pzpos, cnt, sizeof(pzpos[0]), vop_zpos_cmp, NULL);
1208
1209         for (i = 0, cnt = 0; i < vop_data->win_size; i++) {
1210                 const struct vop_win_data *win_data = &vop_data->win[i];
1211                 int shift = i * 2;
1212
1213                 if (win_data->phy) {
1214                         struct vop_zpos *zpos = &pzpos[cnt++];
1215
1216                         dsp_layer_sel |= zpos->win_id << shift;
1217                 } else {
1218                         dsp_layer_sel |= i << shift;
1219                 }
1220         }
1221
1222         s->dsp_layer_sel = dsp_layer_sel;
1223
1224 err_free_pzpos:
1225         kfree(pzpos);
1226         return ret;
1227 }
1228
1229 static void vop_crtc_atomic_flush(struct drm_crtc *crtc,
1230                                   struct drm_crtc_state *old_crtc_state)
1231 {
1232         struct rockchip_crtc_state *s =
1233                         to_rockchip_crtc_state(crtc->state);
1234         struct vop *vop = to_vop(crtc);
1235
1236         if (WARN_ON(!vop->is_enabled))
1237                 return;
1238
1239         spin_lock(&vop->reg_lock);
1240
1241         VOP_CTRL_SET(vop, dsp_layer_sel, s->dsp_layer_sel);
1242         vop_cfg_done(vop);
1243
1244         spin_unlock(&vop->reg_lock);
1245 }
1246
1247 static void vop_crtc_atomic_begin(struct drm_crtc *crtc,
1248                                   struct drm_crtc_state *old_crtc_state)
1249 {
1250         struct vop *vop = to_vop(crtc);
1251
1252         if (crtc->state->event) {
1253                 WARN_ON(drm_crtc_vblank_get(crtc) != 0);
1254
1255                 vop->event = crtc->state->event;
1256                 crtc->state->event = NULL;
1257         }
1258 }
1259
1260 static const struct drm_crtc_helper_funcs vop_crtc_helper_funcs = {
1261         .enable = vop_crtc_enable,
1262         .disable = vop_crtc_disable,
1263         .mode_fixup = vop_crtc_mode_fixup,
1264         .atomic_check = vop_crtc_atomic_check,
1265         .atomic_flush = vop_crtc_atomic_flush,
1266         .atomic_begin = vop_crtc_atomic_begin,
1267 };
1268
1269 static void vop_crtc_destroy(struct drm_crtc *crtc)
1270 {
1271         drm_crtc_cleanup(crtc);
1272 }
1273
1274 static struct drm_crtc_state *vop_crtc_duplicate_state(struct drm_crtc *crtc)
1275 {
1276         struct rockchip_crtc_state *rockchip_state;
1277
1278         rockchip_state = kzalloc(sizeof(*rockchip_state), GFP_KERNEL);
1279         if (!rockchip_state)
1280                 return NULL;
1281
1282         __drm_atomic_helper_crtc_duplicate_state(crtc, &rockchip_state->base);
1283         return &rockchip_state->base;
1284 }
1285
1286 static void vop_crtc_destroy_state(struct drm_crtc *crtc,
1287                                    struct drm_crtc_state *state)
1288 {
1289         struct rockchip_crtc_state *s = to_rockchip_crtc_state(state);
1290
1291         __drm_atomic_helper_crtc_destroy_state(crtc, &s->base);
1292         kfree(s);
1293 }
1294
1295 static const struct drm_crtc_funcs vop_crtc_funcs = {
1296         .set_config = drm_atomic_helper_set_config,
1297         .page_flip = drm_atomic_helper_page_flip,
1298         .destroy = vop_crtc_destroy,
1299         .reset = drm_atomic_helper_crtc_reset,
1300         .atomic_duplicate_state = vop_crtc_duplicate_state,
1301         .atomic_destroy_state = vop_crtc_destroy_state,
1302 };
1303
1304 static bool vop_win_pending_is_complete(struct vop_win *vop_win)
1305 {
1306         struct drm_plane *plane = &vop_win->base;
1307         struct vop_plane_state *state = to_vop_plane_state(plane->state);
1308         dma_addr_t yrgb_mst;
1309
1310         if (!state->enable)
1311                 return VOP_WIN_GET(vop_win->vop, vop_win, enable) == 0;
1312
1313         yrgb_mst = VOP_WIN_GET_YRGBADDR(vop_win->vop, vop_win);
1314
1315         return yrgb_mst == state->yrgb_mst;
1316 }
1317
1318 static void vop_handle_vblank(struct vop *vop)
1319 {
1320         struct drm_device *drm = vop->drm_dev;
1321         struct drm_crtc *crtc = &vop->crtc;
1322         unsigned long flags;
1323         int i;
1324
1325         for (i = 0; i < vop->num_wins; i++) {
1326                 if (!vop_win_pending_is_complete(&vop->win[i]))
1327                         return;
1328         }
1329
1330         if (vop->event) {
1331                 spin_lock_irqsave(&drm->event_lock, flags);
1332
1333                 drm_crtc_send_vblank_event(crtc, vop->event);
1334                 drm_crtc_vblank_put(crtc);
1335                 vop->event = NULL;
1336
1337                 spin_unlock_irqrestore(&drm->event_lock, flags);
1338         }
1339         if (!completion_done(&vop->wait_update_complete))
1340                 complete(&vop->wait_update_complete);
1341 }
1342
1343 static irqreturn_t vop_isr(int irq, void *data)
1344 {
1345         struct vop *vop = data;
1346         struct drm_crtc *crtc = &vop->crtc;
1347         uint32_t active_irqs;
1348         unsigned long flags;
1349         int ret = IRQ_NONE;
1350
1351         /*
1352          * interrupt register has interrupt status, enable and clear bits, we
1353          * must hold irq_lock to avoid a race with enable/disable_vblank().
1354         */
1355         spin_lock_irqsave(&vop->irq_lock, flags);
1356
1357         active_irqs = VOP_INTR_GET_TYPE(vop, status, INTR_MASK);
1358         /* Clear all active interrupt sources */
1359         if (active_irqs)
1360                 VOP_INTR_SET_TYPE(vop, clear, active_irqs, 1);
1361
1362         spin_unlock_irqrestore(&vop->irq_lock, flags);
1363
1364         /* This is expected for vop iommu irqs, since the irq is shared */
1365         if (!active_irqs)
1366                 return IRQ_NONE;
1367
1368         if (active_irqs & DSP_HOLD_VALID_INTR) {
1369                 complete(&vop->dsp_hold_completion);
1370                 active_irqs &= ~DSP_HOLD_VALID_INTR;
1371                 ret = IRQ_HANDLED;
1372         }
1373
1374         if (active_irqs & FS_INTR) {
1375                 drm_crtc_handle_vblank(crtc);
1376                 vop_handle_vblank(vop);
1377                 active_irqs &= ~FS_INTR;
1378                 ret = IRQ_HANDLED;
1379         }
1380
1381         /* Unhandled irqs are spurious. */
1382         if (active_irqs)
1383                 DRM_ERROR("Unknown VOP IRQs: %#02x\n", active_irqs);
1384
1385         return ret;
1386 }
1387
1388 static int vop_plane_init(struct vop *vop, struct vop_win *win,
1389                           unsigned long possible_crtcs)
1390 {
1391         struct drm_plane *share = NULL;
1392         unsigned int rotations = 0;
1393         struct drm_property *prop;
1394         int ret;
1395
1396         if (win->parent)
1397                 share = &win->parent->base;
1398
1399         ret = drm_share_plane_init(vop->drm_dev, &win->base, share,
1400                                    possible_crtcs, &vop_plane_funcs,
1401                                    win->data_formats, win->nformats, win->type);
1402         if (ret) {
1403                 DRM_ERROR("failed to initialize plane\n");
1404                 return ret;
1405         }
1406         drm_plane_helper_add(&win->base, &plane_helper_funcs);
1407         drm_object_attach_property(&win->base.base,
1408                                    vop->plane_zpos_prop, win->win_id);
1409
1410         if (VOP_WIN_SUPPORT(vop, win, xmirror))
1411                 rotations |= BIT(DRM_REFLECT_X);
1412
1413         if (VOP_WIN_SUPPORT(vop, win, ymirror))
1414                 rotations |= BIT(DRM_REFLECT_Y);
1415
1416         if (rotations) {
1417                 rotations |= BIT(DRM_ROTATE_0);
1418                 prop = drm_mode_create_rotation_property(vop->drm_dev,
1419                                                          rotations);
1420                 if (!prop) {
1421                         DRM_ERROR("failed to create zpos property\n");
1422                         return -EINVAL;
1423                 }
1424                 drm_object_attach_property(&win->base.base, prop,
1425                                            BIT(DRM_ROTATE_0));
1426                 win->rotation_prop = prop;
1427         }
1428
1429         return 0;
1430 }
1431
1432 static int vop_create_crtc(struct vop *vop)
1433 {
1434         struct device *dev = vop->dev;
1435         struct drm_device *drm_dev = vop->drm_dev;
1436         struct drm_plane *primary = NULL, *cursor = NULL, *plane, *tmp;
1437         struct drm_crtc *crtc = &vop->crtc;
1438         struct device_node *port;
1439         int ret;
1440         int i;
1441
1442         /*
1443          * Create drm_plane for primary and cursor planes first, since we need
1444          * to pass them to drm_crtc_init_with_planes, which sets the
1445          * "possible_crtcs" to the newly initialized crtc.
1446          */
1447         for (i = 0; i < vop->num_wins; i++) {
1448                 struct vop_win *win = &vop->win[i];
1449
1450                 if (win->type != DRM_PLANE_TYPE_PRIMARY &&
1451                     win->type != DRM_PLANE_TYPE_CURSOR)
1452                         continue;
1453
1454                 ret = vop_plane_init(vop, win, 0);
1455                 if (ret)
1456                         goto err_cleanup_planes;
1457
1458                 plane = &win->base;
1459                 if (plane->type == DRM_PLANE_TYPE_PRIMARY)
1460                         primary = plane;
1461                 else if (plane->type == DRM_PLANE_TYPE_CURSOR)
1462                         cursor = plane;
1463
1464         }
1465
1466         ret = drm_crtc_init_with_planes(drm_dev, crtc, primary, cursor,
1467                                         &vop_crtc_funcs, NULL);
1468         if (ret)
1469                 goto err_cleanup_planes;
1470
1471         drm_crtc_helper_add(crtc, &vop_crtc_helper_funcs);
1472
1473         /*
1474          * Create drm_planes for overlay windows with possible_crtcs restricted
1475          * to the newly created crtc.
1476          */
1477         for (i = 0; i < vop->num_wins; i++) {
1478                 struct vop_win *win = &vop->win[i];
1479                 unsigned long possible_crtcs = 1 << drm_crtc_index(crtc);
1480
1481                 if (win->type != DRM_PLANE_TYPE_OVERLAY)
1482                         continue;
1483
1484                 ret = vop_plane_init(vop, win, possible_crtcs);
1485                 if (ret)
1486                         goto err_cleanup_crtc;
1487         }
1488
1489         port = of_get_child_by_name(dev->of_node, "port");
1490         if (!port) {
1491                 DRM_ERROR("no port node found in %s\n",
1492                           dev->of_node->full_name);
1493                 ret = -ENOENT;
1494                 goto err_cleanup_crtc;
1495         }
1496
1497         init_completion(&vop->dsp_hold_completion);
1498         init_completion(&vop->wait_update_complete);
1499         crtc->port = port;
1500         rockchip_register_crtc_funcs(crtc, &private_crtc_funcs);
1501
1502         return 0;
1503
1504 err_cleanup_crtc:
1505         drm_crtc_cleanup(crtc);
1506 err_cleanup_planes:
1507         list_for_each_entry_safe(plane, tmp, &drm_dev->mode_config.plane_list,
1508                                  head)
1509                 drm_plane_cleanup(plane);
1510         return ret;
1511 }
1512
1513 static void vop_destroy_crtc(struct vop *vop)
1514 {
1515         struct drm_crtc *crtc = &vop->crtc;
1516         struct drm_device *drm_dev = vop->drm_dev;
1517         struct drm_plane *plane, *tmp;
1518
1519         rockchip_unregister_crtc_funcs(crtc);
1520         of_node_put(crtc->port);
1521
1522         /*
1523          * We need to cleanup the planes now.  Why?
1524          *
1525          * The planes are "&vop->win[i].base".  That means the memory is
1526          * all part of the big "struct vop" chunk of memory.  That memory
1527          * was devm allocated and associated with this component.  We need to
1528          * free it ourselves before vop_unbind() finishes.
1529          */
1530         list_for_each_entry_safe(plane, tmp, &drm_dev->mode_config.plane_list,
1531                                  head)
1532                 vop_plane_destroy(plane);
1533
1534         /*
1535          * Destroy CRTC after vop_plane_destroy() since vop_disable_plane()
1536          * references the CRTC.
1537          */
1538         drm_crtc_cleanup(crtc);
1539 }
1540
1541 /*
1542  * Initialize the vop->win array elements.
1543  */
1544 static int vop_win_init(struct vop *vop)
1545 {
1546         const struct vop_data *vop_data = vop->data;
1547         unsigned int i, j;
1548         unsigned int num_wins = 0;
1549         struct drm_property *prop;
1550
1551         for (i = 0; i < vop_data->win_size; i++) {
1552                 struct vop_win *vop_win = &vop->win[num_wins];
1553                 const struct vop_win_data *win_data = &vop_data->win[i];
1554
1555                 if (!win_data->phy)
1556                         continue;
1557
1558                 vop_win->phy = win_data->phy;
1559                 vop_win->offset = win_data->base;
1560                 vop_win->type = win_data->type;
1561                 vop_win->data_formats = win_data->phy->data_formats;
1562                 vop_win->nformats = win_data->phy->nformats;
1563                 vop_win->vop = vop;
1564                 vop_win->win_id = i;
1565                 vop_win->area_id = 0;
1566                 num_wins++;
1567
1568                 for (j = 0; j < win_data->area_size; j++) {
1569                         struct vop_win *vop_area = &vop->win[num_wins];
1570                         const struct vop_win_phy *area = win_data->area[j];
1571
1572                         vop_area->parent = vop_win;
1573                         vop_area->offset = vop_win->offset;
1574                         vop_area->phy = area;
1575                         vop_area->type = DRM_PLANE_TYPE_OVERLAY;
1576                         vop_area->data_formats = vop_win->data_formats;
1577                         vop_area->nformats = vop_win->nformats;
1578                         vop_area->vop = vop;
1579                         vop_area->win_id = i;
1580                         vop_area->area_id = j;
1581                         num_wins++;
1582                 }
1583         }
1584
1585         vop->num_wins = num_wins;
1586
1587         prop = drm_property_create_range(vop->drm_dev, DRM_MODE_PROP_ATOMIC,
1588                                          "ZPOS", 0, vop->data->win_size);
1589         if (!prop) {
1590                 DRM_ERROR("failed to create zpos property\n");
1591                 return -EINVAL;
1592         }
1593         vop->plane_zpos_prop = prop;
1594
1595         return 0;
1596 }
1597
1598 static int vop_bind(struct device *dev, struct device *master, void *data)
1599 {
1600         struct platform_device *pdev = to_platform_device(dev);
1601         const struct vop_data *vop_data;
1602         struct drm_device *drm_dev = data;
1603         struct vop *vop;
1604         struct resource *res;
1605         size_t alloc_size;
1606         int ret, irq, i;
1607         int num_wins = 0;
1608
1609         vop_data = of_device_get_match_data(dev);
1610         if (!vop_data)
1611                 return -ENODEV;
1612
1613         for (i = 0; i < vop_data->win_size; i++) {
1614                 const struct vop_win_data *win_data = &vop_data->win[i];
1615
1616                 num_wins += win_data->area_size + 1;
1617         }
1618
1619         /* Allocate vop struct and its vop_win array */
1620         alloc_size = sizeof(*vop) + sizeof(*vop->win) * num_wins;
1621         vop = devm_kzalloc(dev, alloc_size, GFP_KERNEL);
1622         if (!vop)
1623                 return -ENOMEM;
1624
1625         vop->dev = dev;
1626         vop->data = vop_data;
1627         vop->drm_dev = drm_dev;
1628         vop->num_wins = num_wins;
1629         dev_set_drvdata(dev, vop);
1630
1631         ret = vop_win_init(vop);
1632         if (ret)
1633                 return ret;
1634
1635         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1636         vop->len = resource_size(res);
1637         vop->regs = devm_ioremap_resource(dev, res);
1638         if (IS_ERR(vop->regs))
1639                 return PTR_ERR(vop->regs);
1640
1641         vop->regsbak = devm_kzalloc(dev, vop->len, GFP_KERNEL);
1642         if (!vop->regsbak)
1643                 return -ENOMEM;
1644
1645         vop->hclk = devm_clk_get(vop->dev, "hclk_vop");
1646         if (IS_ERR(vop->hclk)) {
1647                 dev_err(vop->dev, "failed to get hclk source\n");
1648                 return PTR_ERR(vop->hclk);
1649         }
1650         vop->aclk = devm_clk_get(vop->dev, "aclk_vop");
1651         if (IS_ERR(vop->aclk)) {
1652                 dev_err(vop->dev, "failed to get aclk source\n");
1653                 return PTR_ERR(vop->aclk);
1654         }
1655         vop->dclk = devm_clk_get(vop->dev, "dclk_vop");
1656         if (IS_ERR(vop->dclk)) {
1657                 dev_err(vop->dev, "failed to get dclk source\n");
1658                 return PTR_ERR(vop->dclk);
1659         }
1660
1661         irq = platform_get_irq(pdev, 0);
1662         if (irq < 0) {
1663                 dev_err(dev, "cannot find irq for vop\n");
1664                 return irq;
1665         }
1666         vop->irq = (unsigned int)irq;
1667
1668         spin_lock_init(&vop->reg_lock);
1669         spin_lock_init(&vop->irq_lock);
1670
1671         mutex_init(&vop->vsync_mutex);
1672
1673         ret = devm_request_irq(dev, vop->irq, vop_isr,
1674                                IRQF_SHARED, dev_name(dev), vop);
1675         if (ret)
1676                 return ret;
1677
1678         /* IRQ is initially disabled; it gets enabled in power_on */
1679         disable_irq(vop->irq);
1680
1681         ret = vop_create_crtc(vop);
1682         if (ret)
1683                 return ret;
1684
1685         pm_runtime_enable(&pdev->dev);
1686         return 0;
1687 }
1688
1689 static void vop_unbind(struct device *dev, struct device *master, void *data)
1690 {
1691         struct vop *vop = dev_get_drvdata(dev);
1692
1693         pm_runtime_disable(dev);
1694         vop_destroy_crtc(vop);
1695 }
1696
1697 const struct component_ops vop_component_ops = {
1698         .bind = vop_bind,
1699         .unbind = vop_unbind,
1700 };
1701 EXPORT_SYMBOL_GPL(vop_component_ops);