2 * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
3 * Author:Mark Yao <mark.yao@rock-chips.com>
5 * This software is licensed under the terms of the GNU General Public
6 * License version 2, as published by the Free Software Foundation, and
7 * may be copied, distributed, and modified under those terms.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
17 #include <drm/drm_atomic.h>
18 #include <drm/drm_crtc.h>
19 #include <drm/drm_crtc_helper.h>
20 #include <drm/drm_plane_helper.h>
22 #include <linux/kernel.h>
23 #include <linux/module.h>
24 #include <linux/platform_device.h>
25 #include <linux/clk.h>
27 #include <linux/of_device.h>
28 #include <linux/pm_runtime.h>
29 #include <linux/component.h>
31 #include <linux/reset.h>
32 #include <linux/delay.h>
33 #include <linux/sort.h>
35 #include "rockchip_drm_drv.h"
36 #include "rockchip_drm_gem.h"
37 #include "rockchip_drm_fb.h"
38 #include "rockchip_drm_vop.h"
40 #define VOP_REG_SUPPORT(vop, reg) \
41 (!reg.major || (reg.major == VOP_MAJOR(vop->data->version) && \
42 reg.begin_minor <= VOP_MINOR(vop->data->version) && \
43 reg.end_minor >= VOP_MINOR(vop->data->version) && \
46 #define VOP_WIN_SUPPORT(vop, win, name) \
47 VOP_REG_SUPPORT(vop, win->phy->name)
49 #define VOP_CTRL_SUPPORT(vop, win, name) \
50 VOP_REG_SUPPORT(vop, vop->data->ctrl->name)
52 #define VOP_INTR_SUPPORT(vop, win, name) \
53 VOP_REG_SUPPORT(vop, vop->data->intr->name)
55 #define __REG_SET(x, off, mask, shift, v, write_mask, relaxed) \
56 vop_mask_write(x, off, mask, shift, v, write_mask, relaxed)
58 #define _REG_SET(vop, name, off, reg, mask, v, relaxed) \
60 if (VOP_REG_SUPPORT(vop, reg)) \
61 __REG_SET(vop, off + reg.offset, mask, reg.shift, \
62 v, reg.write_mask, relaxed); \
64 dev_dbg(vop->dev, "Warning: not support "#name"\n"); \
67 #define REG_SET(x, name, off, reg, v, relaxed) \
68 _REG_SET(x, name, off, reg, reg.mask, v, relaxed)
69 #define REG_SET_MASK(x, name, off, reg, mask, v, relaxed) \
70 _REG_SET(x, name, off, reg, reg.mask & mask, v, relaxed)
72 #define VOP_WIN_SET(x, win, name, v) \
73 REG_SET(x, name, win->offset, VOP_WIN_NAME(win, name), v, true)
74 #define VOP_SCL_SET(x, win, name, v) \
75 REG_SET(x, name, win->offset, win->phy->scl->name, v, true)
76 #define VOP_SCL_SET_EXT(x, win, name, v) \
77 REG_SET(x, name, win->offset, win->phy->scl->ext->name, v, true)
79 #define VOP_CTRL_SET(x, name, v) \
80 REG_SET(x, name, 0, (x)->data->ctrl->name, v, false)
82 #define VOP_INTR_GET(vop, name) \
83 vop_read_reg(vop, 0, &vop->data->ctrl->name)
85 #define VOP_INTR_SET(vop, name, mask, v) \
86 REG_SET_MASK(vop, name, 0, vop->data->intr->name, \
89 #define VOP_INTR_SET_TYPE(vop, name, type, v) \
91 int i, reg = 0, mask = 0; \
92 for (i = 0; i < vop->data->intr->nintrs; i++) { \
93 if (vop->data->intr->intrs[i] & type) { \
98 VOP_INTR_SET(vop, name, mask, reg); \
100 #define VOP_INTR_GET_TYPE(vop, name, type) \
101 vop_get_intr_type(vop, &vop->data->intr->name, type)
103 #define VOP_CTRL_GET(x, name) \
104 vop_read_reg(x, 0, vop->data->ctrl->name)
106 #define VOP_WIN_GET(x, win, name) \
107 vop_read_reg(x, win->offset, &VOP_WIN_NAME(win, name))
109 #define VOP_WIN_NAME(win, name) \
110 (vop_get_win_phy(win, &win->phy->name)->name)
112 #define VOP_WIN_GET_YRGBADDR(vop, win) \
113 vop_readl(vop, win->offset + VOP_WIN_NAME(win, yrgb_mst).offset)
115 #define to_vop(x) container_of(x, struct vop, crtc)
116 #define to_vop_win(x) container_of(x, struct vop_win, base)
117 #define to_vop_plane_state(x) container_of(x, struct vop_plane_state, base)
124 struct vop_plane_state {
125 struct drm_plane_state base;
129 struct drm_rect dest;
135 struct vop_win *parent;
136 struct drm_plane base;
141 enum drm_plane_type type;
142 const struct vop_win_phy *phy;
143 const uint32_t *data_formats;
147 struct drm_property *rotation_prop;
148 struct vop_plane_state state;
152 struct drm_crtc crtc;
154 struct drm_device *drm_dev;
155 struct drm_property *plane_zpos_prop;
158 /* mutex vsync_ work */
159 struct mutex vsync_mutex;
160 bool vsync_work_pending;
161 struct completion dsp_hold_completion;
162 struct completion wait_update_complete;
163 struct drm_pending_vblank_event *event;
165 const struct vop_data *data;
171 /* physical map length of vop register */
174 /* one time only one process allowed to config the register */
176 /* lock vop irq reg */
185 /* vop share memory frequency */
189 struct reset_control *dclk_rst;
191 struct vop_win win[];
194 static inline void vop_writel(struct vop *vop, uint32_t offset, uint32_t v)
196 writel(v, vop->regs + offset);
197 vop->regsbak[offset >> 2] = v;
200 static inline uint32_t vop_readl(struct vop *vop, uint32_t offset)
202 return readl(vop->regs + offset);
205 static inline uint32_t vop_read_reg(struct vop *vop, uint32_t base,
206 const struct vop_reg *reg)
208 return (vop_readl(vop, base + reg->offset) >> reg->shift) & reg->mask;
211 static inline void vop_mask_write(struct vop *vop, uint32_t offset,
212 uint32_t mask, uint32_t shift, uint32_t v,
213 bool write_mask, bool relaxed)
219 v = ((v & mask) << shift) | (mask << (shift + 16));
221 uint32_t cached_val = vop->regsbak[offset >> 2];
223 v = (cached_val & ~(mask << shift)) | ((v & mask) << shift);
224 vop->regsbak[offset >> 2] = v;
228 writel_relaxed(v, vop->regs + offset);
230 writel(v, vop->regs + offset);
233 static inline const struct vop_win_phy *
234 vop_get_win_phy(struct vop_win *win, const struct vop_reg *reg)
236 if (!reg->mask && win->parent)
237 return win->parent->phy;
242 static inline uint32_t vop_get_intr_type(struct vop *vop,
243 const struct vop_reg *reg, int type)
246 uint32_t regs = vop_read_reg(vop, 0, reg);
248 for (i = 0; i < vop->data->intr->nintrs; i++) {
249 if ((type & vop->data->intr->intrs[i]) && (regs & 1 << i))
250 ret |= vop->data->intr->intrs[i];
256 static inline void vop_cfg_done(struct vop *vop)
258 VOP_CTRL_SET(vop, cfg_done, 1);
261 static bool has_rb_swapped(uint32_t format)
264 case DRM_FORMAT_XBGR8888:
265 case DRM_FORMAT_ABGR8888:
266 case DRM_FORMAT_BGR888:
267 case DRM_FORMAT_BGR565:
274 static enum vop_data_format vop_convert_format(uint32_t format)
277 case DRM_FORMAT_XRGB8888:
278 case DRM_FORMAT_ARGB8888:
279 case DRM_FORMAT_XBGR8888:
280 case DRM_FORMAT_ABGR8888:
281 return VOP_FMT_ARGB8888;
282 case DRM_FORMAT_RGB888:
283 case DRM_FORMAT_BGR888:
284 return VOP_FMT_RGB888;
285 case DRM_FORMAT_RGB565:
286 case DRM_FORMAT_BGR565:
287 return VOP_FMT_RGB565;
288 case DRM_FORMAT_NV12:
289 return VOP_FMT_YUV420SP;
290 case DRM_FORMAT_NV16:
291 return VOP_FMT_YUV422SP;
292 case DRM_FORMAT_NV24:
293 return VOP_FMT_YUV444SP;
295 DRM_ERROR("unsupport format[%08x]\n", format);
300 static bool is_yuv_support(uint32_t format)
303 case DRM_FORMAT_NV12:
304 case DRM_FORMAT_NV16:
305 case DRM_FORMAT_NV24:
312 static bool is_alpha_support(uint32_t format)
315 case DRM_FORMAT_ARGB8888:
316 case DRM_FORMAT_ABGR8888:
323 static uint16_t scl_vop_cal_scale(enum scale_mode mode, uint32_t src,
324 uint32_t dst, bool is_horizontal,
325 int vsu_mode, int *vskiplines)
327 uint16_t val = 1 << SCL_FT_DEFAULT_FIXPOINT_SHIFT;
330 if (mode == SCALE_UP)
331 val = GET_SCL_FT_BIC(src, dst);
332 else if (mode == SCALE_DOWN)
333 val = GET_SCL_FT_BILI_DN(src, dst);
335 if (mode == SCALE_UP) {
336 if (vsu_mode == SCALE_UP_BIL)
337 val = GET_SCL_FT_BILI_UP(src, dst);
339 val = GET_SCL_FT_BIC(src, dst);
340 } else if (mode == SCALE_DOWN) {
342 *vskiplines = scl_get_vskiplines(src, dst);
343 val = scl_get_bili_dn_vskip(src, dst,
346 val = GET_SCL_FT_BILI_DN(src, dst);
354 static void scl_vop_cal_scl_fac(struct vop *vop, struct vop_win *win,
355 uint32_t src_w, uint32_t src_h, uint32_t dst_w,
356 uint32_t dst_h, uint32_t pixel_format)
358 uint16_t yrgb_hor_scl_mode, yrgb_ver_scl_mode;
359 uint16_t cbcr_hor_scl_mode = SCALE_NONE;
360 uint16_t cbcr_ver_scl_mode = SCALE_NONE;
361 int hsub = drm_format_horz_chroma_subsampling(pixel_format);
362 int vsub = drm_format_vert_chroma_subsampling(pixel_format);
363 bool is_yuv = is_yuv_support(pixel_format);
364 uint16_t cbcr_src_w = src_w / hsub;
365 uint16_t cbcr_src_h = src_h / vsub;
375 DRM_ERROR("Maximum destination width (3840) exceeded\n");
379 if (!win->phy->scl->ext) {
380 VOP_SCL_SET(vop, win, scale_yrgb_x,
381 scl_cal_scale2(src_w, dst_w));
382 VOP_SCL_SET(vop, win, scale_yrgb_y,
383 scl_cal_scale2(src_h, dst_h));
385 VOP_SCL_SET(vop, win, scale_cbcr_x,
386 scl_cal_scale2(cbcr_src_w, dst_w));
387 VOP_SCL_SET(vop, win, scale_cbcr_y,
388 scl_cal_scale2(cbcr_src_h, dst_h));
393 yrgb_hor_scl_mode = scl_get_scl_mode(src_w, dst_w);
394 yrgb_ver_scl_mode = scl_get_scl_mode(src_h, dst_h);
397 cbcr_hor_scl_mode = scl_get_scl_mode(cbcr_src_w, dst_w);
398 cbcr_ver_scl_mode = scl_get_scl_mode(cbcr_src_h, dst_h);
399 if (cbcr_hor_scl_mode == SCALE_DOWN)
400 lb_mode = scl_vop_cal_lb_mode(dst_w, true);
402 lb_mode = scl_vop_cal_lb_mode(cbcr_src_w, true);
404 if (yrgb_hor_scl_mode == SCALE_DOWN)
405 lb_mode = scl_vop_cal_lb_mode(dst_w, false);
407 lb_mode = scl_vop_cal_lb_mode(src_w, false);
410 VOP_SCL_SET_EXT(vop, win, lb_mode, lb_mode);
411 if (lb_mode == LB_RGB_3840X2) {
412 if (yrgb_ver_scl_mode != SCALE_NONE) {
413 DRM_ERROR("ERROR : not allow yrgb ver scale\n");
416 if (cbcr_ver_scl_mode != SCALE_NONE) {
417 DRM_ERROR("ERROR : not allow cbcr ver scale\n");
420 vsu_mode = SCALE_UP_BIL;
421 } else if (lb_mode == LB_RGB_2560X4) {
422 vsu_mode = SCALE_UP_BIL;
424 vsu_mode = SCALE_UP_BIC;
427 val = scl_vop_cal_scale(yrgb_hor_scl_mode, src_w, dst_w,
429 VOP_SCL_SET(vop, win, scale_yrgb_x, val);
430 val = scl_vop_cal_scale(yrgb_ver_scl_mode, src_h, dst_h,
431 false, vsu_mode, &vskiplines);
432 VOP_SCL_SET(vop, win, scale_yrgb_y, val);
434 VOP_SCL_SET_EXT(vop, win, vsd_yrgb_gt4, vskiplines == 4);
435 VOP_SCL_SET_EXT(vop, win, vsd_yrgb_gt2, vskiplines == 2);
437 VOP_SCL_SET_EXT(vop, win, yrgb_hor_scl_mode, yrgb_hor_scl_mode);
438 VOP_SCL_SET_EXT(vop, win, yrgb_ver_scl_mode, yrgb_ver_scl_mode);
439 VOP_SCL_SET_EXT(vop, win, yrgb_hsd_mode, SCALE_DOWN_BIL);
440 VOP_SCL_SET_EXT(vop, win, yrgb_vsd_mode, SCALE_DOWN_BIL);
441 VOP_SCL_SET_EXT(vop, win, yrgb_vsu_mode, vsu_mode);
443 val = scl_vop_cal_scale(cbcr_hor_scl_mode, cbcr_src_w,
444 dst_w, true, 0, NULL);
445 VOP_SCL_SET(vop, win, scale_cbcr_x, val);
446 val = scl_vop_cal_scale(cbcr_ver_scl_mode, cbcr_src_h,
447 dst_h, false, vsu_mode, &vskiplines);
448 VOP_SCL_SET(vop, win, scale_cbcr_y, val);
450 VOP_SCL_SET_EXT(vop, win, vsd_cbcr_gt4, vskiplines == 4);
451 VOP_SCL_SET_EXT(vop, win, vsd_cbcr_gt2, vskiplines == 2);
452 VOP_SCL_SET_EXT(vop, win, cbcr_hor_scl_mode, cbcr_hor_scl_mode);
453 VOP_SCL_SET_EXT(vop, win, cbcr_ver_scl_mode, cbcr_ver_scl_mode);
454 VOP_SCL_SET_EXT(vop, win, cbcr_hsd_mode, SCALE_DOWN_BIL);
455 VOP_SCL_SET_EXT(vop, win, cbcr_vsd_mode, SCALE_DOWN_BIL);
456 VOP_SCL_SET_EXT(vop, win, cbcr_vsu_mode, vsu_mode);
460 static void vop_dsp_hold_valid_irq_enable(struct vop *vop)
464 if (WARN_ON(!vop->is_enabled))
467 spin_lock_irqsave(&vop->irq_lock, flags);
469 VOP_INTR_SET_TYPE(vop, enable, DSP_HOLD_VALID_INTR, 1);
471 spin_unlock_irqrestore(&vop->irq_lock, flags);
474 static void vop_dsp_hold_valid_irq_disable(struct vop *vop)
478 if (WARN_ON(!vop->is_enabled))
481 spin_lock_irqsave(&vop->irq_lock, flags);
483 VOP_INTR_SET_TYPE(vop, enable, DSP_HOLD_VALID_INTR, 0);
485 spin_unlock_irqrestore(&vop->irq_lock, flags);
488 static void vop_enable(struct drm_crtc *crtc)
490 struct vop *vop = to_vop(crtc);
496 ret = clk_enable(vop->hclk);
498 dev_err(vop->dev, "failed to enable hclk - %d\n", ret);
502 ret = clk_enable(vop->dclk);
504 dev_err(vop->dev, "failed to enable dclk - %d\n", ret);
505 goto err_disable_hclk;
508 ret = clk_enable(vop->aclk);
510 dev_err(vop->dev, "failed to enable aclk - %d\n", ret);
511 goto err_disable_dclk;
514 ret = pm_runtime_get_sync(vop->dev);
516 dev_err(vop->dev, "failed to get pm runtime: %d\n", ret);
521 * Slave iommu shares power, irq and clock with vop. It was associated
522 * automatically with this master device via common driver code.
523 * Now that we have enabled the clock we attach it to the shared drm
526 ret = rockchip_drm_dma_attach_device(vop->drm_dev, vop->dev);
528 dev_err(vop->dev, "failed to attach dma mapping, %d\n", ret);
529 goto err_disable_aclk;
532 memcpy(vop->regs, vop->regsbak, vop->len);
534 * At here, vop clock & iommu is enable, R/W vop regs would be safe.
536 vop->is_enabled = true;
538 spin_lock(&vop->reg_lock);
540 VOP_CTRL_SET(vop, standby, 0);
542 spin_unlock(&vop->reg_lock);
544 enable_irq(vop->irq);
546 drm_crtc_vblank_on(crtc);
551 clk_disable(vop->aclk);
553 clk_disable(vop->dclk);
555 clk_disable(vop->hclk);
558 static void vop_crtc_disable(struct drm_crtc *crtc)
560 struct vop *vop = to_vop(crtc);
563 if (!vop->is_enabled)
567 * We need to make sure that all windows are disabled before we
568 * disable that crtc. Otherwise we might try to scan from a destroyed
571 for (i = 0; i < vop->num_wins; i++) {
572 struct vop_win *win = &vop->win[i];
574 spin_lock(&vop->reg_lock);
575 VOP_WIN_SET(vop, win, enable, 0);
576 spin_unlock(&vop->reg_lock);
579 drm_crtc_vblank_off(crtc);
582 * Vop standby will take effect at end of current frame,
583 * if dsp hold valid irq happen, it means standby complete.
585 * we must wait standby complete when we want to disable aclk,
586 * if not, memory bus maybe dead.
588 reinit_completion(&vop->dsp_hold_completion);
589 vop_dsp_hold_valid_irq_enable(vop);
591 spin_lock(&vop->reg_lock);
593 VOP_CTRL_SET(vop, standby, 1);
595 spin_unlock(&vop->reg_lock);
597 wait_for_completion(&vop->dsp_hold_completion);
599 vop_dsp_hold_valid_irq_disable(vop);
601 disable_irq(vop->irq);
603 vop->is_enabled = false;
606 * vop standby complete, so iommu detach is safe.
608 rockchip_drm_dma_detach_device(vop->drm_dev, vop->dev);
610 pm_runtime_put(vop->dev);
611 clk_disable(vop->dclk);
612 clk_disable(vop->aclk);
613 clk_disable(vop->hclk);
616 static void vop_plane_destroy(struct drm_plane *plane)
618 drm_plane_cleanup(plane);
621 static int vop_plane_prepare_fb(struct drm_plane *plane,
622 const struct drm_plane_state *new_state)
624 if (plane->state->fb)
625 drm_framebuffer_reference(plane->state->fb);
630 static void vop_plane_cleanup_fb(struct drm_plane *plane,
631 const struct drm_plane_state *old_state)
634 drm_framebuffer_unreference(old_state->fb);
637 static int vop_plane_atomic_check(struct drm_plane *plane,
638 struct drm_plane_state *state)
640 struct drm_crtc *crtc = state->crtc;
641 struct drm_framebuffer *fb = state->fb;
642 struct vop_win *win = to_vop_win(plane);
643 struct vop_plane_state *vop_plane_state = to_vop_plane_state(state);
644 struct drm_crtc_state *crtc_state;
647 struct drm_rect *dest = &vop_plane_state->dest;
648 struct drm_rect *src = &vop_plane_state->src;
649 struct drm_rect clip;
650 int min_scale = win->phy->scl ? FRAC_16_16(1, 8) :
651 DRM_PLANE_HELPER_NO_SCALING;
652 int max_scale = win->phy->scl ? FRAC_16_16(8, 1) :
653 DRM_PLANE_HELPER_NO_SCALING;
655 crtc = crtc ? crtc : plane->state->crtc;
657 * Both crtc or plane->state->crtc can be null.
662 crtc_state = drm_atomic_get_crtc_state(state->state, crtc);
663 if (IS_ERR(crtc_state))
664 return PTR_ERR(crtc_state);
666 src->x1 = state->src_x;
667 src->y1 = state->src_y;
668 src->x2 = state->src_x + state->src_w;
669 src->y2 = state->src_y + state->src_h;
670 dest->x1 = state->crtc_x;
671 dest->y1 = state->crtc_y;
672 dest->x2 = state->crtc_x + state->crtc_w;
673 dest->y2 = state->crtc_y + state->crtc_h;
677 clip.x2 = crtc_state->mode.hdisplay;
678 clip.y2 = crtc_state->mode.vdisplay;
680 ret = drm_plane_helper_check_update(plane, crtc, state->fb,
684 true, true, &visible);
691 vop_plane_state->format = vop_convert_format(fb->pixel_format);
692 if (vop_plane_state->format < 0)
693 return vop_plane_state->format;
696 * Src.x1 can be odd when do clip, but yuv plane start point
697 * need align with 2 pixel.
699 if (is_yuv_support(fb->pixel_format) && ((src->x1 >> 16) % 2))
702 vop_plane_state->enable = true;
707 vop_plane_state->enable = false;
711 static void vop_plane_atomic_disable(struct drm_plane *plane,
712 struct drm_plane_state *old_state)
714 struct vop_plane_state *vop_plane_state = to_vop_plane_state(old_state);
715 struct vop_win *win = to_vop_win(plane);
716 struct vop *vop = to_vop(old_state->crtc);
718 if (!old_state->crtc)
721 spin_lock(&vop->reg_lock);
723 VOP_WIN_SET(vop, win, enable, 0);
725 spin_unlock(&vop->reg_lock);
727 vop_plane_state->enable = false;
730 static void vop_plane_atomic_update(struct drm_plane *plane,
731 struct drm_plane_state *old_state)
733 struct drm_plane_state *state = plane->state;
734 struct drm_crtc *crtc = state->crtc;
735 struct vop_win *win = to_vop_win(plane);
736 struct vop_plane_state *vop_plane_state = to_vop_plane_state(state);
737 struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc->state);
738 struct vop *vop = to_vop(state->crtc);
739 struct drm_framebuffer *fb = state->fb;
740 unsigned int actual_w, actual_h;
741 unsigned int dsp_stx, dsp_sty;
742 uint32_t act_info, dsp_info, dsp_st;
743 struct drm_rect *src = &vop_plane_state->src;
744 struct drm_rect *dest = &vop_plane_state->dest;
745 struct drm_gem_object *obj, *uv_obj;
746 struct rockchip_gem_object *rk_obj, *rk_uv_obj;
747 unsigned long offset;
749 int ymirror, xmirror;
754 * can't update plane when vop is disabled.
759 if (WARN_ON(!vop->is_enabled))
762 if (!vop_plane_state->enable) {
763 vop_plane_atomic_disable(plane, old_state);
767 obj = rockchip_fb_get_gem_obj(fb, 0);
768 rk_obj = to_rockchip_obj(obj);
770 actual_w = drm_rect_width(src) >> 16;
771 actual_h = drm_rect_height(src) >> 16;
772 act_info = (actual_h - 1) << 16 | ((actual_w - 1) & 0xffff);
774 dsp_info = (drm_rect_height(dest) - 1) << 16;
775 dsp_info |= (drm_rect_width(dest) - 1) & 0xffff;
777 dsp_stx = dest->x1 + crtc->mode.htotal - crtc->mode.hsync_start;
778 dsp_sty = dest->y1 + crtc->mode.vtotal - crtc->mode.vsync_start;
779 dsp_st = dsp_sty << 16 | (dsp_stx & 0xffff);
781 offset = (src->x1 >> 16) * drm_format_plane_cpp(fb->pixel_format, 0);
782 if (state->rotation & BIT(DRM_REFLECT_Y))
783 offset += ((src->y2 >> 16) - 1) * fb->pitches[0];
785 offset += (src->y1 >> 16) * fb->pitches[0];
786 vop_plane_state->yrgb_mst = rk_obj->dma_addr + offset + fb->offsets[0];
788 ymirror = !!(state->rotation & BIT(DRM_REFLECT_Y));
789 xmirror = !!(state->rotation & BIT(DRM_REFLECT_X));
791 spin_lock(&vop->reg_lock);
793 VOP_WIN_SET(vop, win, xmirror, xmirror);
794 VOP_WIN_SET(vop, win, ymirror, ymirror);
795 VOP_WIN_SET(vop, win, format, vop_plane_state->format);
796 VOP_WIN_SET(vop, win, yrgb_vir, fb->pitches[0] >> 2);
797 VOP_WIN_SET(vop, win, yrgb_mst, vop_plane_state->yrgb_mst);
798 if (is_yuv_support(fb->pixel_format)) {
799 int hsub = drm_format_horz_chroma_subsampling(fb->pixel_format);
800 int vsub = drm_format_vert_chroma_subsampling(fb->pixel_format);
801 int bpp = drm_format_plane_cpp(fb->pixel_format, 1);
803 uv_obj = rockchip_fb_get_gem_obj(fb, 1);
804 rk_uv_obj = to_rockchip_obj(uv_obj);
806 offset = (src->x1 >> 16) * bpp / hsub;
807 offset += (src->y1 >> 16) * fb->pitches[1] / vsub;
809 dma_addr = rk_uv_obj->dma_addr + offset + fb->offsets[1];
810 VOP_WIN_SET(vop, win, uv_vir, fb->pitches[1] >> 2);
811 VOP_WIN_SET(vop, win, uv_mst, dma_addr);
814 scl_vop_cal_scl_fac(vop, win, actual_w, actual_h,
815 drm_rect_width(dest), drm_rect_height(dest),
818 VOP_WIN_SET(vop, win, act_info, act_info);
819 VOP_WIN_SET(vop, win, dsp_info, dsp_info);
820 VOP_WIN_SET(vop, win, dsp_st, dsp_st);
822 rb_swap = has_rb_swapped(fb->pixel_format);
823 VOP_WIN_SET(vop, win, rb_swap, rb_swap);
825 if (is_alpha_support(fb->pixel_format) &&
826 (s->dsp_layer_sel & 0x3) != win->win_id) {
827 VOP_WIN_SET(vop, win, dst_alpha_ctl,
828 DST_FACTOR_M0(ALPHA_SRC_INVERSE));
829 val = SRC_ALPHA_EN(1) | SRC_COLOR_M0(ALPHA_SRC_PRE_MUL) |
830 SRC_ALPHA_M0(ALPHA_STRAIGHT) |
831 SRC_BLEND_M0(ALPHA_PER_PIX) |
832 SRC_ALPHA_CAL_M0(ALPHA_NO_SATURATION) |
833 SRC_FACTOR_M0(ALPHA_ONE);
834 VOP_WIN_SET(vop, win, src_alpha_ctl, val);
835 VOP_WIN_SET(vop, win, alpha_mode, 1);
836 VOP_WIN_SET(vop, win, alpha_en, 1);
838 VOP_WIN_SET(vop, win, src_alpha_ctl, SRC_ALPHA_EN(0));
839 VOP_WIN_SET(vop, win, alpha_en, 0);
842 VOP_WIN_SET(vop, win, enable, 1);
843 spin_unlock(&vop->reg_lock);
846 static const struct drm_plane_helper_funcs plane_helper_funcs = {
847 .prepare_fb = vop_plane_prepare_fb,
848 .cleanup_fb = vop_plane_cleanup_fb,
849 .atomic_check = vop_plane_atomic_check,
850 .atomic_update = vop_plane_atomic_update,
851 .atomic_disable = vop_plane_atomic_disable,
854 void vop_atomic_plane_reset(struct drm_plane *plane)
856 struct vop_win *win = to_vop_win(plane);
857 struct vop_plane_state *vop_plane_state =
858 to_vop_plane_state(plane->state);
860 if (plane->state && plane->state->fb)
861 drm_framebuffer_unreference(plane->state->fb);
863 kfree(vop_plane_state);
864 vop_plane_state = kzalloc(sizeof(*vop_plane_state), GFP_KERNEL);
865 if (!vop_plane_state)
868 vop_plane_state->zpos = win->win_id;
869 plane->state = &vop_plane_state->base;
870 plane->state->plane = plane;
873 struct drm_plane_state *
874 vop_atomic_plane_duplicate_state(struct drm_plane *plane)
876 struct vop_plane_state *old_vop_plane_state;
877 struct vop_plane_state *vop_plane_state;
879 if (WARN_ON(!plane->state))
882 old_vop_plane_state = to_vop_plane_state(plane->state);
883 vop_plane_state = kmemdup(old_vop_plane_state,
884 sizeof(*vop_plane_state), GFP_KERNEL);
885 if (!vop_plane_state)
888 __drm_atomic_helper_plane_duplicate_state(plane,
889 &vop_plane_state->base);
891 return &vop_plane_state->base;
894 static void vop_atomic_plane_destroy_state(struct drm_plane *plane,
895 struct drm_plane_state *state)
897 struct vop_plane_state *vop_state = to_vop_plane_state(state);
899 __drm_atomic_helper_plane_destroy_state(plane, state);
904 static int vop_atomic_plane_set_property(struct drm_plane *plane,
905 struct drm_plane_state *state,
906 struct drm_property *property,
909 struct vop_win *win = to_vop_win(plane);
910 struct vop_plane_state *plane_state = to_vop_plane_state(state);
912 if (property == win->vop->plane_zpos_prop) {
913 plane_state->zpos = val;
917 if (property == win->rotation_prop) {
918 state->rotation = val;
922 DRM_ERROR("failed to set vop plane property\n");
926 static int vop_atomic_plane_get_property(struct drm_plane *plane,
927 const struct drm_plane_state *state,
928 struct drm_property *property,
931 struct vop_win *win = to_vop_win(plane);
932 struct vop_plane_state *plane_state = to_vop_plane_state(state);
934 if (property == win->vop->plane_zpos_prop) {
935 *val = plane_state->zpos;
939 if (property == win->rotation_prop) {
940 *val = state->rotation;
944 DRM_ERROR("failed to get vop plane property\n");
948 static const struct drm_plane_funcs vop_plane_funcs = {
949 .update_plane = drm_atomic_helper_update_plane,
950 .disable_plane = drm_atomic_helper_disable_plane,
951 .destroy = vop_plane_destroy,
952 .reset = vop_atomic_plane_reset,
953 .atomic_duplicate_state = vop_atomic_plane_duplicate_state,
954 .atomic_destroy_state = vop_atomic_plane_destroy_state,
955 .atomic_set_property = vop_atomic_plane_set_property,
956 .atomic_get_property = vop_atomic_plane_get_property,
959 static int vop_crtc_enable_vblank(struct drm_crtc *crtc)
961 struct vop *vop = to_vop(crtc);
964 if (WARN_ON(!vop->is_enabled))
967 spin_lock_irqsave(&vop->irq_lock, flags);
969 VOP_INTR_SET_TYPE(vop, enable, FS_INTR, 1);
971 spin_unlock_irqrestore(&vop->irq_lock, flags);
976 static void vop_crtc_disable_vblank(struct drm_crtc *crtc)
978 struct vop *vop = to_vop(crtc);
981 if (WARN_ON(!vop->is_enabled))
984 spin_lock_irqsave(&vop->irq_lock, flags);
986 VOP_INTR_SET_TYPE(vop, enable, FS_INTR, 0);
988 spin_unlock_irqrestore(&vop->irq_lock, flags);
991 static void vop_crtc_wait_for_update(struct drm_crtc *crtc)
993 struct vop *vop = to_vop(crtc);
995 reinit_completion(&vop->wait_update_complete);
996 WARN_ON(!wait_for_completion_timeout(&vop->wait_update_complete, 100));
999 static void vop_crtc_cancel_pending_vblank(struct drm_crtc *crtc,
1000 struct drm_file *file_priv)
1002 struct drm_device *drm = crtc->dev;
1003 struct vop *vop = to_vop(crtc);
1004 struct drm_pending_vblank_event *e;
1005 unsigned long flags;
1007 spin_lock_irqsave(&drm->event_lock, flags);
1009 if (e && e->base.file_priv == file_priv) {
1012 e->base.destroy(&e->base);
1013 file_priv->event_space += sizeof(e->event);
1015 spin_unlock_irqrestore(&drm->event_lock, flags);
1018 static const struct rockchip_crtc_funcs private_crtc_funcs = {
1019 .enable_vblank = vop_crtc_enable_vblank,
1020 .disable_vblank = vop_crtc_disable_vblank,
1021 .wait_for_update = vop_crtc_wait_for_update,
1022 .cancel_pending_vblank = vop_crtc_cancel_pending_vblank,
1025 static bool vop_crtc_mode_fixup(struct drm_crtc *crtc,
1026 const struct drm_display_mode *mode,
1027 struct drm_display_mode *adjusted_mode)
1029 struct vop *vop = to_vop(crtc);
1031 adjusted_mode->clock =
1032 clk_round_rate(vop->dclk, mode->clock * 1000) / 1000;
1037 static void vop_crtc_enable(struct drm_crtc *crtc)
1039 struct vop *vop = to_vop(crtc);
1040 const struct vop_data *vop_data = vop->data;
1041 struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc->state);
1042 struct drm_display_mode *adjusted_mode = &crtc->state->adjusted_mode;
1043 u16 hsync_len = adjusted_mode->hsync_end - adjusted_mode->hsync_start;
1044 u16 hdisplay = adjusted_mode->hdisplay;
1045 u16 htotal = adjusted_mode->htotal;
1046 u16 hact_st = adjusted_mode->htotal - adjusted_mode->hsync_start;
1047 u16 hact_end = hact_st + hdisplay;
1048 u16 vdisplay = adjusted_mode->vdisplay;
1049 u16 vtotal = adjusted_mode->vtotal;
1050 u16 vsync_len = adjusted_mode->vsync_end - adjusted_mode->vsync_start;
1051 u16 vact_st = adjusted_mode->vtotal - adjusted_mode->vsync_start;
1052 u16 vact_end = vact_st + vdisplay;
1057 * If dclk rate is zero, mean that scanout is stop,
1058 * we don't need wait any more.
1060 if (clk_get_rate(vop->dclk)) {
1062 * Rk3288 vop timing register is immediately, when configure
1063 * display timing on display time, may cause tearing.
1065 * Vop standby will take effect at end of current frame,
1066 * if dsp hold valid irq happen, it means standby complete.
1069 * standby and wait complete --> |----
1072 * |---> dsp hold irq
1073 * configure display timing --> |
1075 * | new frame start.
1078 reinit_completion(&vop->dsp_hold_completion);
1079 vop_dsp_hold_valid_irq_enable(vop);
1081 spin_lock(&vop->reg_lock);
1083 VOP_CTRL_SET(vop, standby, 1);
1085 spin_unlock(&vop->reg_lock);
1087 wait_for_completion(&vop->dsp_hold_completion);
1089 vop_dsp_hold_valid_irq_disable(vop);
1093 val |= (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC) ? 0 : 1;
1094 val |= (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC) ? 0 : (1 << 1);
1095 VOP_CTRL_SET(vop, pin_pol, val);
1096 switch (s->output_type) {
1097 case DRM_MODE_CONNECTOR_LVDS:
1098 VOP_CTRL_SET(vop, rgb_en, 1);
1099 VOP_CTRL_SET(vop, rgb_pin_pol, val);
1101 case DRM_MODE_CONNECTOR_eDP:
1102 VOP_CTRL_SET(vop, edp_en, 1);
1103 VOP_CTRL_SET(vop, edp_pin_pol, val);
1105 case DRM_MODE_CONNECTOR_HDMIA:
1106 VOP_CTRL_SET(vop, hdmi_en, 1);
1107 VOP_CTRL_SET(vop, hdmi_pin_pol, val);
1109 case DRM_MODE_CONNECTOR_DSI:
1110 VOP_CTRL_SET(vop, mipi_en, 1);
1111 VOP_CTRL_SET(vop, mipi_pin_pol, val);
1114 DRM_ERROR("unsupport connector_type[%d]\n", s->output_type);
1117 if (s->output_mode == ROCKCHIP_OUT_MODE_AAAA &&
1118 !(vop_data->feature & VOP_FEATURE_OUTPUT_10BIT))
1119 s->output_mode = ROCKCHIP_OUT_MODE_P888;
1121 VOP_CTRL_SET(vop, out_mode, s->output_mode);
1123 VOP_CTRL_SET(vop, htotal_pw, (htotal << 16) | hsync_len);
1124 val = hact_st << 16;
1126 VOP_CTRL_SET(vop, hact_st_end, val);
1127 VOP_CTRL_SET(vop, hpost_st_end, val);
1129 VOP_CTRL_SET(vop, vtotal_pw, (vtotal << 16) | vsync_len);
1130 val = vact_st << 16;
1132 VOP_CTRL_SET(vop, vact_st_end, val);
1133 VOP_CTRL_SET(vop, vpost_st_end, val);
1135 clk_set_rate(vop->dclk, adjusted_mode->clock * 1000);
1137 VOP_CTRL_SET(vop, standby, 0);
1140 static int vop_zpos_cmp(const void *a, const void *b)
1142 struct vop_zpos *pa = (struct vop_zpos *)a;
1143 struct vop_zpos *pb = (struct vop_zpos *)b;
1145 return pa->zpos - pb->zpos;
1148 static int vop_crtc_atomic_check(struct drm_crtc *crtc,
1149 struct drm_crtc_state *crtc_state)
1151 struct drm_atomic_state *state = crtc_state->state;
1152 struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state);
1153 struct vop *vop = to_vop(crtc);
1154 const struct vop_data *vop_data = vop->data;
1155 struct drm_plane *plane;
1156 struct drm_plane_state *pstate;
1157 struct vop_plane_state *plane_state;
1158 struct vop_zpos *pzpos;
1159 int dsp_layer_sel = 0;
1160 int i, j, cnt = 0, ret = 0;
1162 pzpos = kmalloc_array(vop_data->win_size, sizeof(*pzpos), GFP_KERNEL);
1166 for (i = 0; i < vop_data->win_size; i++) {
1167 const struct vop_win_data *win_data = &vop_data->win[i];
1168 struct vop_win *win;
1173 for (j = 0; j < vop->num_wins; j++) {
1176 if (win->win_id == i && !win->area_id)
1179 if (WARN_ON(j >= vop->num_wins)) {
1181 goto err_free_pzpos;
1185 pstate = state->plane_states[drm_plane_index(plane)];
1187 * plane might not have changed, in which case take
1191 pstate = plane->state;
1192 plane_state = to_vop_plane_state(pstate);
1193 pzpos[cnt].zpos = plane_state->zpos;
1194 pzpos[cnt++].win_id = win->win_id;
1197 sort(pzpos, cnt, sizeof(pzpos[0]), vop_zpos_cmp, NULL);
1199 for (i = 0, cnt = 0; i < vop_data->win_size; i++) {
1200 const struct vop_win_data *win_data = &vop_data->win[i];
1203 if (win_data->phy) {
1204 struct vop_zpos *zpos = &pzpos[cnt++];
1206 dsp_layer_sel |= zpos->win_id << shift;
1208 dsp_layer_sel |= i << shift;
1212 s->dsp_layer_sel = dsp_layer_sel;
1219 static void vop_crtc_atomic_flush(struct drm_crtc *crtc,
1220 struct drm_crtc_state *old_crtc_state)
1222 struct rockchip_crtc_state *s =
1223 to_rockchip_crtc_state(crtc->state);
1224 struct vop *vop = to_vop(crtc);
1226 if (WARN_ON(!vop->is_enabled))
1229 spin_lock(&vop->reg_lock);
1231 VOP_CTRL_SET(vop, dsp_layer_sel, s->dsp_layer_sel);
1234 spin_unlock(&vop->reg_lock);
1237 static void vop_crtc_atomic_begin(struct drm_crtc *crtc,
1238 struct drm_crtc_state *old_crtc_state)
1240 struct vop *vop = to_vop(crtc);
1242 if (crtc->state->event) {
1243 WARN_ON(drm_crtc_vblank_get(crtc) != 0);
1245 vop->event = crtc->state->event;
1246 crtc->state->event = NULL;
1250 static const struct drm_crtc_helper_funcs vop_crtc_helper_funcs = {
1251 .enable = vop_crtc_enable,
1252 .disable = vop_crtc_disable,
1253 .mode_fixup = vop_crtc_mode_fixup,
1254 .atomic_check = vop_crtc_atomic_check,
1255 .atomic_flush = vop_crtc_atomic_flush,
1256 .atomic_begin = vop_crtc_atomic_begin,
1259 static void vop_crtc_destroy(struct drm_crtc *crtc)
1261 drm_crtc_cleanup(crtc);
1264 static struct drm_crtc_state *vop_crtc_duplicate_state(struct drm_crtc *crtc)
1266 struct rockchip_crtc_state *rockchip_state;
1268 rockchip_state = kzalloc(sizeof(*rockchip_state), GFP_KERNEL);
1269 if (!rockchip_state)
1272 __drm_atomic_helper_crtc_duplicate_state(crtc, &rockchip_state->base);
1273 return &rockchip_state->base;
1276 static void vop_crtc_destroy_state(struct drm_crtc *crtc,
1277 struct drm_crtc_state *state)
1279 struct rockchip_crtc_state *s = to_rockchip_crtc_state(state);
1281 __drm_atomic_helper_crtc_destroy_state(crtc, &s->base);
1285 static const struct drm_crtc_funcs vop_crtc_funcs = {
1286 .set_config = drm_atomic_helper_set_config,
1287 .page_flip = drm_atomic_helper_page_flip,
1288 .destroy = vop_crtc_destroy,
1289 .reset = drm_atomic_helper_crtc_reset,
1290 .atomic_duplicate_state = vop_crtc_duplicate_state,
1291 .atomic_destroy_state = vop_crtc_destroy_state,
1294 static bool vop_win_pending_is_complete(struct vop_win *vop_win)
1296 struct drm_plane *plane = &vop_win->base;
1297 struct vop_plane_state *state = to_vop_plane_state(plane->state);
1298 dma_addr_t yrgb_mst;
1301 return VOP_WIN_GET(vop_win->vop, vop_win, enable) == 0;
1303 yrgb_mst = VOP_WIN_GET_YRGBADDR(vop_win->vop, vop_win);
1305 return yrgb_mst == state->yrgb_mst;
1308 static void vop_handle_vblank(struct vop *vop)
1310 struct drm_device *drm = vop->drm_dev;
1311 struct drm_crtc *crtc = &vop->crtc;
1312 unsigned long flags;
1315 for (i = 0; i < vop->num_wins; i++) {
1316 if (!vop_win_pending_is_complete(&vop->win[i]))
1321 spin_lock_irqsave(&drm->event_lock, flags);
1323 drm_crtc_send_vblank_event(crtc, vop->event);
1324 drm_crtc_vblank_put(crtc);
1327 spin_unlock_irqrestore(&drm->event_lock, flags);
1329 if (!completion_done(&vop->wait_update_complete))
1330 complete(&vop->wait_update_complete);
1333 static irqreturn_t vop_isr(int irq, void *data)
1335 struct vop *vop = data;
1336 struct drm_crtc *crtc = &vop->crtc;
1337 uint32_t active_irqs;
1338 unsigned long flags;
1342 * interrupt register has interrupt status, enable and clear bits, we
1343 * must hold irq_lock to avoid a race with enable/disable_vblank().
1345 spin_lock_irqsave(&vop->irq_lock, flags);
1347 active_irqs = VOP_INTR_GET_TYPE(vop, status, INTR_MASK);
1348 /* Clear all active interrupt sources */
1350 VOP_INTR_SET_TYPE(vop, clear, active_irqs, 1);
1352 spin_unlock_irqrestore(&vop->irq_lock, flags);
1354 /* This is expected for vop iommu irqs, since the irq is shared */
1358 if (active_irqs & DSP_HOLD_VALID_INTR) {
1359 complete(&vop->dsp_hold_completion);
1360 active_irqs &= ~DSP_HOLD_VALID_INTR;
1364 if (active_irqs & FS_INTR) {
1365 drm_crtc_handle_vblank(crtc);
1366 vop_handle_vblank(vop);
1367 active_irqs &= ~FS_INTR;
1371 /* Unhandled irqs are spurious. */
1373 DRM_ERROR("Unknown VOP IRQs: %#02x\n", active_irqs);
1378 static int vop_plane_init(struct vop *vop, struct vop_win *win,
1379 unsigned long possible_crtcs)
1381 struct drm_plane *share = NULL;
1382 unsigned int rotations = 0;
1383 struct drm_property *prop;
1387 share = &win->parent->base;
1389 ret = drm_share_plane_init(vop->drm_dev, &win->base, share,
1390 possible_crtcs, &vop_plane_funcs,
1391 win->data_formats, win->nformats, win->type);
1393 DRM_ERROR("failed to initialize plane\n");
1396 drm_plane_helper_add(&win->base, &plane_helper_funcs);
1397 drm_object_attach_property(&win->base.base,
1398 vop->plane_zpos_prop, win->win_id);
1400 if (VOP_WIN_SUPPORT(vop, win, xmirror))
1401 rotations |= BIT(DRM_REFLECT_X);
1403 if (VOP_WIN_SUPPORT(vop, win, ymirror))
1404 rotations |= BIT(DRM_REFLECT_Y);
1407 rotations |= BIT(DRM_ROTATE_0);
1408 prop = drm_mode_create_rotation_property(vop->drm_dev,
1411 DRM_ERROR("failed to create zpos property\n");
1414 drm_object_attach_property(&win->base.base, prop,
1416 win->rotation_prop = prop;
1422 static int vop_create_crtc(struct vop *vop)
1424 struct device *dev = vop->dev;
1425 struct drm_device *drm_dev = vop->drm_dev;
1426 struct drm_plane *primary = NULL, *cursor = NULL, *plane, *tmp;
1427 struct drm_crtc *crtc = &vop->crtc;
1428 struct device_node *port;
1433 * Create drm_plane for primary and cursor planes first, since we need
1434 * to pass them to drm_crtc_init_with_planes, which sets the
1435 * "possible_crtcs" to the newly initialized crtc.
1437 for (i = 0; i < vop->num_wins; i++) {
1438 struct vop_win *win = &vop->win[i];
1440 if (win->type != DRM_PLANE_TYPE_PRIMARY &&
1441 win->type != DRM_PLANE_TYPE_CURSOR)
1444 ret = vop_plane_init(vop, win, 0);
1446 goto err_cleanup_planes;
1449 if (plane->type == DRM_PLANE_TYPE_PRIMARY)
1451 else if (plane->type == DRM_PLANE_TYPE_CURSOR)
1456 ret = drm_crtc_init_with_planes(drm_dev, crtc, primary, cursor,
1457 &vop_crtc_funcs, NULL);
1459 goto err_cleanup_planes;
1461 drm_crtc_helper_add(crtc, &vop_crtc_helper_funcs);
1464 * Create drm_planes for overlay windows with possible_crtcs restricted
1465 * to the newly created crtc.
1467 for (i = 0; i < vop->num_wins; i++) {
1468 struct vop_win *win = &vop->win[i];
1469 unsigned long possible_crtcs = 1 << drm_crtc_index(crtc);
1471 if (win->type != DRM_PLANE_TYPE_OVERLAY)
1474 ret = vop_plane_init(vop, win, possible_crtcs);
1476 goto err_cleanup_crtc;
1479 port = of_get_child_by_name(dev->of_node, "port");
1481 DRM_ERROR("no port node found in %s\n",
1482 dev->of_node->full_name);
1484 goto err_cleanup_crtc;
1487 init_completion(&vop->dsp_hold_completion);
1488 init_completion(&vop->wait_update_complete);
1490 rockchip_register_crtc_funcs(crtc, &private_crtc_funcs);
1495 drm_crtc_cleanup(crtc);
1497 list_for_each_entry_safe(plane, tmp, &drm_dev->mode_config.plane_list,
1499 drm_plane_cleanup(plane);
1503 static void vop_destroy_crtc(struct vop *vop)
1505 struct drm_crtc *crtc = &vop->crtc;
1506 struct drm_device *drm_dev = vop->drm_dev;
1507 struct drm_plane *plane, *tmp;
1509 rockchip_unregister_crtc_funcs(crtc);
1510 of_node_put(crtc->port);
1513 * We need to cleanup the planes now. Why?
1515 * The planes are "&vop->win[i].base". That means the memory is
1516 * all part of the big "struct vop" chunk of memory. That memory
1517 * was devm allocated and associated with this component. We need to
1518 * free it ourselves before vop_unbind() finishes.
1520 list_for_each_entry_safe(plane, tmp, &drm_dev->mode_config.plane_list,
1522 vop_plane_destroy(plane);
1525 * Destroy CRTC after vop_plane_destroy() since vop_disable_plane()
1526 * references the CRTC.
1528 drm_crtc_cleanup(crtc);
1531 static int vop_initial(struct vop *vop)
1533 struct reset_control *ahb_rst;
1536 vop->hclk = devm_clk_get(vop->dev, "hclk_vop");
1537 if (IS_ERR(vop->hclk)) {
1538 dev_err(vop->dev, "failed to get hclk source\n");
1539 return PTR_ERR(vop->hclk);
1541 vop->aclk = devm_clk_get(vop->dev, "aclk_vop");
1542 if (IS_ERR(vop->aclk)) {
1543 dev_err(vop->dev, "failed to get aclk source\n");
1544 return PTR_ERR(vop->aclk);
1546 vop->dclk = devm_clk_get(vop->dev, "dclk_vop");
1547 if (IS_ERR(vop->dclk)) {
1548 dev_err(vop->dev, "failed to get dclk source\n");
1549 return PTR_ERR(vop->dclk);
1552 ret = clk_prepare(vop->dclk);
1554 dev_err(vop->dev, "failed to prepare dclk\n");
1558 /* Enable both the hclk and aclk to setup the vop */
1559 ret = clk_prepare_enable(vop->hclk);
1561 dev_err(vop->dev, "failed to prepare/enable hclk\n");
1562 goto err_unprepare_dclk;
1565 ret = clk_prepare_enable(vop->aclk);
1567 dev_err(vop->dev, "failed to prepare/enable aclk\n");
1568 goto err_disable_hclk;
1572 * do hclk_reset, reset all vop registers.
1574 ahb_rst = devm_reset_control_get(vop->dev, "ahb");
1575 if (IS_ERR(ahb_rst)) {
1576 dev_err(vop->dev, "failed to get ahb reset\n");
1577 ret = PTR_ERR(ahb_rst);
1578 goto err_disable_aclk;
1580 reset_control_assert(ahb_rst);
1581 usleep_range(10, 20);
1582 reset_control_deassert(ahb_rst);
1584 memcpy(vop->regsbak, vop->regs, vop->len);
1586 VOP_CTRL_SET(vop, global_regdone_en, 1);
1588 for (i = 0; i < vop->num_wins; i++) {
1589 struct vop_win *win = &vop->win[i];
1591 VOP_WIN_SET(vop, win, gate, 1);
1597 * do dclk_reset, let all config take affect.
1599 vop->dclk_rst = devm_reset_control_get(vop->dev, "dclk");
1600 if (IS_ERR(vop->dclk_rst)) {
1601 dev_err(vop->dev, "failed to get dclk reset\n");
1602 ret = PTR_ERR(vop->dclk_rst);
1603 goto err_disable_aclk;
1605 reset_control_assert(vop->dclk_rst);
1606 usleep_range(10, 20);
1607 reset_control_deassert(vop->dclk_rst);
1609 clk_disable(vop->hclk);
1610 clk_disable(vop->aclk);
1612 vop->is_enabled = false;
1617 clk_disable_unprepare(vop->aclk);
1619 clk_disable_unprepare(vop->hclk);
1621 clk_unprepare(vop->dclk);
1626 * Initialize the vop->win array elements.
1628 static int vop_win_init(struct vop *vop)
1630 const struct vop_data *vop_data = vop->data;
1632 unsigned int num_wins = 0;
1633 struct drm_property *prop;
1635 for (i = 0; i < vop_data->win_size; i++) {
1636 struct vop_win *vop_win = &vop->win[num_wins];
1637 const struct vop_win_data *win_data = &vop_data->win[i];
1642 vop_win->phy = win_data->phy;
1643 vop_win->offset = win_data->base;
1644 vop_win->type = win_data->type;
1645 vop_win->data_formats = win_data->phy->data_formats;
1646 vop_win->nformats = win_data->phy->nformats;
1648 vop_win->win_id = i;
1649 vop_win->area_id = 0;
1652 for (j = 0; j < win_data->area_size; j++) {
1653 struct vop_win *vop_area = &vop->win[num_wins];
1654 const struct vop_win_phy *area = win_data->area[j];
1656 vop_area->parent = vop_win;
1657 vop_area->offset = vop_win->offset;
1658 vop_area->phy = area;
1659 vop_area->type = DRM_PLANE_TYPE_OVERLAY;
1660 vop_area->data_formats = vop_win->data_formats;
1661 vop_area->nformats = vop_win->nformats;
1662 vop_area->vop = vop;
1663 vop_area->win_id = i;
1664 vop_area->area_id = j;
1669 vop->num_wins = num_wins;
1671 prop = drm_property_create_range(vop->drm_dev, DRM_MODE_PROP_ATOMIC,
1672 "ZPOS", 0, vop->data->win_size);
1674 DRM_ERROR("failed to create zpos property\n");
1677 vop->plane_zpos_prop = prop;
1682 static int vop_bind(struct device *dev, struct device *master, void *data)
1684 struct platform_device *pdev = to_platform_device(dev);
1685 const struct vop_data *vop_data;
1686 struct drm_device *drm_dev = data;
1688 struct resource *res;
1693 vop_data = of_device_get_match_data(dev);
1697 for (i = 0; i < vop_data->win_size; i++) {
1698 const struct vop_win_data *win_data = &vop_data->win[i];
1700 num_wins += win_data->area_size + 1;
1703 /* Allocate vop struct and its vop_win array */
1704 alloc_size = sizeof(*vop) + sizeof(*vop->win) * num_wins;
1705 vop = devm_kzalloc(dev, alloc_size, GFP_KERNEL);
1710 vop->data = vop_data;
1711 vop->drm_dev = drm_dev;
1712 vop->num_wins = num_wins;
1713 dev_set_drvdata(dev, vop);
1715 ret = vop_win_init(vop);
1719 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1720 vop->len = resource_size(res);
1721 vop->regs = devm_ioremap_resource(dev, res);
1722 if (IS_ERR(vop->regs))
1723 return PTR_ERR(vop->regs);
1725 vop->regsbak = devm_kzalloc(dev, vop->len, GFP_KERNEL);
1729 ret = vop_initial(vop);
1731 dev_err(&pdev->dev, "cannot initial vop dev - err %d\n", ret);
1735 irq = platform_get_irq(pdev, 0);
1737 dev_err(dev, "cannot find irq for vop\n");
1740 vop->irq = (unsigned int)irq;
1742 spin_lock_init(&vop->reg_lock);
1743 spin_lock_init(&vop->irq_lock);
1745 mutex_init(&vop->vsync_mutex);
1747 ret = devm_request_irq(dev, vop->irq, vop_isr,
1748 IRQF_SHARED, dev_name(dev), vop);
1752 /* IRQ is initially disabled; it gets enabled in power_on */
1753 disable_irq(vop->irq);
1755 ret = vop_create_crtc(vop);
1759 pm_runtime_enable(&pdev->dev);
1763 static void vop_unbind(struct device *dev, struct device *master, void *data)
1765 struct vop *vop = dev_get_drvdata(dev);
1767 pm_runtime_disable(dev);
1768 vop_destroy_crtc(vop);
1771 const struct component_ops vop_component_ops = {
1773 .unbind = vop_unbind,
1775 EXPORT_SYMBOL_GPL(vop_component_ops);