drivers/gpu/drm/rockchip/rockchip_drm_vop.c

   1 /*
   2  * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
   3  * Author:Mark Yao <mark.yao@rock-chips.com>
   4  *
   5  * This software is licensed under the terms of the GNU General Public
   6  * License version 2, as published by the Free Software Foundation, and
   7  * may be copied, distributed, and modified under those terms.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  */
  14
  15 #include <drm/drm.h>
  16 #include <drm/drmP.h>
  17 #include <drm/drm_atomic.h>
  18 #include <drm/drm_crtc.h>
  19 #include <drm/drm_crtc_helper.h>
  20 #include <drm/drm_plane_helper.h>
  21
  22 #include <linux/kernel.h>
  23 #include <linux/module.h>
  24 #include <linux/platform_device.h>
  25 #include <linux/clk.h>
  26 #include <linux/of.h>
  27 #include <linux/of_device.h>
  28 #include <linux/pm_runtime.h>
  29 #include <linux/component.h>
  30
  31 #include <linux/reset.h>
  32 #include <linux/delay.h>
  33 #include <linux/sort.h>
  34
  35 #include "rockchip_drm_drv.h"
  36 #include "rockchip_drm_gem.h"
  37 #include "rockchip_drm_fb.h"
  38 #include "rockchip_drm_vop.h"
  39
  40 #define VOP_REG_SUPPORT(vop, reg) \
  41                 (!reg.major || (reg.major == VOP_MAJOR(vop->data->version) && \
  42                 reg.begin_minor <= VOP_MINOR(vop->data->version) && \
  43                 reg.end_minor >= VOP_MINOR(vop->data->version) && \
  44                 reg.mask))
  45
  46 #define VOP_WIN_SUPPORT(vop, win, name) \
  47                 VOP_REG_SUPPORT(vop, win->phy->name)
  48
  49 #define VOP_CTRL_SUPPORT(vop, win, name) \
  50                 VOP_REG_SUPPORT(vop, vop->data->ctrl->name)
  51
  52 #define VOP_INTR_SUPPORT(vop, win, name) \
  53                 VOP_REG_SUPPORT(vop, vop->data->intr->name)
  54
  55 #define __REG_SET(x, off, mask, shift, v, write_mask, relaxed) \
  56                 vop_mask_write(x, off, mask, shift, v, write_mask, relaxed)
  57
  58 #define _REG_SET(vop, name, off, reg, mask, v, relaxed) \
  59         do { \
  60                 if (VOP_REG_SUPPORT(vop, reg)) \
  61                         __REG_SET(vop, off + reg.offset, mask, reg.shift, \
  62                                   v, reg.write_mask, relaxed); \
  63                 else \
  64                         dev_dbg(vop->dev, "Warning: not support "#name"\n"); \
  65         } while(0)
  66
  67 #define REG_SET(x, name, off, reg, v, relaxed) \
  68                 _REG_SET(x, name, off, reg, reg.mask, v, relaxed)
  69 #define REG_SET_MASK(x, name, off, reg, mask, v, relaxed) \
  70                 _REG_SET(x, name, off, reg, reg.mask & mask, v, relaxed)
  71
  72 #define VOP_WIN_SET(x, win, name, v) \
  73                 REG_SET(x, name, win->offset, VOP_WIN_NAME(win, name), v, true)
  74 #define VOP_SCL_SET(x, win, name, v) \
  75                 REG_SET(x, name, win->offset, win->phy->scl->name, v, true)
  76 #define VOP_SCL_SET_EXT(x, win, name, v) \
  77                 REG_SET(x, name, win->offset, win->phy->scl->ext->name, v, true)
  78
  79 #define VOP_CTRL_SET(x, name, v) \
  80                 REG_SET(x, name, 0, (x)->data->ctrl->name, v, false)
  81
  82 #define VOP_INTR_GET(vop, name) \
  83                 vop_read_reg(vop, 0, &vop->data->ctrl->name)
  84
  85 #define VOP_INTR_SET(vop, name, mask, v) \
  86                 REG_SET_MASK(vop, name, 0, vop->data->intr->name, \
  87                              mask, v, false)
  88
  89 #define VOP_INTR_SET_TYPE(vop, name, type, v) \
  90         do { \
  91                 int i, reg = 0, mask = 0; \
  92                 for (i = 0; i < vop->data->intr->nintrs; i++) { \
  93                         if (vop->data->intr->intrs[i] & type) { \
  94                                 reg |= (v) << i; \
  95                                 mask |= 1 << i; \
  96                         } \
  97                 } \
  98                 VOP_INTR_SET(vop, name, mask, reg); \
  99         } while (0)
 100 #define VOP_INTR_GET_TYPE(vop, name, type) \
 101                 vop_get_intr_type(vop, &vop->data->intr->name, type)
 102
 103 #define VOP_CTRL_GET(x, name) \
 104                 vop_read_reg(x, 0, vop->data->ctrl->name)
 105
 106 #define VOP_WIN_GET(x, win, name) \
 107                 vop_read_reg(x, win->offset, &VOP_WIN_NAME(win, name))
 108
 109 #define VOP_WIN_NAME(win, name) \
 110                 (vop_get_win_phy(win, &win->phy->name)->name)
 111
 112 #define VOP_WIN_GET_YRGBADDR(vop, win) \
 113                 vop_readl(vop, win->offset + VOP_WIN_NAME(win, yrgb_mst).offset)
 114
 115 #define to_vop(x) container_of(x, struct vop, crtc)
 116 #define to_vop_win(x) container_of(x, struct vop_win, base)
 117 #define to_vop_plane_state(x) container_of(x, struct vop_plane_state, base)
 118
 119 struct vop_zpos {
 120         int win_id;
 121         int zpos;
 122 };
 123
 124 struct vop_plane_state {
 125         struct drm_plane_state base;
 126         int format;
 127         int zpos;
 128         struct drm_rect src;
 129         struct drm_rect dest;
 130         dma_addr_t yrgb_mst;
 131         bool enable;
 132 };
 133
 134 struct vop_win {
 135         struct vop_win *parent;
 136         struct drm_plane base;
 137
 138         int win_id;
 139         int area_id;
 140         uint32_t offset;
 141         enum drm_plane_type type;
 142         const struct vop_win_phy *phy;
 143         const uint32_t *data_formats;
 144         uint32_t nformats;
 145         struct vop *vop;
 146
 147         struct drm_property *rotation_prop;
 148         struct vop_plane_state state;
 149 };
 150
 151 struct vop {
 152         struct drm_crtc crtc;
 153         struct device *dev;
 154         struct drm_device *drm_dev;
 155         struct drm_property *plane_zpos_prop;
 156         bool is_enabled;
 157
 158         /* mutex vsync_ work */
 159         struct mutex vsync_mutex;
 160         bool vsync_work_pending;
 161         struct completion dsp_hold_completion;
 162         struct completion wait_update_complete;
 163         struct drm_pending_vblank_event *event;
 164
 165         const struct vop_data *data;
 166         int num_wins;
 167
 168         uint32_t *regsbak;
 169         void __iomem *regs;
 170
 171         /* physical map length of vop register */
 172         uint32_t len;
 173
 174         /* one time only one process allowed to config the register */
 175         spinlock_t reg_lock;
 176         /* lock vop irq reg */
 177         spinlock_t irq_lock;
 178
 179         unsigned int irq;
 180
 181         /* vop AHP clk */
 182         struct clk *hclk;
 183         /* vop dclk */
 184         struct clk *dclk;
 185         /* vop share memory frequency */
 186         struct clk *aclk;
 187
 188         /* vop dclk reset */
 189         struct reset_control *dclk_rst;
 190
 191         struct vop_win win[];
 192 };
 193
 194 static inline void vop_writel(struct vop *vop, uint32_t offset, uint32_t v)
 195 {
 196         writel(v, vop->regs + offset);
 197         vop->regsbak[offset >> 2] = v;
 198 }
 199
 200 static inline uint32_t vop_readl(struct vop *vop, uint32_t offset)
 201 {
 202         return readl(vop->regs + offset);
 203 }
 204
 205 static inline uint32_t vop_read_reg(struct vop *vop, uint32_t base,
 206                                     const struct vop_reg *reg)
 207 {
 208         return (vop_readl(vop, base + reg->offset) >> reg->shift) & reg->mask;
 209 }
 210
 211 static inline void vop_mask_write(struct vop *vop, uint32_t offset,
 212                                   uint32_t mask, uint32_t shift, uint32_t v,
 213                                   bool write_mask, bool relaxed)
 214 {
 215         if (!mask)
 216                 return;
 217
 218         if (write_mask) {
 219                 v = ((v & mask) << shift) | (mask << (shift + 16));
 220         } else {
 221                 uint32_t cached_val = vop->regsbak[offset >> 2];
 222
 223                 v = (cached_val & ~(mask << shift)) | ((v & mask) << shift);
 224                 vop->regsbak[offset >> 2] = v;
 225         }
 226
 227         if (relaxed)
 228                 writel_relaxed(v, vop->regs + offset);
 229         else
 230                 writel(v, vop->regs + offset);
 231 }
 232
 233 static inline const struct vop_win_phy *
 234 vop_get_win_phy(struct vop_win *win, const struct vop_reg *reg)
 235 {
 236         if (!reg->mask && win->parent)
 237                 return win->parent->phy;
 238
 239         return win->phy;
 240 }
 241
 242 static inline uint32_t vop_get_intr_type(struct vop *vop,
 243                                          const struct vop_reg *reg, int type)
 244 {
 245         uint32_t i, ret = 0;
 246         uint32_t regs = vop_read_reg(vop, 0, reg);
 247
 248         for (i = 0; i < vop->data->intr->nintrs; i++) {
 249                 if ((type & vop->data->intr->intrs[i]) && (regs & 1 << i))
 250                         ret |= vop->data->intr->intrs[i];
 251         }
 252
 253         return ret;
 254 }
 255
 256 static inline void vop_cfg_done(struct vop *vop)
 257 {
 258         VOP_CTRL_SET(vop, cfg_done, 1);
 259 }
 260
 261 static bool has_rb_swapped(uint32_t format)
 262 {
 263         switch (format) {
 264         case DRM_FORMAT_XBGR8888:
 265         case DRM_FORMAT_ABGR8888:
 266         case DRM_FORMAT_BGR888:
 267         case DRM_FORMAT_BGR565:
 268                 return true;
 269         default:
 270                 return false;
 271         }
 272 }
 273
 274 static enum vop_data_format vop_convert_format(uint32_t format)
 275 {
 276         switch (format) {
 277         case DRM_FORMAT_XRGB8888:
 278         case DRM_FORMAT_ARGB8888:
 279         case DRM_FORMAT_XBGR8888:
 280         case DRM_FORMAT_ABGR8888:
 281                 return VOP_FMT_ARGB8888;
 282         case DRM_FORMAT_RGB888:
 283         case DRM_FORMAT_BGR888:
 284                 return VOP_FMT_RGB888;
 285         case DRM_FORMAT_RGB565:
 286         case DRM_FORMAT_BGR565:
 287                 return VOP_FMT_RGB565;
 288         case DRM_FORMAT_NV12:
 289                 return VOP_FMT_YUV420SP;
 290         case DRM_FORMAT_NV16:
 291                 return VOP_FMT_YUV422SP;
 292         case DRM_FORMAT_NV24:
 293                 return VOP_FMT_YUV444SP;
 294         default:
 295                 DRM_ERROR("unsupport format[%08x]\n", format);
 296                 return -EINVAL;
 297         }
 298 }
 299
 300 static bool is_yuv_support(uint32_t format)
 301 {
 302         switch (format) {
 303         case DRM_FORMAT_NV12:
 304         case DRM_FORMAT_NV16:
 305         case DRM_FORMAT_NV24:
 306                 return true;
 307         default:
 308                 return false;
 309         }
 310 }
 311
 312 static bool is_alpha_support(uint32_t format)
 313 {
 314         switch (format) {
 315         case DRM_FORMAT_ARGB8888:
 316         case DRM_FORMAT_ABGR8888:
 317                 return true;
 318         default:
 319                 return false;
 320         }
 321 }
 322
 323 static uint16_t scl_vop_cal_scale(enum scale_mode mode, uint32_t src,
 324                                   uint32_t dst, bool is_horizontal,
 325                                   int vsu_mode, int *vskiplines)
 326 {
 327         uint16_t val = 1 << SCL_FT_DEFAULT_FIXPOINT_SHIFT;
 328
 329         if (is_horizontal) {
 330                 if (mode == SCALE_UP)
 331                         val = GET_SCL_FT_BIC(src, dst);
 332                 else if (mode == SCALE_DOWN)
 333                         val = GET_SCL_FT_BILI_DN(src, dst);
 334         } else {
 335                 if (mode == SCALE_UP) {
 336                         if (vsu_mode == SCALE_UP_BIL)
 337                                 val = GET_SCL_FT_BILI_UP(src, dst);
 338                         else
 339                                 val = GET_SCL_FT_BIC(src, dst);
 340                 } else if (mode == SCALE_DOWN) {
 341                         if (vskiplines) {
 342                                 *vskiplines = scl_get_vskiplines(src, dst);
 343                                 val = scl_get_bili_dn_vskip(src, dst,
 344                                                             *vskiplines);
 345                         } else {
 346                                 val = GET_SCL_FT_BILI_DN(src, dst);
 347                         }
 348                 }
 349         }
 350
 351         return val;
 352 }
 353
 354 static void scl_vop_cal_scl_fac(struct vop *vop, struct vop_win *win,
 355                                 uint32_t src_w, uint32_t src_h, uint32_t dst_w,
 356                                 uint32_t dst_h, uint32_t pixel_format)
 357 {
 358         uint16_t yrgb_hor_scl_mode, yrgb_ver_scl_mode;
 359         uint16_t cbcr_hor_scl_mode = SCALE_NONE;
 360         uint16_t cbcr_ver_scl_mode = SCALE_NONE;
 361         int hsub = drm_format_horz_chroma_subsampling(pixel_format);
 362         int vsub = drm_format_vert_chroma_subsampling(pixel_format);
 363         bool is_yuv = is_yuv_support(pixel_format);
 364         uint16_t cbcr_src_w = src_w / hsub;
 365         uint16_t cbcr_src_h = src_h / vsub;
 366         uint16_t vsu_mode;
 367         uint16_t lb_mode;
 368         uint32_t val;
 369         int vskiplines = 0;
 370
 371         if (!win->phy->scl)
 372                 return;
 373
 374         if (dst_w > 3840) {
 375                 DRM_ERROR("Maximum destination width (3840) exceeded\n");
 376                 return;
 377         }
 378
 379         if (!win->phy->scl->ext) {
 380                 VOP_SCL_SET(vop, win, scale_yrgb_x,
 381                             scl_cal_scale2(src_w, dst_w));
 382                 VOP_SCL_SET(vop, win, scale_yrgb_y,
 383                             scl_cal_scale2(src_h, dst_h));
 384                 if (is_yuv) {
 385                         VOP_SCL_SET(vop, win, scale_cbcr_x,
 386                                     scl_cal_scale2(cbcr_src_w, dst_w));
 387                         VOP_SCL_SET(vop, win, scale_cbcr_y,
 388                                     scl_cal_scale2(cbcr_src_h, dst_h));
 389                 }
 390                 return;
 391         }
 392
 393         yrgb_hor_scl_mode = scl_get_scl_mode(src_w, dst_w);
 394         yrgb_ver_scl_mode = scl_get_scl_mode(src_h, dst_h);
 395
 396         if (is_yuv) {
 397                 cbcr_hor_scl_mode = scl_get_scl_mode(cbcr_src_w, dst_w);
 398                 cbcr_ver_scl_mode = scl_get_scl_mode(cbcr_src_h, dst_h);
 399                 if (cbcr_hor_scl_mode == SCALE_DOWN)
 400                         lb_mode = scl_vop_cal_lb_mode(dst_w, true);
 401                 else
 402                         lb_mode = scl_vop_cal_lb_mode(cbcr_src_w, true);
 403         } else {
 404                 if (yrgb_hor_scl_mode == SCALE_DOWN)
 405                         lb_mode = scl_vop_cal_lb_mode(dst_w, false);
 406                 else
 407                         lb_mode = scl_vop_cal_lb_mode(src_w, false);
 408         }
 409
 410         VOP_SCL_SET_EXT(vop, win, lb_mode, lb_mode);
 411         if (lb_mode == LB_RGB_3840X2) {
 412                 if (yrgb_ver_scl_mode != SCALE_NONE) {
 413                         DRM_ERROR("ERROR : not allow yrgb ver scale\n");
 414                         return;
 415                 }
 416                 if (cbcr_ver_scl_mode != SCALE_NONE) {
 417                         DRM_ERROR("ERROR : not allow cbcr ver scale\n");
 418                         return;
 419                 }
 420                 vsu_mode = SCALE_UP_BIL;
 421         } else if (lb_mode == LB_RGB_2560X4) {
 422                 vsu_mode = SCALE_UP_BIL;
 423         } else {
 424                 vsu_mode = SCALE_UP_BIC;
 425         }
 426
 427         val = scl_vop_cal_scale(yrgb_hor_scl_mode, src_w, dst_w,
 428                                 true, 0, NULL);
 429         VOP_SCL_SET(vop, win, scale_yrgb_x, val);
 430         val = scl_vop_cal_scale(yrgb_ver_scl_mode, src_h, dst_h,
 431                                 false, vsu_mode, &vskiplines);
 432         VOP_SCL_SET(vop, win, scale_yrgb_y, val);
 433
 434         VOP_SCL_SET_EXT(vop, win, vsd_yrgb_gt4, vskiplines == 4);
 435         VOP_SCL_SET_EXT(vop, win, vsd_yrgb_gt2, vskiplines == 2);
 436
 437         VOP_SCL_SET_EXT(vop, win, yrgb_hor_scl_mode, yrgb_hor_scl_mode);
 438         VOP_SCL_SET_EXT(vop, win, yrgb_ver_scl_mode, yrgb_ver_scl_mode);
 439         VOP_SCL_SET_EXT(vop, win, yrgb_hsd_mode, SCALE_DOWN_BIL);
 440         VOP_SCL_SET_EXT(vop, win, yrgb_vsd_mode, SCALE_DOWN_BIL);
 441         VOP_SCL_SET_EXT(vop, win, yrgb_vsu_mode, vsu_mode);
 442         if (is_yuv) {
 443                 val = scl_vop_cal_scale(cbcr_hor_scl_mode, cbcr_src_w,
 444                                         dst_w, true, 0, NULL);
 445                 VOP_SCL_SET(vop, win, scale_cbcr_x, val);
 446                 val = scl_vop_cal_scale(cbcr_ver_scl_mode, cbcr_src_h,
 447                                         dst_h, false, vsu_mode, &vskiplines);
 448                 VOP_SCL_SET(vop, win, scale_cbcr_y, val);
 449
 450                 VOP_SCL_SET_EXT(vop, win, vsd_cbcr_gt4, vskiplines == 4);
 451                 VOP_SCL_SET_EXT(vop, win, vsd_cbcr_gt2, vskiplines == 2);
 452                 VOP_SCL_SET_EXT(vop, win, cbcr_hor_scl_mode, cbcr_hor_scl_mode);
 453                 VOP_SCL_SET_EXT(vop, win, cbcr_ver_scl_mode, cbcr_ver_scl_mode);
 454                 VOP_SCL_SET_EXT(vop, win, cbcr_hsd_mode, SCALE_DOWN_BIL);
 455                 VOP_SCL_SET_EXT(vop, win, cbcr_vsd_mode, SCALE_DOWN_BIL);
 456                 VOP_SCL_SET_EXT(vop, win, cbcr_vsu_mode, vsu_mode);
 457         }
 458 }
 459
 460 static void vop_dsp_hold_valid_irq_enable(struct vop *vop)
 461 {
 462         unsigned long flags;
 463
 464         if (WARN_ON(!vop->is_enabled))
 465                 return;
 466
 467         spin_lock_irqsave(&vop->irq_lock, flags);
 468
 469         VOP_INTR_SET_TYPE(vop, enable, DSP_HOLD_VALID_INTR, 1);
 470
 471         spin_unlock_irqrestore(&vop->irq_lock, flags);
 472 }
 473
 474 static void vop_dsp_hold_valid_irq_disable(struct vop *vop)
 475 {
 476         unsigned long flags;
 477
 478         if (WARN_ON(!vop->is_enabled))
 479                 return;
 480
 481         spin_lock_irqsave(&vop->irq_lock, flags);
 482
 483         VOP_INTR_SET_TYPE(vop, enable, DSP_HOLD_VALID_INTR, 0);
 484
 485         spin_unlock_irqrestore(&vop->irq_lock, flags);
 486 }
 487
 488 static void vop_enable(struct drm_crtc *crtc)
 489 {
 490         struct vop *vop = to_vop(crtc);
 491         int ret;
 492
 493         if (vop->is_enabled)
 494                 return;
 495
 496         ret = clk_enable(vop->hclk);
 497         if (ret < 0) {
 498                 dev_err(vop->dev, "failed to enable hclk - %d\n", ret);
 499                 return;
 500         }
 501
 502         ret = clk_enable(vop->dclk);
 503         if (ret < 0) {
 504                 dev_err(vop->dev, "failed to enable dclk - %d\n", ret);
 505                 goto err_disable_hclk;
 506         }
 507
 508         ret = clk_enable(vop->aclk);
 509         if (ret < 0) {
 510                 dev_err(vop->dev, "failed to enable aclk - %d\n", ret);
 511                 goto err_disable_dclk;
 512         }
 513
 514         ret = pm_runtime_get_sync(vop->dev);
 515         if (ret < 0) {
 516                 dev_err(vop->dev, "failed to get pm runtime: %d\n", ret);
 517                 return;
 518         }
 519
 520         /*
 521          * Slave iommu shares power, irq and clock with vop.  It was associated
 522          * automatically with this master device via common driver code.
 523          * Now that we have enabled the clock we attach it to the shared drm
 524          * mapping.
 525          */
 526         ret = rockchip_drm_dma_attach_device(vop->drm_dev, vop->dev);
 527         if (ret) {
 528                 dev_err(vop->dev, "failed to attach dma mapping, %d\n", ret);
 529                 goto err_disable_aclk;
 530         }
 531
 532         memcpy(vop->regs, vop->regsbak, vop->len);
 533         /*
 534          * At here, vop clock & iommu is enable, R/W vop regs would be safe.
 535          */
 536         vop->is_enabled = true;
 537
 538         spin_lock(&vop->reg_lock);
 539
 540         VOP_CTRL_SET(vop, standby, 0);
 541
 542         spin_unlock(&vop->reg_lock);
 543
 544         enable_irq(vop->irq);
 545
 546         drm_crtc_vblank_on(crtc);
 547
 548         return;
 549
 550 err_disable_aclk:
 551         clk_disable(vop->aclk);
 552 err_disable_dclk:
 553         clk_disable(vop->dclk);
 554 err_disable_hclk:
 555         clk_disable(vop->hclk);
 556 }
 557
 558 static void vop_crtc_disable(struct drm_crtc *crtc)
 559 {
 560         struct vop *vop = to_vop(crtc);
 561         int i;
 562
 563         if (!vop->is_enabled)
 564                 return;
 565
 566         /*
 567          * We need to make sure that all windows are disabled before we
 568          * disable that crtc. Otherwise we might try to scan from a destroyed
 569          * buffer later.
 570          */
 571         for (i = 0; i < vop->num_wins; i++) {
 572                 struct vop_win *win = &vop->win[i];
 573
 574                 spin_lock(&vop->reg_lock);
 575                 VOP_WIN_SET(vop, win, enable, 0);
 576                 spin_unlock(&vop->reg_lock);
 577         }
 578
 579         drm_crtc_vblank_off(crtc);
 580
 581         /*
 582          * Vop standby will take effect at end of current frame,
 583          * if dsp hold valid irq happen, it means standby complete.
 584          *
 585          * we must wait standby complete when we want to disable aclk,
 586          * if not, memory bus maybe dead.
 587          */
 588         reinit_completion(&vop->dsp_hold_completion);
 589         vop_dsp_hold_valid_irq_enable(vop);
 590
 591         spin_lock(&vop->reg_lock);
 592
 593         VOP_CTRL_SET(vop, standby, 1);
 594
 595         spin_unlock(&vop->reg_lock);
 596
 597         wait_for_completion(&vop->dsp_hold_completion);
 598
 599         vop_dsp_hold_valid_irq_disable(vop);
 600
 601         disable_irq(vop->irq);
 602
 603         vop->is_enabled = false;
 604
 605         /*
 606          * vop standby complete, so iommu detach is safe.
 607          */
 608         rockchip_drm_dma_detach_device(vop->drm_dev, vop->dev);
 609
 610         pm_runtime_put(vop->dev);
 611         clk_disable(vop->dclk);
 612         clk_disable(vop->aclk);
 613         clk_disable(vop->hclk);
 614 }
 615
 616 static void vop_plane_destroy(struct drm_plane *plane)
 617 {
 618         drm_plane_cleanup(plane);
 619 }
 620
 621 static int vop_plane_prepare_fb(struct drm_plane *plane,
 622                                 const struct drm_plane_state *new_state)
 623 {
 624         if (plane->state->fb)
 625                 drm_framebuffer_reference(plane->state->fb);
 626
 627         return 0;
 628 }
 629
 630 static void vop_plane_cleanup_fb(struct drm_plane *plane,
 631                                  const struct drm_plane_state *old_state)
 632 {
 633         if (old_state->fb)
 634                 drm_framebuffer_unreference(old_state->fb);
 635 }
 636
 637 static int vop_plane_atomic_check(struct drm_plane *plane,
 638                            struct drm_plane_state *state)
 639 {
 640         struct drm_crtc *crtc = state->crtc;
 641         struct drm_framebuffer *fb = state->fb;
 642         struct vop_win *win = to_vop_win(plane);
 643         struct vop_plane_state *vop_plane_state = to_vop_plane_state(state);
 644         struct drm_crtc_state *crtc_state;
 645         bool visible;
 646         int ret;
 647         struct drm_rect *dest = &vop_plane_state->dest;
 648         struct drm_rect *src = &vop_plane_state->src;
 649         struct drm_rect clip;
 650         int min_scale = win->phy->scl ? FRAC_16_16(1, 8) :
 651                                         DRM_PLANE_HELPER_NO_SCALING;
 652         int max_scale = win->phy->scl ? FRAC_16_16(8, 1) :
 653                                         DRM_PLANE_HELPER_NO_SCALING;
 654
 655         crtc = crtc ? crtc : plane->state->crtc;
 656         /*
 657          * Both crtc or plane->state->crtc can be null.
 658          */
 659         if (!crtc || !fb)
 660                 goto out_disable;
 661
 662         crtc_state = drm_atomic_get_crtc_state(state->state, crtc);
 663         if (IS_ERR(crtc_state))
 664                 return PTR_ERR(crtc_state);
 665
 666         src->x1 = state->src_x;
 667         src->y1 = state->src_y;
 668         src->x2 = state->src_x + state->src_w;
 669         src->y2 = state->src_y + state->src_h;
 670         dest->x1 = state->crtc_x;
 671         dest->y1 = state->crtc_y;
 672         dest->x2 = state->crtc_x + state->crtc_w;
 673         dest->y2 = state->crtc_y + state->crtc_h;
 674
 675         clip.x1 = 0;
 676         clip.y1 = 0;
 677         clip.x2 = crtc_state->mode.hdisplay;
 678         clip.y2 = crtc_state->mode.vdisplay;
 679
 680         ret = drm_plane_helper_check_update(plane, crtc, state->fb,
 681                                             src, dest, &clip,
 682                                             min_scale,
 683                                             max_scale,
 684                                             true, true, &visible);
 685         if (ret)
 686                 return ret;
 687
 688         if (!visible)
 689                 goto out_disable;
 690
 691         vop_plane_state->format = vop_convert_format(fb->pixel_format);
 692         if (vop_plane_state->format < 0)
 693                 return vop_plane_state->format;
 694
 695         /*
 696          * Src.x1 can be odd when do clip, but yuv plane start point
 697          * need align with 2 pixel.
 698          */
 699         if (is_yuv_support(fb->pixel_format) && ((src->x1 >> 16) % 2))
 700                 return -EINVAL;
 701
 702         vop_plane_state->enable = true;
 703
 704         return 0;
 705
 706 out_disable:
 707         vop_plane_state->enable = false;
 708         return 0;
 709 }
 710
 711 static void vop_plane_atomic_disable(struct drm_plane *plane,
 712                                      struct drm_plane_state *old_state)
 713 {
 714         struct vop_plane_state *vop_plane_state = to_vop_plane_state(old_state);
 715         struct vop_win *win = to_vop_win(plane);
 716         struct vop *vop = to_vop(old_state->crtc);
 717
 718         if (!old_state->crtc)
 719                 return;
 720
 721         spin_lock(&vop->reg_lock);
 722
 723         VOP_WIN_SET(vop, win, enable, 0);
 724
 725         spin_unlock(&vop->reg_lock);
 726
 727         vop_plane_state->enable = false;
 728 }
 729
 730 static void vop_plane_atomic_update(struct drm_plane *plane,
 731                 struct drm_plane_state *old_state)
 732 {
 733         struct drm_plane_state *state = plane->state;
 734         struct drm_crtc *crtc = state->crtc;
 735         struct vop_win *win = to_vop_win(plane);
 736         struct vop_plane_state *vop_plane_state = to_vop_plane_state(state);
 737         struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc->state);
 738         struct vop *vop = to_vop(state->crtc);
 739         struct drm_framebuffer *fb = state->fb;
 740         unsigned int actual_w, actual_h;
 741         unsigned int dsp_stx, dsp_sty;
 742         uint32_t act_info, dsp_info, dsp_st;
 743         struct drm_rect *src = &vop_plane_state->src;
 744         struct drm_rect *dest = &vop_plane_state->dest;
 745         struct drm_gem_object *obj, *uv_obj;
 746         struct rockchip_gem_object *rk_obj, *rk_uv_obj;
 747         unsigned long offset;
 748         dma_addr_t dma_addr;
 749         int ymirror, xmirror;
 750         uint32_t val;
 751         bool rb_swap;
 752
 753         /*
 754          * can't update plane when vop is disabled.
 755          */
 756         if (!crtc)
 757                 return;
 758
 759         if (WARN_ON(!vop->is_enabled))
 760                 return;
 761
 762         if (!vop_plane_state->enable) {
 763                 vop_plane_atomic_disable(plane, old_state);
 764                 return;
 765         }
 766
 767         obj = rockchip_fb_get_gem_obj(fb, 0);
 768         rk_obj = to_rockchip_obj(obj);
 769
 770         actual_w = drm_rect_width(src) >> 16;
 771         actual_h = drm_rect_height(src) >> 16;
 772         act_info = (actual_h - 1) << 16 | ((actual_w - 1) & 0xffff);
 773
 774         dsp_info = (drm_rect_height(dest) - 1) << 16;
 775         dsp_info |= (drm_rect_width(dest) - 1) & 0xffff;
 776
 777         dsp_stx = dest->x1 + crtc->mode.htotal - crtc->mode.hsync_start;
 778         dsp_sty = dest->y1 + crtc->mode.vtotal - crtc->mode.vsync_start;
 779         dsp_st = dsp_sty << 16 | (dsp_stx & 0xffff);
 780
 781         offset = (src->x1 >> 16) * drm_format_plane_cpp(fb->pixel_format, 0);
 782         if (state->rotation & BIT(DRM_REFLECT_Y))
 783                 offset += ((src->y2 >> 16) - 1) * fb->pitches[0];
 784         else
 785                 offset += (src->y1 >> 16) * fb->pitches[0];
 786         vop_plane_state->yrgb_mst = rk_obj->dma_addr + offset + fb->offsets[0];
 787
 788         ymirror = !!(state->rotation & BIT(DRM_REFLECT_Y));
 789         xmirror = !!(state->rotation & BIT(DRM_REFLECT_X));
 790
 791         spin_lock(&vop->reg_lock);
 792
 793         VOP_WIN_SET(vop, win, xmirror, xmirror);
 794         VOP_WIN_SET(vop, win, ymirror, ymirror);
 795         VOP_WIN_SET(vop, win, format, vop_plane_state->format);
 796         VOP_WIN_SET(vop, win, yrgb_vir, fb->pitches[0] >> 2);
 797         VOP_WIN_SET(vop, win, yrgb_mst, vop_plane_state->yrgb_mst);
 798         if (is_yuv_support(fb->pixel_format)) {
 799                 int hsub = drm_format_horz_chroma_subsampling(fb->pixel_format);
 800                 int vsub = drm_format_vert_chroma_subsampling(fb->pixel_format);
 801                 int bpp = drm_format_plane_cpp(fb->pixel_format, 1);
 802
 803                 uv_obj = rockchip_fb_get_gem_obj(fb, 1);
 804                 rk_uv_obj = to_rockchip_obj(uv_obj);
 805
 806                 offset = (src->x1 >> 16) * bpp / hsub;
 807                 offset += (src->y1 >> 16) * fb->pitches[1] / vsub;
 808
 809                 dma_addr = rk_uv_obj->dma_addr + offset + fb->offsets[1];
 810                 VOP_WIN_SET(vop, win, uv_vir, fb->pitches[1] >> 2);
 811                 VOP_WIN_SET(vop, win, uv_mst, dma_addr);
 812         }
 813
 814         scl_vop_cal_scl_fac(vop, win, actual_w, actual_h,
 815                             drm_rect_width(dest), drm_rect_height(dest),
 816                             fb->pixel_format);
 817
 818         VOP_WIN_SET(vop, win, act_info, act_info);
 819         VOP_WIN_SET(vop, win, dsp_info, dsp_info);
 820         VOP_WIN_SET(vop, win, dsp_st, dsp_st);
 821
 822         rb_swap = has_rb_swapped(fb->pixel_format);
 823         VOP_WIN_SET(vop, win, rb_swap, rb_swap);
 824
 825         if (is_alpha_support(fb->pixel_format) &&
 826             (s->dsp_layer_sel & 0x3) != win->win_id) {
 827                 VOP_WIN_SET(vop, win, dst_alpha_ctl,
 828                             DST_FACTOR_M0(ALPHA_SRC_INVERSE));
 829                 val = SRC_ALPHA_EN(1) | SRC_COLOR_M0(ALPHA_SRC_PRE_MUL) |
 830                         SRC_ALPHA_M0(ALPHA_STRAIGHT) |
 831                         SRC_BLEND_M0(ALPHA_PER_PIX) |
 832                         SRC_ALPHA_CAL_M0(ALPHA_NO_SATURATION) |
 833                         SRC_FACTOR_M0(ALPHA_ONE);
 834                 VOP_WIN_SET(vop, win, src_alpha_ctl, val);
 835                 VOP_WIN_SET(vop, win, alpha_mode, 1);
 836                 VOP_WIN_SET(vop, win, alpha_en, 1);
 837         } else {
 838                 VOP_WIN_SET(vop, win, src_alpha_ctl, SRC_ALPHA_EN(0));
 839                 VOP_WIN_SET(vop, win, alpha_en, 0);
 840         }
 841
 842         VOP_WIN_SET(vop, win, enable, 1);
 843         spin_unlock(&vop->reg_lock);
 844 }
 845
 846 static const struct drm_plane_helper_funcs plane_helper_funcs = {
 847         .prepare_fb = vop_plane_prepare_fb,
 848         .cleanup_fb = vop_plane_cleanup_fb,
 849         .atomic_check = vop_plane_atomic_check,
 850         .atomic_update = vop_plane_atomic_update,
 851         .atomic_disable = vop_plane_atomic_disable,
 852 };
 853
 854 void vop_atomic_plane_reset(struct drm_plane *plane)
 855 {
 856         struct vop_win *win = to_vop_win(plane);
 857         struct vop_plane_state *vop_plane_state =
 858                                         to_vop_plane_state(plane->state);
 859
 860         if (plane->state && plane->state->fb)
 861                 drm_framebuffer_unreference(plane->state->fb);
 862
 863         kfree(vop_plane_state);
 864         vop_plane_state = kzalloc(sizeof(*vop_plane_state), GFP_KERNEL);
 865         if (!vop_plane_state)
 866                 return;
 867
 868         vop_plane_state->zpos = win->win_id;
 869         plane->state = &vop_plane_state->base;
 870         plane->state->plane = plane;
 871 }
 872
 873 struct drm_plane_state *
 874 vop_atomic_plane_duplicate_state(struct drm_plane *plane)
 875 {
 876         struct vop_plane_state *old_vop_plane_state;
 877         struct vop_plane_state *vop_plane_state;
 878
 879         if (WARN_ON(!plane->state))
 880                 return NULL;
 881
 882         old_vop_plane_state = to_vop_plane_state(plane->state);
 883         vop_plane_state = kmemdup(old_vop_plane_state,
 884                                   sizeof(*vop_plane_state), GFP_KERNEL);
 885         if (!vop_plane_state)
 886                 return NULL;
 887
 888         __drm_atomic_helper_plane_duplicate_state(plane,
 889                                                   &vop_plane_state->base);
 890
 891         return &vop_plane_state->base;
 892 }
 893
 894 static void vop_atomic_plane_destroy_state(struct drm_plane *plane,
 895                                            struct drm_plane_state *state)
 896 {
 897         struct vop_plane_state *vop_state = to_vop_plane_state(state);
 898
 899         __drm_atomic_helper_plane_destroy_state(plane, state);
 900
 901         kfree(vop_state);
 902 }
 903
 904 static int vop_atomic_plane_set_property(struct drm_plane *plane,
 905                                          struct drm_plane_state *state,
 906                                          struct drm_property *property,
 907                                          uint64_t val)
 908 {
 909         struct vop_win *win = to_vop_win(plane);
 910         struct vop_plane_state *plane_state = to_vop_plane_state(state);
 911
 912         if (property == win->vop->plane_zpos_prop) {
 913                 plane_state->zpos = val;
 914                 return 0;
 915         }
 916
 917         if (property == win->rotation_prop) {
 918                 state->rotation = val;
 919                 return 0;
 920         }
 921
 922         DRM_ERROR("failed to set vop plane property\n");
 923         return -EINVAL;
 924 }
 925
 926 static int vop_atomic_plane_get_property(struct drm_plane *plane,
 927                                          const struct drm_plane_state *state,
 928                                          struct drm_property *property,
 929                                          uint64_t *val)
 930 {
 931         struct vop_win *win = to_vop_win(plane);
 932         struct vop_plane_state *plane_state = to_vop_plane_state(state);
 933
 934         if (property == win->vop->plane_zpos_prop) {
 935                 *val = plane_state->zpos;
 936                 return 0;
 937         }
 938
 939         if (property == win->rotation_prop) {
 940                 *val = state->rotation;
 941                 return 0;
 942         }
 943
 944         DRM_ERROR("failed to get vop plane property\n");
 945         return -EINVAL;
 946 }
 947
 948 static const struct drm_plane_funcs vop_plane_funcs = {
 949         .update_plane   = drm_atomic_helper_update_plane,
 950         .disable_plane  = drm_atomic_helper_disable_plane,
 951         .destroy = vop_plane_destroy,
 952         .reset = vop_atomic_plane_reset,
 953         .atomic_duplicate_state = vop_atomic_plane_duplicate_state,
 954         .atomic_destroy_state = vop_atomic_plane_destroy_state,
 955         .atomic_set_property = vop_atomic_plane_set_property,
 956         .atomic_get_property = vop_atomic_plane_get_property,
 957 };
 958
 959 static int vop_crtc_enable_vblank(struct drm_crtc *crtc)
 960 {
 961         struct vop *vop = to_vop(crtc);
 962         unsigned long flags;
 963
 964         if (WARN_ON(!vop->is_enabled))
 965                 return -EPERM;
 966
 967         spin_lock_irqsave(&vop->irq_lock, flags);
 968
 969         VOP_INTR_SET_TYPE(vop, enable, FS_INTR, 1);
 970
 971         spin_unlock_irqrestore(&vop->irq_lock, flags);
 972
 973         return 0;
 974 }
 975
 976 static void vop_crtc_disable_vblank(struct drm_crtc *crtc)
 977 {
 978         struct vop *vop = to_vop(crtc);
 979         unsigned long flags;
 980
 981         if (WARN_ON(!vop->is_enabled))
 982                 return;
 983
 984         spin_lock_irqsave(&vop->irq_lock, flags);
 985
 986         VOP_INTR_SET_TYPE(vop, enable, FS_INTR, 0);
 987
 988         spin_unlock_irqrestore(&vop->irq_lock, flags);
 989 }
 990
 991 static void vop_crtc_wait_for_update(struct drm_crtc *crtc)
 992 {
 993         struct vop *vop = to_vop(crtc);
 994
 995         reinit_completion(&vop->wait_update_complete);
 996         WARN_ON(!wait_for_completion_timeout(&vop->wait_update_complete, 100));
 997 }
 998
 999 static void vop_crtc_cancel_pending_vblank(struct drm_crtc *crtc,
1000                                            struct drm_file *file_priv)
1001 {
1002         struct drm_device *drm = crtc->dev;
1003         struct vop *vop = to_vop(crtc);
1004         struct drm_pending_vblank_event *e;
1005         unsigned long flags;
1006
1007         spin_lock_irqsave(&drm->event_lock, flags);
1008         e = vop->event;
1009         if (e && e->base.file_priv == file_priv) {
1010                 vop->event = NULL;
1011
1012                 e->base.destroy(&e->base);
1013                 file_priv->event_space += sizeof(e->event);
1014         }
1015         spin_unlock_irqrestore(&drm->event_lock, flags);
1016 }
1017
1018 static const struct rockchip_crtc_funcs private_crtc_funcs = {
1019         .enable_vblank = vop_crtc_enable_vblank,
1020         .disable_vblank = vop_crtc_disable_vblank,
1021         .wait_for_update = vop_crtc_wait_for_update,
1022         .cancel_pending_vblank = vop_crtc_cancel_pending_vblank,
1023 };
1024
1025 static bool vop_crtc_mode_fixup(struct drm_crtc *crtc,
1026                                 const struct drm_display_mode *mode,
1027                                 struct drm_display_mode *adjusted_mode)
1028 {
1029         struct vop *vop = to_vop(crtc);
1030
1031         adjusted_mode->clock =
1032                 clk_round_rate(vop->dclk, mode->clock * 1000) / 1000;
1033
1034         return true;
1035 }
1036
1037 static void vop_crtc_enable(struct drm_crtc *crtc)
1038 {
1039         struct vop *vop = to_vop(crtc);
1040         const struct vop_data *vop_data = vop->data;
1041         struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc->state);
1042         struct drm_display_mode *adjusted_mode = &crtc->state->adjusted_mode;
1043         u16 hsync_len = adjusted_mode->hsync_end - adjusted_mode->hsync_start;
1044         u16 hdisplay = adjusted_mode->hdisplay;
1045         u16 htotal = adjusted_mode->htotal;
1046         u16 hact_st = adjusted_mode->htotal - adjusted_mode->hsync_start;
1047         u16 hact_end = hact_st + hdisplay;
1048         u16 vdisplay = adjusted_mode->vdisplay;
1049         u16 vtotal = adjusted_mode->vtotal;
1050         u16 vsync_len = adjusted_mode->vsync_end - adjusted_mode->vsync_start;
1051         u16 vact_st = adjusted_mode->vtotal - adjusted_mode->vsync_start;
1052         u16 vact_end = vact_st + vdisplay;
1053         uint32_t val;
1054
1055         vop_enable(crtc);
1056         /*
1057          * If dclk rate is zero, mean that scanout is stop,
1058          * we don't need wait any more.
1059          */
1060         if (clk_get_rate(vop->dclk)) {
1061                 /*
1062                  * Rk3288 vop timing register is immediately, when configure
1063                  * display timing on display time, may cause tearing.
1064                  *
1065                  * Vop standby will take effect at end of current frame,
1066                  * if dsp hold valid irq happen, it means standby complete.
1067                  *
1068                  * mode set:
1069                  *    standby and wait complete --> |----
1070                  *                                  | display time
1071                  *                                  |----
1072                  *                                  |---> dsp hold irq
1073                  *     configure display timing --> |
1074                  *         standby exit             |
1075                  *                                  | new frame start.
1076                  */
1077
1078                 reinit_completion(&vop->dsp_hold_completion);
1079                 vop_dsp_hold_valid_irq_enable(vop);
1080
1081                 spin_lock(&vop->reg_lock);
1082
1083                 VOP_CTRL_SET(vop, standby, 1);
1084
1085                 spin_unlock(&vop->reg_lock);
1086
1087                 wait_for_completion(&vop->dsp_hold_completion);
1088
1089                 vop_dsp_hold_valid_irq_disable(vop);
1090         }
1091
1092         val = 0x8;
1093         val |= (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC) ? 0 : 1;
1094         val |= (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC) ? 0 : (1 << 1);
1095         VOP_CTRL_SET(vop, pin_pol, val);
1096         switch (s->output_type) {
1097         case DRM_MODE_CONNECTOR_LVDS:
1098                 VOP_CTRL_SET(vop, rgb_en, 1);
1099                 VOP_CTRL_SET(vop, rgb_pin_pol, val);
1100                 break;
1101         case DRM_MODE_CONNECTOR_eDP:
1102                 VOP_CTRL_SET(vop, edp_en, 1);
1103                 VOP_CTRL_SET(vop, edp_pin_pol, val);
1104                 break;
1105         case DRM_MODE_CONNECTOR_HDMIA:
1106                 VOP_CTRL_SET(vop, hdmi_en, 1);
1107                 VOP_CTRL_SET(vop, hdmi_pin_pol, val);
1108                 break;
1109         case DRM_MODE_CONNECTOR_DSI:
1110                 VOP_CTRL_SET(vop, mipi_en, 1);
1111                 VOP_CTRL_SET(vop, mipi_pin_pol, val);
1112                 break;
1113         default:
1114                 DRM_ERROR("unsupport connector_type[%d]\n", s->output_type);
1115         }
1116
1117         if (s->output_mode == ROCKCHIP_OUT_MODE_AAAA &&
1118             !(vop_data->feature & VOP_FEATURE_OUTPUT_10BIT))
1119                 s->output_mode = ROCKCHIP_OUT_MODE_P888;
1120
1121         VOP_CTRL_SET(vop, out_mode, s->output_mode);
1122
1123         VOP_CTRL_SET(vop, htotal_pw, (htotal << 16) | hsync_len);
1124         val = hact_st << 16;
1125         val |= hact_end;
1126         VOP_CTRL_SET(vop, hact_st_end, val);
1127         VOP_CTRL_SET(vop, hpost_st_end, val);
1128
1129         VOP_CTRL_SET(vop, vtotal_pw, (vtotal << 16) | vsync_len);
1130         val = vact_st << 16;
1131         val |= vact_end;
1132         VOP_CTRL_SET(vop, vact_st_end, val);
1133         VOP_CTRL_SET(vop, vpost_st_end, val);
1134
1135         clk_set_rate(vop->dclk, adjusted_mode->clock * 1000);
1136
1137         VOP_CTRL_SET(vop, standby, 0);
1138 }
1139
1140 static int vop_zpos_cmp(const void *a, const void *b)
1141 {
1142         struct vop_zpos *pa = (struct vop_zpos *)a;
1143         struct vop_zpos *pb = (struct vop_zpos *)b;
1144
1145         return pa->zpos - pb->zpos;
1146 }
1147
1148 static int vop_crtc_atomic_check(struct drm_crtc *crtc,
1149                                  struct drm_crtc_state *crtc_state)
1150 {
1151         struct drm_atomic_state *state = crtc_state->state;
1152         struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state);
1153         struct vop *vop = to_vop(crtc);
1154         const struct vop_data *vop_data = vop->data;
1155         struct drm_plane *plane;
1156         struct drm_plane_state *pstate;
1157         struct vop_plane_state *plane_state;
1158         struct vop_zpos *pzpos;
1159         int dsp_layer_sel = 0;
1160         int i, j, cnt = 0, ret = 0;
1161
1162         pzpos = kmalloc_array(vop_data->win_size, sizeof(*pzpos), GFP_KERNEL);
1163         if (!pzpos)
1164                 return -ENOMEM;
1165
1166         for (i = 0; i < vop_data->win_size; i++) {
1167                 const struct vop_win_data *win_data = &vop_data->win[i];
1168                 struct vop_win *win;
1169
1170                 if (!win_data->phy)
1171                         continue;
1172
1173                 for (j = 0; j < vop->num_wins; j++) {
1174                         win = &vop->win[j];
1175
1176                         if (win->win_id == i && !win->area_id)
1177                                 break;
1178                 }
1179                 if (WARN_ON(j >= vop->num_wins)) {
1180                         ret = -EINVAL;
1181                         goto err_free_pzpos;
1182                 }
1183
1184                 plane = &win->base;
1185                 pstate = state->plane_states[drm_plane_index(plane)];
1186                 /*
1187                  * plane might not have changed, in which case take
1188                  * current state:
1189                  */
1190                 if (!pstate)
1191                         pstate = plane->state;
1192                 plane_state = to_vop_plane_state(pstate);
1193                 pzpos[cnt].zpos = plane_state->zpos;
1194                 pzpos[cnt++].win_id = win->win_id;
1195         }
1196
1197         sort(pzpos, cnt, sizeof(pzpos[0]), vop_zpos_cmp, NULL);
1198
1199         for (i = 0, cnt = 0; i < vop_data->win_size; i++) {
1200                 const struct vop_win_data *win_data = &vop_data->win[i];
1201                 int shift = i * 2;
1202
1203                 if (win_data->phy) {
1204                         struct vop_zpos *zpos = &pzpos[cnt++];
1205
1206                         dsp_layer_sel |= zpos->win_id << shift;
1207                 } else {
1208                         dsp_layer_sel |= i << shift;
1209                 }
1210         }
1211
1212         s->dsp_layer_sel = dsp_layer_sel;
1213
1214 err_free_pzpos:
1215         kfree(pzpos);
1216         return ret;
1217 }
1218
1219 static void vop_crtc_atomic_flush(struct drm_crtc *crtc,
1220                                   struct drm_crtc_state *old_crtc_state)
1221 {
1222         struct rockchip_crtc_state *s =
1223                         to_rockchip_crtc_state(crtc->state);
1224         struct vop *vop = to_vop(crtc);
1225
1226         if (WARN_ON(!vop->is_enabled))
1227                 return;
1228
1229         spin_lock(&vop->reg_lock);
1230
1231         VOP_CTRL_SET(vop, dsp_layer_sel, s->dsp_layer_sel);
1232         vop_cfg_done(vop);
1233
1234         spin_unlock(&vop->reg_lock);
1235 }
1236
1237 static void vop_crtc_atomic_begin(struct drm_crtc *crtc,
1238                                   struct drm_crtc_state *old_crtc_state)
1239 {
1240         struct vop *vop = to_vop(crtc);
1241
1242         if (crtc->state->event) {
1243                 WARN_ON(drm_crtc_vblank_get(crtc) != 0);
1244
1245                 vop->event = crtc->state->event;
1246                 crtc->state->event = NULL;
1247         }
1248 }
1249
1250 static const struct drm_crtc_helper_funcs vop_crtc_helper_funcs = {
1251         .enable = vop_crtc_enable,
1252         .disable = vop_crtc_disable,
1253         .mode_fixup = vop_crtc_mode_fixup,
1254         .atomic_check = vop_crtc_atomic_check,
1255         .atomic_flush = vop_crtc_atomic_flush,
1256         .atomic_begin = vop_crtc_atomic_begin,
1257 };
1258
1259 static void vop_crtc_destroy(struct drm_crtc *crtc)
1260 {
1261         drm_crtc_cleanup(crtc);
1262 }
1263
1264 static struct drm_crtc_state *vop_crtc_duplicate_state(struct drm_crtc *crtc)
1265 {
1266         struct rockchip_crtc_state *rockchip_state;
1267
1268         rockchip_state = kzalloc(sizeof(*rockchip_state), GFP_KERNEL);
1269         if (!rockchip_state)
1270                 return NULL;
1271
1272         __drm_atomic_helper_crtc_duplicate_state(crtc, &rockchip_state->base);
1273         return &rockchip_state->base;
1274 }
1275
1276 static void vop_crtc_destroy_state(struct drm_crtc *crtc,
1277                                    struct drm_crtc_state *state)
1278 {
1279         struct rockchip_crtc_state *s = to_rockchip_crtc_state(state);
1280
1281         __drm_atomic_helper_crtc_destroy_state(crtc, &s->base);
1282         kfree(s);
1283 }
1284
1285 static const struct drm_crtc_funcs vop_crtc_funcs = {
1286         .set_config = drm_atomic_helper_set_config,
1287         .page_flip = drm_atomic_helper_page_flip,
1288         .destroy = vop_crtc_destroy,
1289         .reset = drm_atomic_helper_crtc_reset,
1290         .atomic_duplicate_state = vop_crtc_duplicate_state,
1291         .atomic_destroy_state = vop_crtc_destroy_state,
1292 };
1293
1294 static bool vop_win_pending_is_complete(struct vop_win *vop_win)
1295 {
1296         struct drm_plane *plane = &vop_win->base;
1297         struct vop_plane_state *state = to_vop_plane_state(plane->state);
1298         dma_addr_t yrgb_mst;
1299
1300         if (!state->enable)
1301                 return VOP_WIN_GET(vop_win->vop, vop_win, enable) == 0;
1302
1303         yrgb_mst = VOP_WIN_GET_YRGBADDR(vop_win->vop, vop_win);
1304
1305         return yrgb_mst == state->yrgb_mst;
1306 }
1307
1308 static void vop_handle_vblank(struct vop *vop)
1309 {
1310         struct drm_device *drm = vop->drm_dev;
1311         struct drm_crtc *crtc = &vop->crtc;
1312         unsigned long flags;
1313         int i;
1314
1315         for (i = 0; i < vop->num_wins; i++) {
1316                 if (!vop_win_pending_is_complete(&vop->win[i]))
1317                         return;
1318         }
1319
1320         if (vop->event) {
1321                 spin_lock_irqsave(&drm->event_lock, flags);
1322
1323                 drm_crtc_send_vblank_event(crtc, vop->event);
1324                 drm_crtc_vblank_put(crtc);
1325                 vop->event = NULL;
1326
1327                 spin_unlock_irqrestore(&drm->event_lock, flags);
1328         }
1329         if (!completion_done(&vop->wait_update_complete))
1330                 complete(&vop->wait_update_complete);
1331 }
1332
1333 static irqreturn_t vop_isr(int irq, void *data)
1334 {
1335         struct vop *vop = data;
1336         struct drm_crtc *crtc = &vop->crtc;
1337         uint32_t active_irqs;
1338         unsigned long flags;
1339         int ret = IRQ_NONE;
1340
1341         /*
1342          * interrupt register has interrupt status, enable and clear bits, we
1343          * must hold irq_lock to avoid a race with enable/disable_vblank().
1344         */
1345         spin_lock_irqsave(&vop->irq_lock, flags);
1346
1347         active_irqs = VOP_INTR_GET_TYPE(vop, status, INTR_MASK);
1348         /* Clear all active interrupt sources */
1349         if (active_irqs)
1350                 VOP_INTR_SET_TYPE(vop, clear, active_irqs, 1);
1351
1352         spin_unlock_irqrestore(&vop->irq_lock, flags);
1353
1354         /* This is expected for vop iommu irqs, since the irq is shared */
1355         if (!active_irqs)
1356                 return IRQ_NONE;
1357
1358         if (active_irqs & DSP_HOLD_VALID_INTR) {
1359                 complete(&vop->dsp_hold_completion);
1360                 active_irqs &= ~DSP_HOLD_VALID_INTR;
1361                 ret = IRQ_HANDLED;
1362         }
1363
1364         if (active_irqs & FS_INTR) {
1365                 drm_crtc_handle_vblank(crtc);
1366                 vop_handle_vblank(vop);
1367                 active_irqs &= ~FS_INTR;
1368                 ret = IRQ_HANDLED;
1369         }
1370
1371         /* Unhandled irqs are spurious. */
1372         if (active_irqs)
1373                 DRM_ERROR("Unknown VOP IRQs: %#02x\n", active_irqs);
1374
1375         return ret;
1376 }
1377
1378 static int vop_plane_init(struct vop *vop, struct vop_win *win,
1379                           unsigned long possible_crtcs)
1380 {
1381         struct drm_plane *share = NULL;
1382         unsigned int rotations = 0;
1383         struct drm_property *prop;
1384         int ret;
1385
1386         if (win->parent)
1387                 share = &win->parent->base;
1388
1389         ret = drm_share_plane_init(vop->drm_dev, &win->base, share,
1390                                    possible_crtcs, &vop_plane_funcs,
1391                                    win->data_formats, win->nformats, win->type);
1392         if (ret) {
1393                 DRM_ERROR("failed to initialize plane\n");
1394                 return ret;
1395         }
1396         drm_plane_helper_add(&win->base, &plane_helper_funcs);
1397         drm_object_attach_property(&win->base.base,
1398                                    vop->plane_zpos_prop, win->win_id);
1399
1400         if (VOP_WIN_SUPPORT(vop, win, xmirror))
1401                 rotations |= BIT(DRM_REFLECT_X);
1402
1403         if (VOP_WIN_SUPPORT(vop, win, ymirror))
1404                 rotations |= BIT(DRM_REFLECT_Y);
1405
1406         if (rotations) {
1407                 rotations |= BIT(DRM_ROTATE_0);
1408                 prop = drm_mode_create_rotation_property(vop->drm_dev,
1409                                                          rotations);
1410                 if (!prop) {
1411                         DRM_ERROR("failed to create zpos property\n");
1412                         return -EINVAL;
1413                 }
1414                 drm_object_attach_property(&win->base.base, prop,
1415                                            BIT(DRM_ROTATE_0));
1416                 win->rotation_prop = prop;
1417         }
1418
1419         return 0;
1420 }
1421
1422 static int vop_create_crtc(struct vop *vop)
1423 {
1424         struct device *dev = vop->dev;
1425         struct drm_device *drm_dev = vop->drm_dev;
1426         struct drm_plane *primary = NULL, *cursor = NULL, *plane, *tmp;
1427         struct drm_crtc *crtc = &vop->crtc;
1428         struct device_node *port;
1429         int ret;
1430         int i;
1431
1432         /*
1433          * Create drm_plane for primary and cursor planes first, since we need
1434          * to pass them to drm_crtc_init_with_planes, which sets the
1435          * "possible_crtcs" to the newly initialized crtc.
1436          */
1437         for (i = 0; i < vop->num_wins; i++) {
1438                 struct vop_win *win = &vop->win[i];
1439
1440                 if (win->type != DRM_PLANE_TYPE_PRIMARY &&
1441                     win->type != DRM_PLANE_TYPE_CURSOR)
1442                         continue;
1443
1444                 ret = vop_plane_init(vop, win, 0);
1445                 if (ret)
1446                         goto err_cleanup_planes;
1447
1448                 plane = &win->base;
1449                 if (plane->type == DRM_PLANE_TYPE_PRIMARY)
1450                         primary = plane;
1451                 else if (plane->type == DRM_PLANE_TYPE_CURSOR)
1452                         cursor = plane;
1453
1454         }
1455
1456         ret = drm_crtc_init_with_planes(drm_dev, crtc, primary, cursor,
1457                                         &vop_crtc_funcs, NULL);
1458         if (ret)
1459                 goto err_cleanup_planes;
1460
1461         drm_crtc_helper_add(crtc, &vop_crtc_helper_funcs);
1462
1463         /*
1464          * Create drm_planes for overlay windows with possible_crtcs restricted
1465          * to the newly created crtc.
1466          */
1467         for (i = 0; i < vop->num_wins; i++) {
1468                 struct vop_win *win = &vop->win[i];
1469                 unsigned long possible_crtcs = 1 << drm_crtc_index(crtc);
1470
1471                 if (win->type != DRM_PLANE_TYPE_OVERLAY)
1472                         continue;
1473
1474                 ret = vop_plane_init(vop, win, possible_crtcs);
1475                 if (ret)
1476                         goto err_cleanup_crtc;
1477         }
1478
1479         port = of_get_child_by_name(dev->of_node, "port");
1480         if (!port) {
1481                 DRM_ERROR("no port node found in %s\n",
1482                           dev->of_node->full_name);
1483                 ret = -ENOENT;
1484                 goto err_cleanup_crtc;
1485         }
1486
1487         init_completion(&vop->dsp_hold_completion);
1488         init_completion(&vop->wait_update_complete);
1489         crtc->port = port;
1490         rockchip_register_crtc_funcs(crtc, &private_crtc_funcs);
1491
1492         return 0;
1493
1494 err_cleanup_crtc:
1495         drm_crtc_cleanup(crtc);
1496 err_cleanup_planes:
1497         list_for_each_entry_safe(plane, tmp, &drm_dev->mode_config.plane_list,
1498                                  head)
1499                 drm_plane_cleanup(plane);
1500         return ret;
1501 }
1502
1503 static void vop_destroy_crtc(struct vop *vop)
1504 {
1505         struct drm_crtc *crtc = &vop->crtc;
1506         struct drm_device *drm_dev = vop->drm_dev;
1507         struct drm_plane *plane, *tmp;
1508
1509         rockchip_unregister_crtc_funcs(crtc);
1510         of_node_put(crtc->port);
1511
1512         /*
1513          * We need to cleanup the planes now.  Why?
1514          *
1515          * The planes are "&vop->win[i].base".  That means the memory is
1516          * all part of the big "struct vop" chunk of memory.  That memory
1517          * was devm allocated and associated with this component.  We need to
1518          * free it ourselves before vop_unbind() finishes.
1519          */
1520         list_for_each_entry_safe(plane, tmp, &drm_dev->mode_config.plane_list,
1521                                  head)
1522                 vop_plane_destroy(plane);
1523
1524         /*
1525          * Destroy CRTC after vop_plane_destroy() since vop_disable_plane()
1526          * references the CRTC.
1527          */
1528         drm_crtc_cleanup(crtc);
1529 }
1530
1531 static int vop_initial(struct vop *vop)
1532 {
1533         struct reset_control *ahb_rst;
1534         int i, ret;
1535
1536         vop->hclk = devm_clk_get(vop->dev, "hclk_vop");
1537         if (IS_ERR(vop->hclk)) {
1538                 dev_err(vop->dev, "failed to get hclk source\n");
1539                 return PTR_ERR(vop->hclk);
1540         }
1541         vop->aclk = devm_clk_get(vop->dev, "aclk_vop");
1542         if (IS_ERR(vop->aclk)) {
1543                 dev_err(vop->dev, "failed to get aclk source\n");
1544                 return PTR_ERR(vop->aclk);
1545         }
1546         vop->dclk = devm_clk_get(vop->dev, "dclk_vop");
1547         if (IS_ERR(vop->dclk)) {
1548                 dev_err(vop->dev, "failed to get dclk source\n");
1549                 return PTR_ERR(vop->dclk);
1550         }
1551
1552         ret = clk_prepare(vop->dclk);
1553         if (ret < 0) {
1554                 dev_err(vop->dev, "failed to prepare dclk\n");
1555                 return ret;
1556         }
1557
1558         /* Enable both the hclk and aclk to setup the vop */
1559         ret = clk_prepare_enable(vop->hclk);
1560         if (ret < 0) {
1561                 dev_err(vop->dev, "failed to prepare/enable hclk\n");
1562                 goto err_unprepare_dclk;
1563         }
1564
1565         ret = clk_prepare_enable(vop->aclk);
1566         if (ret < 0) {
1567                 dev_err(vop->dev, "failed to prepare/enable aclk\n");
1568                 goto err_disable_hclk;
1569         }
1570
1571         /*
1572          * do hclk_reset, reset all vop registers.
1573          */
1574         ahb_rst = devm_reset_control_get(vop->dev, "ahb");
1575         if (IS_ERR(ahb_rst)) {
1576                 dev_err(vop->dev, "failed to get ahb reset\n");
1577                 ret = PTR_ERR(ahb_rst);
1578                 goto err_disable_aclk;
1579         }
1580         reset_control_assert(ahb_rst);
1581         usleep_range(10, 20);
1582         reset_control_deassert(ahb_rst);
1583
1584         memcpy(vop->regsbak, vop->regs, vop->len);
1585
1586         VOP_CTRL_SET(vop, global_regdone_en, 1);
1587
1588         for (i = 0; i < vop->num_wins; i++) {
1589                 struct vop_win *win = &vop->win[i];
1590
1591                 VOP_WIN_SET(vop, win, gate, 1);
1592         }
1593
1594         vop_cfg_done(vop);
1595
1596         /*
1597          * do dclk_reset, let all config take affect.
1598          */
1599         vop->dclk_rst = devm_reset_control_get(vop->dev, "dclk");
1600         if (IS_ERR(vop->dclk_rst)) {
1601                 dev_err(vop->dev, "failed to get dclk reset\n");
1602                 ret = PTR_ERR(vop->dclk_rst);
1603                 goto err_disable_aclk;
1604         }
1605         reset_control_assert(vop->dclk_rst);
1606         usleep_range(10, 20);
1607         reset_control_deassert(vop->dclk_rst);
1608
1609         clk_disable(vop->hclk);
1610         clk_disable(vop->aclk);
1611
1612         vop->is_enabled = false;
1613
1614         return 0;
1615
1616 err_disable_aclk:
1617         clk_disable_unprepare(vop->aclk);
1618 err_disable_hclk:
1619         clk_disable_unprepare(vop->hclk);
1620 err_unprepare_dclk:
1621         clk_unprepare(vop->dclk);
1622         return ret;
1623 }
1624
1625 /*
1626  * Initialize the vop->win array elements.
1627  */
1628 static int vop_win_init(struct vop *vop)
1629 {
1630         const struct vop_data *vop_data = vop->data;
1631         unsigned int i, j;
1632         unsigned int num_wins = 0;
1633         struct drm_property *prop;
1634
1635         for (i = 0; i < vop_data->win_size; i++) {
1636                 struct vop_win *vop_win = &vop->win[num_wins];
1637                 const struct vop_win_data *win_data = &vop_data->win[i];
1638
1639                 if (!win_data->phy)
1640                         continue;
1641
1642                 vop_win->phy = win_data->phy;
1643                 vop_win->offset = win_data->base;
1644                 vop_win->type = win_data->type;
1645                 vop_win->data_formats = win_data->phy->data_formats;
1646                 vop_win->nformats = win_data->phy->nformats;
1647                 vop_win->vop = vop;
1648                 vop_win->win_id = i;
1649                 vop_win->area_id = 0;
1650                 num_wins++;
1651
1652                 for (j = 0; j < win_data->area_size; j++) {
1653                         struct vop_win *vop_area = &vop->win[num_wins];
1654                         const struct vop_win_phy *area = win_data->area[j];
1655
1656                         vop_area->parent = vop_win;
1657                         vop_area->offset = vop_win->offset;
1658                         vop_area->phy = area;
1659                         vop_area->type = DRM_PLANE_TYPE_OVERLAY;
1660                         vop_area->data_formats = vop_win->data_formats;
1661                         vop_area->nformats = vop_win->nformats;
1662                         vop_area->vop = vop;
1663                         vop_area->win_id = i;
1664                         vop_area->area_id = j;
1665                         num_wins++;
1666                 }
1667         }
1668
1669         vop->num_wins = num_wins;
1670
1671         prop = drm_property_create_range(vop->drm_dev, DRM_MODE_PROP_ATOMIC,
1672                                          "ZPOS", 0, vop->data->win_size);
1673         if (!prop) {
1674                 DRM_ERROR("failed to create zpos property\n");
1675                 return -EINVAL;
1676         }
1677         vop->plane_zpos_prop = prop;
1678
1679         return 0;
1680 }
1681
1682 static int vop_bind(struct device *dev, struct device *master, void *data)
1683 {
1684         struct platform_device *pdev = to_platform_device(dev);
1685         const struct vop_data *vop_data;
1686         struct drm_device *drm_dev = data;
1687         struct vop *vop;
1688         struct resource *res;
1689         size_t alloc_size;
1690         int ret, irq, i;
1691         int num_wins = 0;
1692
1693         vop_data = of_device_get_match_data(dev);
1694         if (!vop_data)
1695                 return -ENODEV;
1696
1697         for (i = 0; i < vop_data->win_size; i++) {
1698                 const struct vop_win_data *win_data = &vop_data->win[i];
1699
1700                 num_wins += win_data->area_size + 1;
1701         }
1702
1703         /* Allocate vop struct and its vop_win array */
1704         alloc_size = sizeof(*vop) + sizeof(*vop->win) * num_wins;
1705         vop = devm_kzalloc(dev, alloc_size, GFP_KERNEL);
1706         if (!vop)
1707                 return -ENOMEM;
1708
1709         vop->dev = dev;
1710         vop->data = vop_data;
1711         vop->drm_dev = drm_dev;
1712         vop->num_wins = num_wins;
1713         dev_set_drvdata(dev, vop);
1714
1715         ret = vop_win_init(vop);
1716         if (ret)
1717                 return ret;
1718
1719         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1720         vop->len = resource_size(res);
1721         vop->regs = devm_ioremap_resource(dev, res);
1722         if (IS_ERR(vop->regs))
1723                 return PTR_ERR(vop->regs);
1724
1725         vop->regsbak = devm_kzalloc(dev, vop->len, GFP_KERNEL);
1726         if (!vop->regsbak)
1727                 return -ENOMEM;
1728
1729         ret = vop_initial(vop);
1730         if (ret < 0) {
1731                 dev_err(&pdev->dev, "cannot initial vop dev - err %d\n", ret);
1732                 return ret;
1733         }
1734
1735         irq = platform_get_irq(pdev, 0);
1736         if (irq < 0) {
1737                 dev_err(dev, "cannot find irq for vop\n");
1738                 return irq;
1739         }
1740         vop->irq = (unsigned int)irq;
1741
1742         spin_lock_init(&vop->reg_lock);
1743         spin_lock_init(&vop->irq_lock);
1744
1745         mutex_init(&vop->vsync_mutex);
1746
1747         ret = devm_request_irq(dev, vop->irq, vop_isr,
1748                                IRQF_SHARED, dev_name(dev), vop);
1749         if (ret)
1750                 return ret;
1751
1752         /* IRQ is initially disabled; it gets enabled in power_on */
1753         disable_irq(vop->irq);
1754
1755         ret = vop_create_crtc(vop);
1756         if (ret)
1757                 return ret;
1758
1759         pm_runtime_enable(&pdev->dev);
1760         return 0;
1761 }
1762
1763 static void vop_unbind(struct device *dev, struct device *master, void *data)
1764 {
1765         struct vop *vop = dev_get_drvdata(dev);
1766
1767         pm_runtime_disable(dev);
1768         vop_destroy_crtc(vop);
1769 }
1770
1771 const struct component_ops vop_component_ops = {
1772         .bind = vop_bind,
1773         .unbind = vop_unbind,
1774 };
1775 EXPORT_SYMBOL_GPL(vop_component_ops);