drivers/clk/rockchip/clk-rk3288.c

   1 /*
   2  * Copyright (c) 2014 MundoReader S.L.
   3  * Author: Heiko Stuebner <heiko@sntech.de>
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation; either version 2 of the License, or
   8  * (at your option) any later version.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15
  16 #include <linux/clk-provider.h>
  17 #include <linux/of.h>
  18 #include <linux/of_address.h>
  19 #include <linux/syscore_ops.h>
  20 #include <dt-bindings/clock/rk3288-cru.h>
  21 #include "clk.h"
  22
  23 #define RK3288_GRF_SOC_CON(x)   (0x244 + x * 4)
  24 #define RK3288_GRF_SOC_STATUS1  0x284
  25
  26 enum rk3288_plls {
  27         apll, dpll, cpll, gpll, npll,
  28 };
  29
  30 static struct rockchip_pll_rate_table rk3288_pll_rates[] = {
  31         RK3066_PLL_RATE(2208000000, 1, 92, 1),
  32         RK3066_PLL_RATE(2184000000, 1, 91, 1),
  33         RK3066_PLL_RATE(2160000000, 1, 90, 1),
  34         RK3066_PLL_RATE(2136000000, 1, 89, 1),
  35         RK3066_PLL_RATE(2112000000, 1, 88, 1),
  36         RK3066_PLL_RATE(2088000000, 1, 87, 1),
  37         RK3066_PLL_RATE(2064000000, 1, 86, 1),
  38         RK3066_PLL_RATE(2040000000, 1, 85, 1),
  39         RK3066_PLL_RATE(2016000000, 1, 84, 1),
  40         RK3066_PLL_RATE(1992000000, 1, 83, 1),
  41         RK3066_PLL_RATE(1968000000, 1, 82, 1),
  42         RK3066_PLL_RATE(1944000000, 1, 81, 1),
  43         RK3066_PLL_RATE(1920000000, 1, 80, 1),
  44         RK3066_PLL_RATE(1896000000, 1, 79, 1),
  45         RK3066_PLL_RATE(1872000000, 1, 78, 1),
  46         RK3066_PLL_RATE(1848000000, 1, 77, 1),
  47         RK3066_PLL_RATE(1824000000, 1, 76, 1),
  48         RK3066_PLL_RATE(1800000000, 1, 75, 1),
  49         RK3066_PLL_RATE(1776000000, 1, 74, 1),
  50         RK3066_PLL_RATE(1752000000, 1, 73, 1),
  51         RK3066_PLL_RATE(1728000000, 1, 72, 1),
  52         RK3066_PLL_RATE(1704000000, 1, 71, 1),
  53         RK3066_PLL_RATE(1680000000, 1, 70, 1),
  54         RK3066_PLL_RATE(1656000000, 1, 69, 1),
  55         RK3066_PLL_RATE(1632000000, 1, 68, 1),
  56         RK3066_PLL_RATE(1608000000, 1, 67, 1),
  57         RK3066_PLL_RATE(1560000000, 1, 65, 1),
  58         RK3066_PLL_RATE(1512000000, 1, 63, 1),
  59         RK3066_PLL_RATE(1488000000, 1, 62, 1),
  60         RK3066_PLL_RATE(1464000000, 1, 61, 1),
  61         RK3066_PLL_RATE(1440000000, 1, 60, 1),
  62         RK3066_PLL_RATE(1416000000, 1, 59, 1),
  63         RK3066_PLL_RATE(1392000000, 1, 58, 1),
  64         RK3066_PLL_RATE(1368000000, 1, 57, 1),
  65         RK3066_PLL_RATE(1344000000, 1, 56, 1),
  66         RK3066_PLL_RATE(1320000000, 1, 55, 1),
  67         RK3066_PLL_RATE(1296000000, 1, 54, 1),
  68         RK3066_PLL_RATE(1272000000, 1, 53, 1),
  69         RK3066_PLL_RATE(1248000000, 1, 52, 1),
  70         RK3066_PLL_RATE(1224000000, 1, 51, 1),
  71         RK3066_PLL_RATE(1200000000, 1, 50, 1),
  72         RK3066_PLL_RATE(1188000000, 2, 99, 1),
  73         RK3066_PLL_RATE(1176000000, 1, 49, 1),
  74         RK3066_PLL_RATE(1128000000, 1, 47, 1),
  75         RK3066_PLL_RATE(1104000000, 1, 46, 1),
  76         RK3066_PLL_RATE(1008000000, 1, 84, 2),
  77         RK3066_PLL_RATE( 912000000, 1, 76, 2),
  78         RK3066_PLL_RATE( 891000000, 8, 594, 2),
  79         RK3066_PLL_RATE( 888000000, 1, 74, 2),
  80         RK3066_PLL_RATE( 816000000, 1, 68, 2),
  81         RK3066_PLL_RATE( 798000000, 2, 133, 2),
  82         RK3066_PLL_RATE( 792000000, 1, 66, 2),
  83         RK3066_PLL_RATE( 768000000, 1, 64, 2),
  84         RK3066_PLL_RATE( 742500000, 8, 495, 2),
  85         RK3066_PLL_RATE( 696000000, 1, 58, 2),
  86         RK3066_PLL_RATE( 600000000, 1, 50, 2),
  87         RK3066_PLL_RATE_NB(594000000, 1, 198, 8, 1),
  88         RK3066_PLL_RATE( 552000000, 1, 46, 2),
  89         RK3066_PLL_RATE( 504000000, 1, 84, 4),
  90         RK3066_PLL_RATE( 500000000, 3, 125, 2),
  91         RK3066_PLL_RATE( 456000000, 1, 76, 4),
  92         RK3066_PLL_RATE( 408000000, 1, 68, 4),
  93         RK3066_PLL_RATE( 400000000, 3, 100, 2),
  94         RK3066_PLL_RATE( 384000000, 2, 128, 4),
  95         RK3066_PLL_RATE( 360000000, 1, 60, 4),
  96         RK3066_PLL_RATE( 312000000, 1, 52, 4),
  97         RK3066_PLL_RATE( 300000000, 1, 50, 4),
  98         RK3066_PLL_RATE( 297000000, 2, 198, 8),
  99         RK3066_PLL_RATE( 252000000, 1, 84, 8),
 100         RK3066_PLL_RATE( 216000000, 1, 72, 8),
 101         RK3066_PLL_RATE( 148500000, 2, 99, 8),
 102         RK3066_PLL_RATE( 126000000, 1, 84, 16),
 103         RK3066_PLL_RATE(  48000000, 1, 64, 32),
 104         { /* sentinel */ },
 105 };
 106
 107 #define RK3288_DIV_ACLK_CORE_M0_MASK    0xf
 108 #define RK3288_DIV_ACLK_CORE_M0_SHIFT   0
 109 #define RK3288_DIV_ACLK_CORE_MP_MASK    0xf
 110 #define RK3288_DIV_ACLK_CORE_MP_SHIFT   4
 111 #define RK3288_DIV_L2RAM_MASK           0x7
 112 #define RK3288_DIV_L2RAM_SHIFT          0
 113 #define RK3288_DIV_ATCLK_MASK           0x1f
 114 #define RK3288_DIV_ATCLK_SHIFT          4
 115 #define RK3288_DIV_PCLK_DBGPRE_MASK     0x1f
 116 #define RK3288_DIV_PCLK_DBGPRE_SHIFT    9
 117
 118 #define RK3288_CLKSEL0(_core_m0, _core_mp)                              \
 119         {                                                               \
 120                 .reg = RK3288_CLKSEL_CON(0),                            \
 121                 .val = HIWORD_UPDATE(_core_m0, RK3288_DIV_ACLK_CORE_M0_MASK, \
 122                                 RK3288_DIV_ACLK_CORE_M0_SHIFT) |        \
 123                        HIWORD_UPDATE(_core_mp, RK3288_DIV_ACLK_CORE_MP_MASK, \
 124                                 RK3288_DIV_ACLK_CORE_MP_SHIFT),         \
 125         }
 126 #define RK3288_CLKSEL37(_l2ram, _atclk, _pclk_dbg_pre)                  \
 127         {                                                               \
 128                 .reg = RK3288_CLKSEL_CON(37),                           \
 129                 .val = HIWORD_UPDATE(_l2ram, RK3288_DIV_L2RAM_MASK,     \
 130                                 RK3288_DIV_L2RAM_SHIFT) |               \
 131                        HIWORD_UPDATE(_atclk, RK3288_DIV_ATCLK_MASK,     \
 132                                 RK3288_DIV_ATCLK_SHIFT) |               \
 133                        HIWORD_UPDATE(_pclk_dbg_pre,                     \
 134                                 RK3288_DIV_PCLK_DBGPRE_MASK,            \
 135                                 RK3288_DIV_PCLK_DBGPRE_SHIFT),          \
 136         }
 137
 138 #define RK3288_CPUCLK_RATE(_prate, _core_m0, _core_mp, _l2ram, _atclk, _pdbg) \
 139         {                                                               \
 140                 .prate = _prate,                                        \
 141                 .divs = {                                               \
 142                         RK3288_CLKSEL0(_core_m0, _core_mp),             \
 143                         RK3288_CLKSEL37(_l2ram, _atclk, _pdbg),         \
 144                 },                                                      \
 145         }
 146
 147 static struct rockchip_cpuclk_rate_table rk3288_cpuclk_rates[] __initdata = {
 148         RK3288_CPUCLK_RATE(1800000000, 1, 3, 1, 3, 3),
 149         RK3288_CPUCLK_RATE(1704000000, 1, 3, 1, 3, 3),
 150         RK3288_CPUCLK_RATE(1608000000, 1, 3, 1, 3, 3),
 151         RK3288_CPUCLK_RATE(1512000000, 1, 3, 1, 3, 3),
 152         RK3288_CPUCLK_RATE(1416000000, 1, 3, 1, 3, 3),
 153         RK3288_CPUCLK_RATE(1200000000, 1, 3, 1, 3, 3),
 154         RK3288_CPUCLK_RATE(1008000000, 1, 3, 1, 3, 3),
 155         RK3288_CPUCLK_RATE( 816000000, 1, 3, 1, 3, 3),
 156         RK3288_CPUCLK_RATE( 696000000, 1, 3, 1, 3, 3),
 157         RK3288_CPUCLK_RATE( 600000000, 1, 3, 1, 3, 3),
 158         RK3288_CPUCLK_RATE( 408000000, 1, 3, 1, 3, 3),
 159         RK3288_CPUCLK_RATE( 312000000, 1, 3, 1, 3, 3),
 160         RK3288_CPUCLK_RATE( 216000000, 1, 3, 1, 3, 3),
 161         RK3288_CPUCLK_RATE( 126000000, 1, 3, 1, 3, 3),
 162 };
 163
 164 static const struct rockchip_cpuclk_reg_data rk3288_cpuclk_data = {
 165         .core_reg = RK3288_CLKSEL_CON(0),
 166         .div_core_shift = 8,
 167         .div_core_mask = 0x1f,
 168         .mux_core_shift = 15,
 169 };
 170
 171 PNAME(mux_pll_p)                = { "xin24m", "xin32k" };
 172 PNAME(mux_armclk_p)             = { "apll_core", "gpll_core" };
 173 PNAME(mux_ddrphy_p)             = { "dpll_ddr", "gpll_ddr" };
 174 PNAME(mux_aclk_cpu_src_p)       = { "cpll_aclk_cpu", "gpll_aclk_cpu" };
 175
 176 PNAME(mux_pll_src_cpll_gpll_p)          = { "cpll", "gpll" };
 177 PNAME(mux_pll_src_npll_cpll_gpll_p)     = { "npll", "cpll", "gpll" };
 178 PNAME(mux_pll_src_cpll_gpll_npll_p)     = { "cpll", "gpll", "npll" };
 179 PNAME(mux_pll_src_cpll_gpll_usb480m_p)  = { "cpll", "gpll", "usbphy480m_src" };
 180 PNAME(mux_pll_src_cpll_gll_usb_npll_p)  = { "cpll", "gpll", "usbphy480m_src", "npll" };
 181
 182 PNAME(mux_mmc_src_p)    = { "cpll", "gpll", "xin24m", "xin24m" };
 183 PNAME(mux_i2s_pre_p)    = { "i2s_src", "i2s_frac", "ext_i2s", "xin12m" };
 184 PNAME(mux_i2s_clkout_p) = { "i2s_pre", "xin12m" };
 185 PNAME(mux_spdif_p)      = { "spdif_pre", "spdif_frac", "xin12m" };
 186 PNAME(mux_spdif_8ch_p)  = { "spdif_8ch_pre", "spdif_8ch_frac", "xin12m" };
 187 PNAME(mux_uart0_p)      = { "uart0_src", "uart0_frac", "xin24m" };
 188 PNAME(mux_uart1_p)      = { "uart1_src", "uart1_frac", "xin24m" };
 189 PNAME(mux_uart2_p)      = { "uart2_src", "uart2_frac", "xin24m" };
 190 PNAME(mux_uart3_p)      = { "uart3_src", "uart3_frac", "xin24m" };
 191 PNAME(mux_uart4_p)      = { "uart4_src", "uart4_frac", "xin24m" };
 192 PNAME(mux_vip_out_p)    = { "vip_src", "xin24m" };
 193 PNAME(mux_mac_p)        = { "mac_pll_src", "ext_gmac" };
 194 PNAME(mux_hsadcout_p)   = { "hsadc_src", "ext_hsadc" };
 195 PNAME(mux_edp_24m_p)    = { "ext_edp_24m", "xin24m" };
 196 PNAME(mux_tspout_p)     = { "cpll", "gpll", "npll", "xin27m" };
 197
 198 PNAME(mux_usbphy480m_p)         = { "sclk_otgphy1", "sclk_otgphy2",
 199                                     "sclk_otgphy0" };
 200 PNAME(mux_hsicphy480m_p)        = { "cpll", "gpll", "usbphy480m_src" };
 201 PNAME(mux_hsicphy12m_p)         = { "hsicphy12m_xin12m", "hsicphy12m_usbphy" };
 202
 203 static struct rockchip_pll_clock rk3288_pll_clks[] __initdata = {
 204         [apll] = PLL(pll_rk3066, PLL_APLL, "apll", mux_pll_p, 0, RK3288_PLL_CON(0),
 205                      RK3288_MODE_CON, 0, 6, 0, rk3288_pll_rates),
 206         [dpll] = PLL(pll_rk3066, PLL_DPLL, "dpll", mux_pll_p, 0, RK3288_PLL_CON(4),
 207                      RK3288_MODE_CON, 4, 5, 0, NULL),
 208         [cpll] = PLL(pll_rk3066, PLL_CPLL, "cpll", mux_pll_p, 0, RK3288_PLL_CON(8),
 209                      RK3288_MODE_CON, 8, 7, ROCKCHIP_PLL_SYNC_RATE, rk3288_pll_rates),
 210         [gpll] = PLL(pll_rk3066, PLL_GPLL, "gpll", mux_pll_p, 0, RK3288_PLL_CON(12),
 211                      RK3288_MODE_CON, 12, 8, ROCKCHIP_PLL_SYNC_RATE, rk3288_pll_rates),
 212         [npll] = PLL(pll_rk3066, PLL_NPLL, "npll",  mux_pll_p, 0, RK3288_PLL_CON(16),
 213                      RK3288_MODE_CON, 14, 9, ROCKCHIP_PLL_SYNC_RATE, rk3288_pll_rates),
 214 };
 215
 216 static struct clk_div_table div_hclk_cpu_t[] = {
 217         { .val = 0, .div = 1 },
 218         { .val = 1, .div = 2 },
 219         { .val = 3, .div = 4 },
 220         { /* sentinel */},
 221 };
 222
 223 #define MFLAGS CLK_MUX_HIWORD_MASK
 224 #define DFLAGS CLK_DIVIDER_HIWORD_MASK
 225 #define GFLAGS (CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE)
 226 #define IFLAGS ROCKCHIP_INVERTER_HIWORD_MASK
 227
 228 static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = {
 229         /*
 230          * Clock-Architecture Diagram 1
 231          */
 232
 233         GATE(0, "apll_core", "apll", CLK_IGNORE_UNUSED,
 234                         RK3288_CLKGATE_CON(0), 1, GFLAGS),
 235         GATE(0, "gpll_core", "gpll", CLK_IGNORE_UNUSED,
 236                         RK3288_CLKGATE_CON(0), 2, GFLAGS),
 237
 238         COMPOSITE_NOMUX(0, "armcore0", "armclk", CLK_IGNORE_UNUSED,
 239                         RK3288_CLKSEL_CON(36), 0, 3, DFLAGS | CLK_DIVIDER_READ_ONLY,
 240                         RK3288_CLKGATE_CON(12), 0, GFLAGS),
 241         COMPOSITE_NOMUX(0, "armcore1", "armclk", CLK_IGNORE_UNUSED,
 242                         RK3288_CLKSEL_CON(36), 4, 3, DFLAGS | CLK_DIVIDER_READ_ONLY,
 243                         RK3288_CLKGATE_CON(12), 1, GFLAGS),
 244         COMPOSITE_NOMUX(0, "armcore2", "armclk", CLK_IGNORE_UNUSED,
 245                         RK3288_CLKSEL_CON(36), 8, 3, DFLAGS | CLK_DIVIDER_READ_ONLY,
 246                         RK3288_CLKGATE_CON(12), 2, GFLAGS),
 247         COMPOSITE_NOMUX(0, "armcore3", "armclk", CLK_IGNORE_UNUSED,
 248                         RK3288_CLKSEL_CON(36), 12, 3, DFLAGS | CLK_DIVIDER_READ_ONLY,
 249                         RK3288_CLKGATE_CON(12), 3, GFLAGS),
 250         COMPOSITE_NOMUX(0, "l2ram", "armclk", CLK_IGNORE_UNUSED,
 251                         RK3288_CLKSEL_CON(37), 0, 3, DFLAGS | CLK_DIVIDER_READ_ONLY,
 252                         RK3288_CLKGATE_CON(12), 4, GFLAGS),
 253         COMPOSITE_NOMUX(0, "aclk_core_m0", "armclk", CLK_IGNORE_UNUSED,
 254                         RK3288_CLKSEL_CON(0), 0, 4, DFLAGS | CLK_DIVIDER_READ_ONLY,
 255                         RK3288_CLKGATE_CON(12), 5, GFLAGS),
 256         COMPOSITE_NOMUX(0, "aclk_core_mp", "armclk", CLK_IGNORE_UNUSED,
 257                         RK3288_CLKSEL_CON(0), 4, 4, DFLAGS | CLK_DIVIDER_READ_ONLY,
 258                         RK3288_CLKGATE_CON(12), 6, GFLAGS),
 259         COMPOSITE_NOMUX(0, "atclk", "armclk", 0,
 260                         RK3288_CLKSEL_CON(37), 4, 5, DFLAGS | CLK_DIVIDER_READ_ONLY,
 261                         RK3288_CLKGATE_CON(12), 7, GFLAGS),
 262         COMPOSITE_NOMUX(0, "pclk_dbg_pre", "armclk", CLK_IGNORE_UNUSED,
 263                         RK3288_CLKSEL_CON(37), 9, 5, DFLAGS | CLK_DIVIDER_READ_ONLY,
 264                         RK3288_CLKGATE_CON(12), 8, GFLAGS),
 265         GATE(0, "pclk_dbg", "pclk_dbg_pre", 0,
 266                         RK3288_CLKGATE_CON(12), 9, GFLAGS),
 267         GATE(0, "cs_dbg", "pclk_dbg_pre", CLK_IGNORE_UNUSED,
 268                         RK3288_CLKGATE_CON(12), 10, GFLAGS),
 269         GATE(0, "pclk_core_niu", "pclk_dbg_pre", 0,
 270                         RK3288_CLKGATE_CON(12), 11, GFLAGS),
 271
 272         GATE(0, "dpll_ddr", "dpll", CLK_IGNORE_UNUSED,
 273                         RK3288_CLKGATE_CON(0), 8, GFLAGS),
 274         GATE(0, "gpll_ddr", "gpll", 0,
 275                         RK3288_CLKGATE_CON(0), 9, GFLAGS),
 276         COMPOSITE_NOGATE(0, "ddrphy", mux_ddrphy_p, CLK_IGNORE_UNUSED,
 277                         RK3288_CLKSEL_CON(26), 2, 1, MFLAGS, 0, 2,
 278                                         DFLAGS | CLK_DIVIDER_POWER_OF_TWO),
 279
 280         GATE(0, "gpll_aclk_cpu", "gpll", CLK_IGNORE_UNUSED,
 281                         RK3288_CLKGATE_CON(0), 10, GFLAGS),
 282         GATE(0, "cpll_aclk_cpu", "cpll", CLK_IGNORE_UNUSED,
 283                         RK3288_CLKGATE_CON(0), 11, GFLAGS),
 284         COMPOSITE_NOGATE(0, "aclk_cpu_src", mux_aclk_cpu_src_p, CLK_IGNORE_UNUSED,
 285                         RK3288_CLKSEL_CON(1), 15, 1, MFLAGS, 3, 5, DFLAGS),
 286         DIV(0, "aclk_cpu_pre", "aclk_cpu_src", CLK_SET_RATE_PARENT,
 287                         RK3288_CLKSEL_CON(1), 0, 3, DFLAGS),
 288         GATE(ACLK_CPU, "aclk_cpu", "aclk_cpu_pre", CLK_IGNORE_UNUSED,
 289                         RK3288_CLKGATE_CON(0), 3, GFLAGS),
 290         COMPOSITE_NOMUX(PCLK_CPU, "pclk_cpu", "aclk_cpu_pre", CLK_IGNORE_UNUSED,
 291                         RK3288_CLKSEL_CON(1), 12, 3, DFLAGS,
 292                         RK3288_CLKGATE_CON(0), 5, GFLAGS),
 293         COMPOSITE_NOMUX_DIVTBL(HCLK_CPU, "hclk_cpu", "aclk_cpu_pre", CLK_IGNORE_UNUSED,
 294                         RK3288_CLKSEL_CON(1), 8, 2, DFLAGS, div_hclk_cpu_t,
 295                         RK3288_CLKGATE_CON(0), 4, GFLAGS),
 296         GATE(0, "c2c_host", "aclk_cpu_src", 0,
 297                         RK3288_CLKGATE_CON(13), 8, GFLAGS),
 298         COMPOSITE_NOMUX(0, "crypto", "aclk_cpu_pre", 0,
 299                         RK3288_CLKSEL_CON(26), 6, 2, DFLAGS,
 300                         RK3288_CLKGATE_CON(5), 4, GFLAGS),
 301         GATE(0, "aclk_bus_2pmu", "aclk_cpu_pre", CLK_IGNORE_UNUSED,
 302                         RK3288_CLKGATE_CON(0), 7, GFLAGS),
 303
 304         COMPOSITE(0, "i2s_src", mux_pll_src_cpll_gpll_p, 0,
 305                         RK3288_CLKSEL_CON(4), 15, 1, MFLAGS, 0, 7, DFLAGS,
 306                         RK3288_CLKGATE_CON(4), 1, GFLAGS),
 307         COMPOSITE_FRACMUX(0, "i2s_frac", "i2s_src", CLK_SET_RATE_PARENT,
 308                         RK3288_CLKSEL_CON(8), 0,
 309                         RK3288_CLKGATE_CON(4), 2, GFLAGS,
 310                 MUX(0, "i2s_pre", mux_i2s_pre_p, CLK_SET_RATE_PARENT,
 311                                 RK3288_CLKSEL_CON(4), 8, 2, MFLAGS)),
 312         COMPOSITE_NODIV(SCLK_I2S0_OUT, "i2s0_clkout", mux_i2s_clkout_p, 0,
 313                         RK3288_CLKSEL_CON(4), 12, 1, MFLAGS,
 314                         RK3288_CLKGATE_CON(4), 0, GFLAGS),
 315         GATE(SCLK_I2S0, "sclk_i2s0", "i2s_pre", CLK_SET_RATE_PARENT,
 316                         RK3288_CLKGATE_CON(4), 3, GFLAGS),
 317
 318         MUX(0, "spdif_src", mux_pll_src_cpll_gpll_p, 0,
 319                         RK3288_CLKSEL_CON(5), 15, 1, MFLAGS),
 320         COMPOSITE_NOMUX(0, "spdif_pre", "spdif_src", CLK_SET_RATE_PARENT,
 321                         RK3288_CLKSEL_CON(5), 0, 7, DFLAGS,
 322                         RK3288_CLKGATE_CON(4), 4, GFLAGS),
 323         COMPOSITE_FRACMUX(0, "spdif_frac", "spdif_src", CLK_SET_RATE_PARENT,
 324                         RK3288_CLKSEL_CON(9), 0,
 325                         RK3288_CLKGATE_CON(4), 5, GFLAGS,
 326                 MUX(0, "spdif_mux", mux_spdif_p, CLK_SET_RATE_PARENT,
 327                                 RK3288_CLKSEL_CON(5), 8, 2, MFLAGS)),
 328         GATE(SCLK_SPDIF, "sclk_spdif", "spdif_mux", CLK_SET_RATE_PARENT,
 329                         RK3288_CLKGATE_CON(4), 6, GFLAGS),
 330         COMPOSITE_NOMUX(0, "spdif_8ch_pre", "spdif_src", CLK_SET_RATE_PARENT,
 331                         RK3288_CLKSEL_CON(40), 0, 7, DFLAGS,
 332                         RK3288_CLKGATE_CON(4), 7, GFLAGS),
 333         COMPOSITE_FRACMUX(0, "spdif_8ch_frac", "spdif_8ch_pre", CLK_SET_RATE_PARENT,
 334                         RK3288_CLKSEL_CON(41), 0,
 335                         RK3288_CLKGATE_CON(4), 8, GFLAGS,
 336                 MUX(0, "spdif_8ch_mux", mux_spdif_8ch_p, CLK_SET_RATE_PARENT,
 337                                 RK3288_CLKSEL_CON(40), 8, 2, MFLAGS)),
 338         GATE(SCLK_SPDIF8CH, "sclk_spdif_8ch", "spdif_8ch_mux", CLK_SET_RATE_PARENT,
 339                         RK3288_CLKGATE_CON(4), 9, GFLAGS),
 340
 341         GATE(0, "sclk_acc_efuse", "xin24m", 0,
 342                         RK3288_CLKGATE_CON(0), 12, GFLAGS),
 343
 344         GATE(SCLK_TIMER0, "sclk_timer0", "xin24m", 0,
 345                         RK3288_CLKGATE_CON(1), 0, GFLAGS),
 346         GATE(SCLK_TIMER1, "sclk_timer1", "xin24m", 0,
 347                         RK3288_CLKGATE_CON(1), 1, GFLAGS),
 348         GATE(SCLK_TIMER2, "sclk_timer2", "xin24m", 0,
 349                         RK3288_CLKGATE_CON(1), 2, GFLAGS),
 350         GATE(SCLK_TIMER3, "sclk_timer3", "xin24m", 0,
 351                         RK3288_CLKGATE_CON(1), 3, GFLAGS),
 352         GATE(SCLK_TIMER4, "sclk_timer4", "xin24m", 0,
 353                         RK3288_CLKGATE_CON(1), 4, GFLAGS),
 354         GATE(SCLK_TIMER5, "sclk_timer5", "xin24m", 0,
 355                         RK3288_CLKGATE_CON(1), 5, GFLAGS),
 356
 357         /*
 358          * Clock-Architecture Diagram 2
 359          */
 360
 361         COMPOSITE(0, "aclk_vepu", mux_pll_src_cpll_gpll_usb480m_p, 0,
 362                         RK3288_CLKSEL_CON(32), 6, 2, MFLAGS, 0, 5, DFLAGS,
 363                         RK3288_CLKGATE_CON(3), 9, GFLAGS),
 364         COMPOSITE(0, "aclk_vdpu", mux_pll_src_cpll_gpll_usb480m_p, 0,
 365                         RK3288_CLKSEL_CON(32), 14, 2, MFLAGS, 8, 5, DFLAGS,
 366                         RK3288_CLKGATE_CON(3), 11, GFLAGS),
 367         /*
 368          * We use aclk_vdpu by default GRF_SOC_CON0[7] setting in system,
 369          * so we ignore the mux and make clocks nodes as following,
 370          */
 371         GATE(ACLK_VCODEC, "aclk_vcodec", "aclk_vdpu", 0,
 372                 RK3288_CLKGATE_CON(9), 0, GFLAGS),
 373         /*
 374          * We introduce a virtul node of hclk_vodec_pre_v to split one clock
 375          * struct with a gate and a fix divider into two node in software.
 376          */
 377         GATE(0, "hclk_vcodec_pre_v", "aclk_vdpu", 0,
 378                 RK3288_CLKGATE_CON(3), 10, GFLAGS),
 379         GATE(HCLK_VCODEC, "hclk_vcodec", "hclk_vcodec_pre", 0,
 380                 RK3288_CLKGATE_CON(9), 1, GFLAGS),
 381
 382         COMPOSITE(0, "aclk_vio0", mux_pll_src_cpll_gpll_usb480m_p, CLK_IGNORE_UNUSED,
 383                         RK3288_CLKSEL_CON(31), 6, 2, MFLAGS, 0, 5, DFLAGS,
 384                         RK3288_CLKGATE_CON(3), 0, GFLAGS),
 385         DIV(0, "hclk_vio", "aclk_vio0", 0,
 386                         RK3288_CLKSEL_CON(28), 8, 5, DFLAGS),
 387         COMPOSITE(0, "aclk_vio1", mux_pll_src_cpll_gpll_usb480m_p, CLK_IGNORE_UNUSED,
 388                         RK3288_CLKSEL_CON(31), 14, 2, MFLAGS, 8, 5, DFLAGS,
 389                         RK3288_CLKGATE_CON(3), 2, GFLAGS),
 390
 391         COMPOSITE(0, "aclk_rga_pre", mux_pll_src_cpll_gpll_usb480m_p, 0,
 392                         RK3288_CLKSEL_CON(30), 6, 2, MFLAGS, 0, 5, DFLAGS,
 393                         RK3288_CLKGATE_CON(3), 5, GFLAGS),
 394         COMPOSITE(SCLK_RGA, "sclk_rga", mux_pll_src_cpll_gpll_usb480m_p, 0,
 395                         RK3288_CLKSEL_CON(30), 14, 2, MFLAGS, 8, 5, DFLAGS,
 396                         RK3288_CLKGATE_CON(3), 4, GFLAGS),
 397
 398         COMPOSITE(DCLK_VOP0, "dclk_vop0", mux_pll_src_cpll_gpll_npll_p, 0,
 399                         RK3288_CLKSEL_CON(27), 0, 2, MFLAGS, 8, 8, DFLAGS,
 400                         RK3288_CLKGATE_CON(3), 1, GFLAGS),
 401         COMPOSITE(DCLK_VOP1, "dclk_vop1", mux_pll_src_cpll_gpll_npll_p, 0,
 402                         RK3288_CLKSEL_CON(29), 6, 2, MFLAGS, 8, 8, DFLAGS,
 403                         RK3288_CLKGATE_CON(3), 3, GFLAGS),
 404
 405         COMPOSITE_NODIV(SCLK_EDP_24M, "sclk_edp_24m", mux_edp_24m_p, 0,
 406                         RK3288_CLKSEL_CON(28), 15, 1, MFLAGS,
 407                         RK3288_CLKGATE_CON(3), 12, GFLAGS),
 408         COMPOSITE(SCLK_EDP, "sclk_edp", mux_pll_src_cpll_gpll_npll_p, 0,
 409                         RK3288_CLKSEL_CON(28), 6, 2, MFLAGS, 0, 6, DFLAGS,
 410                         RK3288_CLKGATE_CON(3), 13, GFLAGS),
 411
 412         COMPOSITE(SCLK_ISP, "sclk_isp", mux_pll_src_cpll_gpll_npll_p, 0,
 413                         RK3288_CLKSEL_CON(6), 6, 2, MFLAGS, 0, 6, DFLAGS,
 414                         RK3288_CLKGATE_CON(3), 14, GFLAGS),
 415         COMPOSITE(SCLK_ISP_JPE, "sclk_isp_jpe", mux_pll_src_cpll_gpll_npll_p, 0,
 416                         RK3288_CLKSEL_CON(6), 14, 2, MFLAGS, 8, 6, DFLAGS,
 417                         RK3288_CLKGATE_CON(3), 15, GFLAGS),
 418
 419         GATE(SCLK_HDMI_HDCP, "sclk_hdmi_hdcp", "xin24m", 0,
 420                         RK3288_CLKGATE_CON(5), 12, GFLAGS),
 421         GATE(SCLK_HDMI_CEC, "sclk_hdmi_cec", "xin32k", 0,
 422                         RK3288_CLKGATE_CON(5), 11, GFLAGS),
 423
 424         COMPOSITE(ACLK_HEVC, "aclk_hevc", mux_pll_src_cpll_gpll_npll_p, 0,
 425                         RK3288_CLKSEL_CON(39), 14, 2, MFLAGS, 8, 5, DFLAGS,
 426                         RK3288_CLKGATE_CON(13), 13, GFLAGS),
 427         DIV(HCLK_HEVC, "hclk_hevc", "aclk_hevc", 0,
 428                         RK3288_CLKSEL_CON(40), 12, 2, DFLAGS),
 429
 430         COMPOSITE(SCLK_HEVC_CABAC, "sclk_hevc_cabac", mux_pll_src_cpll_gpll_npll_p, 0,
 431                         RK3288_CLKSEL_CON(42), 6, 2, MFLAGS, 0, 5, DFLAGS,
 432                         RK3288_CLKGATE_CON(13), 14, GFLAGS),
 433         COMPOSITE(SCLK_HEVC_CORE, "sclk_hevc_core", mux_pll_src_cpll_gpll_npll_p, 0,
 434                         RK3288_CLKSEL_CON(42), 14, 2, MFLAGS, 8, 5, DFLAGS,
 435                         RK3288_CLKGATE_CON(13), 15, GFLAGS),
 436
 437         COMPOSITE_NODIV(0, "vip_src", mux_pll_src_cpll_gpll_p, 0,
 438                         RK3288_CLKSEL_CON(26), 8, 1, MFLAGS,
 439                         RK3288_CLKGATE_CON(3), 7, GFLAGS),
 440         COMPOSITE_NOGATE(0, "sclk_vip_out", mux_vip_out_p, 0,
 441                         RK3288_CLKSEL_CON(26), 15, 1, MFLAGS, 9, 5, DFLAGS),
 442
 443         DIV(0, "pclk_pd_alive", "gpll", 0,
 444                         RK3288_CLKSEL_CON(33), 8, 5, DFLAGS),
 445         COMPOSITE_NOMUX(0, "pclk_pd_pmu", "gpll", CLK_IGNORE_UNUSED,
 446                         RK3288_CLKSEL_CON(33), 0, 5, DFLAGS,
 447                         RK3288_CLKGATE_CON(5), 8, GFLAGS),
 448
 449         COMPOSITE(SCLK_GPU, "sclk_gpu", mux_pll_src_cpll_gll_usb_npll_p, 0,
 450                         RK3288_CLKSEL_CON(34), 6, 2, MFLAGS, 0, 5, DFLAGS,
 451                         RK3288_CLKGATE_CON(5), 7, GFLAGS),
 452
 453         COMPOSITE(0, "aclk_peri_src", mux_pll_src_cpll_gpll_p, CLK_IGNORE_UNUSED,
 454                         RK3288_CLKSEL_CON(10), 15, 1, MFLAGS, 0, 5, DFLAGS,
 455                         RK3288_CLKGATE_CON(2), 0, GFLAGS),
 456         COMPOSITE_NOMUX(PCLK_PERI, "pclk_peri", "aclk_peri_src", 0,
 457                         RK3288_CLKSEL_CON(10), 12, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO,
 458                         RK3288_CLKGATE_CON(2), 3, GFLAGS),
 459         COMPOSITE_NOMUX(HCLK_PERI, "hclk_peri", "aclk_peri_src", CLK_IGNORE_UNUSED,
 460                         RK3288_CLKSEL_CON(10), 8, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO,
 461                         RK3288_CLKGATE_CON(2), 2, GFLAGS),
 462         GATE(ACLK_PERI, "aclk_peri", "aclk_peri_src", CLK_IGNORE_UNUSED,
 463                         RK3288_CLKGATE_CON(2), 1, GFLAGS),
 464
 465         /*
 466          * Clock-Architecture Diagram 3
 467          */
 468
 469         COMPOSITE(SCLK_SPI0, "sclk_spi0", mux_pll_src_cpll_gpll_p, 0,
 470                         RK3288_CLKSEL_CON(25), 7, 1, MFLAGS, 0, 7, DFLAGS,
 471                         RK3288_CLKGATE_CON(2), 9, GFLAGS),
 472         COMPOSITE(SCLK_SPI1, "sclk_spi1", mux_pll_src_cpll_gpll_p, 0,
 473                         RK3288_CLKSEL_CON(25), 15, 1, MFLAGS, 8, 7, DFLAGS,
 474                         RK3288_CLKGATE_CON(2), 10, GFLAGS),
 475         COMPOSITE(SCLK_SPI2, "sclk_spi2", mux_pll_src_cpll_gpll_p, 0,
 476                         RK3288_CLKSEL_CON(39), 7, 1, MFLAGS, 0, 7, DFLAGS,
 477                         RK3288_CLKGATE_CON(2), 11, GFLAGS),
 478
 479         COMPOSITE(SCLK_SDMMC, "sclk_sdmmc", mux_mmc_src_p, 0,
 480                         RK3288_CLKSEL_CON(11), 6, 2, MFLAGS, 0, 6, DFLAGS,
 481                         RK3288_CLKGATE_CON(13), 0, GFLAGS),
 482         COMPOSITE(SCLK_SDIO0, "sclk_sdio0", mux_mmc_src_p, 0,
 483                         RK3288_CLKSEL_CON(12), 6, 2, MFLAGS, 0, 6, DFLAGS,
 484                         RK3288_CLKGATE_CON(13), 1, GFLAGS),
 485         COMPOSITE(SCLK_SDIO1, "sclk_sdio1", mux_mmc_src_p, 0,
 486                         RK3288_CLKSEL_CON(34), 14, 2, MFLAGS, 8, 6, DFLAGS,
 487                         RK3288_CLKGATE_CON(13), 2, GFLAGS),
 488         COMPOSITE(SCLK_EMMC, "sclk_emmc", mux_mmc_src_p, 0,
 489                         RK3288_CLKSEL_CON(12), 14, 2, MFLAGS, 8, 6, DFLAGS,
 490                         RK3288_CLKGATE_CON(13), 3, GFLAGS),
 491
 492         MMC(SCLK_SDMMC_DRV,    "sdmmc_drv",    "sclk_sdmmc", RK3288_SDMMC_CON0, 1),
 493         MMC(SCLK_SDMMC_SAMPLE, "sdmmc_sample", "sclk_sdmmc", RK3288_SDMMC_CON1, 0),
 494
 495         MMC(SCLK_SDIO0_DRV,    "sdio0_drv",    "sclk_sdio0", RK3288_SDIO0_CON0, 1),
 496         MMC(SCLK_SDIO0_SAMPLE, "sdio0_sample", "sclk_sdio0", RK3288_SDIO0_CON1, 0),
 497
 498         MMC(SCLK_SDIO1_DRV,    "sdio1_drv",    "sclk_sdio1", RK3288_SDIO1_CON0, 1),
 499         MMC(SCLK_SDIO1_SAMPLE, "sdio1_sample", "sclk_sdio1", RK3288_SDIO1_CON1, 0),
 500
 501         MMC(SCLK_EMMC_DRV,     "emmc_drv",     "sclk_emmc",  RK3288_EMMC_CON0,  1),
 502         MMC(SCLK_EMMC_SAMPLE,  "emmc_sample",  "sclk_emmc",  RK3288_EMMC_CON1,  0),
 503
 504         COMPOSITE(0, "sclk_tspout", mux_tspout_p, 0,
 505                         RK3288_CLKSEL_CON(35), 14, 2, MFLAGS, 8, 5, DFLAGS,
 506                         RK3288_CLKGATE_CON(4), 11, GFLAGS),
 507         COMPOSITE(0, "sclk_tsp", mux_pll_src_cpll_gpll_npll_p, 0,
 508                         RK3288_CLKSEL_CON(35), 6, 2, MFLAGS, 0, 5, DFLAGS,
 509                         RK3288_CLKGATE_CON(4), 10, GFLAGS),
 510
 511         GATE(SCLK_OTGPHY0, "sclk_otgphy0", "usb480m", CLK_IGNORE_UNUSED,
 512                         RK3288_CLKGATE_CON(13), 4, GFLAGS),
 513         GATE(SCLK_OTGPHY1, "sclk_otgphy1", "usb480m", CLK_IGNORE_UNUSED,
 514                         RK3288_CLKGATE_CON(13), 5, GFLAGS),
 515         GATE(SCLK_OTGPHY2, "sclk_otgphy2", "usb480m", CLK_IGNORE_UNUSED,
 516                         RK3288_CLKGATE_CON(13), 6, GFLAGS),
 517         GATE(SCLK_OTG_ADP, "sclk_otg_adp", "xin32k", CLK_IGNORE_UNUSED,
 518                         RK3288_CLKGATE_CON(13), 7, GFLAGS),
 519
 520         COMPOSITE_NOMUX(SCLK_TSADC, "sclk_tsadc", "xin32k", 0,
 521                         RK3288_CLKSEL_CON(2), 0, 6, DFLAGS,
 522                         RK3288_CLKGATE_CON(2), 7, GFLAGS),
 523
 524         COMPOSITE_NOMUX(SCLK_SARADC, "sclk_saradc", "xin24m", 0,
 525                         RK3288_CLKSEL_CON(24), 8, 8, DFLAGS,
 526                         RK3288_CLKGATE_CON(2), 8, GFLAGS),
 527
 528         GATE(SCLK_PS2C, "sclk_ps2c", "xin24m", 0,
 529                         RK3288_CLKGATE_CON(5), 13, GFLAGS),
 530
 531         COMPOSITE(SCLK_NANDC0, "sclk_nandc0", mux_pll_src_cpll_gpll_p, 0,
 532                         RK3288_CLKSEL_CON(38), 7, 1, MFLAGS, 0, 5, DFLAGS,
 533                         RK3288_CLKGATE_CON(5), 5, GFLAGS),
 534         COMPOSITE(SCLK_NANDC1, "sclk_nandc1", mux_pll_src_cpll_gpll_p, 0,
 535                         RK3288_CLKSEL_CON(38), 15, 1, MFLAGS, 8, 5, DFLAGS,
 536                         RK3288_CLKGATE_CON(5), 6, GFLAGS),
 537
 538         COMPOSITE(0, "uart0_src", mux_pll_src_cpll_gll_usb_npll_p, 0,
 539                         RK3288_CLKSEL_CON(13), 13, 2, MFLAGS, 0, 7, DFLAGS,
 540                         RK3288_CLKGATE_CON(1), 8, GFLAGS),
 541         COMPOSITE_FRACMUX(0, "uart0_frac", "uart0_src", CLK_SET_RATE_PARENT,
 542                         RK3288_CLKSEL_CON(17), 0,
 543                         RK3288_CLKGATE_CON(1), 9, GFLAGS,
 544                 MUX(SCLK_UART0, "sclk_uart0", mux_uart0_p, CLK_SET_RATE_PARENT,
 545                                 RK3288_CLKSEL_CON(13), 8, 2, MFLAGS)),
 546         MUX(0, "uart_src", mux_pll_src_cpll_gpll_p, 0,
 547                         RK3288_CLKSEL_CON(13), 15, 1, MFLAGS),
 548         COMPOSITE_NOMUX(0, "uart1_src", "uart_src", 0,
 549                         RK3288_CLKSEL_CON(14), 0, 7, DFLAGS,
 550                         RK3288_CLKGATE_CON(1), 10, GFLAGS),
 551         COMPOSITE_FRACMUX(0, "uart1_frac", "uart1_src", CLK_SET_RATE_PARENT,
 552                         RK3288_CLKSEL_CON(18), 0,
 553                         RK3288_CLKGATE_CON(1), 11, GFLAGS,
 554                 MUX(SCLK_UART1, "sclk_uart1", mux_uart1_p, CLK_SET_RATE_PARENT,
 555                                 RK3288_CLKSEL_CON(14), 8, 2, MFLAGS)),
 556         COMPOSITE_NOMUX(0, "uart2_src", "uart_src", 0,
 557                         RK3288_CLKSEL_CON(15), 0, 7, DFLAGS,
 558                         RK3288_CLKGATE_CON(1), 12, GFLAGS),
 559         COMPOSITE_FRACMUX(0, "uart2_frac", "uart2_src", CLK_SET_RATE_PARENT,
 560                         RK3288_CLKSEL_CON(19), 0,
 561                         RK3288_CLKGATE_CON(1), 13, GFLAGS,
 562                 MUX(SCLK_UART2, "sclk_uart2", mux_uart2_p, CLK_SET_RATE_PARENT,
 563                                 RK3288_CLKSEL_CON(15), 8, 2, MFLAGS)),
 564         COMPOSITE_NOMUX(0, "uart3_src", "uart_src", 0,
 565                         RK3288_CLKSEL_CON(16), 0, 7, DFLAGS,
 566                         RK3288_CLKGATE_CON(1), 14, GFLAGS),
 567         COMPOSITE_FRACMUX(0, "uart3_frac", "uart3_src", CLK_SET_RATE_PARENT,
 568                         RK3288_CLKSEL_CON(20), 0,
 569                         RK3288_CLKGATE_CON(1), 15, GFLAGS,
 570                 MUX(SCLK_UART3, "sclk_uart3", mux_uart3_p, CLK_SET_RATE_PARENT,
 571                                 RK3288_CLKSEL_CON(16), 8, 2, MFLAGS)),
 572         COMPOSITE_NOMUX(0, "uart4_src", "uart_src", 0,
 573                         RK3288_CLKSEL_CON(3), 0, 7, DFLAGS,
 574                         RK3288_CLKGATE_CON(2), 12, GFLAGS),
 575         COMPOSITE_FRACMUX(0, "uart4_frac", "uart4_src", CLK_SET_RATE_PARENT,
 576                         RK3288_CLKSEL_CON(7), 0,
 577                         RK3288_CLKGATE_CON(2), 13, GFLAGS,
 578                 MUX(SCLK_UART4, "sclk_uart4", mux_uart4_p, CLK_SET_RATE_PARENT,
 579                                 RK3288_CLKSEL_CON(3), 8, 2, MFLAGS)),
 580
 581         COMPOSITE(0, "mac_pll_src", mux_pll_src_npll_cpll_gpll_p, 0,
 582                         RK3288_CLKSEL_CON(21), 0, 2, MFLAGS, 8, 5, DFLAGS,
 583                         RK3288_CLKGATE_CON(2), 5, GFLAGS),
 584         MUX(SCLK_MAC, "mac_clk", mux_mac_p, CLK_SET_RATE_PARENT,
 585                         RK3288_CLKSEL_CON(21), 4, 1, MFLAGS),
 586         GATE(SCLK_MACREF_OUT, "sclk_macref_out", "mac_clk", 0,
 587                         RK3288_CLKGATE_CON(5), 3, GFLAGS),
 588         GATE(SCLK_MACREF, "sclk_macref", "mac_clk", 0,
 589                         RK3288_CLKGATE_CON(5), 2, GFLAGS),
 590         GATE(SCLK_MAC_RX, "sclk_mac_rx", "mac_clk", 0,
 591                         RK3288_CLKGATE_CON(5), 0, GFLAGS),
 592         GATE(SCLK_MAC_TX, "sclk_mac_tx", "mac_clk", 0,
 593                         RK3288_CLKGATE_CON(5), 1, GFLAGS),
 594
 595         COMPOSITE(0, "hsadc_src", mux_pll_src_cpll_gpll_p, 0,
 596                         RK3288_CLKSEL_CON(22), 0, 1, MFLAGS, 8, 8, DFLAGS,
 597                         RK3288_CLKGATE_CON(2), 6, GFLAGS),
 598         MUX(0, "sclk_hsadc_out", mux_hsadcout_p, 0,
 599                         RK3288_CLKSEL_CON(22), 4, 1, MFLAGS),
 600         INVERTER(SCLK_HSADC, "sclk_hsadc", "sclk_hsadc_out",
 601                         RK3288_CLKSEL_CON(22), 7, IFLAGS),
 602
 603         GATE(0, "jtag", "ext_jtag", 0,
 604                         RK3288_CLKGATE_CON(4), 14, GFLAGS),
 605
 606         COMPOSITE_NODIV(SCLK_USBPHY480M_SRC, "usbphy480m_src", mux_usbphy480m_p, 0,
 607                         RK3288_CLKSEL_CON(13), 11, 2, MFLAGS,
 608                         RK3288_CLKGATE_CON(5), 14, GFLAGS),
 609         COMPOSITE_NODIV(SCLK_HSICPHY480M, "sclk_hsicphy480m", mux_hsicphy480m_p, 0,
 610                         RK3288_CLKSEL_CON(29), 0, 2, MFLAGS,
 611                         RK3288_CLKGATE_CON(3), 6, GFLAGS),
 612         GATE(0, "hsicphy12m_xin12m", "xin12m", 0,
 613                         RK3288_CLKGATE_CON(13), 9, GFLAGS),
 614         DIV(0, "hsicphy12m_usbphy", "sclk_hsicphy480m", 0,
 615                         RK3288_CLKSEL_CON(11), 8, 6, DFLAGS),
 616         MUX(SCLK_HSICPHY12M, "sclk_hsicphy12m", mux_hsicphy12m_p, 0,
 617                         RK3288_CLKSEL_CON(22), 4, 1, MFLAGS),
 618
 619         /*
 620          * Clock-Architecture Diagram 4
 621          */
 622
 623         /* aclk_cpu gates */
 624         GATE(0, "sclk_intmem0", "aclk_cpu", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(10), 5, GFLAGS),
 625         GATE(0, "sclk_intmem1", "aclk_cpu", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(10), 6, GFLAGS),
 626         GATE(0, "sclk_intmem2", "aclk_cpu", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(10), 7, GFLAGS),
 627         GATE(ACLK_DMAC1, "aclk_dmac1", "aclk_cpu", 0, RK3288_CLKGATE_CON(10), 12, GFLAGS),
 628         GATE(0, "aclk_strc_sys", "aclk_cpu", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(10), 13, GFLAGS),
 629         GATE(0, "aclk_intmem", "aclk_cpu", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(10), 4, GFLAGS),
 630         GATE(ACLK_CRYPTO, "aclk_crypto", "aclk_cpu", 0, RK3288_CLKGATE_CON(11), 6, GFLAGS),
 631         GATE(0, "aclk_ccp", "aclk_cpu", 0, RK3288_CLKGATE_CON(11), 8, GFLAGS),
 632
 633         /* hclk_cpu gates */
 634         GATE(HCLK_CRYPTO, "hclk_crypto", "hclk_cpu", 0, RK3288_CLKGATE_CON(11), 7, GFLAGS),
 635         GATE(HCLK_I2S0, "hclk_i2s0", "hclk_cpu", 0, RK3288_CLKGATE_CON(10), 8, GFLAGS),
 636         GATE(HCLK_ROM, "hclk_rom", "hclk_cpu", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(10), 9, GFLAGS),
 637         GATE(HCLK_SPDIF, "hclk_spdif", "hclk_cpu", 0, RK3288_CLKGATE_CON(10), 10, GFLAGS),
 638         GATE(HCLK_SPDIF8CH, "hclk_spdif_8ch", "hclk_cpu", 0, RK3288_CLKGATE_CON(10), 11, GFLAGS),
 639
 640         /* pclk_cpu gates */
 641         GATE(PCLK_PWM, "pclk_pwm", "pclk_cpu", 0, RK3288_CLKGATE_CON(10), 0, GFLAGS),
 642         GATE(PCLK_TIMER, "pclk_timer", "pclk_cpu", 0, RK3288_CLKGATE_CON(10), 1, GFLAGS),
 643         GATE(PCLK_I2C0, "pclk_i2c0", "pclk_cpu", 0, RK3288_CLKGATE_CON(10), 2, GFLAGS),
 644         GATE(PCLK_I2C2, "pclk_i2c2", "pclk_cpu", 0, RK3288_CLKGATE_CON(10), 3, GFLAGS),
 645         GATE(PCLK_DDRUPCTL0, "pclk_ddrupctl0", "pclk_cpu", 0, RK3288_CLKGATE_CON(10), 14, GFLAGS),
 646         GATE(PCLK_PUBL0, "pclk_publ0", "pclk_cpu", 0, RK3288_CLKGATE_CON(10), 15, GFLAGS),
 647         GATE(PCLK_DDRUPCTL1, "pclk_ddrupctl1", "pclk_cpu", 0, RK3288_CLKGATE_CON(11), 0, GFLAGS),
 648         GATE(PCLK_PUBL1, "pclk_publ1", "pclk_cpu", 0, RK3288_CLKGATE_CON(11), 1, GFLAGS),
 649         GATE(0, "pclk_efuse_1024", "pclk_cpu", 0, RK3288_CLKGATE_CON(11), 2, GFLAGS),
 650         GATE(PCLK_TZPC, "pclk_tzpc", "pclk_cpu", 0, RK3288_CLKGATE_CON(11), 3, GFLAGS),
 651         GATE(PCLK_UART2, "pclk_uart2", "pclk_cpu", 0, RK3288_CLKGATE_CON(11), 9, GFLAGS),
 652         GATE(0, "pclk_efuse_256", "pclk_cpu", 0, RK3288_CLKGATE_CON(11), 10, GFLAGS),
 653         GATE(PCLK_RKPWM, "pclk_rkpwm", "pclk_cpu", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(11), 11, GFLAGS),
 654
 655         /* ddrctrl [DDR Controller PHY clock] gates */
 656         GATE(0, "nclk_ddrupctl0", "ddrphy", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(11), 4, GFLAGS),
 657         GATE(0, "nclk_ddrupctl1", "ddrphy", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(11), 5, GFLAGS),
 658
 659         /* ddrphy gates */
 660         GATE(0, "sclk_ddrphy0", "ddrphy", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(4), 12, GFLAGS),
 661         GATE(0, "sclk_ddrphy1", "ddrphy", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(4), 13, GFLAGS),
 662
 663         /* aclk_peri gates */
 664         GATE(0, "aclk_peri_axi_matrix", "aclk_peri", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(6), 2, GFLAGS),
 665         GATE(ACLK_DMAC2, "aclk_dmac2", "aclk_peri", 0, RK3288_CLKGATE_CON(6), 3, GFLAGS),
 666         GATE(0, "aclk_peri_niu", "aclk_peri", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(7), 11, GFLAGS),
 667         GATE(ACLK_MMU, "aclk_mmu", "aclk_peri", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(8), 12, GFLAGS),
 668         GATE(ACLK_GMAC, "aclk_gmac", "aclk_peri", 0, RK3288_CLKGATE_CON(8), 0, GFLAGS),
 669         GATE(HCLK_GPS, "hclk_gps", "aclk_peri", 0, RK3288_CLKGATE_CON(8), 2, GFLAGS),
 670
 671         /* hclk_peri gates */
 672         GATE(0, "hclk_peri_matrix", "hclk_peri", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(6), 0, GFLAGS),
 673         GATE(HCLK_OTG0, "hclk_otg0", "hclk_peri", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(7), 4, GFLAGS),
 674         GATE(HCLK_USBHOST0, "hclk_host0", "hclk_peri", 0, RK3288_CLKGATE_CON(7), 6, GFLAGS),
 675         GATE(HCLK_USBHOST1, "hclk_host1", "hclk_peri", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(7), 7, GFLAGS),
 676         GATE(HCLK_HSIC, "hclk_hsic", "hclk_peri", 0, RK3288_CLKGATE_CON(7), 8, GFLAGS),
 677         GATE(0, "hclk_usb_peri", "hclk_peri", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(7), 9, GFLAGS),
 678         GATE(0, "hclk_peri_ahb_arbi", "hclk_peri", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(7), 10, GFLAGS),
 679         GATE(0, "hclk_emem", "hclk_peri", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(7), 12, GFLAGS),
 680         GATE(0, "hclk_mem", "hclk_peri", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(7), 13, GFLAGS),
 681         GATE(HCLK_NANDC0, "hclk_nandc0", "hclk_peri", 0, RK3288_CLKGATE_CON(7), 14, GFLAGS),
 682         GATE(HCLK_NANDC1, "hclk_nandc1", "hclk_peri", 0, RK3288_CLKGATE_CON(7), 15, GFLAGS),
 683         GATE(HCLK_TSP, "hclk_tsp", "hclk_peri", 0, RK3288_CLKGATE_CON(8), 8, GFLAGS),
 684         GATE(HCLK_SDMMC, "hclk_sdmmc", "hclk_peri", 0, RK3288_CLKGATE_CON(8), 3, GFLAGS),
 685         GATE(HCLK_SDIO0, "hclk_sdio0", "hclk_peri", 0, RK3288_CLKGATE_CON(8), 4, GFLAGS),
 686         GATE(HCLK_SDIO1, "hclk_sdio1", "hclk_peri", 0, RK3288_CLKGATE_CON(8), 5, GFLAGS),
 687         GATE(HCLK_EMMC, "hclk_emmc", "hclk_peri", 0, RK3288_CLKGATE_CON(8), 6, GFLAGS),
 688         GATE(HCLK_HSADC, "hclk_hsadc", "hclk_peri", 0, RK3288_CLKGATE_CON(8), 7, GFLAGS),
 689         GATE(0, "pmu_hclk_otg0", "hclk_peri", 0, RK3288_CLKGATE_CON(7), 5, GFLAGS),
 690
 691         /* pclk_peri gates */
 692         GATE(0, "pclk_peri_matrix", "pclk_peri", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(6), 1, GFLAGS),
 693         GATE(PCLK_SPI0, "pclk_spi0", "pclk_peri", 0, RK3288_CLKGATE_CON(6), 4, GFLAGS),
 694         GATE(PCLK_SPI1, "pclk_spi1", "pclk_peri", 0, RK3288_CLKGATE_CON(6), 5, GFLAGS),
 695         GATE(PCLK_SPI2, "pclk_spi2", "pclk_peri", 0, RK3288_CLKGATE_CON(6), 6, GFLAGS),
 696         GATE(PCLK_PS2C, "pclk_ps2c", "pclk_peri", 0, RK3288_CLKGATE_CON(6), 7, GFLAGS),
 697         GATE(PCLK_UART0, "pclk_uart0", "pclk_peri", 0, RK3288_CLKGATE_CON(6), 8, GFLAGS),
 698         GATE(PCLK_UART1, "pclk_uart1", "pclk_peri", 0, RK3288_CLKGATE_CON(6), 9, GFLAGS),
 699         GATE(PCLK_I2C4, "pclk_i2c4", "pclk_peri", 0, RK3288_CLKGATE_CON(6), 15, GFLAGS),
 700         GATE(PCLK_UART3, "pclk_uart3", "pclk_peri", 0, RK3288_CLKGATE_CON(6), 11, GFLAGS),
 701         GATE(PCLK_UART4, "pclk_uart4", "pclk_peri", 0, RK3288_CLKGATE_CON(6), 12, GFLAGS),
 702         GATE(PCLK_I2C1, "pclk_i2c1", "pclk_peri", 0, RK3288_CLKGATE_CON(6), 13, GFLAGS),
 703         GATE(PCLK_I2C3, "pclk_i2c3", "pclk_peri", 0, RK3288_CLKGATE_CON(6), 14, GFLAGS),
 704         GATE(PCLK_SARADC, "pclk_saradc", "pclk_peri", 0, RK3288_CLKGATE_CON(7), 1, GFLAGS),
 705         GATE(PCLK_TSADC, "pclk_tsadc", "pclk_peri", 0, RK3288_CLKGATE_CON(7), 2, GFLAGS),
 706         GATE(PCLK_SIM, "pclk_sim", "pclk_peri", 0, RK3288_CLKGATE_CON(7), 3, GFLAGS),
 707         GATE(PCLK_I2C5, "pclk_i2c5", "pclk_peri", 0, RK3288_CLKGATE_CON(7), 0, GFLAGS),
 708         GATE(PCLK_GMAC, "pclk_gmac", "pclk_peri", 0, RK3288_CLKGATE_CON(8), 1, GFLAGS),
 709
 710         GATE(SCLK_LCDC_PWM0, "sclk_lcdc_pwm0", "xin24m", 0, RK3288_CLKGATE_CON(13), 10, GFLAGS),
 711         GATE(SCLK_LCDC_PWM1, "sclk_lcdc_pwm1", "xin24m", 0, RK3288_CLKGATE_CON(13), 11, GFLAGS),
 712         GATE(SCLK_PVTM_CORE, "sclk_pvtm_core", "xin24m", 0, RK3288_CLKGATE_CON(5), 9, GFLAGS),
 713         GATE(SCLK_PVTM_GPU, "sclk_pvtm_gpu", "xin24m", 0, RK3288_CLKGATE_CON(5), 10, GFLAGS),
 714         GATE(0, "sclk_mipidsi_24m", "xin24m", 0, RK3288_CLKGATE_CON(5), 15, GFLAGS),
 715
 716         /* sclk_gpu gates */
 717         GATE(ACLK_GPU, "aclk_gpu", "sclk_gpu", 0, RK3288_CLKGATE_CON(18), 0, GFLAGS),
 718
 719         /* pclk_pd_alive gates */
 720         GATE(PCLK_GPIO8, "pclk_gpio8", "pclk_pd_alive", 0, RK3288_CLKGATE_CON(14), 8, GFLAGS),
 721         GATE(PCLK_GPIO7, "pclk_gpio7", "pclk_pd_alive", 0, RK3288_CLKGATE_CON(14), 7, GFLAGS),
 722         GATE(PCLK_GPIO1, "pclk_gpio1", "pclk_pd_alive", 0, RK3288_CLKGATE_CON(14), 1, GFLAGS),
 723         GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_pd_alive", 0, RK3288_CLKGATE_CON(14), 2, GFLAGS),
 724         GATE(PCLK_GPIO3, "pclk_gpio3", "pclk_pd_alive", 0, RK3288_CLKGATE_CON(14), 3, GFLAGS),
 725         GATE(PCLK_GPIO4, "pclk_gpio4", "pclk_pd_alive", 0, RK3288_CLKGATE_CON(14), 4, GFLAGS),
 726         GATE(PCLK_GPIO5, "pclk_gpio5", "pclk_pd_alive", 0, RK3288_CLKGATE_CON(14), 5, GFLAGS),
 727         GATE(PCLK_GPIO6, "pclk_gpio6", "pclk_pd_alive", 0, RK3288_CLKGATE_CON(14), 6, GFLAGS),
 728         GATE(PCLK_GRF, "pclk_grf", "pclk_pd_alive", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(14), 11, GFLAGS),
 729         GATE(0, "pclk_alive_niu", "pclk_pd_alive", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(14), 12, GFLAGS),
 730
 731         /* pclk_pd_pmu gates */
 732         GATE(PCLK_PMU, "pclk_pmu", "pclk_pd_pmu", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(17), 0, GFLAGS),
 733         GATE(0, "pclk_intmem1", "pclk_pd_pmu", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(17), 1, GFLAGS),
 734         GATE(0, "pclk_pmu_niu", "pclk_pd_pmu", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(17), 2, GFLAGS),
 735         GATE(PCLK_SGRF, "pclk_sgrf", "pclk_pd_pmu", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(17), 3, GFLAGS),
 736         GATE(PCLK_GPIO0, "pclk_gpio0", "pclk_pd_pmu", 0, RK3288_CLKGATE_CON(17), 4, GFLAGS),
 737
 738         /* hclk_vio gates */
 739         GATE(HCLK_RGA, "hclk_rga", "hclk_vio", 0, RK3288_CLKGATE_CON(15), 1, GFLAGS),
 740         GATE(HCLK_VOP0, "hclk_vop0", "hclk_vio", 0, RK3288_CLKGATE_CON(15), 6, GFLAGS),
 741         GATE(HCLK_VOP1, "hclk_vop1", "hclk_vio", 0, RK3288_CLKGATE_CON(15), 8, GFLAGS),
 742         GATE(HCLK_VIO_AHB_ARBI, "hclk_vio_ahb_arbi", "hclk_vio", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(15), 9, GFLAGS),
 743         GATE(HCLK_VIO_NIU, "hclk_vio_niu", "hclk_vio", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(15), 10, GFLAGS),
 744         GATE(HCLK_VIP, "hclk_vip", "hclk_vio", 0, RK3288_CLKGATE_CON(15), 15, GFLAGS),
 745         GATE(HCLK_IEP, "hclk_iep", "hclk_vio", 0, RK3288_CLKGATE_CON(15), 3, GFLAGS),
 746         GATE(HCLK_ISP, "hclk_isp", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 1, GFLAGS),
 747         GATE(HCLK_VIO2_H2P, "hclk_vio2_h2p", "hclk_vio", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(16), 10, GFLAGS),
 748         GATE(PCLK_MIPI_DSI0, "pclk_mipi_dsi0", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 4, GFLAGS),
 749         GATE(PCLK_MIPI_DSI1, "pclk_mipi_dsi1", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 5, GFLAGS),
 750         GATE(PCLK_MIPI_CSI, "pclk_mipi_csi", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 6, GFLAGS),
 751         GATE(PCLK_LVDS_PHY, "pclk_lvds_phy", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 7, GFLAGS),
 752         GATE(PCLK_EDP_CTRL, "pclk_edp_ctrl", "hclk_vio", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(16), 8, GFLAGS),
 753         GATE(PCLK_HDMI_CTRL, "pclk_hdmi_ctrl", "hclk_vio", 0, RK3288_CLKGATE_CON(16), 9, GFLAGS),
 754         GATE(PCLK_VIO2_H2P, "pclk_vio2_h2p", "hclk_vio", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(16), 11, GFLAGS),
 755
 756         /* aclk_vio0 gates */
 757         GATE(ACLK_VOP0, "aclk_vop0", "aclk_vio0", 0, RK3288_CLKGATE_CON(15), 5, GFLAGS),
 758         GATE(ACLK_IEP, "aclk_iep", "aclk_vio0", 0, RK3288_CLKGATE_CON(15), 2, GFLAGS),
 759         GATE(ACLK_VIO0_NIU, "aclk_vio0_niu", "aclk_vio0", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(15), 11, GFLAGS),
 760         GATE(ACLK_VIP, "aclk_vip", "aclk_vio0", 0, RK3288_CLKGATE_CON(15), 14, GFLAGS),
 761
 762         /* aclk_vio1 gates */
 763         GATE(ACLK_VOP1, "aclk_vop1", "aclk_vio1", 0, RK3288_CLKGATE_CON(15), 7, GFLAGS),
 764         GATE(ACLK_ISP, "aclk_isp", "aclk_vio1", 0, RK3288_CLKGATE_CON(16), 2, GFLAGS),
 765         GATE(ACLK_VIO1_NIU, "aclk_vio1_niu", "aclk_vio1", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(15), 12, GFLAGS),
 766
 767         /* aclk_rga_pre gates */
 768         GATE(ACLK_RGA, "aclk_rga", "aclk_rga_pre", 0, RK3288_CLKGATE_CON(15), 0, GFLAGS),
 769         GATE(ACLK_RGA_NIU, "aclk_rga_niu", "aclk_rga_pre", CLK_IGNORE_UNUSED, RK3288_CLKGATE_CON(15), 13, GFLAGS),
 770
 771         /*
 772          * Other ungrouped clocks.
 773          */
 774
 775         GATE(0, "pclk_vip_in", "ext_vip", 0, RK3288_CLKGATE_CON(16), 0, GFLAGS),
 776         INVERTER(0, "pclk_vip", "pclk_vip_in", RK3288_CLKSEL_CON(29), 4, IFLAGS),
 777         GATE(0, "pclk_isp_in", "ext_isp", 0, RK3288_CLKGATE_CON(16), 3, GFLAGS),
 778         INVERTER(0, "pclk_isp", "pclk_isp_in", RK3288_CLKSEL_CON(29), 3, IFLAGS),
 779 };
 780
 781 static const char *const rk3288_critical_clocks[] __initconst = {
 782         "aclk_cpu",
 783         "aclk_peri",
 784         "hclk_peri",
 785         "pclk_pd_pmu",
 786 };
 787
 788 #ifdef CONFIG_PM_SLEEP
 789 static void __iomem *rk3288_cru_base;
 790
 791 /* Some CRU registers will be reset in maskrom when the system
 792  * wakes up from fastboot.
 793  * So save them before suspend, restore them after resume.
 794  */
 795 static const int rk3288_saved_cru_reg_ids[] = {
 796         RK3288_MODE_CON,
 797         RK3288_CLKSEL_CON(0),
 798         RK3288_CLKSEL_CON(1),
 799         RK3288_CLKSEL_CON(10),
 800         RK3288_CLKSEL_CON(33),
 801         RK3288_CLKSEL_CON(37),
 802 };
 803
 804 static u32 rk3288_saved_cru_regs[ARRAY_SIZE(rk3288_saved_cru_reg_ids)];
 805
 806 static int rk3288_clk_suspend(void)
 807 {
 808         int i, reg_id;
 809
 810         for (i = 0; i < ARRAY_SIZE(rk3288_saved_cru_reg_ids); i++) {
 811                 reg_id = rk3288_saved_cru_reg_ids[i];
 812
 813                 rk3288_saved_cru_regs[i] =
 814                                 readl_relaxed(rk3288_cru_base + reg_id);
 815         }
 816
 817         /*
 818          * Switch PLLs other than DPLL (for SDRAM) to slow mode to
 819          * avoid crashes on resume. The Mask ROM on the system will
 820          * put APLL, CPLL, and GPLL into slow mode at resume time
 821          * anyway (which is why we restore them), but we might not
 822          * even make it to the Mask ROM if this isn't done at suspend
 823          * time.
 824          *
 825          * NOTE: only APLL truly matters here, but we'll do them all.
 826          */
 827
 828         writel_relaxed(0xf3030000, rk3288_cru_base + RK3288_MODE_CON);
 829
 830         return 0;
 831 }
 832
 833 static void rk3288_clk_resume(void)
 834 {
 835         int i, reg_id;
 836
 837         for (i = ARRAY_SIZE(rk3288_saved_cru_reg_ids) - 1; i >= 0; i--) {
 838                 reg_id = rk3288_saved_cru_reg_ids[i];
 839
 840                 writel_relaxed(rk3288_saved_cru_regs[i] | 0xffff0000,
 841                                rk3288_cru_base + reg_id);
 842         }
 843 }
 844
 845 static struct syscore_ops rk3288_clk_syscore_ops = {
 846         .suspend = rk3288_clk_suspend,
 847         .resume = rk3288_clk_resume,
 848 };
 849
 850 static void rk3288_clk_sleep_init(void __iomem *reg_base)
 851 {
 852         rk3288_cru_base = reg_base;
 853         register_syscore_ops(&rk3288_clk_syscore_ops);
 854 }
 855
 856 #else /* CONFIG_PM_SLEEP */
 857 static void rk3288_clk_sleep_init(void __iomem *reg_base) {}
 858 #endif
 859
 860 static void __init rk3288_clk_init(struct device_node *np)
 861 {
 862         void __iomem *reg_base;
 863         struct clk *clk;
 864
 865         reg_base = of_iomap(np, 0);
 866         if (!reg_base) {
 867                 pr_err("%s: could not map cru region\n", __func__);
 868                 return;
 869         }
 870
 871         rockchip_clk_init(np, reg_base, CLK_NR_CLKS);
 872
 873         /* xin12m is created by an cru-internal divider */
 874         clk = clk_register_fixed_factor(NULL, "xin12m", "xin24m", 0, 1, 2);
 875         if (IS_ERR(clk))
 876                 pr_warn("%s: could not register clock xin12m: %ld\n",
 877                         __func__, PTR_ERR(clk));
 878
 879
 880         clk = clk_register_fixed_factor(NULL, "usb480m", "xin24m", 0, 20, 1);
 881         if (IS_ERR(clk))
 882                 pr_warn("%s: could not register clock usb480m: %ld\n",
 883                         __func__, PTR_ERR(clk));
 884
 885         clk = clk_register_fixed_factor(NULL, "hclk_vcodec_pre",
 886                                         "hclk_vcodec_pre_v", 0, 1, 4);
 887         if (IS_ERR(clk))
 888                 pr_warn("%s: could not register clock hclk_vcodec_pre: %ld\n",
 889                         __func__, PTR_ERR(clk));
 890
 891         /* Watchdog pclk is controlled by RK3288_SGRF_SOC_CON0[1]. */
 892         clk = clk_register_fixed_factor(NULL, "pclk_wdt", "pclk_pd_alive", 0, 1, 1);
 893         if (IS_ERR(clk))
 894                 pr_warn("%s: could not register clock pclk_wdt: %ld\n",
 895                         __func__, PTR_ERR(clk));
 896         else
 897                 rockchip_clk_add_lookup(clk, PCLK_WDT);
 898
 899         rockchip_clk_register_plls(rk3288_pll_clks,
 900                                    ARRAY_SIZE(rk3288_pll_clks),
 901                                    RK3288_GRF_SOC_STATUS1);
 902         rockchip_clk_register_branches(rk3288_clk_branches,
 903                                   ARRAY_SIZE(rk3288_clk_branches));
 904         rockchip_clk_protect_critical(rk3288_critical_clocks,
 905                                       ARRAY_SIZE(rk3288_critical_clocks));
 906
 907         rockchip_clk_register_armclk(ARMCLK, "armclk",
 908                         mux_armclk_p, ARRAY_SIZE(mux_armclk_p),
 909                         &rk3288_cpuclk_data, rk3288_cpuclk_rates,
 910                         ARRAY_SIZE(rk3288_cpuclk_rates));
 911
 912         rockchip_register_softrst(np, 12, reg_base + RK3288_SOFTRST_CON(0),
 913                                   ROCKCHIP_SOFTRST_HIWORD_MASK);
 914
 915         rockchip_register_restart_notifier(RK3288_GLB_SRST_FST);
 916         rk3288_clk_sleep_init(reg_base);
 917 }
 918 CLK_OF_DECLARE(rk3288_cru, "rockchip,rk3288-cru", rk3288_clk_init);