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5 <title>The LLVM Target-Independent Code Generator</title>
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10 <div class="doc_title">
11 The LLVM Target-Independent Code Generator
15 <li><a href="#introduction">Introduction</a>
17 <li><a href="#required">Required components in the code generator</a></li>
18 <li><a href="#high-level-design">The high-level design of the code generator</a></li>
19 <li><a href="#tablegen">Using TableGen for target description</a></li>
22 <li><a href="#targetdesc">Target description classes</a>
24 <li><a href="#targetmachine">The <tt>TargetMachine</tt> class</a></li>
25 <li><a href="#targetdata">The <tt>TargetData</tt> class</a></li>
26 <li><a href="#mregisterinfo">The <tt>MRegisterInfo</tt> class</a></li>
27 <li><a href="#targetinstrinfo">The <tt>TargetInstrInfo</tt> class</a></li>
28 <li><a href="#targetframeinfo">The <tt>TargetFrameInfo</tt> class</a></li>
29 <li><a href="#targetjitinfo">The <tt>TargetJITInfo</tt> class</a></li>
32 <li><a href="#codegendesc">Machine code description classes</a>
34 <li><a href="#codegenalgs">Target-independent code generation algorithms</a>
36 <li><a href="#targetimpls">Target description implementations</a>
38 <li><a href="#x86">The X86 backend</a></li>
44 <div class="doc_author">
45 <p>Written by <a href="mailto:sabre@nondot.org">Chris Lattner</a></p>
48 <!-- *********************************************************************** -->
49 <div class="doc_section">
50 <a name="introduction">Introduction</a>
52 <!-- *********************************************************************** -->
54 <div class="doc_text">
56 <p>The LLVM target-independent code generator is a framework that provides a
57 suite of reusable components for translating the LLVM internal representation to
58 the machine code for a specified target -- either in assembly form (suitable for
59 a static compiler) or in binary machine code format (usable for a JIT compiler).
60 The LLVM target-independent code generator consists of four main components:</p>
63 <li><a href="#targetdesc">Abstract target description</a> interfaces which
64 capture improtant properties about various aspects of the machine independently
65 of how they will be used. These interfaces are defined in
66 <tt>include/llvm/Target/</tt>.</li>
68 <li>Classes used to represent the <a href="#codegendesc">machine code</a> being
69 generator for a target. These classes are intended to be abstract enough to
70 represent the machine code for <i>any</i> target machine. These classes are
71 defined in <tt>include/llvm/CodeGen/</tt>.</li>
73 <li><a href="#codegenalgs">Target-independent algorithms</a> used to implement
74 various phases of native code generation (register allocation, scheduling, stack
75 frame representation, etc). This code lives in <tt>lib/CodeGen/</tt>.</li>
77 <li><a href="#targetimpls">Implementations of the abstract target description
78 interfaces</a> for particular targets. These machine descriptions make use of
79 the components provided by LLVM, and can optionally provide custom
80 target-specific passes, to build complete code generators for a specific target.
81 Target descriptions live in <tt>lib/Target/</tt>.</li>
86 Depending on which part of the code generator you are interested in working on,
87 different pieces of this will be useful to you. In any case, you should be
88 familiar with the <a href="#targetdesc">target description</a> and <a
89 href="#codegendesc">machine code representation</a> classes. If you want to add
90 a backend for a new target, you will need <a href="#targetimpls">implement the
91 targe description</a> classes for your new target and understand the <a
92 href="LangRef.html">LLVM code representation</a>. If you are interested in
93 implementing a new <a href="#codegenalgs">code generation algorithm</a>, it
94 should only depend on the target-description and machine code representation
95 classes, ensuring that it is portable.
100 <!-- ======================================================================= -->
101 <div class="doc_subsection">
102 <a name="required">Required components in the code generator</a>
105 <div class="doc_text">
107 <p>The two pieces of the LLVM code generator are the high-level interface to the
108 code generator and the set of reusable components that can be used to build
109 target-specific backends. The two most important interfaces (<a
110 href="#targetmachine"><tt>TargetMachine</tt></a> and <a
111 href="#targetdata"><tt>TargetData</tt></a> classes) are the only ones that are
112 required to be defined for a backend to fit into the LLVM system, but the others
113 must be defined if the reusable code generator components are going to be
116 <p>This design has two important implications. The first is that LLVM can
117 support completely non-traditional code generation targets. For example, the C
118 backend does not require register allocation, instruction selection, or any of
119 the other standard components provided by the system. As such, it only
120 implements these two interfaces, and does its own thing. Another example of a
121 code generator like this is a (purely hypothetical) backend that converts LLVM
122 to the GCC RTL form and uses GCC to emit machine code for a target.</p>
124 <p>The other implication of this design is that it is possible to design and
125 implement radically different code generators in the LLVM system that do not
126 make use of any of the built-in components. Doing so is not recommended at all,
127 but could be required for radically different targets that do not fit into the
128 LLVM machine description model: programmable FPGAs for example.</p>
132 <!-- ======================================================================= -->
133 <div class="doc_subsection">
134 <a name="high-level-design">The high-level design of the code generator</a></li>
137 <div class="doc_text">
139 <p>The LLVM target-indendent code generator is designed to support efficient and
140 quality code generation for standard register-based microprocessors. Code
141 generation in this model is divided into the following stages:</p>
144 <li><b>Instruction Selection</b> - Determining a efficient implementation of the
145 input LLVM code in the target instruction set. This stage produces the initial
146 code for the program in the target instruction set the makes use of virtual
147 registers in SSA form and physical registers that represent any required
148 register assignments due to target constraints or calling conventions.</li>
150 <li><b>SSA-based Machine Code Optimizations</b> - This (optional) stage consists
151 of a series of machine-code optimizations that operate on the SSA-form produced
152 by the instruction selector. Optimizations like modulo-scheduling, normal
153 scheduling, or peephole optimization work here.</li>
155 <li><b>Register Allocation</b> - The target code is transformed from an infinite
156 virtual register file in SSA form to the concrete register file used by the
157 target. This phase introduces spill code and eliminates all virtual register
158 references from the program.</li>
160 <li><b>Prolog/Epilog Code Insertion</b> - Once the machine code has been
161 generated for the function and the amount of stack space required is known (used
162 for LLVM alloca's and spill slots), the prolog and epilog code for the function
163 can be inserted and "abstract stack location references" can be eliminated.
164 This stage is responsible for implementing optimizations like frame-pointer
165 elimination and stack packing.</li>
167 <li><b>Late Machine Code Optimizations</b> - Optimizations that operate on
168 "final" machine code can go here, such as spill code scheduling and peephole
171 <li><b>Code Emission</b> - The final stage actually outputs the machine code for
172 the current function, either in the target assembler format or in machine
178 The code generator is based on the assumption that the instruction selector will
179 use an optimal pattern matching selector to create high-quality sequences of
180 native code. Alternative code generator designs based on pattern expansion and
181 aggressive iterative peephole optimization are much slower. This design is
182 designed to permit efficient compilation (important for JIT environments) and
183 aggressive optimization (used when generate code offline) by allowing components
184 of varying levels of sophisication to be used for any step of compilation.</p>
187 In addition to these stages, target implementations can insert arbitrary
188 target-specific passes into the flow. For example, the X86 target uses a
189 special pass to handle the 80x87 floating point stack architecture. Other
190 targets with unusual requirements can be supported with custom passes as needed.
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197 <div class="doc_subsection">
198 <a name="tablegen">Using TableGen for target description</a></li>
201 <div class="doc_text">
203 <p>The target description classes require a detailed descriptions of the target
204 architecture. These target descriptions often have a large amount of common
205 information (e.g., an add instruction is almost identical to a sub instruction).
206 In order to allow the maximum amount of commonality to be factored out, the LLVM
207 code generator uses the <a href="TableGenFundamentals.html">TableGen</a> tool to
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214 <div class="doc_section">
215 <a name="targetdesc">Target description classes</a>
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219 <div class="doc_text">
221 <p>The LLVM target description classes (which are located in the
222 <tt>include/llvm/Target</tt> directory) provide an abstract description of the
223 target machine, independent of any particular client. These classes are
224 designed to capture the <i>abstract</i> properties of the target (such as what
225 instruction and registers it has), and do not incorporate any particular pieces
226 of code generation algorithms (these interfaces do not take interference graphs
227 as inputs or other algorithm-specific data structures).</p>
229 <p>All of the target description classes (except the <tt><a
230 href="#targetdata">TargetData</a></tt> class) are designed to be subclassed by
231 the concrete target implementation, and have virtual methods implemented. To
232 get to these implementations, <tt><a
233 href="#targetmachine">TargetMachine</a></tt> class provides accessors that
234 should be implemented by the target.</p>
238 <!-- ======================================================================= -->
239 <div class="doc_subsection">
240 <a name="targetmachine">The <tt>TargetMachine</tt> class</a>
243 <div class="doc_text">
245 <p>The <tt>TargetMachine</tt> class provides virtual methods that are used to
246 access the target-specific implementations of the various target description
247 classes (with the <tt>getInstrInfo</tt>, <tt>getRegisterInfo</tt>,
248 <tt>getFrameInfo</tt>, ... methods). This class is designed to be subclassed by
249 a concrete target implementation (e.g., <tt>X86TargetMachine</tt>) which
250 implements the various virtual methods. The only required target description
251 class is the <a href="#targetdata"><tt>TargetData</tt></a> class, but if the
252 code generator components are to be used, the other interfaces should be
253 implemented as well.</p>
258 <!-- ======================================================================= -->
259 <div class="doc_subsection">
260 <a name="targetdata">The <tt>TargetData</tt> class</a>
263 <div class="doc_text">
265 <p>The <tt>TargetData</tt> class is the only required target description class,
266 and it is the only class that is not extensible (it cannot be derived from). It
267 specifies information about how the target lays out memory for structures, the
268 alignment requirements for various data types, the size of pointers in the
269 target, and whether the target is little- or big-endian.</p>
274 <!-- ======================================================================= -->
275 <div class="doc_subsection">
276 <a name="mregisterinfo">The <tt>MRegisterInfo</tt> class</a></li>
279 <div class="doc_text">
281 <p>The <tt>MRegisterInfo</tt> class (which will eventually be renamed to
282 <tt>TargetRegisterInfo</tt>) is used to describe the register file of the
283 target and any interactions between the registers.</p>
285 <p>Registers in the code generator are represented in the code generator by
286 unsigned numbers. Physical registers (those that actually exist in the target
287 description) are unique small numbers, and virtual registers are generally
290 <p>Each register in the processor description has an associated
291 <tt>MRegisterDesc</tt> entry, which provides a textual name for the register
292 (used for assembly output and debugging dumps), a set of aliases (used to
293 indicate that one register overlaps with another), and some flag bits.
296 <p>In addition to the per-register description, the <tt>MRegisterInfo</tt> class
297 exposes a set of processor specific register classes (instances of the
298 <tt>TargetRegisterClass</tt> class). Each register class contains sets of
299 registers that have the same properties (for example, they are all 32-bit
300 integer registers). Each SSA virtual register created by the instruction
301 selector has an associated register class. When the register allocator runs, it
302 replaces virtual registers with a physical register in the set.</p>
305 The target-specific implementations of these classes is auto-generated from a <a
306 href="TableGenFundamentals.html">TableGen</a> description of the register file.
311 <!-- ======================================================================= -->
312 <div class="doc_subsection">
313 <a name="targetinstrinfo">The <tt>TargetInstrInfo</tt> class</a></li>
316 <!-- ======================================================================= -->
317 <div class="doc_subsection">
318 <a name="targetframeinfo">The <tt>TargetFrameInfo</tt> class</a></li>
321 <!-- ======================================================================= -->
322 <div class="doc_subsection">
323 <a name="targetjitinfo">The <tt>TargetJITInfo</tt> class</a></li>
326 <!-- *********************************************************************** -->
327 <div class="doc_section">
328 <a name="codegendesc">Machine code description classes</a>
330 <!-- *********************************************************************** -->
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