2 * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
9 * a) This file is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
14 * This file is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use,
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
42 #include <dt-bindings/pwm/pwm.h>
43 #include <dt-bindings/input/input.h>
44 #include "rk3399.dtsi"
45 #include "rk3399-android.dtsi"
48 compatible = "rockchip,rk3399-box","rockchip,rk3399";
50 vcc1v8_s0: vcc1v8-s0 {
51 compatible = "regulator-fixed";
52 regulator-name = "vcc1v8_s0";
53 regulator-min-microvolt = <1800000>;
54 regulator-max-microvolt = <1800000>;
59 compatible = "regulator-fixed";
60 regulator-name = "vcc_sys";
61 regulator-min-microvolt = <5000000>;
62 regulator-max-microvolt = <5000000>;
66 vcc_phy: vcc-phy-regulator {
67 compatible = "regulator-fixed";
68 regulator-name = "vcc_phy";
73 vcc3v3_sys: vcc3v3-sys {
74 compatible = "regulator-fixed";
75 regulator-name = "vcc3v3_sys";
76 regulator-min-microvolt = <3300000>;
77 regulator-max-microvolt = <3300000>;
79 vin-supply = <&vcc_sys>;
82 vcc5v0_host: vcc5v0-host-regulator {
83 compatible = "regulator-fixed";
85 gpio = <&gpio4 25 GPIO_ACTIVE_HIGH>;
86 pinctrl-names = "default";
87 pinctrl-0 = <&host_vbus_drv>;
88 regulator-name = "vcc5v0_host";
92 compatible = "pwm-regulator";
93 pwms = <&pwm2 0 25000 0>;
94 regulator-name = "vdd_log";
95 regulator-min-microvolt = <800000>;
96 regulator-max-microvolt = <1400000>;
100 /* for rockchip boot on */
101 rockchip,pwm_id= <2>;
102 rockchip,pwm_voltage = <900000>;
104 vin-supply = <&vcc_sys>;
107 clkin_gmac: external-gmac-clock {
108 compatible = "fixed-clock";
109 clock-frequency = <125000000>;
110 clock-output-names = "clkin_gmac";
115 compatible = "rockchip,rk3399-io-voltage-domain";
116 rockchip,grf = <&grf>;
118 bt656-supply = <&vcc1v8_s0>; /* bt656_gpio2ab_ms */
119 audio-supply = <&vcc1v8_s0>; /* audio_gpio3d4a_ms */
120 sdmmc-supply = <&vcc_sd>; /* sdmmc_gpio4b_ms */
121 gpio1830-supply = <&vcc_3v0>; /* gpio1833_gpio4cd_ms */
125 compatible = "rockchip,rk3399-pmu-io-voltage-domain";
126 rockchip,grf = <&pmugrf>;
128 pmu1830-supply = <&vcc_1v8>;
133 compatible = "simple-audio-card";
134 simple-audio-card,name = "ROCKCHIP,SPDIF";
135 simple-audio-card,cpu {
136 sound-dai = <&spdif>;
138 simple-audio-card,codec {
139 sound-dai = <&spdif_out>;
143 spdif_out: spdif-out {
145 compatible = "linux,spdif-dit";
146 #sound-dai-cells = <0>;
149 hdmi_sound: hdmi-sound {
151 compatible = "simple-audio-card";
152 simple-audio-card,format = "i2s";
153 simple-audio-card,mclk-fs = <256>;
154 simple-audio-card,name = "rockchip,hdmi";
155 simple-audio-card,cpu {
158 simple-audio-card,codec {
159 sound-dai = <&dw_hdmi_audio>;
163 dw_hdmi_audio: dw-hdmi-audio {
165 compatible = "rockchip,dw-hdmi-audio";
166 #sound-dai-cells = <0>;
169 sdio_pwrseq: sdio-pwrseq {
170 compatible = "mmc-pwrseq-simple";
172 clock-names = "ext_clock";
173 pinctrl-names = "default";
174 pinctrl-0 = <&wifi_enable_h>;
177 * On the module itself this is one of these (depending
178 * on the actual card populated):
179 * - SDIO_RESET_L_WL_REG_ON
180 * - PDN (power down when low)
182 reset-gpios = <&gpio0 10 GPIO_ACTIVE_LOW>;
186 compatible = "wlan-platdata";
187 rockchip,grf = <&grf>;
188 wifi_chip_type = "ap6354";
190 WIFI,host_wake_irq = <&gpio0 3 GPIO_ACTIVE_HIGH>;
195 compatible = "bluetooth-platdata";
196 /* wifi-bt-power-toggle; */
197 uart_rts_gpios = <&gpio2 19 GPIO_ACTIVE_LOW>;
198 pinctrl-names = "default", "rts_gpio";
199 pinctrl-0 = <&uart0_rts>;
200 pinctrl-1 = <&uart0_gpios>;
201 /* BT,power_gpio = <&gpio3 19 GPIO_ACTIVE_HIGH>; */
202 BT,reset_gpio = <&gpio0 9 GPIO_ACTIVE_HIGH>;
203 BT,wake_gpio = <&gpio2 26 GPIO_ACTIVE_HIGH>;
204 BT,wake_host_irq = <&gpio0 4 GPIO_ACTIVE_HIGH>;
210 clock-frequency = <100000000>;
211 clock-freq-min-max = <400000 100000000>;
219 vqmmc-supply = <&vcc_sd>;
220 pinctrl-names = "default";
221 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>;
226 clock-frequency = <100000000>;
227 clock-freq-min-max = <200000 100000000>;
233 keep-power-in-suspend;
234 mmc-pwrseq = <&sdio_pwrseq>;
237 pinctrl-names = "default";
238 pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>;
244 freq-sel = <200000000>;
255 mmc-hs400-enhanced-strobe;
261 rockchip,i2s-broken-burst-len;
262 rockchip,playback-channels = <8>;
263 rockchip,capture-channels = <8>;
264 #sound-dai-cells = <0>;
268 #sound-dai-cells = <0>;
272 pinctrl-0 = <&spdif_bus_1>;
274 #sound-dai-cells = <0>;
279 opp-hz = /bits/ 64 <408000000>;
280 opp-microvolt = <800000>;
281 clock-latency-ns = <40000>;
284 opp-hz = /bits/ 64 <600000000>;
285 opp-microvolt = <800000>;
288 opp-hz = /bits/ 64 <816000000>;
289 opp-microvolt = <800000>;
292 opp-hz = /bits/ 64 <1008000000>;
293 opp-microvolt = <875000>;
296 opp-hz = /bits/ 64 <1200000000>;
297 opp-microvolt = <925000>;
300 opp-hz = /bits/ 64 <1416000000>;
301 opp-microvolt = <1050000>;
304 opp-hz = /bits/ 64 <1512000000>;
305 opp-microvolt = <1075000>;
311 opp-hz = /bits/ 64 <408000000>;
312 opp-microvolt = <800000>;
313 clock-latency-ns = <40000>;
316 opp-hz = /bits/ 64 <600000000>;
317 opp-microvolt = <800000>;
320 opp-hz = /bits/ 64 <816000000>;
321 opp-microvolt = <825000>;
324 opp-hz = /bits/ 64 <1008000000>;
325 opp-microvolt = <875000>;
328 opp-hz = /bits/ 64 <1200000000>;
329 opp-microvolt = <950000>;
332 opp-hz = /bits/ 64 <1416000000>;
333 opp-microvolt = <1025000>;
336 opp-hz = /bits/ 64 <1608000000>;
337 opp-microvolt = <1100000>;
340 opp-hz = /bits/ 64 <1800000000>;
341 opp-microvolt = <1175000>;
344 opp-hz = /bits/ 64 <1992000000>;
345 opp-microvolt = <1250000>;
354 518 335 /* 1008MHz */
355 617 428 /* 1200MHz */
356 728 573 /* 1416MHz */
357 827 724 /* 1608MHz */
358 925 900 /* 1800MHz */
359 1024 1108 /* 1992MHz */
390 518 335 /* 1008MHz */
391 617 428 /* 1200MHz */
392 728 573 /* 1416MHz */
393 827 724 /* 1608MHz */
394 925 900 /* 1800MHz */
395 1024 1108 /* 1992MHz */
423 opp-hz = /bits/ 64 <200000000>;
424 opp-microvolt = <800000>;
427 opp-hz = /bits/ 64 <300000000>;
428 opp-microvolt = <800000>;
431 opp-hz = /bits/ 64 <400000000>;
432 opp-microvolt = <800000>;
435 opp-hz = /bits/ 64 <500000000>;
436 opp-microvolt = <850000>;
439 opp-hz = /bits/ 64 <600000000>;
440 opp-microvolt = <900000>;
443 opp-hz = /bits/ 64 <700000000>;
444 opp-microvolt = <950000>;
447 opp-hz = /bits/ 64 <800000000>;
448 opp-microvolt = <975000>;
454 i2c-scl-rising-time-ns = <168>;
455 i2c-scl-falling-time-ns = <4>;
456 clock-frequency = <400000>;
458 vdd_cpu_b: syr827@40 {
459 compatible = "silergy,syr827";
461 regulator-compatible = "fan53555-reg";
462 regulator-name = "vdd_cpu_b";
463 regulator-min-microvolt = <712500>;
464 regulator-max-microvolt = <1500000>;
465 regulator-ramp-delay = <1000>;
466 fcs,suspend-voltage-selector = <0>;
469 vin-supply = <&vcc_sys>;
470 regulator-state-mem {
471 regulator-off-in-suspend;
476 compatible = "silergy,syr828";
478 regulator-compatible = "fan53555-reg";
479 regulator-name = "vdd_gpu";
480 regulator-min-microvolt = <712500>;
481 regulator-max-microvolt = <1500000>;
482 regulator-ramp-delay = <1000>;
483 fcs,suspend-voltage-selector = <1>;
486 vin-supply = <&vcc_sys>;
487 regulator-state-mem {
488 regulator-off-in-suspend;
493 compatible = "rockchip,rk808";
495 interrupt-parent = <&gpio1>;
496 interrupts = <21 IRQ_TYPE_LEVEL_LOW>;
497 pinctrl-names = "default";
498 pinctrl-0 = <&pmic_int_l>;
499 rockchip,system-power-controller;
502 clock-output-names = "xin32k", "rk808-clkout2";
504 vcc1-supply = <&vcc_sys>;
505 vcc2-supply = <&vcc_sys>;
506 vcc3-supply = <&vcc_sys>;
507 vcc4-supply = <&vcc_sys>;
508 vcc6-supply = <&vcc_sys>;
509 vcc7-supply = <&vcc_sys>;
510 vcc8-supply = <&vcc3v3_sys>;
511 vcc9-supply = <&vcc_sys>;
512 vcc10-supply = <&vcc_sys>;
513 vcc11-supply = <&vcc_sys>;
514 vcc12-supply = <&vcc3v3_sys>;
515 vddio-supply = <&vcc_1v8>;
518 vdd_center: DCDC_REG1 {
519 regulator-name = "vdd_center";
520 regulator-min-microvolt = <750000>;
521 regulator-max-microvolt = <1350000>;
524 regulator-state-mem {
525 regulator-off-in-suspend;
529 vdd_cpu_l: DCDC_REG2 {
530 regulator-name = "vdd_cpu_l";
531 regulator-min-microvolt = <750000>;
532 regulator-max-microvolt = <1350000>;
535 regulator-state-mem {
536 regulator-off-in-suspend;
541 regulator-name = "vcc_ddr";
544 regulator-state-mem {
545 regulator-on-in-suspend;
550 regulator-name = "vcc_1v8";
551 regulator-min-microvolt = <1800000>;
552 regulator-max-microvolt = <1800000>;
555 regulator-state-mem {
556 regulator-on-in-suspend;
557 regulator-suspend-microvolt = <1800000>;
561 vcc1v8_dvp: LDO_REG1 {
562 regulator-name = "vcc1v8_dvp";
563 regulator-min-microvolt = <1800000>;
564 regulator-max-microvolt = <1800000>;
567 regulator-state-mem {
568 regulator-on-in-suspend;
569 regulator-suspend-microvolt = <1800000>;
573 vcca1v8_hdmi: LDO_REG2 {
574 regulator-name = "vcca1v8_hdmi";
575 regulator-min-microvolt = <1800000>;
576 regulator-max-microvolt = <1800000>;
579 regulator-state-mem {
580 regulator-on-in-suspend;
581 regulator-suspend-microvolt = <1800000>;
586 regulator-name = "vcca_1v8";
587 regulator-min-microvolt = <1800000>;
588 regulator-max-microvolt = <1800000>;
591 regulator-state-mem {
592 regulator-on-in-suspend;
593 regulator-suspend-microvolt = <1800000>;
598 regulator-name = "vcc_sd";
599 regulator-min-microvolt = <1800000>;
600 regulator-max-microvolt = <3300000>;
603 regulator-state-mem {
604 regulator-on-in-suspend;
605 regulator-suspend-microvolt = <3300000>;
609 vcc3v0_sd: LDO_REG5 {
610 regulator-name = "vcc3v0_sd";
611 regulator-min-microvolt = <3000000>;
612 regulator-max-microvolt = <3000000>;
615 regulator-state-mem {
616 regulator-on-in-suspend;
617 regulator-suspend-microvolt = <3000000>;
622 regulator-name = "vcc_1v5";
623 regulator-min-microvolt = <1500000>;
624 regulator-max-microvolt = <1500000>;
627 regulator-state-mem {
628 regulator-on-in-suspend;
629 regulator-suspend-microvolt = <1500000>;
633 vcca0v9_hdmi: LDO_REG7 {
634 regulator-name = "vcca0v9_hdmi";
635 regulator-min-microvolt = <900000>;
636 regulator-max-microvolt = <900000>;
639 regulator-state-mem {
640 regulator-on-in-suspend;
641 regulator-suspend-microvolt = <900000>;
646 regulator-name = "vcc_3v0";
647 regulator-min-microvolt = <3000000>;
648 regulator-max-microvolt = <3000000>;
651 regulator-state-mem {
652 regulator-on-in-suspend;
653 regulator-suspend-microvolt = <3000000>;
657 vcc3v3_s3: SWITCH_REG1 {
658 regulator-name = "vcc3v3_s3";
661 regulator-state-mem {
662 regulator-on-in-suspend;
666 vcc3v3_s0: SWITCH_REG2 {
667 regulator-name = "vcc3v3_s0";
670 regulator-state-mem {
671 regulator-on-in-suspend;
679 cpu-supply = <&vdd_cpu_l>;
683 cpu-supply = <&vdd_cpu_l>;
687 cpu-supply = <&vdd_cpu_l>;
691 cpu-supply = <&vdd_cpu_l>;
695 cpu-supply = <&vdd_cpu_b>;
699 cpu-supply = <&vdd_cpu_b>;
704 mali-supply = <&vdd_gpu>;
712 /* tshut mode 0:CRU 1:GPIO */
713 rockchip,hw-tshut-mode = <1>;
714 /* tshut polarity 0:LOW 1:HIGH */
715 rockchip,hw-tshut-polarity = <1>;
722 u2phy0_host: host-port {
723 phy-supply = <&vcc5v0_host>;
731 u2phy1_host: host-port {
732 phy-supply = <&vcc5v0_host>;
738 pinctrl-names = "default";
739 pinctrl-0 = <&uart0_xfer &uart0_cts>;
768 dr_mode = "peripheral";
788 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH 0>;
789 compatible = "rockchip,remotectl-pwm";
794 rockchip,usercode = <0x4040>;
804 <0xe3 KEY_VOLUMEDOWN>,
821 rockchip,usercode = <0xff00>;
831 <0xeb KEY_VOLUMEDOWN>,
836 <0xa9 KEY_VOLUMEDOWN>,
837 <0xa8 KEY_VOLUMEDOWN>,
838 <0xe0 KEY_VOLUMEDOWN>,
839 <0xa5 KEY_VOLUMEDOWN>,
844 <0xed KEY_VOLUMEDOWN>,
846 <0xb3 KEY_VOLUMEDOWN>,
847 <0xf1 KEY_VOLUMEDOWN>,
848 <0xf2 KEY_VOLUMEDOWN>,
850 <0xb4 KEY_VOLUMEDOWN>,
855 rockchip,usercode = <0x1dcc>;
865 <0xfd KEY_VOLUMEDOWN>,
883 <0xb5 KEY_BACKSPACE>;
888 phy-supply = <&vcc_phy>;
890 clock_in_out = "input";
891 snps,reset-gpio = <&gpio3 15 GPIO_ACTIVE_LOW>;
892 snps,reset-active-low;
893 snps,reset-delays-us = <0 10000 50000>;
894 assigned-clocks = <&cru SCLK_RMII_SRC>;
895 assigned-clock-parents = <&clkin_gmac>;
896 pinctrl-names = "default";
897 pinctrl-0 = <&rgmii_pins>;
908 #include <dt-bindings/display/screen-timing/lcd-box.dtsi>
912 native-mode = <&timing1>; /* 1080p */
920 rockchip,disp-mode = <NO_DUAL>;
921 rockchip,disp-policy = <DISPLAY_POLICY_BOX>;
926 rockchip,hdmi_video_source = <DISPLAY_SOURCE_LCDC0>;
935 wifi_enable_h: wifi-enable-h {
937 <0 10 RK_FUNC_GPIO &pcfg_pull_none>;
942 uart0_gpios: uart0-gpios {
944 <2 19 RK_FUNC_GPIO &pcfg_pull_none>;
949 host_vbus_drv: host-vbus-drv {
951 <4 25 RK_FUNC_GPIO &pcfg_pull_none>;
956 pmic_int_l: pmic-int-l {
958 <1 21 RK_FUNC_GPIO &pcfg_pull_up>;