2 * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
9 * a) This file is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
14 * This file is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use,
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
45 bootargs = "earlycon=uart8250,mmio32,0xff690000 swiotlb=1 firmware_class.path=/system/vendor/firmware";
48 fiq_debugger: fiq-debugger {
49 compatible = "rockchip,fiq-debugger";
50 rockchip,serial-id = <2>;
51 rockchip,signal-irq = <186>;
52 rockchip,wake-irq = <0>;
53 rockchip,irq-mode-enable = <1>; /* If enable uart uses irq instead of fiq */
54 rockchip,baudrate = <115200>; /* Only 115200 and 1500000 */
55 pinctrl-names = "default";
56 pinctrl-0 = <&uart2_xfer>;
64 drm_logo: drm-logo@00000000 {
65 compatible = "rockchip,drm-logo";
66 reg = <0x0 0x0 0x0 0x0>;
69 /* global autoconfigured region for contiguous allocations */
71 compatible = "shared-dma-pool";
73 size = <0x0 0x8000000>;
77 /* reg = <0x0 0x0 0x0 0x0> will be updated by uboot */
78 rockchip_logo: rockchip-logo@00000000 {
79 compatible = "rockchip,drm-logo";
80 reg = <0x0 0x0 0x0 0x0>;
85 compatible = "rockchip,ion";
90 reg = <0x00000000 0x02000000>;
98 compatible = "rockchip,rk3368-isp", "rockchip,isp";
99 reg = <0x0 0xff910000 0x0 0x10000>;
100 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
101 power-domains = <&power RK3368_PD_VIO>;
103 <&cru ACLK_RGA>, <&cru HCLK_ISP>, <&cru SCLK_ISP>,
104 <&cru SCLK_ISP>, <&cru PCLK_ISP>, <&cru SCLK_VIP_OUT>,
105 <&cru SCLK_VIP_OUT>, <&cru PCLK_MIPI_CSI>,
106 <&cru PCLK_DPHYRX>, <&cru ACLK_VIO0_NOC>;
108 "aclk_isp", "hclk_isp", "clk_isp",
109 "clk_isp_jpe", "pclkin_isp", "clk_cif_out",
110 "clk_cif_pll", "hclk_mipiphy1",
111 "pclk_dphyrx", "clk_vio0_noc";
113 "default", "isp_dvp8bit2", "isp_dvp10bit", "isp_dvp12bit",
114 "isp_dvp8bit0", "isp_dvp8bit4", "isp_mipi_fl",
115 "isp_mipi_fl_prefl", "isp_flash_as_gpio",
116 "isp_flash_as_trigger_out";
117 pinctrl-0 = <&cif_clkout>;
118 pinctrl-1 = <&cif_clkout &isp_dvp_d2d9>;
119 pinctrl-2 = <&cif_clkout &isp_dvp_d2d9 &isp_dvp_d0d1>;
120 pinctrl-3 = <&cif_clkout &isp_dvp_d2d9 &isp_dvp_d0d1 &isp_dvp_d10d11>;
121 pinctrl-4 = <&cif_clkout &isp_dvp_d0d7>;
122 pinctrl-5 = <&cif_clkout &isp_dvp_d4d11>;
123 pinctrl-6 = <&cif_clkout>;
124 pinctrl-7 = <&cif_clkout &isp_prelight>;
125 pinctrl-8 = <&isp_flash_trigger_as_gpio>;
126 pinctrl-9 = <&isp_flash_trigger>;
127 rockchip,isp,mipiphy = <2>;
128 rockchip,isp,cifphy = <1>;
129 rockchip,isp,mipiphy1,reg = <0xff964000 0x4000>;
130 rockchip,isp,csiphy,reg = <0xff96C000 0x4000>;
131 rockchip,grf = <&grf>;
132 rockchip,cru = <&cru>;
133 rockchip,gpios = <&gpio3 20 GPIO_ACTIVE_HIGH>;
134 rockchip,isp,iommu_enable = <1>;
139 compatible = "rockchip,rga2";
141 reg = <0x0 0xff920000 0x0 0x1000>;
142 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
143 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA>;
144 clock-names = "aclk_rga", "hclk_rga", "clk_rga";
149 hdmi: hdmi@ff980000 {
150 compatible = "rockchip,rk3368-hdmi";
151 reg = <0x0 0xff980000 0x0 0x20000>;
152 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
153 clocks = <&cru PCLK_HDMI_CTRL>,
154 <&cru SCLK_HDMI_HDCP>,
155 <&cru SCLK_HDMI_CEC>;
156 clock-names = "pclk_hdmi", "hdcp_clk_hdmi", "cec_clk_hdmi";
157 power-domains = <&power RK3368_PD_VIO>;
158 resets = <&cru SRST_HDMI>;
159 reset-names = "hdmi";
160 pinctrl-names = "default", "gpio";
161 pinctrl-0 = <&hdmii2c_xfer &hdmi_cec>;
162 pinctrl-1 = <&i2c5_gpio>;
166 dwc_control_usb: dwc-control-usb {
167 compatible = "rockchip,rk3368-dwc-control-usb";
170 rockchip,grf = <&grf>;
171 grf-offset = <0x04bc>; /* GRF_SOC_STATUS for USB2.0 OTG */
172 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
173 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
174 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
175 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
176 interrupt-names = "otg_id", "otg_bvalid",
177 "otg_linestate", "host0_linestate";
178 clocks = <&cru HCLK_USB_PERI>;
179 clock-names = "hclk_usb_peri";
181 otg_drv_gpio = <&gpio0 25 GPIO_ACTIVE_LOW>;
182 rockchip,remote_wakeup;
183 rockchip,usb_irq_wakeup;
186 compatible = "inno,phy";
187 regbase = &dwc_control_usb;
188 rk_usb,bvalid = <0x4bc 23 1>;
189 rk_usb,iddig = <0x4bc 26 1>;
190 rk_usb,vdmsrcen = <0x718 12 1>;
191 rk_usb,vdpsrcen = <0x718 11 1>;
192 rk_usb,rdmpden = <0x718 10 1>;
193 rk_usb,idpsrcen = <0x718 9 1>;
194 rk_usb,idmsinken = <0x718 8 1>;
195 rk_usb,idpsinken = <0x718 7 1>;
196 rk_usb,dpattach = <0x4b8 31 1>;
197 rk_usb,cpdet = <0x4b8 30 1>;
198 rk_usb,dcpattach = <0x4b8 29 1>;
206 memory-region = <&drm_logo>;
208 route_mipi: route-mipi {
210 logo,uboot = "logo.bmp";
211 logo,kernel = "logo_kernel.bmp";
212 logo,mode = "center";
213 charge_logo,mode = "center";
214 connect = <&vop_out_mipi>;
229 clocks = <&cru SCLK_OTGPHY0>, <&cru HCLK_OTG0>;
230 clock-names = "sclk_otgphy0", "otg";
231 resets = <&cru SRST_USBOTG_AHB>,
232 <&cru SRST_USBOTG_PHY>,
233 <&cru SRST_USBOTG_CON>;
234 reset-names = "otg_ahb", "otg_phy", "otg_controller";
235 /* 0 - Normal, 1 - Force Host, 2 - Force Device */
236 rockchip,usb-mode = <0>;
241 hdmii2c_xfer: hdmii2c-xfer {
242 rockchip,pins = <3 26 RK_FUNC_1 &pcfg_pull_none>,
243 <3 27 RK_FUNC_1 &pcfg_pull_none>;
249 rockchip,pins = <3 23 RK_FUNC_1 &pcfg_pull_none>;
254 i2c5_gpio: i2c5-gpio {
255 rockchip,pins = <3 26 RK_FUNC_GPIO &pcfg_pull_none>,
256 <3 27 RK_FUNC_GPIO &pcfg_pull_none>;
261 cif_clkout: cif-clkout {
262 rockchip,pins = <1 11 RK_FUNC_1 &pcfg_pull_none>;//cif_clkout
265 isp_dvp_d2d9: isp-dvp-d2d9 {
267 <1 0 RK_FUNC_1 &pcfg_pull_none>,//cif_data2
268 <1 1 RK_FUNC_1 &pcfg_pull_none>,//cif_data3
269 <1 2 RK_FUNC_1 &pcfg_pull_none>,//cif_data4
270 <1 3 RK_FUNC_1 &pcfg_pull_none>,//cif_data5
271 <1 4 RK_FUNC_1 &pcfg_pull_none>,//cif_data6
272 <1 5 RK_FUNC_1 &pcfg_pull_none>,//cif_data7
273 <1 6 RK_FUNC_1 &pcfg_pull_none>,//cif_data8
274 <1 7 RK_FUNC_1 &pcfg_pull_none>,//cif_data9
275 <1 8 RK_FUNC_1 &pcfg_pull_none>,//cif_sync
276 <1 9 RK_FUNC_1 &pcfg_pull_none>,//cif_href
277 <1 10 RK_FUNC_1 &pcfg_pull_none>,//cif_clkin
278 <1 11 RK_FUNC_1 &pcfg_pull_none>;//cif_clkout
281 isp_dvp_d0d1: isp-dvp-d0d1 {
283 <1 12 RK_FUNC_1 &pcfg_pull_none>,//cif_data0
284 <1 13 RK_FUNC_1 &pcfg_pull_none>;//cif_data1
287 isp_dvp_d10d11:isp_d10d11 {
289 <1 14 RK_FUNC_1 &pcfg_pull_none>,//cif_data10
290 <1 15 RK_FUNC_1 &pcfg_pull_none>;//cif_data11
293 isp_dvp_d0d7: isp-dvp-d0d7 {
295 <1 12 RK_FUNC_1 &pcfg_pull_none>,//cif_data0
296 <1 13 RK_FUNC_1 &pcfg_pull_none>,//cif_data1
297 <1 0 RK_FUNC_1 &pcfg_pull_none>,//cif_data2
298 <1 1 RK_FUNC_1 &pcfg_pull_none>,//cif_data3
299 <1 2 RK_FUNC_1 &pcfg_pull_none>,//cif_data4
300 <1 3 RK_FUNC_1 &pcfg_pull_none>,//cif_data5
301 <1 4 RK_FUNC_1 &pcfg_pull_none>,//cif_data6
302 <1 5 RK_FUNC_1 &pcfg_pull_none>;//cif_data7
305 isp_dvp_d4d11: isp-dvp-d4d11 {
307 <1 2 RK_FUNC_1 &pcfg_pull_none>,//cif_data4
308 <1 3 RK_FUNC_1 &pcfg_pull_none>,//cif_data5
309 <1 4 RK_FUNC_1 &pcfg_pull_none>,//cif_data6
310 <1 5 RK_FUNC_1 &pcfg_pull_none>,//cif_data7
311 <1 6 RK_FUNC_1 &pcfg_pull_none>,//cif_data8
312 <1 7 RK_FUNC_1 &pcfg_pull_none>,//cif_data9
313 <1 14 RK_FUNC_1 &pcfg_pull_none>,//cif_data10
314 <1 17 RK_FUNC_1 &pcfg_pull_none>;//cif_data11
317 isp_shutter: isp-shutter {
319 <3 19 RK_FUNC_2 &pcfg_pull_none>, //SHUTTEREN
320 <3 22 RK_FUNC_2 &pcfg_pull_none>;//SHUTTERTRIG
323 isp_flash_trigger: isp-flash-trigger {
324 rockchip,pins = <3 20 RK_FUNC_2 &pcfg_pull_none>; //ISP_FLASHTRIGOU
327 isp_prelight: isp-prelight {
328 rockchip,pins = <3 21 RK_FUNC_2 &pcfg_pull_none>;//ISP_PRELIGHTTRIG
331 isp_flash_trigger_as_gpio: isp_flash_trigger_as_gpio {
332 rockchip,pins = <3 20 RK_FUNC_GPIO &pcfg_pull_none>;//ISP_FLASHTRIGOU