2 * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
9 * a) This library is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
14 * This library is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use,
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
43 #include <dt-bindings/clock/rk3366-cru.h>
44 #include <dt-bindings/gpio/gpio.h>
45 #include <dt-bindings/interrupt-controller/irq.h>
46 #include <dt-bindings/interrupt-controller/arm-gic.h>
47 #include <dt-bindings/pinctrl/rockchip.h>
48 #include <dt-bindings/display/rk_fb.h>
49 #include <dt-bindings/power/rk3366-power.h>
50 #include <dt-bindings/soc/rockchip_boot-mode.h>
53 compatible = "rockchip,rk3366";
54 interrupt-parent = <&gic>;
73 #address-cells = <0x2>;
78 compatible = "arm,cortex-a53","arm,armv8";
80 enable-method = "psci";
81 clocks = <&cru ARMCLK>;
82 operating-points-v2 = <&cpu0_opp_table>;
87 compatible = "arm,cortex-a53","arm,armv8";
89 enable-method = "psci";
90 operating-points-v2 = <&cpu0_opp_table>;
95 compatible = "arm,cortex-a53","arm,armv8";
97 enable-method = "psci";
98 operating-points-v2 = <&cpu0_opp_table>;
103 compatible = "arm,cortex-a53","arm,armv8";
105 enable-method = "psci";
106 operating-points-v2 = <&cpu0_opp_table>;
110 cpu0_opp_table: opp_table0 {
111 compatible = "operating-points-v2";
115 opp-hz = /bits/ 64 <408000000>;
116 opp-microvolt = <1200000>;
117 clock-latency-ns = <40000>;
121 opp-hz = /bits/ 64 <600000000>;
122 opp-microvolt = <1200000>;
125 opp-hz = /bits/ 64 <816000000>;
126 opp-microvolt = <1200000>;
129 opp-hz = /bits/ 64 <1008000000>;
130 opp-microvolt = <1200000>;
133 opp-hz = /bits/ 64 <1200000000>;
134 opp-microvolt = <1200000>;
139 compatible = "arm,psci-1.0";
144 compatible = "arm,armv8-timer";
145 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
146 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
147 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
148 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
152 compatible = "fixed-clock";
154 clock-frequency = <24000000>;
155 clock-output-names = "xin24m";
158 gic: interrupt-controller@ffb71000 {
159 compatible = "arm,gic-400";
160 interrupt-controller;
161 #interrupt-cells = <3>;
162 #address-cells = <0>;
164 reg = <0x0 0xffb71000 0x0 0x1000>,
165 <0x0 0xffb72000 0x0 0x1000>,
166 <0x0 0xffb74000 0x0 0x2000>,
167 <0x0 0xffb76000 0x0 0x2000>;
168 interrupts = <GIC_PPI 9
169 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
172 nandc0: nandc@ff0c0000 {
173 compatible = "rockchip,rk-nandc";
174 reg = <0x0 0xff0c0000 0x0 0x4000>;
175 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
177 clocks = <&cru SCLK_NANDC0>, <&cru HCLK_NANDC0>;
178 clock-names = "clk_nandc", "hclk_nandc";
182 saradc: saradc@ff100000 {
183 compatible = "rockchip,saradc";
184 reg = <0x0 0xff100000 0x0 0x100>;
185 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
186 #io-channel-cells = <1>;
187 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
188 clock-names = "saradc", "apb_pclk";
193 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
194 reg = <0x0 0xff110000 0x0 0x1000>;
195 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
196 clock-names = "spiclk", "apb_pclk";
197 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
198 pinctrl-names = "default";
199 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
200 #address-cells = <1>;
206 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
207 reg = <0x0 0xff120000 0x0 0x1000>;
208 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
209 clock-names = "spiclk", "apb_pclk";
210 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
211 pinctrl-names = "default";
212 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
213 #address-cells = <1>;
218 sdmmc: rksdmmc@ff400000 {
219 compatible = "rockchip,rk3366-dw-mshc","rockchip,rk3288-dw-mshc";
220 clock-freq-min-max = <400000 150000000>;
221 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
222 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
223 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
224 fifo-depth = <0x100>;
225 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
226 reg = <0x0 0xff400000 0x0 0x4000>;
230 sdio: rksdmmc@ff410000 {
231 compatible = "rockchip,rk3366-dw-mshc","rockchip,rk3288-dw-mshc";
232 clock-freq-min-max = <400000 150000000>;
233 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO0>,
234 <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>;
235 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
236 fifo-depth = <0x100>;
237 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
238 reg = <0x0 0xff410000 0x0 0x4000>;
242 emmc: rksdmmc@ff420000 {
243 compatible = "rockchip,rk3366-dw-mshc","rockchip,rk3288-dw-mshc";
244 clock-freq-min-max = <400000 150000000>;
245 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
246 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
247 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
248 fifo-depth = <0x100>;
249 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
250 reg = <0x0 0xff420000 0x0 0x4000>;
255 compatible = "rockchip,rk3366-gmac";
256 reg = <0x0 0xff440000 0x0 0x10000>;
257 rockchip,grf = <&grf>;
258 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
259 interrupt-names = "macirq";
260 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>,
261 <&cru SCLK_MAC_RX>, <&cru SCLK_MACREF>,
262 <&cru SCLK_MACREF_OUT>, <&cru ACLK_GMAC>,
264 clock-names = "stmmaceth", "mac_clk_rx",
265 "mac_clk_tx", "clk_mac_ref",
266 "clk_mac_refout", "aclk_mac",
268 resets = <&cru SRST_MAC>;
269 reset-names = "stmmaceth";
274 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
275 reg = <0x0 0xff728000 0x0 0x1000>;
276 clocks = <&cru PCLK_I2C0>;
278 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
279 pinctrl-names = "default";
280 pinctrl-0 = <&i2c0_xfer>;
281 #address-cells = <1>;
287 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
288 reg = <0x0 0xff140000 0x0 0x1000>;
289 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
290 #address-cells = <1>;
293 clocks = <&cru PCLK_I2C2>;
294 pinctrl-names = "default";
295 pinctrl-0 = <&i2c2_xfer>;
300 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
301 reg = <0x0 0xff150000 0x0 0x1000>;
302 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
303 #address-cells = <1>;
306 clocks = <&cru PCLK_I2C3>;
307 pinctrl-names = "default";
308 pinctrl-0 = <&i2c3_xfer>;
313 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
314 reg = <0x0 0xff160000 0x0 0x1000>;
315 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
316 #address-cells = <1>;
319 clocks = <&cru PCLK_I2C4>;
320 pinctrl-names = "default";
321 pinctrl-0 = <&i2c4_xfer>;
326 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
327 reg = <0x0 0xff170000 0x0 0x1000>;
328 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
329 #address-cells = <1>;
332 clocks = <&cru PCLK_I2C5>;
333 pinctrl-names = "default";
334 pinctrl-0 = <&i2c5_xfer>;
338 uart0: serial@ff180000 {
339 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
340 reg = <0x0 0xff180000 0x0 0x100>;
341 clock-frequency = <24000000>;
342 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
343 clock-names = "baudclk", "apb_pclk";
344 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
347 pinctrl-names = "default";
348 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
352 uart3: serial@ff1b0000 {
353 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
354 reg = <0x0 0xff1b0000 0x0 0x100>;
355 clock-frequency = <24000000>;
356 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
357 clock-names = "baudclk", "apb_pclk";
358 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
361 pinctrl-names = "default";
362 pinctrl-0 = <&uart3_xfer &uart3_cts &uart3_rts>;
366 usb_otg: usb@ff4c0000 {
367 compatible = "rockchip,rk3368-usb", "rockchip,rk3066-usb",
369 reg = <0x0 0xff4c0000 0x0 0x40000>;
370 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
371 clocks = <&cru HCLK_OTG>;
374 g-np-tx-fifo-size = <16>;
375 g-rx-fifo-size = <275>;
376 g-tx-fifo-size = <256 128 128 64 64 32>;
382 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
383 reg = <0x0 0xff660000 0x0 0x1000>;
384 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
385 #address-cells = <1>;
388 clocks = <&cru PCLK_I2C1>;
389 pinctrl-names = "default";
390 pinctrl-0 = <&i2c1_xfer>;
395 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
396 reg = <0x0 0xff680000 0x0 0x10>;
398 pinctrl-names = "default";
399 pinctrl-0 = <&pwm0_pin>;
400 clocks = <&cru PCLK_RKPWM>;
406 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
407 reg = <0x0 0xff680010 0x0 0x10>;
409 pinctrl-names = "default";
410 pinctrl-0 = <&pwm1_pin>;
411 clocks = <&cru PCLK_RKPWM>;
417 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
418 reg = <0x0 0xff680020 0x0 0x10>;
420 clocks = <&cru PCLK_RKPWM>;
426 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
427 reg = <0x0 0xff680030 0x0 0x10>;
429 pinctrl-names = "default";
430 pinctrl-0 = <&pwm3_t2_pin>;
431 clocks = <&cru PCLK_RKPWM>;
436 uart2: serial@ff690000 {
437 compatible = "rockchip,rk3366-uart", "snps,dw-apb-uart";
438 reg = <0x0 0xff690000 0x0 0x100>;
439 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
440 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
441 clock-names = "baudclk", "apb_pclk";
444 pinctrl-names = "default";
445 pinctrl-0 = <&uart2_t1_xfer>;
449 pmu: power-management@ff730000 {
450 compatible = "rockchip,rk3366-pmu", "syscon", "simple-mfd";
451 reg = <0x0 0xff730000 0x0 0x1000>;
453 power: power-controller {
455 compatible = "rockchip,rk3366-power-controller";
456 #power-domain-cells = <1>;
457 #address-cells = <1>;
461 * Note: Although SCLK_* are the working clocks
462 * of device without including on the NOC, needed for
465 * The clocks on the which NOC:
466 * ACLK_IEP/ACLK_VOP0 are on ACLK_VIO0_NIU.
467 * ACLK_RGA/ACLK_VOP1 are on ACLK_RGA_NIU.
468 * ACLK_ISP is on ACLK_ISP_NIU.
469 * ACLK_HDCP is on ACLK_HDCP_NIU.
470 * The others (HCLK_*,PLCK_*) are on HCLK_VIO_NIU.
472 * Which clock are device clocks:
474 * *_IEP IEP:Image Enhancement Processor
475 * *_ISP ISP:Image Signal Processing
476 * *_VOP* VOP:Visual Output Processor
483 reg = <RK3366_PD_VIO>;
484 clocks = <&cru ACLK_IEP>,
488 <&cru ACLK_VOP_FULL>,
489 <&cru ACLK_VOP_LITE>,
491 <&cru DCLK_VOP_FULL>,
492 <&cru DCLK_VOP_LITE>,
496 <&cru HCLK_VOP_FULL>,
497 <&cru HCLK_VOP_LITE>,
498 <&cru HCLK_VIO_HDCPMMU>,
499 <&cru PCLK_HDMI_CTRL>,
501 <&cru PCLK_MIPI_DSI0>,
502 <&cru SCLK_VOP_FULL_PWM>,
506 <&cru SCLK_HDMI_CEC>,
507 <&cru SCLK_HDMI_HDCP>;
511 * Note: ACLK_VCODEC/HCLK_VCODEC are VCODEC
512 * (video endecoder & decoder) clocks that on the
513 * ACLK_VCODEC_NIU and HCLK_VCODEC_NIU (NOC).
516 reg = <RK3366_PD_VPU>;
517 clocks = <&cru ACLK_VIDEO>,
522 * Note: ACLK_RKVDEC/HCLK_RKVDEC are RKVDEC
523 * (video decoder) clocks that on the
524 * ACLK_RKVDEC_NIU and HCLK_RKVDEC_NIU (NOC).
527 reg = <RK3366_PD_RKVDEC>;
528 clocks = <&cru ACLK_RKVDEC>,
533 reg = <RK3366_PD_VIDEO>;
534 clocks = <&cru ACLK_VIDEO>,
538 <&cru SCLK_HEVC_CABAC>,
539 <&cru SCLK_HEVC_CORE>;
543 * Note: ACLK_GPU is the GPU clock,
544 * and on the ACLK_GPU_NIU (NOC).
547 reg = <RK3366_PD_GPU>;
548 clocks = <&cru ACLK_GPU>;
553 pmugrf: syscon@ff738000 {
554 compatible = "rockchip,rk3366-pmugrf", "syscon", "simple-mfd";
555 reg = <0x0 0xff738000 0x0 0x1000>;
558 compatible = "syscon-reboot-mode";
560 mode-normal = <BOOT_NORMAL>;
561 mode-recovery = <BOOT_RECOVERY>;
562 mode-fastboot = <BOOT_FASTBOOT>;
563 mode-loader = <BOOT_LOADER>;
568 compatible = "arm,amba-bus";
569 #address-cells = <2>;
573 dmac_peri: dma-controller@ff250000 {
574 compatible = "arm,pl330", "arm,primecell";
575 reg = <0x0 0xff250000 0x0 0x4000>;
576 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
577 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
579 clocks = <&cru ACLK_DMAC_PERI>;
580 clock-names = "apb_pclk";
583 dmac_bus: dma-controller@ff600000 {
584 compatible = "arm,pl330", "arm,primecell";
585 reg = <0x0 0xff600000 0x0 0x4000>;
586 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
587 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
589 clocks = <&cru ACLK_DMAC_BUS>;
590 clock-names = "apb_pclk";
594 cru: clock-controller@ff760000 {
595 compatible = "rockchip,rk3366-cru";
596 reg = <0x0 0xff760000 0x0 0x1000>;
597 rockchip,grf = <&grf>;
601 <&cru PLL_CPLL>, <&cru PLL_GPLL>,
602 <&cru PLL_NPLL>, <&cru PLL_MPLL>,
603 <&cru PLL_WPLL>, <&cru PLL_BPLL>,
604 <&cru ACLK_VOP_FULL>, <&cru ACLK_VOP_LITE>,
605 <&cru HCLK_VOP_LITE>,<&cru HCLK_VOP_LITE>;
606 assigned-clock-rates =
607 <750000000>, <576000000>,
608 <594000000>, <594000000>,
609 <480000000>, <520000000>,
610 <375000000>, <288000000>,
611 <100000000>, <100000000>;
614 grf: syscon@ff770000 {
615 compatible = "rockchip,rk3366-grf", "syscon";
616 reg = <0x0 0xff770000 0x0 0x1000>;
619 i2s_2ch: i2s-2ch@ff890000 {
620 compatible = "rockchip,rk3366-i2s", "rockchip,rk3066-i2s";
621 reg = <0x0 0xff890000 0x0 0x1000>;
622 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
623 dmas = <&dmac_bus 6>, <&dmac_bus 7>;
624 dma-names = "tx", "rx";
625 clock-names = "i2s_hclk", "i2s_clk";
626 clocks = <&cru HCLK_I2S_2CH>, <&cru SCLK_I2S_2CH>;
630 i2s_8ch: i2s-8ch@ff898000 {
631 compatible = "rockchip,rk3366-i2s", "rockchip,rk3066-i2s";
632 reg = <0x0 0xff898000 0x0 0x1000>;
633 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
634 dmas = <&dmac_bus 0>, <&dmac_bus 1>;
635 dma-names = "tx", "rx";
636 clock-names = "i2s_hclk", "i2s_clk";
637 clocks = <&cru HCLK_I2S_8CH>, <&cru SCLK_I2S_8CH>;
638 pinctrl-names = "default";
639 pinctrl-0 = <&i2s_8ch_bus>;
644 compatible = "rockchip,rk-fb";
645 rockchip,disp-mode = <DUAL>;
650 compatible = "rockchip,screen";
654 vop_lite: vop@ff8f0000 {
655 compatible = "rockchip,rk3366-lcdc-lite";
656 rockchip,grf = <&grf>;
657 rockchip,pwr18 = <0>;
658 rockchip,iommu-enabled = <1>;
659 reg = <0x0 0xff8f0000 0x0 0x1000>;
660 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
661 clocks = <&cru ACLK_VOP_LITE>, <&cru DCLK_VOP_LITE>, <&cru HCLK_VOP_LITE>;
662 clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc";
663 resets = <&cru SRST_VOP1_AXI>, <&cru SRST_VOP1_DCLK>, <&cru SRST_VOP1_AHB>;
664 reset-names = "axi", "ahb", "dclk";
670 compatible = "rockchip,vopl_mmu";
671 reg = <0x0 0xff8f0f00 0x0 0x100>;
672 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
673 interrupt-names = "vopl_mmu";
678 compatible = "rockchip,rga2";
680 reg = <0x0 0xff920000 0x0 0x1000>;
681 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
682 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA>;
683 clock-names = "aclk_rga", "hclk_rga", "clk_rga";
687 vop_big: vop@ff930000 {
688 compatible = "rockchip,rk3366-lcdc-big";
689 rockchip,grf = <&grf>;
690 rockchip,prop = <PRMRY>;
691 rockchip,pwr18 = <0>;
692 rockchip,iommu-enabled = <1>;
693 reg = <0x0 0xff930000 0x0 0x23f0>;
694 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
695 clocks = <&cru ACLK_VOP_FULL>, <&cru DCLK_VOP_FULL>, <&cru HCLK_VOP_FULL>;
696 clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc";
697 resets = <&cru SRST_VOP0_AXI>, <&cru SRST_VOP0_DCLK>, <&cru SRST_VOP0_AHB>;
698 reset-names = "axi", "ahb", "dclk";
704 compatible = "rockchip,vopb_mmu";
705 reg = <0x0 0xff932400 0x0 0x100>;
706 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
707 interrupt-names = "vop_mmu";
711 dsihost0: mipi@ff960000 {
712 compatible = "rockchip,rk3368-dsi";
714 reg = <0x0 0xff960000 0x0 0x4000>, <0x0 0xff968000 0x0 0x4000>;
715 reg-names = "mipi_dsi_host" ,"mipi_dsi_phy";
716 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
717 clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_DPHYTX>, <&cru PCLK_MIPI_DSI0>;
718 clock-names = "clk_mipi_24m", "pclk_mipi_dsi", "pclk_mipi_dsi_host";
722 lvds: lvds@ff968000 {
723 compatible = "rockchip,rk3366-lvds";
724 rockchip,grf = <&grf>;
725 reg = <0x0 0xff968000 0x0 0x4000>, <0x0 0xff9600a0 0x0 0x20>;
726 reg-names = "mipi_lvds_phy", "mipi_lvds_ctl";
727 clocks = <&cru PCLK_DPHYTX>, <&cru PCLK_MIPI_DSI0>;
728 clock-names = "pclk_lvds", "pclk_lvds_ctl";
732 hdmi: hdmi@ff980000 {
733 compatible = "rockchip,rk3366-hdmi";
734 reg = <0x0 0xff980000 0x0 0x20000>;
735 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
736 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
737 clocks = <&cru PCLK_HDMI_CTRL>,
738 <&cru SCLK_HDMI_HDCP>,
739 <&cru SCLK_HDMI_CEC>,
741 clock-names = "pclk_hdmi",
745 resets = <&cru SRST_HDMI>;
746 reset-names = "hdmi";
747 pinctrl-names = "default", "gpio";
748 pinctrl-0 = <&hdmii2c_xfer &hdmi_cec>;
749 pinctrl-1 = <&i2c5_gpio>;
754 compatible = "rockchip,rk3366-pinctrl";
755 rockchip,grf = <&grf>;
756 rockchip,pmu = <&pmugrf>;
757 #address-cells = <0x2>;
761 gpio0: gpio0@ff750000 {
762 compatible = "rockchip,gpio-bank";
763 reg = <0x0 0xff750000 0x0 0x100>;
764 clocks = <&cru PCLK_GPIO0>;
765 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
770 interrupt-controller;
771 #interrupt-cells = <0x2>;
774 gpio1: gpio1@ff780000 {
775 compatible = "rockchip,gpio-bank";
776 reg = <0x0 0xff758000 0x0 0x100>;
777 clocks = <&cru PCLK_GPIO1>;
778 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
783 interrupt-controller;
784 #interrupt-cells = <0x2>;
787 gpio2: gpio2@ff790000 {
788 compatible = "rockchip,gpio-bank";
789 reg = <0x0 0xff790000 0x0 0x100>;
790 clocks = <&cru PCLK_GPIO2>;
791 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
796 interrupt-controller;
797 #interrupt-cells = <0x2>;
800 gpio3: gpio3@ff7a0000 {
801 compatible = "rockchip,gpio-bank";
802 reg = <0x0 0xff7a0000 0x0 0x100>;
803 clocks = <&cru PCLK_GPIO3>;
804 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
809 interrupt-controller;
810 #interrupt-cells = <0x2>;
813 gpio4: gpio4@ff7b0000 {
814 compatible = "rockchip,gpio-bank";
815 reg = <0x0 0xff7b0000 0x0 0x100>;
816 clocks = <&cru PCLK_GPIO4>;
817 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
822 interrupt-controller;
823 #interrupt-cells = <0x2>;
826 gpio5: gpio5@ff7c0000 {
827 compatible = "rockchip,gpio-bank";
828 reg = <0x0 0xff7c0000 0x0 0x100>;
829 clocks = <&cru PCLK_GPIO5>;
830 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
835 interrupt-controller;
836 #interrupt-cells = <0x2>;
839 pcfg_pull_up: pcfg-pull-up {
843 pcfg_pull_down: pcfg-pull-down {
847 pcfg_pull_none: pcfg-pull-none {
851 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
853 drive-strength = <12>;
859 <3 4 RK_FUNC_2 &pcfg_pull_none>;
864 <2 26 RK_FUNC_2 &pcfg_pull_up>;
869 <2 27 RK_FUNC_2 &pcfg_pull_up>;
872 emmc_bus1: emmc-bus1 {
874 <2 18 RK_FUNC_2 &pcfg_pull_up>;
877 emmc_bus4: emmc-bus4 {
879 <2 18 RK_FUNC_2 &pcfg_pull_up>,
880 <2 19 RK_FUNC_2 &pcfg_pull_up>,
881 <2 20 RK_FUNC_2 &pcfg_pull_up>,
882 <2 21 RK_FUNC_2 &pcfg_pull_up>;
885 emmc_bus8: emmc-bus8 {
887 <2 18 RK_FUNC_2 &pcfg_pull_up>,
888 <2 19 RK_FUNC_2 &pcfg_pull_up>,
889 <2 20 RK_FUNC_2 &pcfg_pull_up>,
890 <2 21 RK_FUNC_2 &pcfg_pull_up>,
891 <2 22 RK_FUNC_2 &pcfg_pull_up>,
892 <2 23 RK_FUNC_2 &pcfg_pull_up>,
893 <2 24 RK_FUNC_2 &pcfg_pull_up>,
894 <2 25 RK_FUNC_2 &pcfg_pull_up>;
900 rockchip,pins = <0 9 RK_FUNC_1 &pcfg_pull_up>;
903 sdmmc_bus1: sdmmc-bus1 {
904 rockchip,pins = <5 0 RK_FUNC_1 &pcfg_pull_up>;
907 sdmmc_bus4: sdmmc-bus4 {
908 rockchip,pins = <5 0 RK_FUNC_1 &pcfg_pull_up>,
909 <5 1 RK_FUNC_1 &pcfg_pull_up>,
910 <5 2 RK_FUNC_1 &pcfg_pull_up>,
911 <5 3 RK_FUNC_1 &pcfg_pull_up>;
914 sdmmc_clk: sdmmc-clk {
915 rockchip,pins = <5 4 RK_FUNC_1 &pcfg_pull_none>;
918 sdmmc_cmd: sdmmc-cmd {
919 rockchip,pins = <5 5 RK_FUNC_1 &pcfg_pull_up>;
924 sdio_bus1: sdio-bus1 {
925 rockchip,pins = <3 12 RK_FUNC_1 &pcfg_pull_up>;
928 sdio_bus4: sdio-bus4 {
929 rockchip,pins = <3 12 RK_FUNC_1 &pcfg_pull_up>,
930 <3 13 RK_FUNC_1 &pcfg_pull_up>,
931 <3 14 RK_FUNC_1 &pcfg_pull_up>,
932 <3 15 RK_FUNC_1 &pcfg_pull_up>;
936 rockchip,pins = <3 16 RK_FUNC_1 &pcfg_pull_up>;
940 rockchip,pins = <3 17 RK_FUNC_1 &pcfg_pull_none>;
944 rockchip,pins = <3 18 RK_FUNC_1 &pcfg_pull_up>;
948 rockchip,pins = <3 19 RK_FUNC_1 &pcfg_pull_up>;
952 rockchip,pins = <3 20 RK_FUNC_1 &pcfg_pull_up>;
956 rockchip,pins = <3 21 RK_FUNC_1 &pcfg_pull_up>;
961 hdmii2c_xfer: hdmii2c-xfer {
963 <5 13 RK_FUNC_2 &pcfg_pull_none>,
964 <5 14 RK_FUNC_2 &pcfg_pull_none>;
971 <5 12 RK_FUNC_1 &pcfg_pull_none>;
976 i2c0_xfer: i2c0-xfer {
978 <0 3 RK_FUNC_1 &pcfg_pull_none>,
979 <0 4 RK_FUNC_1 &pcfg_pull_none>;
984 i2c1_xfer: i2c1-xfer {
986 <4 25 RK_FUNC_1 &pcfg_pull_none>,
987 <4 26 RK_FUNC_1 &pcfg_pull_none>;
992 i2c2_xfer: i2c2-xfer {
994 <5 15 RK_FUNC_2 &pcfg_pull_none>,
995 <5 16 RK_FUNC_2 &pcfg_pull_none>;
1000 i2c3_xfer: i2c3-xfer {
1002 <2 16 RK_FUNC_2 &pcfg_pull_none>,
1003 <2 17 RK_FUNC_2 &pcfg_pull_none>;
1008 i2c4_xfer: i2c4-xfer {
1010 <5 8 RK_FUNC_1 &pcfg_pull_none>,
1011 <5 9 RK_FUNC_1 &pcfg_pull_none>;
1016 i2c5_xfer: i2c5-xfer {
1018 <5 13 RK_FUNC_1 &pcfg_pull_none>,
1019 <5 14 RK_FUNC_1 &pcfg_pull_none>;
1021 i2c5_gpio: i2c5-gpio {
1023 <5 13 RK_FUNC_GPIO &pcfg_pull_none>,
1024 <5 14 RK_FUNC_GPIO &pcfg_pull_none>;
1029 i2s_8ch_bus: i2s-8ch-bus {
1031 <4 16 RK_FUNC_1 &pcfg_pull_none>,
1032 <4 17 RK_FUNC_1 &pcfg_pull_none>,
1033 <4 18 RK_FUNC_1 &pcfg_pull_none>,
1034 <4 19 RK_FUNC_1 &pcfg_pull_none>,
1035 <4 20 RK_FUNC_1 &pcfg_pull_none>,
1036 <4 21 RK_FUNC_1 &pcfg_pull_none>,
1037 <4 22 RK_FUNC_1 &pcfg_pull_none>,
1038 <4 23 RK_FUNC_1 &pcfg_pull_none>,
1039 <4 24 RK_FUNC_1 &pcfg_pull_none>;
1044 spi0_clk: spi0-clk {
1046 <2 29 RK_FUNC_2 &pcfg_pull_up>;
1048 spi0_cs0: spi0-cs0 {
1050 <2 24 RK_FUNC_3 &pcfg_pull_up>;
1052 spi0_cs1: spi0-cs1 {
1054 <2 25 RK_FUNC_3 &pcfg_pull_up>;
1058 <2 23 RK_FUNC_3 &pcfg_pull_up>;
1062 <2 22 RK_FUNC_3 &pcfg_pull_up>;
1067 spi1_clk: spi1-clk {
1069 <2 4 RK_FUNC_3 &pcfg_pull_up>;
1071 spi1_cs0: spi1-cs0 {
1073 <2 5 RK_FUNC_3 &pcfg_pull_up>;
1077 <2 6 RK_FUNC_3 &pcfg_pull_up>;
1081 <2 7 RK_FUNC_3 &pcfg_pull_up>;
1086 uart0_xfer: uart0-xfer {
1088 <3 8 RK_FUNC_1 &pcfg_pull_up>,
1089 <3 9 RK_FUNC_1 &pcfg_pull_none>;
1092 uart0_cts: uart0-cts {
1094 <3 10 RK_FUNC_1 &pcfg_pull_none>;
1097 uart0_rts: uart0-rts {
1099 <3 11 RK_FUNC_1 &pcfg_pull_none>;
1104 uart2_t0_xfer: uart2_t0-xfer {
1106 <0 22 RK_FUNC_1 &pcfg_pull_up>,
1107 <0 21 RK_FUNC_1 &pcfg_pull_none>;
1109 /* no rts / cts for uart2 */
1113 uart2_t1_xfer: uart2_t1-xfer {
1115 <5 0 RK_FUNC_2 &pcfg_pull_up>,
1116 <5 1 RK_FUNC_2 &pcfg_pull_none>;
1118 /* no rts / cts for uart2 */
1122 uart2_t2_xfer: uart2_t2-xfer {
1124 <5 14 RK_FUNC_3 &pcfg_pull_up>,
1125 <5 13 RK_FUNC_3 &pcfg_pull_none>;
1127 /* no rts / cts for uart2 */
1131 uart3_xfer: uart3-xfer {
1133 <5 15 RK_FUNC_1 &pcfg_pull_up>,
1134 <5 16 RK_FUNC_1 &pcfg_pull_none>;
1137 uart3_cts: uart3-cts {
1139 <5 17 RK_FUNC_1 &pcfg_pull_none>;
1142 uart3_rts: uart3-rts {
1144 <5 18 RK_FUNC_1 &pcfg_pull_none>;
1149 pwm0_pin: pwm0-pin {
1151 <0 8 RK_FUNC_1 &pcfg_pull_none>;
1156 pwm1_pin: pwm1-pin {
1158 <1 6 RK_FUNC_2 &pcfg_pull_none>;
1163 pwm2_t0_pin: pwm2_t0-pin {
1165 <2 15 RK_FUNC_3 &pcfg_pull_none>;
1170 pwm2_t1_pin: pwm2_t1-pin {
1172 <5 17 RK_FUNC_2 &pcfg_pull_none>;
1177 pwm3_t0_pin: pwm3_t0-pin {
1179 <1 0 RK_FUNC_2 &pcfg_pull_none>;
1184 pwm3_t1_pin: pwm3_t1-pin {
1186 <0 21 RK_FUNC_2 &pcfg_pull_none>;
1191 pwm3_t2_pin: pwm3_t2-pin {
1193 <5 18 RK_FUNC_2 &pcfg_pull_none>;
1198 lcdc_lcdc: lcdc-lcdc {
1200 <0 24 RK_FUNC_2 &pcfg_pull_none>, /* HSYNC */
1201 <0 25 RK_FUNC_2 &pcfg_pull_none>, /* VSYNC */
1202 <0 26 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D10 */
1203 <0 27 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D11 */
1204 <0 28 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D12 */
1205 <0 29 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D13 */
1206 <0 30 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D14 */
1207 <0 31 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D15 */
1208 <1 0 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D16 */
1209 <1 1 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D17 */
1210 <1 2 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D18 */
1211 <1 3 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D19 */
1212 <1 4 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D20 */
1213 <1 5 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D21 */
1214 <1 6 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D22 */
1215 <1 7 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D23 */
1216 <1 8 RK_FUNC_1 &pcfg_pull_none>, /* DEN */
1217 <1 9 RK_FUNC_1 &pcfg_pull_none>; /* DCLK */
1220 lcdc_gpio: lcdc-gpio {
1222 <0 24 RK_FUNC_GPIO &pcfg_pull_none>, /* HSYNC */
1223 <0 25 RK_FUNC_GPIO &pcfg_pull_none>, /* VSYNC */
1224 <0 26 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D10 */
1225 <0 27 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D11 */
1226 <0 28 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D12 */
1227 <0 29 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D13 */
1228 <0 30 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D14 */
1229 <0 31 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D15 */
1230 <1 0 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D16 */
1231 <1 1 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D17 */
1232 <1 2 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D18 */
1233 <1 3 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D19 */
1234 <1 4 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D20 */
1235 <1 5 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D21 */
1236 <1 6 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D22 */
1237 <1 7 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D23 */
1238 <1 8 RK_FUNC_GPIO &pcfg_pull_none>, /* DEN */
1239 <1 9 RK_FUNC_GPIO &pcfg_pull_none>; /* DCLK */
1244 rgmii_pins: rgmii-pins {
1247 <2 7 RK_FUNC_1 &pcfg_pull_none>,
1249 <2 6 RK_FUNC_1 &pcfg_pull_none>,
1251 <2 5 RK_FUNC_1 &pcfg_pull_none>,
1253 <2 4 RK_FUNC_1 &pcfg_pull_none>,
1255 <2 3 RK_FUNC_1 &pcfg_pull_none>,
1257 <2 2 RK_FUNC_1 &pcfg_pull_none>,
1259 <2 1 RK_FUNC_1 &pcfg_pull_none>,
1261 <2 0 RK_FUNC_1 &pcfg_pull_none>,
1263 /* <2 15 RK_FUNC_1 &pcfg_pull_none>, */
1265 <2 14 RK_FUNC_1 &pcfg_pull_none>,
1267 <2 13 RK_FUNC_1 &pcfg_pull_none>,
1269 <2 12 RK_FUNC_1 &pcfg_pull_none>,
1271 <2 11 RK_FUNC_1 &pcfg_pull_none>,
1273 /* <2 10 RK_FUNC_1 &pcfg_pull_none>, */
1275 <2 9 RK_FUNC_1 &pcfg_pull_none>,
1277 <2 8 RK_FUNC_1 &pcfg_pull_none>;
1280 rmii_pins: rmii-pins {
1283 <2 3 RK_FUNC_1 &pcfg_pull_none>,
1285 <2 2 RK_FUNC_1 &pcfg_pull_none>,
1287 <2 1 RK_FUNC_1 &pcfg_pull_none>,
1289 <2 0 RK_FUNC_1 &pcfg_pull_none>,
1291 /* <2 15 RK_FUNC_1 &pcfg_pull_none>, */
1293 <2 14 RK_FUNC_1 &pcfg_pull_none>,
1295 <2 13 RK_FUNC_1 &pcfg_pull_none>,
1297 <2 12 RK_FUNC_1 &pcfg_pull_none>,
1299 <2 11 RK_FUNC_1 &pcfg_pull_none>,
1301 /* <2 10 RK_FUNC_1 &pcfg_pull_none>, */
1303 <2 9 RK_FUNC_1 &pcfg_pull_none>,
1305 <2 8 RK_FUNC_1 &pcfg_pull_none>;
1310 eth_phy_pwr: eth-phy-pwr {
1312 <0 24 RK_FUNC_GPIO &pcfg_pull_none>;