ARM64: dts: rockchip: rk3366: add cpu dvfs support for tb

Change-Id: Ibcefd6e6c0b351310c3768b9b0c1494a2664ff90
Signed-off-by: Feng Xiao <xf@rock-chips.com>

diff --git a/arch/arm64/boot/dts/rockchip/rk3366-tb.dts b/arch/arm64/boot/dts/rockchip/rk3366-tb.dts
index 4dbfc10ee413d8bf27dd7c55c81d4a7649b7bd6d..85b1fee3a54ebfd7e99ec8a9eaf216297cbb8eab 100644 (file)
--- a/arch/arm64/boot/dts/rockchip/rk3366-tb.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3366-tb.dts
@@ -644,3 +644,7 @@
        rockchip,usb-mode = <0>;
        status = "okay";
 };
+
+&cpu0 {
+       cpu-supply = <&syr827>;
+};
\ No newline at end of file

diff --git a/arch/arm64/boot/dts/rockchip/rk3366.dtsi b/arch/arm64/boot/dts/rockchip/rk3366.dtsi
index 91aa38dcd8eb2678156b0a1ecd5522b793a10c4f..950a3a0ed5626b3b32e0690bef764e87107dea42 100644 (file)
--- a/arch/arm64/boot/dts/rockchip/rk3366.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3366.dtsi
@@ -78,6 +78,8 @@
                        compatible = "arm,cortex-a53","arm,armv8";
                        reg = <0x0 0x0>;
                        enable-method = "psci";
+                       clocks = <&cru ARMCLK>;
+                       operating-points-v2 = <&cpu0_opp_table>;
                };
 
                cpu1: cpu@1 {
@@ -85,6 +87,7 @@
                        compatible = "arm,cortex-a53","arm,armv8";
                        reg = <0x0 0x1>;
                        enable-method = "psci";
+                       operating-points-v2 = <&cpu0_opp_table>;
                };
 
                cpu2: cpu@2 {
@@ -92,6 +95,7 @@
                        compatible = "arm,cortex-a53","arm,armv8";
                        reg = <0x0 0x2>;
                        enable-method = "psci";
+                       operating-points-v2 = <&cpu0_opp_table>;
                };
 
                cpu3: cpu@3 {
@@ -99,6 +103,35 @@
                        compatible = "arm,cortex-a53","arm,armv8";
                        reg = <0x0 0x3>;
                        enable-method = "psci";
+                       operating-points-v2 = <&cpu0_opp_table>;
+               };
+       };
+
+       cpu0_opp_table: opp_table0 {
+               compatible = "operating-points-v2";
+               opp-shared;
+
+               opp00 {
+                       opp-hz = /bits/ 64 <408000000>;
+                       opp-microvolt = <1200000>;
+                       clock-latency-ns = <40000>;
+                       opp-suspend;
+               };
+               opp01 {
+                       opp-hz = /bits/ 64 <600000000>;
+                       opp-microvolt = <1200000>;
+               };
+               opp02 {
+                       opp-hz = /bits/ 64 <816000000>;
+                       opp-microvolt = <1200000>;
+               };
+               opp03 {
+                       opp-hz = /bits/ 64 <1008000000>;
+                       opp-microvolt = <1200000>;
+               };
+               opp04 {
+                       opp-hz = /bits/ 64 <1200000000>;
+                       opp-microvolt = <1200000>;
                };
        };