arch/arm/boot/dts/rk3288.dtsi

   1 #include <dt-bindings/interrupt-controller/arm-gic.h>
   2 #include "skeleton.dtsi"
   3 #include "rk3288-pinctrl.dtsi"
   4
   5 / {
   6         compatible = "rockchip,rk3288";
   7         interrupt-parent = <&gic>;
   8
   9         aliases {
  10                 serial2 = &uart_dbg;
  11                 i2c0 = &i2c0;
  12                 i2c1 = &i2c1;
  13                 i2c2 = &i2c2;
  14                 i2c3 = &i2c3;
  15                 i2c4 = &i2c4;
  16         };
  17
  18         cpus {
  19                 #address-cells = <1>;
  20                 #size-cells = <0>;
  21
  22                 cpu@0 {
  23                         device_type = "cpu";
  24                         compatible = "arm,cortex-a15";
  25                         reg = <0x500>;
  26                 };
  27                 cpu@1 {
  28                         device_type = "cpu";
  29                         compatible = "arm,cortex-a15";
  30                         reg = <0x501>;
  31                 };
  32                 cpu@2 {
  33                         device_type = "cpu";
  34                         compatible = "arm,cortex-a15";
  35                         reg = <0x502>;
  36                 };
  37                 cpu@3 {
  38                         device_type = "cpu";
  39                         compatible = "arm,cortex-a15";
  40                         reg = <0x503>;
  41                 };
  42         };
  43
  44         gic: interrupt-controller@ffc01000 {
  45                 compatible = "arm,cortex-a15-gic";
  46                 interrupt-controller;
  47                 #interrupt-cells = <3>;
  48                 #address-cells = <0>;
  49                 reg = <0xffc01000 0x1000>,
  50                       <0xffc02000 0x1000>;
  51         };
  52
  53         timer {
  54                 compatible = "arm,armv7-timer";
  55                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
  56                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
  57                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
  58                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
  59                 clock-frequency = <24000000>;
  60         };
  61
  62         timer@ff810000 {
  63                 compatible = "rockchip,timer";
  64                 reg = <0xff810000 0x20>;
  65                 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
  66                 rockchip,broadcast = <1>;
  67         };
  68
  69         timer@ff810020 {
  70                 compatible = "rockchip,timer";
  71                 reg = <0xff810020 0x20>;
  72                 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
  73                 rockchip,clocksource = <1>;
  74                 rockchip,count-up = <1>;
  75         };
  76
  77         uart_dbg: serial@ff690000 {
  78                 compatible = "rockchip,serial";
  79                 reg = <0xff690000 0x100>;
  80                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
  81                 clock-frequency = <24000000>;
  82                 reg-shift = <2>;
  83                 reg-io-width = <4>;
  84                 status = "disabled";
  85         };
  86
  87         fiq-debugger {
  88                 compatible = "rockchip,fiq-debugger";
  89                 rockchip,serial-id = <2>;
  90                 rockchip,signal-irq = <106>;
  91                 rockchip,wake-irq = <0>;
  92                 status = "disabled";
  93         };
  94
  95
  96
  97         i2c0: i2c@ff650000 {
  98                 compatible = "rockchip,rk30-i2c";
  99                 reg = <0xff650000 0x1000>;
 100                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 101                 #address-cells = <1>;
 102                 #size-cells = <0>;
 103                 //pinctrl-names = "default", "gpio";
 104                 //pinctrl-0 = <&i2c0_sda &i2c0_scl>;
 105                 //pinctrl-1 = <&i2c0_gpio>;
 106                 //gpios = <&gpio0 GPIO_B7 GPIO_ACTIVE_LOW>, <&gpio0 GPIO_C0 GPIO_ACTIVE_LOW>;
 107                 //clocks = <&clk_gates8 4>;
 108                 rockchip,check-idle = <1>;
 109                 status = "disabled";
 110         };
 111
 112         i2c1: i2c@ff140000 {
 113                 compatible = "rockchip,rk30-i2c";
 114                 reg = <0xff140000 0x1000>;
 115                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 116                 #address-cells = <1>;
 117                 #size-cells = <0>;
 118                 //pinctrl-names = "default", "gpio";
 119                 //pinctrl-0 = <&i2c1_sda &i2c1_scl>;
 120                 //pinctrl-1 = <&i2c1_gpio>;
 121                 //gpios = <&gpio8 GPIO_A4 GPIO_ACTIVE_LOW>, <&gpio8 GPIO_A5 GPIO_ACTIVE_LOW>;
 122                 //clocks = <&clk_gates8 5>;
 123            rockchip,check-idle = <1>;
 124       status = "disabled";
 125
 126
 127         };
 128
 129         i2c2: i2c@ff660000 {
 130                 compatible = "rockchip,rk30-i2c";
 131                 reg = <0xff660000 0x1000>;
 132                 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 133                 #address-cells = <1>;
 134                 #size-cells = <0>;
 135                 //pinctrl-names = "default", "gpio";
 136                 //pinctrl-0 = <&i2c2_sda &i2c2_scl>;
 137                 //pinctrl-1 = <&i2c2_gpio>;
 138                 //gpios = <&gpio6 GPIO_B1 GPIO_ACTIVE_LOW>, <&gpio6 GPIO_B2 GPIO_ACTIVE_LOW>;
 139                 //clocks = <&clk_gates8 6>;
 140                 rockchip,check-idle = <1>;
 141                 status = "disabled";
 142         };
 143
 144         i2c3: i2c@ff150000 {
 145                 compatible = "rockchip,rk30-i2c";
 146                 reg = <0xff150000 0x1000>;
 147                 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 148                 #address-cells = <1>;
 149                 #size-cells = <0>;
 150                 //pinctrl-names = "default", "gpio";
 151                 //pinctrl-0 = <&i2c2_sda &i2c2_scl>;
 152                 //pinctrl-1 = <&i2c2_gpio>;
 153                 //gpios = <&gpio2 GPIO_C1 GPIO_ACTIVE_LOW>, <&gpio2 GPIO_C0 GPIO_ACTIVE_LOW>;
 154                 //clocks = <&clk_gates8 6>;
 155                 rockchip,check-idle = <1>;
 156                 status = "disabled";
 157         };
 158
 159         i2c4: i2c@ff160000 {
 160                 compatible = "rockchip,rk30-i2c";
 161                 reg = <0xff160000 0x1000>;
 162                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 163                 #address-cells = <1>;
 164                 #size-cells = <0>;
 165                 //pinctrl-names = "default", "gpio";
 166                 //pinctrl-0 = <&i2c3_sda &i2c3_scl>;
 167                 //pinctrl-1 = <&i2c3_gpio>;
 168                 //gpios = <&gpio7 GPIO_C1 GPIO_ACTIVE_LOW>, <&gpio7 GPIO_C2 GPIO_ACTIVE_LOW>;
 169                 //clocks = <&clk_gates8 7>;
 170                 rockchip,check-idle = <1>;
 171                 status = "disabled";
 172         };
 173
 174    i2c5: i2c@ff170000 {
 175        compatible = "rockchip,rk30-i2c";
 176        reg = <0xff170000 0x1000>;
 177        interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 178        #address-cells = <1>;
 179        #size-cells = <0>;
 180                 //pinctrl-names = "default", "gpio";
 181                 //pinctrl-0 = <&i2c4_sda &i2c4_scl>;
 182                 //pinctrl-1 = <&i2c4_gpio>;
 183                 //gpios = <&gpio7 GPIO_C3 GPIO_ACTIVE_LOW>, <&gpio7 GPIO_C4 GPIO_ACTIVE_LOW>;
 184                 //clocks = <&clk_gates8 8>;
 185        rockchip,check-idle = <1>;
 186        status = "disabled";
 187     };
 188
 189     adc: adc@ff100000 {
 190         compatible = "rockchip,saradc";
 191         reg = <0xff100000 0x100>;
 192         interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 193         #io-channel-cells = <1>;
 194         io-channel-ranges;
 195         rockchip,adc-vref = <1800>;
 196         clock-frequency = <1000000>;
 197         clock-names = "saradc", "pclk_saradc";
 198         status = "disabled";
 199     };
 200
 201         rga@ff930000 {
 202                 compatible = "rockchip,rga";
 203                 reg = <0xff930000 0x1000>;
 204                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 205     clock-names = "hclk_rga", "aclk_rga";
 206                 status = "disabled";
 207         };
 208
 209         i2s: rockchip-i2s@0xff890000 {
 210                 compatible = "rockchip-i2s";
 211                 reg = <0xff890000 0x10000>;
 212                 i2s-id = <0>;
 213         //      clocks = <&clk_i2s>;
 214         //      clock-names = "i2s_clk","i2s_mclk";
 215                 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 216         //      dmas = <&pdma0 0>,
 217         //              <&pdma0 1>;
 218                 //#dma-cells = <2>;
 219         //      dma-names = "tx", "rx";
 220         //      pinctrl-names = "default", "sleep";
 221         //      pinctrl-0 = <&i2s0_mclk &i2s0_sclk &i2s0_lrckrx &i2s0_lrcktx &i2s0_sdi &i2s0_sdo0 &i2s0_sdo1 &i2s0_sdo2 &i2s0_sdo3>;
 222         //      pinctrl-1 = <&i2s0_gpio>;
 223         };
 224
 225         spdif: rockchip-spdif@0xff8b0000 {
 226                 compatible = "rockchip-spdif";
 227                 reg = <0xff8b0000 0x10000>;     //8channel
 228                 //reg = <ff880000 0x2000>;//2channel
 229         //      clocks = <&clk_spdif>;
 230         //      clock-names = "spdif_mclk";
 231                 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 232         //      dmas = <&pdma0 8>;
 233                 //#dma-cells = <1>;
 234         //      dma-names = "tx";
 235         //      pinctrl-names = "default";
 236         //      pinctrl-0 = <&spdif_tx>;
 237         };
 238         ion: ion{
 239                 compatible = "rockchip,ion";
 240                 #address-cells = <1>;
 241                 #size-cells = <0>;
 242                 rockchip,ion-heap@1 { /* CMA HEAP */
 243                         reg = <1>;
 244                 };
 245                 rockchip,ion-heap@3 { /* SYSTEM HEAP */
 246                         reg = <3>;
 247                 };
 248         };
 249 };