arch/arm/boot/dts/rk3288.dtsi

   1 #include <dt-bindings/interrupt-controller/arm-gic.h>
   2 #include "skeleton.dtsi"
   3 #include "rk3288-pinctrl.dtsi"
   4
   5 / {
   6         compatible = "rockchip,rk3288";
   7         interrupt-parent = <&gic>;
   8
   9         aliases {
  10                 serial2 = &uart_dbg;
  11                 i2c0 = &i2c0;
  12                 i2c1 = &i2c1;
  13                 i2c2 = &i2c2;
  14                 i2c3 = &i2c3;
  15                 i2c4 = &i2c4;
  16         };
  17
  18         cpus {
  19                 #address-cells = <1>;
  20                 #size-cells = <0>;
  21
  22                 cpu@0 {
  23                         device_type = "cpu";
  24                         compatible = "arm,cortex-a15";
  25                         reg = <0x500>;
  26                 };
  27                 cpu@1 {
  28                         device_type = "cpu";
  29                         compatible = "arm,cortex-a15";
  30                         reg = <0x501>;
  31                 };
  32                 cpu@2 {
  33                         device_type = "cpu";
  34                         compatible = "arm,cortex-a15";
  35                         reg = <0x502>;
  36                 };
  37                 cpu@3 {
  38                         device_type = "cpu";
  39                         compatible = "arm,cortex-a15";
  40                         reg = <0x503>;
  41                 };
  42         };
  43
  44         gic: interrupt-controller@ffc01000 {
  45                 compatible = "arm,cortex-a15-gic";
  46                 interrupt-controller;
  47                 #interrupt-cells = <3>;
  48                 #address-cells = <0>;
  49                 reg = <0xffc01000 0x1000>,
  50                       <0xffc02000 0x1000>;
  51         };
  52
  53         timer {
  54                 compatible = "arm,armv7-timer";
  55                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
  56                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
  57                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
  58                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
  59                 clock-frequency = <24000000>;
  60         };
  61
  62         timer@ff810000 {
  63                 compatible = "rockchip,timer";
  64                 reg = <0xff810000 0x20>;
  65                 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
  66                 rockchip,broadcast = <1>;
  67         };
  68
  69         timer@ff810020 {
  70                 compatible = "rockchip,timer";
  71                 reg = <0xff810020 0x20>;
  72                 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
  73                 rockchip,clocksource = <1>;
  74                 rockchip,count-up = <1>;
  75         };
  76
  77         uart_dbg: serial@ff690000 {
  78                 compatible = "rockchip,serial";
  79                 reg = <0xff690000 0x100>;
  80                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
  81                 clock-frequency = <24000000>;
  82                 reg-shift = <2>;
  83                 reg-io-width = <4>;
  84                 status = "disabled";
  85         };
  86
  87         fiq-debugger {
  88                 compatible = "rockchip,fiq-debugger";
  89                 rockchip,serial-id = <2>;
  90                 rockchip,signal-irq = <106>;
  91                 rockchip,wake-irq = <0>;
  92                 status = "disabled";
  93         };
  94
  95
  96
  97         i2c0: i2c@2002d000 {
  98                 compatible = "rockchip,rk30-i2c";
  99                 reg = <0x2002d000 0x1000>;
 100                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 101                 #address-cells = <1>;
 102                 #size-cells = <0>;
 103                 pinctrl-names = "default", "gpio";
 104                 pinctrl-0 = <&i2c0_sda &i2c0_scl>;
 105                 pinctrl-1 = <&i2c0_gpio>;
 106                 gpios = <&gpio1 GPIO_D0 GPIO_ACTIVE_LOW>, <&gpio1 GPIO_D1 GPIO_ACTIVE_LOW>;
 107                 clocks = <&clk_gates8 4>;
 108                 rockchip,check-idle = <1>;
 109                 status = "disabled";
 110         };
 111
 112         i2c1: i2c@2002f000 {
 113                 compatible = "rockchip,rk30-i2c";
 114                 reg = <0x2002f000 0x1000>;
 115                 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 116                 #address-cells = <1>;
 117                 #size-cells = <0>;
 118                 pinctrl-names = "default", "gpio";
 119                 pinctrl-0 = <&i2c1_sda &i2c1_scl>;
 120                 pinctrl-1 = <&i2c1_gpio>;
 121                 gpios = <&gpio1 GPIO_D2 GPIO_ACTIVE_LOW>, <&gpio1 GPIO_D3 GPIO_ACTIVE_LOW>;
 122                 clocks = <&clk_gates8 5>;
 123                 rockchip,check-idle = <1>;
 124                 status = "disabled";
 125         };
 126
 127         i2c2: i2c@20056000 {
 128                 compatible = "rockchip,rk30-i2c";
 129                 reg = <0x20056000 0x1000>;
 130                 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
 131                 #address-cells = <1>;
 132                 #size-cells = <0>;
 133                 pinctrl-names = "default", "gpio";
 134                 pinctrl-0 = <&i2c2_sda &i2c2_scl>;
 135                 pinctrl-1 = <&i2c2_gpio>;
 136                 gpios = <&gpio1 GPIO_D4 GPIO_ACTIVE_LOW>, <&gpio1 GPIO_D5 GPIO_ACTIVE_LOW>;
 137                 clocks = <&clk_gates8 6>;
 138                 rockchip,check-idle = <1>;
 139                 status = "disabled";
 140         };
 141
 142         i2c3: i2c@2005a000 {
 143                 compatible = "rockchip,rk30-i2c";
 144                 reg = <0x2005a000 0x1000>;
 145                 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
 146                 #address-cells = <1>;
 147                 #size-cells = <0>;
 148                 pinctrl-names = "default", "gpio";
 149                 pinctrl-0 = <&i2c3_sda &i2c3_scl>;
 150                 pinctrl-1 = <&i2c3_gpio>;
 151                 gpios = <&gpio3 GPIO_B6 GPIO_ACTIVE_LOW>, <&gpio3 GPIO_B7 GPIO_ACTIVE_LOW>;
 152                 clocks = <&clk_gates8 7>;
 153                 rockchip,check-idle = <1>;
 154                 status = "disabled";
 155         };
 156
 157         i2c4: i2c@2005e000 {
 158                 compatible = "rockchip,rk30-i2c";
 159                 reg = <0x2005e000 0x1000>;
 160                 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
 161                 #address-cells = <1>;
 162                 #size-cells = <0>;
 163                 pinctrl-names = "default", "gpio";
 164                 pinctrl-0 = <&i2c4_sda &i2c4_scl>;
 165                 pinctrl-1 = <&i2c4_gpio>;
 166                 gpios = <&gpio1 GPIO_D6 GPIO_ACTIVE_LOW>, <&gpio1 GPIO_D7 GPIO_ACTIVE_LOW>;
 167                 clocks = <&clk_gates8 8>;
 168                 rockchip,check-idle = <1>;
 169                 status = "disabled";
 170         };
 171
 172     adc: adc@2006c000 {
 173            compatible = "rockchip,saradc";
 174            reg = <0x2006c000 0x100>;
 175            interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 176            #io-channel-cells = <1>;
 177            io-channel-ranges;
 178            rockchip,adc-vref = <1800>;
 179            clock-frequency = <1000000>;
 180            clocks = <&clk_saradc>, <&clk_gates7 14>;
 181            clock-names = "saradc", "pclk_saradc";
 182            status = "disabled";
 183     };
 184
 185         rga@ff930000 {
 186                 compatible = "rockchip,rga";
 187                 reg = <0xff930000 0x1000>;
 188                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 189                 clocks = <&clk_gates6 10>, <&clk_gates6 11>;
 190     clock-names = "hclk_rga", "aclk_rga";
 191                 status = "disabled";
 192         };
 193 };