arch/arm/boot/dts/rk3288.dtsi

   1 #include <dt-bindings/clock/rk_system_status.h>
   2 #include <dt-bindings/interrupt-controller/arm-gic.h>
   3 #include <dt-bindings/rkfb/rk_fb.h>
   4 #include <dt-bindings/rkmipi/mipi_dsi.h>
   5 #include <dt-bindings/suspend/rockchip-pm.h>
   6 #include <dt-bindings/sensor-dev.h>
   7
   8 #include "skeleton.dtsi"
   9 #include "rk3288-pinctrl.dtsi"
  10 #include "rk3288-clocks.dtsi"
  11
  12 / {
  13         compatible = "rockchip,rk3288";
  14         rockchip,sram = <&sram>;
  15         interrupt-parent = <&gic>;
  16
  17         aliases {
  18                 serial0 = &uart_bt;
  19                 serial1 = &uart_bb;
  20                 serial2 = &uart_dbg;
  21                 serial3 = &uart_gps;
  22                 serial4 = &uart_exp;
  23                 i2c0 = &i2c0;
  24                 i2c1 = &i2c1;
  25                 i2c2 = &i2c2;
  26                 i2c3 = &i2c3;
  27                 i2c4 = &i2c4;
  28                 i2c5 = &i2c5;
  29                 lcdc0 = &lcdc0;
  30                 lcdc1 = &lcdc1;
  31                 spi0 = &spi0;
  32                 spi1 = &spi1;
  33                 spi2 = &spi2;
  34         };
  35
  36         cpus {
  37                 #address-cells = <1>;
  38                 #size-cells = <0>;
  39
  40                 cpu@0 {
  41                         device_type = "cpu";
  42                         compatible = "arm,cortex-a15";
  43                         reg = <0x500>;
  44                 };
  45                 cpu@1 {
  46                         device_type = "cpu";
  47                         compatible = "arm,cortex-a15";
  48                         reg = <0x501>;
  49                 };
  50                 cpu@2 {
  51                         device_type = "cpu";
  52                         compatible = "arm,cortex-a15";
  53                         reg = <0x502>;
  54                 };
  55                 cpu@3 {
  56                         device_type = "cpu";
  57                         compatible = "arm,cortex-a15";
  58                         reg = <0x503>;
  59                 };
  60         };
  61
  62         gic: interrupt-controller@ffc01000 {
  63                 compatible = "arm,cortex-a15-gic";
  64                 interrupt-controller;
  65                 #interrupt-cells = <3>;
  66                 #address-cells = <0>;
  67                 reg = <0xffc01000 0x1000>,
  68                       <0xffc02000 0x1000>;
  69         };
  70
  71         arm-pmu {
  72                 compatible = "arm,cortex-a12-pmu";
  73                 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
  74                              <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
  75                              <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
  76                              <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
  77         };
  78
  79         cpu_axi_bus: cpu_axi_bus {
  80                 compatible = "rockchip,cpu_axi_bus";
  81                 #address-cells = <1>;
  82                 #size-cells = <1>;
  83                 ranges;
  84
  85                 qos {
  86                         #address-cells = <1>;
  87                         #size-cells = <1>;
  88                         ranges;
  89                         /* service core */
  90                         cpup {
  91                                 reg = <0xffa80000 0x20>;
  92                         };
  93                         cpum_r {
  94                                 reg = <0xffa80080 0x20>;
  95                         };
  96                         cpum_w {
  97                                 reg = <0xffa80100 0x20>;
  98                         };
  99                         /* service dmac */
 100                         bus_dmac {
 101                                 reg = <0xffa90000 0x20>;
 102                         };
 103                         host {
 104                                 reg = <0xffa90080 0x20>;
 105                         };
 106                         crypto {
 107                                 reg = <0xffa90100 0x20>;
 108                         };
 109                         ccp {
 110                                 reg = <0xffa90180 0x20>;
 111                         };
 112                         ccs {
 113                                 reg = <0xffa90200 0x20>;
 114                         };
 115                         /* service gpu */
 116                         gpu_r {
 117                                 reg = <0xffaa0000 0x20>;
 118                         };
 119                         gpu_w {
 120                                 reg = <0xffaa0080 0x20>;
 121                         };
 122                         /* service peri */
 123                         peri {
 124                                 reg = <0xffab0000 0x20>;
 125                         };
 126                         /* service vio */
 127                         vio1_vop {
 128                                 reg = <0xffad0000 0x20>;
 129                                 rockchip,priority = <2 2>;
 130                         };
 131                         vio1_isp_w0 {
 132                                 reg = <0xffad0100 0x20>;
 133                                 rockchip,priority = <2 2>;
 134                         };
 135                         vio1_isp_w1 {
 136                                 reg = <0xffad0180 0x20>;
 137                         };
 138                         vio0_vop {
 139                                 reg = <0xffad0400 0x20>;
 140                                 rockchip,priority = <2 2>;
 141                         };
 142                         vio0_vip {
 143                                 reg = <0xffad0480 0x20>;
 144                         };
 145                         vio0_iep {
 146                                 reg = <0xffad0500 0x20>;
 147                         };
 148                         vio2_rga_r {
 149                                 reg = <0xffad0800 0x20>;
 150                         };
 151                         vio2_rga_w {
 152                                 reg = <0xffad0880 0x20>;
 153                         };
 154                         vio1_isp_r {
 155                                 reg = <0xffad0900 0x20>;
 156                         };
 157                         /* service video */
 158                         video {
 159                                 reg = <0xffae0000 0x20>;
 160                         };
 161                         /* service hevc */
 162                         hevc_r {
 163                                 reg = <0xffaf0000 0x20>;
 164                         };
 165                         hevc_w {
 166                                 reg = <0xffaf0080 0x20>;
 167                         };
 168                 };
 169
 170                 msch {
 171                         #address-cells = <1>;
 172                         #size-cells = <1>;
 173                         ranges;
 174
 175                         msch@0 {
 176                                 reg = <0xffac0000 0x40>;
 177                                 rockchip,read-latency = <0x34>;
 178                         };
 179                         msch@1 {
 180                                 reg = <0xffac0080 0x40>;
 181                                 rockchip,read-latency = <0x34>;
 182                         };
 183                 };
 184         };
 185
 186         sram: sram@ff710000 {
 187                 compatible = "mmio-sram";
 188                 reg = <0xff710000 0x8000>; /* 32k */
 189                 map-exec;
 190         };
 191
 192         timer {
 193                 compatible = "arm,armv7-timer";
 194                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 195                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 196                 clock-frequency = <24000000>;
 197         };
 198
 199         timer@ff810000 {
 200                 compatible = "rockchip,timer";
 201                 reg = <0xff810000 0x20>;
 202                 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
 203                 rockchip,broadcast = <1>;
 204         };
 205
 206         watchdog: wdt@2004c000 {
 207                 compatible = "rockchip,watch dog";
 208                 reg = <0xff800000 0x100>;
 209                 clocks = <&pclk_pd_alive>;
 210                 clock-names = "pclk_wdt";
 211                 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
 212                 rockchip,irq = <1>;
 213                 rockchip,timeout = <60>;
 214                 rockchip,atboot = <1>;
 215                 rockchip,debug = <0>;
 216                 status = "disabled";
 217         };
 218
 219         amba {
 220                 #address-cells = <1>;
 221                 #size-cells = <1>;
 222                 compatible = "arm,amba-bus";
 223                 interrupt-parent = <&gic>;
 224                 ranges;
 225
 226                 pdma0: pdma@ffb20000 {
 227                         compatible = "arm,pl330", "arm,primecell";
 228                         reg = <0xffb20000 0x4000>;
 229                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 230                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 231                         #dma-cells = <1>;
 232                 };
 233
 234                 pdma1: pdma@ff250000 {
 235                         compatible = "arm,pl330", "arm,primecell";
 236                         reg = <0xff250000 0x4000>;
 237                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
 238                                      <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 239                         #dma-cells = <1>;
 240                 };
 241         };
 242
 243         reset: reset@ff7601b8{
 244                 compatible = "rockchip,reset";
 245                 reg = <0xff7601b8 0x30>;
 246                 rockchip,reset-flag = <ROCKCHIP_RESET_HIWORD_MASK>;
 247                 #reset-cells = <1>;
 248         };
 249
 250         nandc0: nandc@0xff400000 {
 251                 compatible = "rockchip,rk-nandc";
 252                 reg = <0xff400000 0x4000>;
 253                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 254                 nandc_id = <0>;
 255                 clocks = <&clk_nandc0>, <&clk_gates5 5>, <&clk_gates7 14>;
 256                 clock-names = "clk_nandc", "g_clk_nandc", "hclk_nandc";
 257         };
 258
 259         nandc1: nandc@0xff410000 {
 260             compatible = "rockchip,rk-nandc";
 261                 reg = <0xff410000 0x4000>;
 262                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 263                 nandc_id = <1>;
 264                 clocks = <&clk_nandc1>, <&clk_gates5 6>, <&clk_gates7 15>;
 265                 clock-names = "clk_nandc", "g_clk_nandc", "hclk_nandc";
 266         };
 267
 268         nandc0reg: nandc0@0xff400000 {
 269                 compatible = "rockchip,rk-nandc";
 270                 reg = <0xff400000 0x4000>;
 271         };
 272
 273         emmc: rksdmmc@ff0f0000 {
 274                 compatible = "rockchip,rk_mmc", "rockchip,rk32xx-sdmmc";
 275                 reg = <0xff0f0000 0x4000>;
 276                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 277                 #address-cells = <1>;
 278                 #size-cells = <0>;
 279                 //pinctrl-names = "default",,"suspend";
 280                 //pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_wp &sd0_pwr &sd0_bus1 &sd0_bus4>;
 281                 clocks = <&clk_emmc>, <&clk_gates8 6>;
 282                 clock-names = "clk_mmc", "hclk_mmc";
 283                 num-slots = <1>;
 284                 fifo-depth = <0x100>;
 285                 bus-width = <8>;
 286         };
 287
 288         sdmmc: rksdmmc@ff0c0000 {
 289                 compatible = "rockchip,rk_mmc", "rockchip,rk32xx-sdmmc";
 290                 reg = <0xff0c0000 0x4000>;
 291                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 292                 #address-cells = <1>;
 293                 #size-cells = <0>;
 294                 pinctrl-names = "default", "idle";
 295                 pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_dectn &sdmmc0_bus4>;
 296                 pinctrl-1 = <&sdmmc0_gpio>;
 297                 cd-gpios = <&gpio6 GPIO_C6 GPIO_ACTIVE_HIGH>;/*CD GPIO*/
 298                 clocks = <&clk_sdmmc>, <&clk_gates8 3>;
 299                 clock-names = "clk_mmc", "hclk_mmc";
 300                 num-slots = <1>;
 301                 fifo-depth = <0x100>;
 302                 bus-width = <4>;
 303         };
 304
 305         sdio: rksdmmc@ff0d0000 {
 306                 compatible = "rockchip,rk_mmc", "rockchip,rk32xx-sdmmc";
 307                 reg = <0xff0d0000 0x4000>;
 308                 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 309                 #address-cells = <1>;
 310                 #size-cells = <0>;
 311                 pinctrl-names = "default","idle";
 312                 pinctrl-0 = <&sdio0_clk &sdio0_cmd &sdio0_wrprt &sdio0_pwr &sdio0_bkpwr
 313                              &sdio0_intn &sdio0_bus4>;
 314                 pinctrl-1 = <&sdio0_gpio>;
 315                 clocks = <&clk_sdio0>, <&clk_gates8 4>;
 316                 clock-names = "clk_mmc", "hclk_mmc";
 317                 num-slots = <1>;
 318                 fifo-depth = <0x100>;
 319                 bus-width = <4>;
 320         };
 321
 322         sdio1: rksdmmc@ff0e0000 {
 323                 compatible = "rockchip,rk_mmc", "rockchip,rk32xx-sdmmc";
 324                 reg = <0xff0e0000 0x4000>;
 325                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 326                 #address-cells = <1>;
 327                 #size-cells = <0>;
 328                 //pinctrl-names = "default","suspend";
 329                 //pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_cd &sd1_wp &sd1_bus1 &sd1_bus4>;
 330                 /*gate8_0 --hclk_sdmmc_ahb_arbi_gate_en, gate13_2 --clk_sdio1_src_gate_en*/
 331                 clocks = <&clk_sdio1>, <&clk_gates8 5>;
 332                 clock-names = "clk_mmc", "hclk_mmc";
 333                 num-slots = <1>;
 334                 fifo-depth = <0x100>;
 335                 bus-width = <4>;
 336                 status = "disabled";
 337         };
 338
 339         spi0: spi@ff110000 {
 340                 compatible = "rockchip,rockchip-spi";
 341                 reg = <0xff110000 0x1000>;
 342                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 343                 #address-cells = <1>;
 344                 #size-cells = <0>;
 345                 pinctrl-names = "default";
 346                 pinctrl-0 = <&spi0_txd &spi0_rxd &spi0_clk &spi0_cs0 &spi0_cs1>;
 347                 rockchip,spi-src-clk = <0>;
 348                 num-cs = <2>;
 349                 clocks =<&clk_spi0>, <&clk_gates6 4>;
 350                 clock-names = "spi","pclk_spi0";
 351                 //dmas = <&pdma1 11>, <&pdma1 12>;
 352                 //#dma-cells = <2>;
 353                 //dma-names = "tx", "rx";
 354                 status = "disabled";
 355         };
 356
 357         spi1: spi@ff120000 {
 358                 compatible = "rockchip,rockchip-spi";
 359                 reg = <0xff120000 0x1000>;
 360                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 361                 #address-cells = <1>;
 362                 #size-cells = <0>;
 363                 pinctrl-names = "default";
 364                 pinctrl-0 = <&spi1_txd &spi1_rxd &spi1_clk &spi1_cs0>;
 365                 rockchip,spi-src-clk = <1>;
 366                 num-cs = <1>;
 367                 clocks = <&clk_spi1>, <&clk_gates6 5>;
 368                 clock-names = "spi","pclk_spi1";
 369                 //dmas = <&pdma1 13>, <&pdma1 14>;
 370                 //#dma-cells = <2>;
 371                 //dma-names = "tx", "rx";
 372                 status = "disabled";
 373         };
 374
 375         spi2: spi@ff130000 {
 376                 compatible = "rockchip,rockchip-spi";
 377                 reg = <0xff130000 0x1000>;
 378                 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 379                 #address-cells = <1>;
 380                 #size-cells = <0>;
 381                 pinctrl-names = "default";
 382                 pinctrl-0 = <&spi2_txd &spi2_rxd &spi2_clk &spi2_cs0 &spi2_cs1>;
 383                 rockchip,spi-src-clk = <2>;
 384                 num-cs = <2>;
 385                 clocks = <&clk_spi2>, <&clk_gates6 6>;
 386                 clock-names = "spi","pclk_spi2";
 387                 //dmas = <&pdma1 15>, <&pdma1 16>;
 388                 //#dma-cells = <2>;
 389                 //dma-names = "tx", "rx";
 390                 status = "disabled";
 391         };
 392
 393         uart_bt: serial@ff180000 {
 394                 compatible = "rockchip,serial";
 395                 reg = <0xff180000 0x100>;
 396                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 397                 clock-frequency = <24000000>;
 398                 clocks = <&clk_uart0>, <&clk_gates6 8>;
 399                 clock-names = "sclk_uart", "pclk_uart";
 400                 reg-shift = <2>;
 401                 reg-io-width = <4>;
 402                 dmas = <&pdma1 1>, <&pdma1 2>;
 403                 #dma-cells = <2>;
 404                 pinctrl-names = "default";
 405                 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
 406                 status = "disabled";
 407         };
 408
 409         uart_bb: serial@ff190000 {
 410                 compatible = "rockchip,serial";
 411                 reg = <0xff190000 0x100>;
 412                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 413                 clock-frequency = <24000000>;
 414                 clocks = <&clk_uart1>, <&clk_gates6 9>;
 415                 clock-names = "sclk_uart", "pclk_uart";
 416                 reg-shift = <2>;
 417                 reg-io-width = <4>;
 418                 dmas = <&pdma1 3>, <&pdma1 4>;
 419                 #dma-cells = <2>;
 420                 pinctrl-names = "default";
 421                 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
 422                 status = "disabled";
 423         };
 424
 425         uart_dbg: serial@ff690000 {
 426                 compatible = "rockchip,serial";
 427                 reg = <0xff690000 0x100>;
 428                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 429                 clock-frequency = <24000000>;
 430                 clocks = <&clk_uart2>, <&clk_gates11 9>;
 431                 clock-names = "sclk_uart", "pclk_uart";
 432                 reg-shift = <2>;
 433                 reg-io-width = <4>;
 434                 dmas = <&pdma0 4>, <&pdma0 5>;
 435                 #dma-cells = <2>;
 436                 pinctrl-names = "default";
 437                 pinctrl-0 = <&uart2_xfer>;
 438                 status = "disabled";
 439         };
 440
 441         uart_gps: serial@ff1b0000 {
 442                 compatible = "rockchip,serial";
 443                 reg = <0xff1b0000 0x100>;
 444                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 445                 clock-frequency = <24000000>;
 446                 clocks = <&clk_uart3>, <&clk_gates6 11>;
 447                 clock-names = "sclk_uart", "pclk_uart";
 448                 current-speed = <115200>;
 449                 reg-shift = <2>;
 450                 reg-io-width = <4>;
 451                 dmas = <&pdma1 7>, <&pdma1 8>;
 452                 #dma-cells = <2>;
 453                 pinctrl-names = "default";
 454                 pinctrl-0 = <&uart3_xfer &uart3_cts &uart3_rts>;
 455                 status = "disabled";
 456         };
 457
 458         uart_exp: serial@ff1c0000 {
 459                 compatible = "rockchip,serial";
 460                 reg = <0xff1c0000 0x100>;
 461                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 462                 clock-frequency = <24000000>;
 463                 clocks = <&clk_uart4>, <&clk_gates6 12>;
 464                 clock-names = "sclk_uart", "pclk_uart";
 465                 reg-shift = <2>;
 466                 reg-io-width = <4>;
 467                 dmas = <&pdma1 9>, <&pdma1 10>;
 468                 #dma-cells = <2>;
 469                 pinctrl-names = "default";
 470                 pinctrl-0 = <&uart4_xfer &uart4_cts &uart4_rts>;
 471                 status = "disabled";
 472         };
 473
 474         fiq-debugger {
 475                 compatible = "rockchip,fiq-debugger";
 476                 rockchip,serial-id = <2>;
 477                 rockchip,signal-irq = <106>;
 478                 rockchip,wake-irq = <0>;
 479                 status = "disabled";
 480         };
 481
 482         rockchip_clocks_init: clocks-init{
 483                 compatible = "rockchip,clocks-init";
 484                 rockchip,clocks-init-parent =
 485                         <&clk_core &clk_apll>,  <&aclk_bus_src &clk_gpll>,
 486                         <&aclk_peri &clk_gpll>, <&uart_pll_mux &clk_gpll>,
 487                         <&clk_i2s_pll &clk_gpll>, <&clk_spdif_pll &clk_gpll>,
 488                         <&usbphy_480m &otgphy2_480m>;
 489                 rockchip,clocks-init-rate =
 490                         <&clk_core 792000000>,  <&clk_gpll 297000000>,
 491                         /*<&clk_cpll 47000000>,*/       <&clk_npll 1250000000>,
 492                         <&aclk_bus_src 300000000>,      <&aclk_bus 300000000>,
 493                         <&hclk_bus 150000000>,  <&pclk_bus 75000000>,
 494                         <&clk_crypto 150000000>,        <&aclk_peri 300000000>,
 495                         <&hclk_peri 150000000>, <&pclk_peri 75000000>,
 496                         <&clk_gpu 200000000>,   <&aclk_vio0 300000000>,
 497                         <&aclk_vio1 300000000>, <&hclk_vio 75000000>,
 498                         <&pclk_pd_alive 100000000>,     <&pclk_pd_pmu 100000000>,
 499                         <&aclk_hevc 400000000>, <&hclk_hevc 200000000>,
 500                         <&clk_hevc_cabac 300000000>, <&clk_hevc_core 300000000>,
 501                         <&aclk_rga 300000000>, <&clk_rga 300000000>,
 502                         <&clk_vepu 300000000>, <&clk_vdpu 300000000>,
 503                         <&clk_edp 200000000>, <&clk_isp 200000000>,
 504                         <&clk_isp_jpe 400000000>, <&clk_tsp 80000000>,
 505                         <&clk_tspout 80000000>, <&clk_mac 125000000>;
 506                 rockchip,clocks-uboot-has-init =
 507                         <&aclk_vio0>;
 508         };
 509
 510         clocks-enable {
 511                 compatible = "rockchip,clocks-enable";
 512                 clocks =
 513                                 /*PD_CORE*/
 514                                 <&clk_gates0 2>, <&clk_core0>,
 515                                 <&clk_core1>, <&clk_core2>,
 516                                 <&clk_core3>, <&clk_l2ram>,
 517                                 <&aclk_core_m0>, <&aclk_core_mp>,
 518                                 <&atclk_core>, <&pclk_dbg_src>,
 519                                 <&clk_gates12 9>, <&clk_gates12 10>,
 520                                 <&clk_gates12 11>,
 521
 522                                 /*PD_BUS*/
 523                                 <&aclk_bus>, <&clk_gates0 3>,
 524                                 <&hclk_bus>, <&pclk_bus>,
 525                                 <&clk_gates13 8>,
 526                                 <&clk_gates0 7>,
 527
 528                                 /*TIMER*/
 529                                 <&clk_gates1 0>, <&clk_gates1 1>,
 530                                 <&clk_gates1 2>, <&clk_gates1 3>,
 531                                 <&clk_gates1 4>, <&clk_gates1 5>,
 532
 533                                 <&pclk_pd_alive>, <&pclk_pd_pmu>,
 534
 535                                 /*PD_PERI*/
 536                                 <&aclk_peri>, <&hclk_peri>,
 537                                 <&pclk_peri>,
 538
 539                                 /*JTAG*/
 540                                 /*<&clk_gates4 14>,*/
 541
 542                                 /*aclk_bus*/
 543                                 <&clk_gates10 5>,/*aclk_intmem0*/
 544                                 <&clk_gates10 6>,/*aclk_intmem1*/
 545                                 <&clk_gates10 7>,/*aclk_intmem2*/
 546                                 <&clk_gates10 12>,/*aclk_dma1*/
 547                                 <&clk_gates10 13>,/*aclk_strc_sys*/
 548                                 <&clk_gates10 4>,/*aclk_intmem*/
 549
 550                                 /*hclk_bus*/
 551                                 <&clk_gates10 9>,/*hclk_rom*/
 552
 553                                 /*pclk_bus*/
 554                                 <&clk_gates10 1>,/*pclk_timer*/
 555                                 <&clk_gates10 9>,/*rom*/
 556                                 <&clk_gates10 13>,/*aclk strc*/
 557
 558                                 <&clk_gates12 8>,/*aclk strc*/
 559
 560                                 /*aclk_peri*/
 561                                 <&clk_gates6 2>,/*aclk_peri_axi_matrix*/
 562                                 <&clk_gates6 3>,/*aclk_dmac2*/
 563                                 <&clk_gates7 11>,/*aclk_peri_niu*/
 564                                 <&clk_gates8 12>,/*aclk_peri_mmu*/
 565
 566                                 /*hclk_peri*/
 567                                 <&clk_gates6 0>,/*hclk_peri_matrix*/
 568                                 <&clk_gates7 10>,/*hclk_peri_ahb_arbi*/
 569                                 <&clk_gates7 12>,/*hclk_emem_peri*/
 570                                 <&clk_gates7 13>,/*hclk_mem_peri*/
 571
 572                                 /*pclk_peri*/
 573                                 <&clk_gates6 1>,/*pclk_peri_axi_matrix*/
 574
 575                                 /*pclk_pd_alive*/
 576                                 <&clk_gates14 11>,/*pclk_grf*/
 577                                 <&clk_gates14 12>,/*pclk_alive_niu*/
 578
 579                                 /*pclk_pd_pmu*/
 580                                 <&clk_gates17 0>,/*pclk_pmu*/
 581                                 <&clk_gates17 1>,/*pclk_intmem1*/
 582                                 <&clk_gates17 2>,/*pclk_pmu_niu*/
 583                                 <&clk_gates17 3>,/*pclk_sgrf*/
 584
 585                                 /*hclk_vio*/
 586                                 <&clk_gates15 9>,/*hclk_vio_ahb_arbi*/
 587                                 <&clk_gates15 10>,/*hclk_vio_niu*/
 588                                 <&clk_gates16 10>,/*hclk_vio2_h2p*/
 589                                 <&clk_gates16 11>,/*pclk_vio2_h2p*/
 590
 591                                 /*aclk_vio0*/
 592                                 <&clk_gates15 11>,/*aclk_vio0_niu*/
 593
 594                                 /*aclk_vio1*/
 595                                 <&clk_gates15 12>,/*aclk_vio1_niu*/
 596
 597                                 /*HDMI*/
 598                                 //<&clk_gates5 12>,/*hdmi_hdcp_clk*/
 599
 600                                 /*UART*/
 601                                 <&clk_gates11 9>,/*pclk_uart2*/
 602
 603                                 /*480M*/
 604                                 <&usbphy_480m>;
 605         };
 606
 607         i2c0: i2c@ff650000 {
 608                 compatible = "rockchip,rk30-i2c";
 609                 reg = <0xff650000 0x1000>;
 610                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 611                 #address-cells = <1>;
 612                 #size-cells = <0>;
 613                 pinctrl-names = "default", "gpio";
 614                 pinctrl-0 = <&i2c0_sda &i2c0_scl>;
 615                 pinctrl-1 = <&i2c0_gpio>;
 616                 gpios = <&gpio0 GPIO_B7 GPIO_ACTIVE_LOW>, <&gpio0 GPIO_C0 GPIO_ACTIVE_LOW>;
 617                 clocks = <&clk_gates10 2>;
 618                 rockchip,check-idle = <1>;
 619                 status = "disabled";
 620         };
 621
 622         i2c1: i2c@ff140000 {
 623                 compatible = "rockchip,rk30-i2c";
 624                 reg = <0xff140000 0x1000>;
 625                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 626                 #address-cells = <1>;
 627                 #size-cells = <0>;
 628                 pinctrl-names = "default", "gpio";
 629                 pinctrl-0 = <&i2c1_sda &i2c1_scl>;
 630                 pinctrl-1 = <&i2c1_gpio>;
 631                 gpios = <&gpio8 GPIO_A4 GPIO_ACTIVE_LOW>, <&gpio8 GPIO_A5 GPIO_ACTIVE_LOW>;
 632                 clocks = <&clk_gates6 13>;
 633                 rockchip,check-idle = <1>;
 634                 status = "disabled";
 635         };
 636
 637         i2c2: i2c@ff660000 {
 638                 compatible = "rockchip,rk30-i2c";
 639                 reg = <0xff660000 0x1000>;
 640                 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 641                 #address-cells = <1>;
 642                 #size-cells = <0>;
 643                 pinctrl-names = "default", "gpio";
 644                 pinctrl-0 = <&i2c2_sda &i2c2_scl>;
 645                 pinctrl-1 = <&i2c2_gpio>;
 646                 gpios = <&gpio6 GPIO_B1 GPIO_ACTIVE_LOW>, <&gpio6 GPIO_B2 GPIO_ACTIVE_LOW>;
 647                 clocks = <&clk_gates10 3>;
 648                 rockchip,check-idle = <1>;
 649                 status = "disabled";
 650         };
 651
 652         i2c3: i2c@ff150000 {
 653                 compatible = "rockchip,rk30-i2c";
 654                 reg = <0xff150000 0x1000>;
 655                 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 656                 #address-cells = <1>;
 657                 #size-cells = <0>;
 658                 pinctrl-names = "default", "gpio";
 659                 pinctrl-0 = <&i2c3_sda &i2c3_scl>;
 660                 pinctrl-1 = <&i2c3_gpio>;
 661                 gpios = <&gpio2 GPIO_C1 GPIO_ACTIVE_LOW>, <&gpio2 GPIO_C0 GPIO_ACTIVE_LOW>;
 662                 clocks = <&clk_gates6 14>;
 663                 rockchip,check-idle = <1>;
 664                 status = "disabled";
 665         };
 666
 667         i2c4: i2c@ff160000 {
 668                 compatible = "rockchip,rk30-i2c";
 669                 reg = <0xff160000 0x1000>;
 670                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 671                 #address-cells = <1>;
 672                 #size-cells = <0>;
 673                 pinctrl-names = "default", "gpio";
 674                 pinctrl-0 = <&i2c4_sda &i2c4_scl>;
 675                 pinctrl-1 = <&i2c4_gpio>;
 676                 gpios = <&gpio7 GPIO_C1 GPIO_ACTIVE_LOW>, <&gpio7 GPIO_C2 GPIO_ACTIVE_LOW>;
 677                 clocks = <&clk_gates6 15>;
 678                 rockchip,check-idle = <1>;
 679                 status = "disabled";
 680         };
 681
 682         i2c5: i2c@ff170000 {
 683                 compatible = "rockchip,rk30-i2c";
 684                 reg = <0xff170000 0x1000>;
 685                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 686                 #address-cells = <1>;
 687                 #size-cells = <0>;
 688                 pinctrl-names = "default", "gpio";
 689                 pinctrl-0 = <&i2c5_sda &i2c5_scl>;
 690                 pinctrl-1 = <&i2c5_gpio>;
 691                 gpios = <&gpio7 GPIO_C3 GPIO_ACTIVE_LOW>, <&gpio7 GPIO_C4 GPIO_ACTIVE_LOW>;
 692                 clocks = <&clk_gates7 0>;
 693                 rockchip,check-idle = <1>;
 694                 status = "disabled";
 695         };
 696
 697         fb: fb{
 698                 compatible = "rockchip,rk-fb";
 699                 rockchip,disp-mode = <DUAL>;
 700         };
 701
 702         rk_screen: rk_screen{
 703                         compatible = "rockchip,screen";
 704         };
 705
 706         dsihost0: mipi@ff960000{
 707                 compatible = "rockchip,rk32-dsi";
 708                 rockchip,prop = <0>;
 709                 reg = <0xff960000 0x4000>;
 710                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 711                 clocks = <&clk_gates5 15>, <&clk_gates16 4> , <&pd_mipidsi>;
 712                 clock-names = "clk_mipi_24m", "pclk_mipi_dsi", "pd_mipi_dsi";
 713                 status = "disabled";
 714         };
 715
 716         dsihost1: mipi@ff964000{
 717                 compatible = "rockchip,rk32-dsi";
 718                 rockchip,prop = <1>;
 719                 reg = <0xff964000 0x4000>;
 720                 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 721                 clocks = <&clk_gates5 15>, <&clk_gates16 5>, <&pd_mipidsi>;
 722                 clock-names = "clk_mipi_24m", "pclk_mipi_dsi", "pd_mipi_dsi";
 723                 status = "disabled";
 724         };
 725
 726         lvds: lvds@ff96c000 {
 727                 compatible = "rockchip,rk32-lvds";
 728                 reg = <0xff96c000 0x4000>;
 729                 clocks = <&clk_gates16 7>;
 730                 clock-names = "pclk_lvds";
 731         };
 732
 733         edp: edp@ff970000 {
 734                 compatible = "rockchip,rk32-edp";
 735                 reg = <0xff970000 0x4000>;
 736                 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
 737                 clocks = <&clk_edp>, <&clk_edp_24m>, <&clk_gates16 8>;
 738                 clock-names = "clk_edp", "clk_edp_24m", "pclk_edp";
 739         };
 740
 741         hdmi: hdmi@ff980000 {
 742                 compatible = "rockchip,rk3288-hdmi";
 743                 reg = <0xff980000 0x20000>;
 744                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
 745                 pinctrl-names = "default", "sleep";
 746                 pinctrl-0 = <&i2c5_sda &i2c5_scl>;
 747                 pinctrl-1 = <&i2c5_gpio>;
 748                 clocks = <&clk_gates16 9>, <&clk_gates5 12>;
 749                 clock-names = "pclk_hdmi", "hdcp_clk_hdmi";
 750                 status = "disabled";
 751         };
 752
 753         lcdc0: lcdc@ff930000 {
 754                 compatible = "rockchip,rk3288-lcdc";
 755                 rockchip,prop = <PRMRY>;
 756                 rockchip,pwr18 = <0>;
 757                 rockchip,iommu-enabled = <0>;
 758                 reg = <0xff930000 0x10000>;
 759                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 760                 pinctrl-names = "default", "gpio";
 761                 pinctrl-0 = <&lcdc0_lcdc>;
 762                 pinctrl-1 = <&lcdc0_gpio>;
 763                 status = "disabled";
 764                 clocks = <&clk_gates15 5>, <&dclk_lcdc0>, <&clk_gates15 6>, <&pd_vop0>;
 765                 clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc", "pd_lcdc";
 766         };
 767
 768         lcdc1: lcdc@ff940000 {
 769                 compatible = "rockchip,rk3288-lcdc";
 770                 rockchip,prop = <EXTEND>;
 771                 rockchip,pwr18 = <0>;
 772                 rockchip,iommu-enabled = <0>;
 773                 reg = <0xff940000 0x10000>;
 774                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 775                 status = "disabled";
 776                 clocks = <&clk_gates15 7>, <&dclk_lcdc1>, <&clk_gates15 8>, <&pd_vop1>;
 777                 clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc", "pd_lcdc";
 778         };
 779
 780         adc: adc@ff100000 {
 781                 compatible = "rockchip,saradc";
 782                 reg = <0xff100000 0x100>;
 783                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 784                 #io-channel-cells = <1>;
 785                 io-channel-ranges;
 786                 rockchip,adc-vref = <1800>;
 787                 clock-frequency = <1000000>;
 788                 clocks = <&clk_saradc>, <&clk_gates7 1>;
 789                 clock-names = "saradc", "pclk_saradc";
 790                 status = "disabled";
 791         };
 792
 793         rga@ff920000 {
 794                 compatible = "rockchip,rk3288-rga2";
 795                 reg = <0xff920000 0x1000>;
 796                 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
 797                 clocks = <&clk_gates15 1>, <&aclk_rga>, <&clk_rga>;
 798                 clock-names = "hclk_rga", "aclk_rga", "clk_rga";
 799         };
 800
 801         i2s: rockchip-i2s@0xff890000 {
 802                 compatible = "rockchip-i2s";
 803                 reg = <0xff890000 0x10000>;
 804                 i2s-id = <0>;
 805                 clocks = <&clk_i2s>, <&clk_i2s_out>, <&clk_gates10 8>;
 806                 clock-names = "i2s_clk","i2s_mclk", "i2s_hclk";
 807                 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 808                 dmas = <&pdma0 0>, <&pdma0 1>;
 809                 //#dma-cells = <2>;
 810                 dma-names = "tx", "rx";
 811                 pinctrl-names = "default", "sleep";
 812                 pinctrl-0 = <&i2s_mclk &i2s_sclk &i2s_lrckrx &i2s_lrcktx &i2s_sdi &i2s_sdo0 &i2s_sdo1 &i2s_sdo2 &i2s_sdo3>;
 813                 pinctrl-1 = <&i2s_gpio>;
 814         };
 815
 816         spdif: rockchip-spdif@0xff8b0000 {
 817                 compatible = "rockchip-spdif";
 818                 reg = <0xff8b0000 0x10000>;     //8channel
 819                 //reg = <ff880000 0x10000>;//2channel
 820                 clocks = <&clk_spdif>, <&clk_spdif_8ch>,<&clk_gates10 11>;
 821                 clock-names = "spdif_mclk","spdif_8ch_mclk","spdif_hclk";
 822                 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 823                 dmas = <&pdma0 3>;
 824                 //dmas = <&pdma0 2>; //2channel
 825                 //#dma-cells = <1>;
 826                 dma-names = "tx";
 827                 pinctrl-names = "default";
 828                 pinctrl-0 = <&spdif_tx>;
 829         };
 830
 831         vop1pwm: pwm@ff9401a0 {
 832                 compatible = "rockchip,vop-pwm";
 833                 reg = <0xff9401a0 0x10>;
 834                 #pwm-cells = <2>;
 835                 pinctrl-names = "default";
 836                 pinctrl-0 = <&vop1_pwm_pin>;
 837                 clocks = <&clk_gates13 11>;
 838                 clock-names = "pclk_pwm";
 839                 status = "disabled";
 840         };
 841
 842         vop0pwm: pwm@ff9301a0 {
 843                 compatible = "rockchip,vop-pwm";
 844                 reg = <0xff9301a0 0x10>;
 845                 #pwm-cells = <2>;
 846                 pinctrl-names = "default";
 847                 pinctrl-0 = <&vop0_pwm_pin>;
 848                 clocks = <&clk_gates13 10>;
 849                 clock-names = "pclk_pwm";
 850                 status = "disabled";
 851         };
 852
 853         pwm0: pwm@ff680000 {
 854                 compatible = "rockchip,rk-pwm";
 855                 reg = <0xff680000 0x10>;
 856                 #pwm-cells = <2>;
 857                 pinctrl-names = "default";
 858                 pinctrl-0 = <&pwm0_pin>;
 859                 clocks = <&clk_gates11 11>;
 860                 clock-names = "pclk_pwm";
 861                 status = "disabled";
 862         };
 863
 864         pwm1: pwm@ff680010 {
 865                 compatible = "rockchip,rk-pwm";
 866                 reg = <0xff680010 0x10>;
 867                 #pwm-cells = <2>;
 868                 pinctrl-names = "default";
 869                 pinctrl-0 = <&pwm1_pin>;
 870                 clocks = <&clk_gates11 11>;
 871                 clock-names = "pclk_pwm";
 872                 status = "disabled";
 873         };
 874
 875         pwm2: pwm@ff680020 {
 876                 compatible = "rockchip,rk-pwm";
 877                 reg = <0xff680020 0x10>;
 878                 #pwm-cells = <2>;
 879                 pinctrl-names = "default";
 880                 pinctrl-0 = <&pwm2_pin>;
 881                 clocks = <&clk_gates11 11>;
 882                 clock-names = "pclk_pwm";
 883                 status = "disabled";
 884         };
 885
 886         pwm3: pwm@ff680030 {
 887                 compatible = "rockchip,rk-pwm";
 888                 reg = <0xff680030 0x10>;
 889                 #pwm-cells = <2>;
 890                 pinctrl-names = "default";
 891                 pinctrl-0 = <&pwm3_pin>;
 892                 clocks = <&clk_gates11 11>;
 893                 clock-names = "pclk_pwm";
 894                 status = "disabled";
 895         };
 896
 897         dvfs {
 898
 899                 vd_arm: vd_arm {
 900                         regulator_name = "vdd_arm";
 901                         suspend_volt = <1000>; //mV
 902                         pd_core {
 903                                 clk_core_dvfs_table: clk_core {
 904                                         operating-points = <
 905                                                 /* KHz    uV */
 906                                                 312000 1100000
 907                                                 504000 1100000
 908                                                 816000 1100000
 909                                                 1008000 1100000
 910                                                 >;
 911                                         channel = <0>;
 912                                         temp-limit-enable = <1>;
 913                                         target-temp = <80>;
 914                                         normal-temp-limit = <
 915                                         /*delta-temp    delta-freq*/
 916                                                 3       96000
 917                                                 6       144000
 918                                                 9       192000
 919                                                 15      384000
 920                                                 >;
 921                                         performance-temp-limit = <
 922                                                 /*temp    freq*/
 923                                                 100     816000
 924                                                 >;
 925                                         status = "okay";
 926                                         regu-mode-table = <
 927                                                 /*freq     mode*/
 928                                                 1008000    4
 929                                                 0          3
 930                                         >;
 931                                         regu-mode-en = <0>;
 932                                 };
 933                         };
 934                 };
 935
 936                 vd_logic: vd_logic {
 937                         regulator_name = "vdd_logic";
 938                         suspend_volt = <1000>; //mV
 939                         pd_ddr {
 940                                 clk_ddr_dvfs_table: clk_ddr {
 941                                         operating-points = <
 942                                                 /* KHz    uV */
 943                                                 200000 1200000
 944                                                 300000 1200000
 945                                                 400000 1200000
 946                                                 >;
 947                                         channel = <2>;
 948                                         status = "disabled";
 949                                 };
 950                         };
 951
 952                         pd_vio {
 953                                 aclk_vio1_dvfs_table: aclk_vio1 {
 954                                         operating-points = <
 955                                                 /* KHz    uV */
 956                                                 100000 1100000
 957                                                 500000 1100000
 958                                                 >;
 959                                         status = "okay";
 960                                 };
 961                         };
 962                 };
 963
 964                 vd_gpu: vd_gpu {
 965                         regulator_name = "vdd_gpu";
 966                         suspend_volt = <1000>; //mV
 967                         pd_gpu {
 968                                 clk_gpu_dvfs_table: clk_gpu {
 969                                         operating-points = <
 970                                                 /* KHz    uV */
 971                                                 200000 1200000
 972                                                 300000 1200000
 973                                                 400000 1200000
 974                                                 >;
 975                                         channel = <1>;
 976                                         status = "okay";
 977                                         regu-mode-table = <
 978                                                 /*freq     mode*/
 979                                                 200000     4
 980                                                 0          3
 981                                         >;
 982                                         regu-mode-en = <0>;
 983                                 };
 984                         };
 985                 };
 986         };
 987
 988         ion {
 989                 compatible = "rockchip,ion";
 990                 #address-cells = <1>;
 991                 #size-cells = <0>;
 992
 993                 ion_cma: rockchip,ion-heap@1 { /* CMA HEAP */
 994                         compatible = "rockchip,ion-heap";
 995                         rockchip,ion_heap = <1>;
 996                         reg = <0x00000000 0x20000000>; /* 512MB */
 997                 };
 998                 rockchip,ion-heap@3 { /* VMALLOC HEAP */
 999                         compatible = "rockchip,ion-heap";
1000                         rockchip,ion_heap = <3>;
1001                 };
1002         };
1003
1004         vpu: vpu_service@ff9a0000 {
1005                 compatible = "vpu_service";
1006                 iommu_enabled = <0>;
1007                 reg = <0xff9a0000 0x800>;
1008                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1009                 interrupt-names = "irq_enc", "irq_dec";
1010                 clocks = <&clk_vdpu>, <&hclk_vdpu>;
1011                 clock-names = "aclk_vcodec", "hclk_vcodec";
1012                 name = "vpu_service";
1013                 //status = "disabled";
1014         };
1015
1016         hevc: hevc_service@ff9c0000 {
1017                 compatible = "rockchip,hevc_service";
1018                 iommu_enabled = <0>;
1019                 reg = <0xff9c0000 0x800>;
1020                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
1021                 interrupt-names = "irq_dec";
1022                 clocks = <&aclk_hevc>, <&hclk_hevc>, <&clk_hevc_core>, <&clk_hevc_cabac>;
1023                 clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core", "clk_cabac";
1024                 name = "hevc_service";
1025                 //status = "disabled";
1026         };
1027
1028         iep: iep@ff900000 {
1029                 compatible = "rockchip,iep";
1030                 iommu_enabled = <0>;
1031                 reg = <0xff900000 0x800>;
1032                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1033                 clocks = <&clk_gates15 2>, <&clk_gates15 3>;
1034                 clock-names = "aclk_iep", "hclk_iep";
1035                 status = "okay";
1036         };
1037
1038         dwc_control_usb: dwc-control-usb@ff770284 {
1039                 compatible = "rockchip,rk3288-dwc-control-usb";
1040                 reg = <0xff770284 0x04>, <0xff770288 0x04>,
1041                       <0xff7702cc 0x04>, <0xff7702d4 0x04>,
1042                       <0xff770320 0x14>, <0xff770334 0x14>,
1043                       <0xff770348 0x10>, <0xff770358 0x08>,
1044                       <0xff770360 0x08>;
1045                 reg-names = "GRF_SOC_STATUS1" ,"GRF_SOC_STATUS2",
1046                             "GRF_SOC_STATUS19", "GRF_SOC_STATUS21",
1047                             "GRF_UOC0_BASE", "GRF_UOC1_BASE",
1048                             "GRF_UOC2_BASE", "GRF_UOC3_BASE",
1049                             "GRF_UOC4_BASE";
1050                 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
1051                              <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
1052                              <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
1053                 interrupt-names = "otg_id", "otg_bvalid",
1054                                   "otg_linestate", "host0_linestate",
1055                                   "host1_linestate";
1056                 clocks = <&clk_gates7 9>, <&usbphy_480m>,
1057                          <&otgphy1_480m>, <&otgphy2_480m>;
1058                 clock-names = "hclk_usb_peri", "usbphy_480m",
1059                               "usbphy1_480m", "usbphy2_480m";
1060
1061                 usb_bc {
1062                         compatible = "synopsys,phy";
1063                                         /* offset bit mask */
1064                         rk_usb,bvalid     = <0x288 14 1>;
1065                         rk_usb,iddig      = <0x288 17 1>;
1066                         rk_usb,dcdenb     = <0x328 14 1>;
1067                         rk_usb,vdatsrcenb = <0x328  7 1>;
1068                         rk_usb,vdatdetenb = <0x328  6 1>;
1069                         rk_usb,chrgsel    = <0x328  5 1>;
1070                         rk_usb,chgdet     = <0x2cc 23 1>;
1071                         rk_usb,fsvminus   = <0x2cc 25 1>;
1072                         rk_usb,fsvplus    = <0x2cc 24 1>;
1073                 };
1074         };
1075
1076         usb0: usb@ff580000 {
1077                 compatible = "rockchip,rk3288_usb20_otg";
1078                 reg = <0xff580000 0x40000>;
1079                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
1080                 clocks = <&clk_gates13 4>, <&clk_gates7 4>;
1081                 clock-names = "clk_usbphy0", "hclk_usb0";
1082                 resets = <&reset RK3288_SOFT_RST_USBOTG_H>, <&reset RK3288_SOFT_RST_USBOTGPHY>,
1083                                 <&reset RK3288_SOFT_RST_USBOTGC>;
1084                 reset-names = "otg_ahb", "otg_phy", "otg_controller";
1085                 /*0 - Normal, 1 - Force Host, 2 - Force Device*/
1086                 rockchip,usb-mode = <0>;
1087         };
1088
1089         usb1: usb@ff540000 {
1090                 compatible = "rockchip,rk3288_usb20_host";
1091                 reg = <0xff540000 0x40000>;
1092                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
1093                 clocks = <&clk_gates13 6>, <&clk_gates7 7>,
1094                          <&usbphy_480m>;
1095                 clock-names = "clk_usbphy1", "hclk_usb1",
1096                               "usbphy_480m";
1097                 resets = <&reset RK3288_SOFT_RST_USBHOST1_H>, <&reset RK3288_SOFT_RST_USBHOST1PHY>,
1098                                 <&reset RK3288_SOFT_RST_USBHOST1C>;
1099                 reset-names = "host1_ahb", "host1_phy", "host1_controller";
1100         };
1101
1102         usb2: usb@ff500000 {
1103                 compatible = "rockchip,rk3288_rk_ehci_host";
1104                 reg = <0xff500000 0x20000>;
1105                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
1106                 clocks = <&clk_gates13 5>, <&clk_gates7 6>;
1107                 clock-names = "clk_usbphy2", "hclk_usb2";
1108                 resets = <&reset RK3288_SOFT_RST_USBHOST0_H>, <&reset RK3288_SOFT_RST_USBHOST0PHY>,
1109                                 <&reset RK3288_SOFT_RST_USBHOST0C>, <&reset RK3288_SOFT_RST_USB_HOST0>;
1110                 reset-names = "ehci_ahb", "ehci_phy", "ehci_controller", "ehci";
1111         };
1112
1113         usb3: usb@ff520000 {
1114                 compatible = "rockchip,rk3288_rk_ohci_host";
1115                 reg = <0xff520000 0x20000>;
1116                 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
1117                 clocks = <&clk_gates13 5>, <&clk_gates7 6>;
1118                 clock-names = "clk_usbphy3", "hclk_usb3";
1119         };
1120
1121         hsic: hsic@ff5c0000 {
1122                 compatible = "rockchip,rk3288_rk_hsic_host";
1123                 reg = <0xff5c0000 0x40000>;
1124                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
1125                 clocks = <&hsicphy_480m>, <&clk_gates7 8>,
1126                          <&hsicphy_12m>, <&usbphy_480m>,
1127                          <&otgphy1_480m>, <&otgphy2_480m>;
1128                 clock-names = "hsicphy_480m", "hclk_hsic",
1129                               "hsicphy_12m", "usbphy_480m",
1130                               "hsic_usbphy1", "hsic_usbphy2";
1131                 resets = <&reset RK3288_SOFT_RST_HSIC>, <&reset RK3288_SOFT_RST_HSIC_AUX>,
1132                                 <&reset RK3288_SOFT_RST_HSICPHY>;
1133                 reset-names = "hsic_ahb", "hsic_aux", "hsic_phy";
1134         };
1135
1136         gmac: eth@ff290000 {
1137                 compatible = "rockchip,rk3288-gmac";
1138                 reg = <0xff290000 0x10000>;
1139                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;  /*irq=59*/
1140                 interrupt-names = "macirq";
1141                 clocks = <&clk_mac>, <&clk_gates5 0>,
1142                          <&clk_gates5 1>, <&clk_gates5 2>,
1143                          <&clk_gates5 3>, <&clk_gates8 0>,
1144                          <&clk_gates8 1>;
1145                 clock-names = "clk_mac", "mac_clk_rx",
1146                               "mac_clk_tx", "clk_mac_ref",
1147                               "clk_mac_refout", "aclk_mac",
1148                               "pclk_mac";
1149                 phy-mode = "rgmii";
1150                 pinctrl-names = "default";
1151                 pinctrl-0 = <&mac_clk &mac_txpins &mac_rxpins &mac_mdpins>;
1152         };
1153
1154         gpu {
1155                 compatible = "arm,malit764",
1156                              "arm,malit76x",
1157                              "arm,malit7xx",
1158                              "arm,mali-midgard";
1159                 reg = <0xffa30000 0x10000>;
1160                 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
1161                              <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
1162                              <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1163                 interrupt-names = "JOB", "MMU", "GPU";
1164         };
1165
1166         iep_mmu {
1167                 dbgname = "iep";
1168                 compatible = "rockchip,iep_mmu";
1169                 reg = <0xff900800 0x100>;
1170                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1171                 interrupt-names = "iep_mmu";
1172         };
1173
1174         vip_mmu {
1175                 dbgname = "vip";
1176                 compatible = "rockchip,vip_mmu";
1177                 reg = <0xff950800 0x100>;
1178                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
1179                 interrupt-names = "vip_mmu";
1180         };
1181
1182         vopb_mmu {
1183                 dbgname = "vopb";
1184                 compatible = "rockchip,vopb_mmu";
1185                 reg = <0xff930300 0x100>;
1186                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1187                 interrupt-names = "vopb_mmu";
1188         };
1189
1190         vopl_mmu {
1191                 dbgname = "vopl";
1192                 compatible = "rockchip,vopl_mmu";
1193                 reg = <0xff940300 0x100>;
1194                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1195                 interrupt-names = "vopl_mmu";
1196         };
1197
1198         hevc_mmu {
1199                 dbgname = "hevc";
1200                 compatible = "rockchip,hevc_mmu";
1201                 reg = <0xff9c0440 0x40>,
1202                       <0xff9c0480 0x40>;
1203                 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
1204                 interrupt-names = "hevc_mmu";
1205         };
1206
1207         vpu_mmu {
1208                 dbgname = "vpu";
1209                 compatible = "rockchip,vpu_mmu";
1210                 reg = <0xff9a0800 0x100>;
1211                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
1212                 interrupt-names = "vpu_mmu";
1213         };
1214
1215         isp_mmu {
1216                 dbgname = "isp_mmu";
1217                 compatible = "rockchip,isp_mmu";
1218                 reg = <0xff914000 0x100>,
1219                       <0xff915000 0x100>;
1220                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1221                 interrupt-names = "isp_mmu";
1222         };
1223
1224         rockchip_suspend {
1225                 rockchip,ctrbits = <
1226                         (0
1227                          |RKPM_CTR_PWR_DMNS
1228                          |RKPM_CTR_GTCLKS
1229                          |RKPM_CTR_PLLS
1230                  //      |RKPM_CTR_GPIOS
1231                 //       |RKPM_CTR_SYSCLK_DIV
1232                 //       |RKPM_CTR_IDLEAUTO_MD
1233                 //       |RKPM_CTR_ARMOFF_LPMD
1234                          |RKPM_CTR_ARMOFF_LOGDP_LPMD
1235                         )
1236                         >;
1237                 rockchip,pmic-suspend_gpios = <
1238                         RKPM_PINGPIO_BITS_OUTPUT(GPIO7_A1,RKPM_GPIO_OUT_H)
1239                         >;
1240                 rockchip,pmic-resume_gpios = <
1241                         RKPM_PINGPIO_BITS_FUN(PWM1,RKPM_GPIO_PULL_DN)
1242                         >;
1243
1244         };
1245
1246         isp: isp@ff910000{
1247                 compatible = "rockchip,isp";
1248                 reg = <0xff910000 0x10000>;
1249                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1250                 clocks = <&clk_gates16 2>, <&clk_gates16 1>, <&clk_isp>, <&clk_isp_jpe>, <&clkin_isp>, <&clk_cif_out>, <&clk_gates5 15>, <&clk_cif_pll>, <&pd_isp>, <&clk_gates16 6>;
1251                 clock-names = "aclk_isp", "hclk_isp", "clk_isp", "clk_isp_jpe", "pclkin_isp", "clk_cif_out", "clk_mipi_24m", "clk_cif_pll", "pd_isp", "hclk_mipiphy1";
1252                 pinctrl-names = "default", "isp_dvp8bit2", "isp_dvp10bit", "isp_dvp12bit", "isp_dvp8bit0", "isp_mipi_fl", "isp_mipi_fl_prefl","isp_flash_as_gpio","isp_flash_as_trigger_out";
1253                 pinctrl-0 = <&isp_mipi>;
1254                 pinctrl-1 = <&isp_mipi &isp_dvp_d2d9>;
1255                 pinctrl-2 = <&isp_mipi &isp_dvp_d2d9 &isp_dvp_d0d1>;
1256                 pinctrl-3 = <&isp_mipi &isp_dvp_d2d9 &isp_dvp_d0d1 &isp_dvp_d10d11>;
1257                 pinctrl-4 = <&isp_mipi &isp_dvp_d0d7>;
1258                 pinctrl-5 = <&isp_mipi>;
1259                 pinctrl-6 = <&isp_mipi &isp_prelight>;
1260                 pinctrl-7 = <&isp_flash_trigger_as_gpio>;
1261                 pinctrl-8 = <&isp_flash_trigger>;
1262                 rockchip,isp,mipiphy = <2>;
1263                 rockchip,isp,cifphy = <1>;
1264                 rockchip,isp,mipiphy1,reg = <0xff968000 0x4000>;
1265                 rockchip,gpios = <&gpio7 GPIO_B5 GPIO_ACTIVE_HIGH>;
1266                 rockchip,isp,iommu_enable = <1>;
1267                 status = "okay";
1268         };
1269
1270         tsadc: tsadc@ff280000 {
1271                 compatible = "rockchip,tsadc";
1272                 reg = <0xff280000 0x100>;
1273                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
1274                 #io-channel-cells = <1>;
1275                 io-channel-ranges;
1276                 clock-frequency = <10000>;
1277                 clocks = <&clk_tsadc>, <&clk_gates7 2>;
1278                 clock-names = "tsadc", "pclk_tsadc";
1279                 pinctrl-names = "default", "tsadc_int";
1280                 pinctrl-0 = <&tsadc_gpio>;
1281                 pinctrl-1 = <&tsadc_int>;
1282                 tsadc-ht-temp = <120>;
1283                 tsadc-ht-reset-cru = <1>;
1284                 tsadc-ht-pull-gpio = <0>;
1285                 status = "okay";
1286         };
1287
1288         lcdc_vdd_domain: lcdc-vdd-domain {
1289                 compatible = "rockchip,io_vol_domain";
1290                 pinctrl-names = "default", "1.8V", "3.3V";
1291                 pinctrl-0 = <&lcdc_vcc>;
1292                 pinctrl-1 = <&lcdc_vcc_18>;
1293                 pinctrl-2 = <&lcdc_vcc_33>;
1294         };
1295
1296         dpio_vdd_domain: dpio-vdd-domain {
1297                 compatible = "rockchip,io_vol_domain";
1298                 pinctrl-names = "default", "1.8V", "3.3V";
1299                 pinctrl-0 = <&dvp_vcc>;
1300                 pinctrl-1 = <&dvp_vcc_18>;
1301                 pinctrl-2 = <&dvp_vcc_33>;
1302         };
1303
1304         flash0_vdd_domain: flash0-vdd-domain {
1305                 compatible = "rockchip,io_vol_domain";
1306                 pinctrl-names = "default", "1.8V", "3.3V";
1307                 pinctrl-0 = <&flash0_vcc>;
1308                 pinctrl-1 = <&flash0_vcc_18>;
1309                 pinctrl-2 = <&flash0_vcc_33>;
1310         };
1311
1312         flash1_vdd_domain: flash1-vdd-domain {
1313                 compatible = "rockchip,io_vol_domain";
1314                 pinctrl-names = "default", "1.8V", "3.3V";
1315                 pinctrl-0 = <&flash1_vcc>;
1316                 pinctrl-1 = <&flash1_vcc_18>;
1317                 pinctrl-2 = <&flash1_vcc_33>;
1318         };
1319
1320         apio3_vdd_domain: apio3-vdd-domain {
1321                 compatible = "rockchip,io_vol_domain";
1322                 pinctrl-names = "default", "1.8V", "3.3V";
1323                 pinctrl-0 = <&wifi_vcc>;
1324                 pinctrl-1 = <&wifi_vcc_18>;
1325                 pinctrl-2 = <&wifi_vcc_33>;
1326         };
1327
1328         apio5_vdd_domain: apio5-vdd-domain {
1329                 compatible = "rockchip,io_vol_domain";
1330                 pinctrl-names = "default", "1.8V", "3.3V";
1331                 pinctrl-0 = <&bb_vcc>;
1332                 pinctrl-1 = <&bb_vcc_18>;
1333                 pinctrl-2 = <&bb_vcc_33>;
1334         };
1335
1336         apio4_vdd_domain: apio4-vdd-domain {
1337                 compatible = "rockchip,io_vol_domain";
1338                 pinctrl-names = "default", "1.8V", "3.3V";
1339                 pinctrl-0 = <&audio_vcc>;
1340                 pinctrl-1 = <&audio_vcc_18>;
1341                 pinctrl-2 = <&audio_vcc_33>;
1342         };
1343
1344         apio1_vdd_domain: apio0-vdd-domain {
1345                 compatible = "rockchip,io_vol_domain";
1346                 pinctrl-names = "default", "1.8V", "3.3V";
1347                 pinctrl-0 = <&gpio30_vcc>;
1348                 pinctrl-1 = <&gpio30_vcc_18>;
1349                 pinctrl-2 = <&gpio30_vcc_33>;
1350         };
1351
1352         apio2_vdd_domain: apio2-vdd-domain {
1353                 compatible = "rockchip,io_vol_domain";
1354                 pinctrl-names = "default", "1.8V", "3.3V";
1355                 pinctrl-0 = <&gpio1830_vcc>;
1356                 pinctrl-1 = <&gpio1830_vcc_18>;
1357                 pinctrl-2 = <&gpio1830_vcc_33>;
1358         };
1359
1360         sdmmc0_vdd_domain: sdmmc0-vdd-domain {
1361                 compatible = "rockchip,io_vol_domain";
1362                 pinctrl-names = "default", "1.8V", "3.3V";
1363                 pinctrl-0 = <&sdcard_vcc>;
1364                 pinctrl-1 = <&sdcard_vcc_18>;
1365                 pinctrl-2 = <&sdcard_vcc_33>;
1366         };
1367
1368         chosen {
1369                 bootargs = "vmalloc=496M";
1370         };
1371 };