arch/arm/boot/dts/rk3288.dtsi

   1 #include <dt-bindings/clock/ddr.h>
   2 #include <dt-bindings/interrupt-controller/arm-gic.h>
   3 #include <dt-bindings/rkfb/rk_fb.h>
   4 #include <dt-bindings/rkmipi/mipi_dsi.h>
   5 #include <dt-bindings/suspend/rockchip-pm.h>
   6 #include <dt-bindings/sensor-dev.h>
   7
   8 #include "skeleton.dtsi"
   9 #include "rk3288-pinctrl.dtsi"
  10 #include "rk3288-clocks.dtsi"
  11
  12 / {
  13         compatible = "rockchip,rk3288";
  14         rockchip,sram = <&sram>;
  15         interrupt-parent = <&gic>;
  16
  17         aliases {
  18                 serial0 = &uart_bt;
  19                 serial1 = &uart_bb;
  20                 serial2 = &uart_dbg;
  21                 serial3 = &uart_gps;
  22                 serial4 = &uart_exp;
  23                 i2c0 = &i2c0;
  24                 i2c1 = &i2c1;
  25                 i2c2 = &i2c2;
  26                 i2c3 = &i2c3;
  27                 i2c4 = &i2c4;
  28                 i2c5 = &i2c5;
  29                 lcdc0 = &lcdc0;
  30                 lcdc1 = &lcdc1;
  31                 spi0 = &spi0;
  32                 spi1 = &spi1;
  33                 spi2 = &spi2;
  34
  35         };
  36
  37         cpus {
  38                 #address-cells = <1>;
  39                 #size-cells = <0>;
  40
  41                 cpu@0 {
  42                         device_type = "cpu";
  43                         compatible = "arm,cortex-a15";
  44                         reg = <0x500>;
  45                 };
  46                 cpu@1 {
  47                         device_type = "cpu";
  48                         compatible = "arm,cortex-a15";
  49                         reg = <0x501>;
  50                 };
  51                 cpu@2 {
  52                         device_type = "cpu";
  53                         compatible = "arm,cortex-a15";
  54                         reg = <0x502>;
  55                 };
  56                 cpu@3 {
  57                         device_type = "cpu";
  58                         compatible = "arm,cortex-a15";
  59                         reg = <0x503>;
  60                 };
  61         };
  62
  63         gic: interrupt-controller@ffc01000 {
  64                 compatible = "arm,cortex-a15-gic";
  65                 interrupt-controller;
  66                 #interrupt-cells = <3>;
  67                 #address-cells = <0>;
  68                 reg = <0xffc01000 0x1000>,
  69                       <0xffc02000 0x1000>;
  70         };
  71
  72         cpu_axi_bus: cpu_axi_bus {
  73                 compatible = "rockchip,cpu_axi_bus";
  74                 #address-cells = <1>;
  75                 #size-cells = <1>;
  76                 ranges;
  77                 qos {
  78                         #address-cells = <1>;
  79                         #size-cells = <1>;
  80                         ranges;
  81                         /* service core */
  82                         cpup {
  83                                 reg = <0xffa80000 0x20>;
  84                         };
  85                         cpum_r {
  86                                 reg = <0xffa80080 0x20>;
  87                         };
  88                         cpum_w {
  89                                 reg = <0xffa80100 0x20>;
  90                         };
  91                         /* service dmac */
  92                         bus_dmac {
  93                                 reg = <0xffa90000 0x20>;
  94                         };
  95                         host {
  96                                 reg = <0xffa90080 0x20>;
  97                         };
  98                         crypto {
  99                                 reg = <0xffa90100 0x20>;
 100                         };
 101                         ccp {
 102                                 reg = <0xffa90180 0x20>;
 103                         };
 104                         ccs {
 105                                 reg = <0xffa90200 0x20>;
 106                         };
 107                         /* service gpu */
 108                         gpu_r {
 109                                 reg = <0xffaa0000 0x20>;
 110                         };
 111                         gpu_w {
 112                                 reg = <0xffaa0080 0x20>;
 113                         };
 114                         /* service peri */
 115                         peri {
 116                                 reg = <0xffab0000 0x20>;
 117                         };
 118                         /* service vio */
 119                         vio1_vop {
 120                                 reg = <0xffad0000 0x20>;
 121                                 rockchip,priority = <2 2>;
 122                         };
 123                         vio1_isp_w0 {
 124                                 reg = <0xffad0100 0x20>;
 125                         };
 126                         vio1_isp_w1 {
 127                                 reg = <0xffad0180 0x20>;
 128                         };
 129                         vio0_vop {
 130                                 reg = <0xffad0400 0x20>;
 131                                 rockchip,priority = <2 2>;
 132                         };
 133                         vio0_vip {
 134                                 reg = <0xffad0480 0x20>;
 135                         };
 136                         vio0_iep {
 137                                 reg = <0xffad0500 0x20>;
 138                         };
 139                         vio2_rga_r {
 140                                 reg = <0xffad0800 0x20>;
 141                         };
 142                         vio2_rga_w {
 143                                 reg = <0xffad0880 0x20>;
 144                         };
 145                         vio1_isp_r {
 146                                 reg = <0xffad0900 0x20>;
 147                         };
 148                         /* service video */
 149                         video {
 150                                 reg = <0xffae0000 0x20>;
 151                         };
 152                         /* service hevc */
 153                         hevc_r {
 154                                 reg = <0xffaf0000 0x20>;
 155                         };
 156                         hevc_w {
 157                                 reg = <0xffaf0080 0x20>;
 158                         };
 159                 };
 160                 msch {
 161                         #address-cells = <1>;
 162                         #size-cells = <1>;
 163                         ranges;
 164                         msch@0 {
 165                                 reg = <0xffac0000 0x40>;
 166                                 rockchip,read-latency = <0xff>;
 167                         };
 168                         msch@1 {
 169                                 reg = <0xffac0080 0x40>;
 170                                 rockchip,read-latency = <0xff>;
 171                         };
 172                 };
 173         };
 174
 175         sram: sram@ff710000 {
 176                 compatible = "mmio-sram";
 177                 reg = <0xff710000 0x8000>; /* 32k */
 178                 map-exec;
 179         };
 180
 181         timer {
 182                 compatible = "arm,armv7-timer";
 183                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 184                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 185                 clock-frequency = <24000000>;
 186         };
 187
 188         timer@ff810000 {
 189                 compatible = "rockchip,timer";
 190                 reg = <0xff810000 0x20>;
 191                 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
 192                 rockchip,broadcast = <1>;
 193         };
 194
 195         watchdog:wdt@2004c000 {
 196                 compatible = "rockchip,watch dog";
 197                 reg = <0xff800000 0x100>;
 198                 clocks = <&pclk_pd_alive>;
 199                 clock-names = "pclk_wdt";
 200                 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
 201                 rockchip,irq = <0>;
 202                 rockchip,timeout = <60>;
 203                 rockchip,atboot = <1>;
 204                 rockchip,debug = <0>;
 205                 status = "disable";
 206         };
 207
 208     amba {
 209                 #address-cells = <1>;
 210                 #size-cells = <1>;
 211                 compatible = "arm,amba-bus";
 212                 interrupt-parent = <&gic>;
 213                 ranges;
 214
 215                 pdma0: pdma@ffb20000 {
 216                         compatible = "arm,pl330", "arm,primecell";
 217                         reg = <0xffb20000 0x4000>;
 218                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 219                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 220                         #dma-cells = <1>;
 221                 };
 222
 223                 pdma1: pdma@ff250000 {
 224                         compatible = "arm,pl330", "arm,primecell";
 225                         reg = <0xff250000 0x4000>;
 226                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
 227                                      <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 228                         #dma-cells = <1>;
 229                 };
 230         };
 231
 232
 233         nandc0: nandc@0xff400000 {
 234                 compatible = "rockchip,rk-nandc";
 235                 reg = <0xff400000 0x4000>;
 236                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;/*irq=70*/
 237                 nandc_id = <0>;
 238                 clocks = <&clk_nandc0>, <&clk_gates5 5>, <&clk_gates7 14>;
 239                 clock-names = "clk_nandc", "g_clk_nandc","hclk_nandc";
 240                 status = "okay";
 241         };
 242
 243         nandc1: nandc@0xff410000 {
 244             compatible = "rockchip,rk-nandc";
 245                 reg = <0xff410000 0x4000>;
 246                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; /*irq=72*/
 247                 nandc_id = <1>;
 248                 clocks = <&clk_nandc1>, <&clk_gates5 6>, <&clk_gates7 15>;
 249                 clock-names = "clk_nandc","g_clk_nandc","hclk_nandc";
 250                 status = "okay";
 251         };
 252
 253         emmc: rksdmmc@ff0f0000 {
 254                 compatible = "rockchip,rk_mmc";
 255                 reg = <0xff0f0000 0x4000>;
 256                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;/*irq=67*/
 257                 #address-cells = <1>;
 258                 #size-cells = <0>;
 259                 //pinctrl-names = "default",,"suspend";
 260                 //pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_wp &sd0_pwr &sd0_bus1 &sd0_bus4>;
 261
 262                 clocks = <&clk_emmc>, <&clk_gates8 6>;
 263                 clock-names = "clk_mmc", "hclk_mmc";
 264                 num-slots = <1>;
 265                 fifo-depth = <0x100>;
 266                 bus-width = <8>;
 267         };
 268
 269         sdmmc: rksdmmc@ff0c0000 {
 270           compatible = "rockchip,rk_mmc";
 271                 reg = <0xff0c0000 0x4000>;
 272                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; /*irq=64*/
 273           #address-cells = <1>;
 274           #size-cells = <0>;
 275
 276                 pinctrl-names = "default","idle";
 277           pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_dectn &sdmmc0_bus4>;
 278           pinctrl-1 = <&sdmmc0_gpio>;
 279
 280                 clocks = <&clk_sdmmc>, <&clk_gates8 3>;
 281                 clock-names = "clk_mmc", "hclk_mmc";
 282         num-slots = <1>;
 283           fifo-depth = <0x100>;
 284           bus-width = <4>;
 285
 286         };
 287
 288         sdio: rksdmmc@ff0d0000 {
 289                 compatible = "rockchip,rk_mmc";
 290           reg = <0xff0d0000 0x4000>;
 291           interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 292           #address-cells = <1>;
 293           #size-cells = <0>;
 294           pinctrl-names = "default","idle";
 295           pinctrl-0 = <&sdio0_clk &sdio0_cmd &sdio0_dectn  &sdio0_wrprt &sdio0_pwr &sdio0_bkpwr
 296                                          &sdio0_intn &sdio0_bus4>;
 297           pinctrl-1 = <&sdio0_gpio>;
 298
 299                 clocks = <&clk_sdio0>, <&clk_gates8 4>;
 300                 clock-names = "clk_mmc", "hclk_mmc";
 301     num-slots = <1>;
 302
 303           fifo-depth = <0x100>;
 304           bus-width = <4>;
 305         };
 306
 307         sdio1: rksdmmc@ff0e0000 {
 308                 compatible = "rockchip,rk_mmc";
 309                 reg = <0xff0e0000 0x4000>;
 310                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 311                 #address-cells = <1>;
 312                 #size-cells = <0>;
 313                 //pinctrl-names = "default","suspend";
 314                 //pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_cd &sd1_wp &sd1_bus1 &sd1_bus4>;
 315
 316                 /*gate8_0 --hclk_sdmmc_ahb_arbi_gate_en, gate13_2 --clk_sdio1_src_gate_en*/
 317                 clocks = <&clk_sdio1>, <&clk_gates8 5>;
 318                 clock-names = "clk_mmc", "hclk_mmc";
 319                 num-slots = <1>;
 320
 321                 fifo-depth = <0x100>;
 322                 bus-width = <4>;
 323                 status = "disabled";
 324         };
 325
 326         spi0: spi@ff110000 {
 327                 compatible = "rockchip,rockchip-spi";
 328                 reg = <0xff110000 0x1000>;
 329                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 330                 #address-cells = <1>;
 331                 #size-cells = <0>;
 332                 pinctrl-names = "default";
 333                 pinctrl-0 = <&spi0_txd &spi0_rxd &spi0_clk &spi0_cs0 &spi0_cs1>;
 334                 rockchip,spi-src-clk = <0>;
 335                 num-cs = <2>;
 336                 clocks =<&clk_spi0>, <&clk_gates6 4>;
 337                 clock-names = "spi","pclk_spi0";
 338                 //dmas = <&pdma1 11>, <&pdma1 12>;
 339                 //#dma-cells = <2>;
 340                 //dma-names = "tx", "rx";
 341                 status = "disabled";
 342         };
 343
 344         spi1: spi@ff120000 {
 345                 compatible = "rockchip,rockchip-spi";
 346                 reg = <0xff120000 0x1000>;
 347                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 348                 #address-cells = <1>;
 349                 #size-cells = <0>;
 350                 pinctrl-names = "default";
 351                 pinctrl-0 = <&spi1_txd &spi1_rxd &spi1_clk &spi1_cs0>;
 352                 rockchip,spi-src-clk = <1>;
 353                 num-cs = <1>;
 354                 clocks = <&clk_spi1>, <&clk_gates6 5>;
 355                 clock-names = "spi","pclk_spi1";
 356                 //dmas = <&pdma1 13>, <&pdma1 14>;
 357                 //#dma-cells = <2>;
 358                 //dma-names = "tx", "rx";
 359                 status = "disabled";
 360         };
 361
 362         spi2: spi@ff130000 {
 363                 compatible = "rockchip,rockchip-spi";
 364                 reg = <0xff130000 0x1000>;
 365                 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 366                 #address-cells = <1>;
 367                 #size-cells = <0>;
 368                 pinctrl-names = "default";
 369                 pinctrl-0 = <&spi2_txd &spi2_rxd &spi2_clk &spi2_cs0 &spi2_cs1>;
 370                 rockchip,spi-src-clk = <2>;
 371                 num-cs = <2>;
 372                 clocks = <&clk_spi2>, <&clk_gates6 6>;
 373                 clock-names = "spi","pclk_spi2";
 374                 //dmas = <&pdma1 15>, <&pdma1 16>;
 375                 //#dma-cells = <2>;
 376                 //dma-names = "tx", "rx";
 377                 status = "disabled";
 378         };
 379
 380         uart_bt: serial@ff180000 {
 381                 compatible = "rockchip,serial";
 382                 reg = <0xff180000 0x100>;
 383                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 384                 clock-frequency = <24000000>;
 385                 clocks = <&clk_uart0>, <&clk_gates6 8>;
 386                 clock-names = "sclk_uart", "pclk_uart";
 387                 reg-shift = <2>;
 388                 reg-io-width = <4>;
 389                 dmas = <&pdma1 1>, <&pdma1 2>;
 390                 #dma-cells = <2>;
 391                 pinctrl-names = "default";
 392                 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
 393                 status = "disabled";
 394         };
 395
 396         uart_bb: serial@ff190000 {
 397                 compatible = "rockchip,serial";
 398                 reg = <0xff190000 0x100>;
 399                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 400                 clock-frequency = <24000000>;
 401                 clocks = <&clk_uart1>, <&clk_gates6 9>;
 402                 clock-names = "sclk_uart", "pclk_uart";
 403                 reg-shift = <2>;
 404                 reg-io-width = <4>;
 405                 dmas = <&pdma1 3>, <&pdma1 4>;
 406                 #dma-cells = <2>;
 407                 pinctrl-names = "default";
 408                 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
 409                 status = "disabled";
 410         };
 411
 412         uart_dbg: serial@ff690000 {
 413                 compatible = "rockchip,serial";
 414                 reg = <0xff690000 0x100>;
 415                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 416                 clock-frequency = <24000000>;
 417                 clocks = <&clk_uart2>, <&clk_gates11 9>;
 418                 clock-names = "sclk_uart", "pclk_uart";
 419                 reg-shift = <2>;
 420                 reg-io-width = <4>;
 421                 dmas = <&pdma0 4>, <&pdma0 5>;
 422                 #dma-cells = <2>;
 423                 pinctrl-names = "default";
 424                 pinctrl-0 = <&uart2_xfer>;
 425                 status = "disabled";
 426         };
 427
 428         uart_gps: serial@ff1b0000 {
 429                 compatible = "rockchip,serial";
 430                 reg = <0xff1b0000 0x100>;
 431                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 432                 clock-frequency = <24000000>;
 433                 clocks = <&clk_uart3>, <&clk_gates6 11>;
 434                 clock-names = "sclk_uart", "pclk_uart";
 435                 current-speed = <115200>;
 436                 reg-shift = <2>;
 437                 reg-io-width = <4>;
 438                 dmas = <&pdma1 7>, <&pdma1 8>;
 439                 #dma-cells = <2>;
 440                 pinctrl-names = "default";
 441                 pinctrl-0 = <&uart3_xfer &uart3_cts &uart3_rts>;
 442                 status = "disabled";
 443         };
 444
 445         uart_exp: serial@ff1c0000 {
 446                 compatible = "rockchip,serial";
 447                 reg = <0xff1c0000 0x100>;
 448                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 449                 clock-frequency = <24000000>;
 450                 clocks = <&clk_uart4>, <&clk_gates6 12>;
 451                 clock-names = "sclk_uart", "pclk_uart";
 452                 reg-shift = <2>;
 453                 reg-io-width = <4>;
 454                 dmas = <&pdma1 9>, <&pdma1 10>;
 455                 #dma-cells = <2>;
 456                 pinctrl-names = "default";
 457                 pinctrl-0 = <&uart4_xfer &uart4_cts &uart4_rts>;
 458                 status = "disabled";
 459         };
 460
 461         fiq-debugger {
 462                 compatible = "rockchip,fiq-debugger";
 463                 rockchip,serial-id = <2>;
 464                 rockchip,signal-irq = <106>;
 465                 rockchip,wake-irq = <0>;
 466                 status = "disabled";
 467         };
 468
 469         clocks-init{
 470                 compatible = "rockchip,clocks-init";
 471                 rockchip,clocks-init-parent =
 472                         <&clk_core &clk_apll>,  <&aclk_bus_src &clk_gpll>,
 473                         <&aclk_peri &clk_gpll>, <&uart_pll_mux &clk_gpll>,
 474                         <&clk_i2s_pll &clk_cpll>;
 475                 rockchip,clocks-init-rate =
 476                         <&clk_core 792000000>,  <&clk_gpll 594000000>,
 477                         <&clk_cpll 384000000>,  <&clk_npll 500000000>,
 478                         <&aclk_bus_src 300000000>,      <&aclk_bus 300000000>,
 479                         <&hclk_bus 150000000>,  <&pclk_bus 75000000>,
 480                         <&clk_crypto 150000000>,        <&aclk_peri 300000000>,
 481                         <&hclk_peri 150000000>, <&pclk_peri 75000000>,
 482                         <&clk_gpu 200000000>,   <&aclk_vio0 300000000>,
 483                         <&aclk_vio1 300000000>, <&hclk_vio 75000000>,
 484                         <&pclk_pd_alive 100000000>,     <&pclk_pd_pmu 100000000>,
 485                         <&aclk_hevc 400000000>, <&hclk_hevc 200000000>,
 486                         <&clk_hevc_cabac 300000000>, <&clk_hevc_core 300000000>,
 487                         <&aclk_rga 300000000>, <&clk_rga 300000000>,
 488                         <&clk_vepu 300000000>, <&clk_vdpu 300000000>,
 489                         <&clk_edp 200000000>, <&clk_isp 200000000>,
 490                         <&clk_isp_jpe 400000000>, <&clk_tsp 80000000>,
 491                         <&clk_tspout 80000000>, <&clk_mac 125000000>;
 492         };
 493
 494         clocks-enable {
 495                 compatible = "rockchip,clocks-enable";
 496                 clocks =
 497                                 /*PD_CORE*/
 498                                 <&clk_gates0 2>, <&clk_core0>,
 499                                 <&clk_core1>, <&clk_core2>,
 500                                 <&clk_core3>, <&clk_l2ram>,
 501                                 <&aclk_core_m0>, <&aclk_core_mp>,
 502                                 <&atclk_core>, <&pclk_dbg_src>,
 503
 504                                 /*PD_BUS*/
 505                                 <&aclk_bus>, <&clk_gates0 3>,
 506                                 <&hclk_bus>, <&pclk_bus>,
 507                                 <&clk_gates13 8>, <&clk_crypto>,
 508                                 <&clk_gates0 7>,
 509
 510                                 /*TIMER*/
 511                                 <&clk_gates1 0>, <&clk_gates1 1>,
 512                                 <&clk_gates1 2>, <&clk_gates1 3>,
 513                                 <&clk_gates1 4>, <&clk_gates1 5>,
 514
 515                                 <&pclk_pd_alive>, <&pclk_pd_pmu>,
 516
 517                                 /*PD_PERI*/
 518                                 <&aclk_peri>, <&hclk_peri>,
 519                                 <&pclk_peri>,
 520
 521                                 /*JTAG*/
 522                                 /*<&clk_gates4 14>,*/
 523
 524                                 /*aclk_bus*/
 525                                 <&clk_gates10 5>,/*aclk_intmem0*/
 526                                 <&clk_gates10 6>,/*aclk_intmem1*/
 527                                 <&clk_gates10 7>,/*aclk_intmem2*/
 528                                 <&clk_gates10 12>,/*aclk_dma1*/
 529                                 <&clk_gates10 13>,/*aclk_strc_sys*/
 530                                 <&clk_gates10 4>,/*aclk_intmem*/
 531                                 <&clk_gates11 6>,/*aclk_crypto*/
 532                                 <&clk_gates11 8>,/*aclk_ccp*/
 533
 534                                 /*hclk_bus*/
 535                                 <&clk_gates11 7>,/*hclk_crypto*/
 536                                 <&clk_gates10 9>,/*hclk_rom*/
 537
 538                                 /*pclk_bus*/
 539                                 <&clk_gates10 1>,/*pclk_timer*/
 540                                 <&clk_gates10 9>,/*rom*/
 541                                 <&clk_gates10 13>,/*aclk strc*/
 542
 543                                 <&clk_gates12 8>,/*aclk strc*/
 544
 545                                 /*aclk_peri*/
 546                                 <&clk_gates6 2>,/*aclk_peri_axi_matrix*/
 547                                 <&clk_gates6 3>,/*aclk_dmac2*/
 548                                 <&clk_gates7 11>,/*aclk_peri_niu*/
 549                                 <&clk_gates8 12>,/*aclk_peri_mmu*/
 550
 551                                 /*hclk_peri*/
 552                                 <&clk_gates6 0>,/*hclk_peri_matrix*/
 553                                 <&clk_gates7 10>,/*hclk_peri_ahb_arbi*/
 554                                 <&clk_gates7 12>,/*hclk_emem_peri*/
 555                                 <&clk_gates7 13>,/*hclk_mem_peri*/
 556
 557                                 /*pclk_peri*/
 558                                 <&clk_gates6 1>,/*pclk_peri_axi_matrix*/
 559
 560                                 /*pclk_pd_alive*/
 561                                 <&clk_gates14 11>,/*pclk_grf*/
 562                                 <&clk_gates14 12>,/*pclk_alive_niu*/
 563
 564                                 /*pclk_pd_pmu*/
 565                                 <&clk_gates17 0>,/*pclk_pmu*/
 566                                 <&clk_gates17 1>,/*pclk_intmem1*/
 567                                 <&clk_gates17 2>,/*pclk_pmu_niu*/
 568                                 <&clk_gates17 3>,/*pclk_sgrf*/
 569
 570                                 /*hclk_vio*/
 571                                 <&clk_gates15 9>,/*hclk_vio_ahb_arbi*/
 572                                 <&clk_gates15 10>,/*hclk_vio_niu*/
 573                                 <&clk_gates16 10>,/*hclk_vio2_h2p*/
 574                                 <&clk_gates16 11>,/*pclk_vio2_h2p*/
 575
 576                                 /*aclk_vio0*/
 577                                 <&clk_gates15 11>,/*aclk_vio0_niu*/
 578
 579                                 /*aclk_vio1*/
 580                                 <&clk_gates15 12>,/*aclk_vio1_niu*/
 581
 582                                 /*HDMI*/
 583                                 <&clk_gates5 12>,/*hdmi_hdcp_clk*/
 584
 585                                 /*UART*/
 586                                 <&clk_gates11 9>;/*pclk_uart2*/
 587         };
 588
 589         i2c0: i2c@ff650000 {
 590                 compatible = "rockchip,rk30-i2c";
 591                 reg = <0xff650000 0x1000>;
 592                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 593                 #address-cells = <1>;
 594                 #size-cells = <0>;
 595                 pinctrl-names = "default", "gpio";
 596                 pinctrl-0 = <&i2c0_sda &i2c0_scl>;
 597                 pinctrl-1 = <&i2c0_gpio>;
 598                 gpios = <&gpio0 GPIO_B7 GPIO_ACTIVE_LOW>, <&gpio0 GPIO_C0 GPIO_ACTIVE_LOW>;
 599                 clocks = <&clk_gates10 2>;
 600                 rockchip,check-idle = <1>;
 601                 status = "disabled";
 602         };
 603
 604         i2c1: i2c@ff140000 {
 605                 compatible = "rockchip,rk30-i2c";
 606                 reg = <0xff140000 0x1000>;
 607                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 608                 #address-cells = <1>;
 609                 #size-cells = <0>;
 610                 pinctrl-names = "default", "gpio";
 611                 pinctrl-0 = <&i2c1_sda &i2c1_scl>;
 612                 pinctrl-1 = <&i2c1_gpio>;
 613                 gpios = <&gpio8 GPIO_A4 GPIO_ACTIVE_LOW>, <&gpio8 GPIO_A5 GPIO_ACTIVE_LOW>;
 614                 clocks = <&clk_gates10 3>;
 615                 rockchip,check-idle = <1>;
 616                 status = "disabled";
 617         };
 618
 619         i2c2: i2c@ff660000 {
 620                 compatible = "rockchip,rk30-i2c";
 621                 reg = <0xff660000 0x1000>;
 622                 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 623                 #address-cells = <1>;
 624                 #size-cells = <0>;
 625                 pinctrl-names = "default", "gpio";
 626                 pinctrl-0 = <&i2c2_sda &i2c2_scl>;
 627                 pinctrl-1 = <&i2c2_gpio>;
 628                 gpios = <&gpio6 GPIO_B1 GPIO_ACTIVE_LOW>, <&gpio6 GPIO_B2 GPIO_ACTIVE_LOW>;
 629                 clocks = <&clk_gates6 13>;
 630                 rockchip,check-idle = <1>;
 631                 status = "disabled";
 632         };
 633
 634         i2c3: i2c@ff150000 {
 635                 compatible = "rockchip,rk30-i2c";
 636                 reg = <0xff150000 0x1000>;
 637                 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 638                 #address-cells = <1>;
 639                 #size-cells = <0>;
 640                 pinctrl-names = "default", "gpio";
 641                 pinctrl-0 = <&i2c3_sda &i2c3_scl>;
 642                 pinctrl-1 = <&i2c3_gpio>;
 643                 gpios = <&gpio2 GPIO_C1 GPIO_ACTIVE_LOW>, <&gpio2 GPIO_C0 GPIO_ACTIVE_LOW>;
 644                 clocks = <&clk_gates6 14>;
 645                 rockchip,check-idle = <1>;
 646                 status = "disabled";
 647         };
 648
 649         i2c4: i2c@ff160000 {
 650                 compatible = "rockchip,rk30-i2c";
 651                 reg = <0xff160000 0x1000>;
 652                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 653                 #address-cells = <1>;
 654                 #size-cells = <0>;
 655                 pinctrl-names = "default", "gpio";
 656                 pinctrl-0 = <&i2c4_sda &i2c4_scl>;
 657                 pinctrl-1 = <&i2c4_gpio>;
 658                 gpios = <&gpio7 GPIO_C1 GPIO_ACTIVE_LOW>, <&gpio7 GPIO_C2 GPIO_ACTIVE_LOW>;
 659                 clocks = <&clk_gates6 15>;
 660                 rockchip,check-idle = <1>;
 661                 status = "disabled";
 662         };
 663
 664         i2c5: i2c@ff170000 {
 665                 compatible = "rockchip,rk30-i2c";
 666                 reg = <0xff170000 0x1000>;
 667                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 668                 #address-cells = <1>;
 669                 #size-cells = <0>;
 670                 pinctrl-names = "default", "gpio";
 671                 pinctrl-0 = <&i2c5_sda &i2c5_scl>;
 672                 pinctrl-1 = <&i2c5_gpio>;
 673                 gpios = <&gpio7 GPIO_C3 GPIO_ACTIVE_LOW>, <&gpio7 GPIO_C4 GPIO_ACTIVE_LOW>;
 674                 clocks = <&clk_gates7 0>;
 675                 rockchip,check-idle = <1>;
 676                 status = "disabled";
 677         };
 678
 679
 680         fb: fb{
 681                 compatible = "rockchip,rk-fb";
 682                 rockchip,disp-mode = <DUAL>;
 683         };
 684
 685         rk_screen: rk_screen{
 686                         compatible = "rockchip,screen";
 687         };
 688
 689         dsihost0: mipi@ff960000{
 690                 compatible = "rockchip,rk32-dsi";
 691                 rockchip,prop = <0>;
 692                 reg = <0xff960000 0x4000>;
 693                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 694                 clocks = <&clk_gates5 15>, <&clk_gates16 4>;
 695                 clock-names = "clk_mipi_24m", "pclk_mipi_dsi";
 696                 status = "disabled";
 697         };
 698
 699         dsihost1: mipi@ff964000{
 700                 compatible = "rockchip,rk32-dsi";
 701                 rockchip,prop = <1>;
 702                 reg = <0xff964000 0x4000>;
 703                 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 704                 clocks = <&clk_gates5 15>, <&clk_gates16 5>;
 705                 clock-names = "clk_mipi_24m", "pclk_mipi_dsi";
 706                 status = "disabled";
 707         };
 708
 709         lvds: lvds@ff96c000 {
 710                 compatible = "rockchip,rk32-lvds";
 711                 reg = <0xff96c000 0x4000>;
 712                 clocks = <&clk_gates16 7>;
 713                 clock-names = "pclk_lvds";
 714         };
 715
 716         edp: edp@ff970000 {
 717                 compatible = "rockchip,rk32-edp";
 718                 reg = <0xff970000 0x4000>;
 719                 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
 720                 clocks = <&clk_edp>, <&clk_edp_24m>, <&clk_gates16 8>;
 721                 clock-names = "clk_edp", "clk_edp_24m", "pclk_edp";
 722         };
 723
 724         hdmi: hdmi@ff980000 {
 725                 compatible = "rockchip,rk3288-hdmi";
 726                 reg = <0xff980000 0x20000>;
 727                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
 728                 pinctrl-names = "default", "gpio";
 729                 pinctrl-0 = <&i2c5_sda &i2c5_scl>;
 730                 pinctrl-1 = <&i2c5_gpio>;
 731                 clocks = <&clk_gates16 9>, <&clk_gates5 12>;
 732                 clock-names = "pclk_hdmi", "hdcp_clk_hdmi";
 733                 status = "disabled";
 734         };
 735
 736         lcdc1: lcdc@ff940000 {
 737                 compatible = "rockchip,rk3288-lcdc";
 738                 rockchip,prop = <PRMRY>;
 739                 rochchip,pwr18 = <0>;
 740                 reg = <0xff940000 0x10000>;
 741                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 742                 pinctrl-names = "default", "gpio";
 743                 pinctrl-0 = <&lcdc0_lcdc>;
 744                 pinctrl-1 = <&lcdc0_gpio>;
 745                 status = "disabled";
 746                 clocks = <&clk_gates15 7>, <&dclk_lcdc1>, <&clk_gates15 8>;
 747                 clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc";
 748         };
 749
 750         lcdc0: lcdc@ff930000 {
 751                 compatible = "rockchip,rk3288-lcdc";
 752                 rockchip,prop = <EXTEND>;
 753                 rockchip,pwr18 = <0>;
 754                 reg = <0xff930000 0x10000>;
 755                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 756                 //pinctrl-names = "default", "gpio";
 757                 //pinctrl-0 = <&lcdc0_lcdc>;
 758                 //pinctrl-1 = <&lcdc0_gpio>;
 759                 status = "disabled";
 760                 clocks = <&clk_gates15 5>, <&dclk_lcdc0>, <&clk_gates15 6>;
 761                 clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc";
 762         };
 763
 764         adc: adc@ff100000 {
 765                 compatible = "rockchip,saradc";
 766                 reg = <0xff100000 0x100>;
 767                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 768                 #io-channel-cells = <1>;
 769                 io-channel-ranges;
 770                 rockchip,adc-vref = <1800>;
 771                 clock-frequency = <1000000>;
 772                 clocks = <&clk_saradc>, <&clk_gates7 1>;
 773                 clock-names = "saradc", "pclk_saradc";
 774                 status = "disabled";
 775         };
 776
 777         rga@ff920000 {
 778                 compatible = "rockchip,rga";
 779                 reg = <0xff920000 0x1000>;
 780                 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
 781                 clocks = <&clk_gates15 1>, <&aclk_rga>, <&clk_rga>;
 782                 clock-names = "hclk_rga", "aclk_rga", "clk_rga";
 783         };
 784
 785         i2s: rockchip-i2s@0xff890000 {
 786                 compatible = "rockchip-i2s";
 787                 reg = <0xff890000 0x10000>;
 788                 i2s-id = <0>;
 789                 clocks = <&clk_i2s>, <&clk_i2s_out>, <&clk_gates10 8>;
 790                 clock-names = "i2s_clk","i2s_mclk", "i2s_hclk";
 791                 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 792                 dmas = <&pdma0 0>,
 793                         <&pdma0 1>;
 794                 //#dma-cells = <2>;
 795                 dma-names = "tx", "rx";
 796                 pinctrl-names = "default", "sleep";
 797                 pinctrl-0 = <&i2s_mclk &i2s_sclk &i2s_lrckrx &i2s_lrcktx &i2s_sdi &i2s_sdo0 &i2s_sdo1 &i2s_sdo2 &i2s_sdo3>;
 798                 pinctrl-1 = <&i2s_gpio>;
 799         };
 800
 801         spdif: rockchip-spdif@0xff8b0000 {
 802                 compatible = "rockchip-spdif";
 803                 reg = <0xff8b0000 0x10000>;     //8channel
 804                 //reg = <ff880000 0x10000>;//2channel
 805                 clocks = <&clk_spdif>, <&clk_spdif_8ch>;
 806                 clock-names = "spdif_mclk","spdif_8ch_mclk";
 807                 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 808                 dmas = <&pdma0 3>;
 809                 //dmas = <&pdma0 2>; //2channel
 810                 //#dma-cells = <1>;
 811                 dma-names = "tx";
 812                 pinctrl-names = "default";
 813                 pinctrl-0 = <&spdif_tx>;
 814         };
 815
 816         pwm0: pwm@ff680000 {
 817                 compatible = "rockchip,rk-pwm";
 818                 reg = <0xff680000 0x10>;
 819                 #pwm-cells = <2>;
 820                 pinctrl-names = "default";
 821                 pinctrl-0 = <&pwm0_pin>;
 822                 clocks = <&clk_gates11 11>;
 823                 clock-names = "pclk_pwm";
 824                 status = "okay";
 825         };
 826
 827         pwm1: pwm@ff680010 {
 828                 compatible = "rockchip,rk-pwm";
 829                 reg = <0xff680010 0x10>;
 830                 #pwm-cells = <2>;
 831                 pinctrl-names = "default";
 832                 pinctrl-0 = <&pwm1_pin>;
 833                 clocks = <&clk_gates11 11>;
 834                 clock-names = "pclk_pwm";
 835                 status = "disabled";
 836         };
 837
 838         pwm2: pwm@ff680020 {
 839                 compatible = "rockchip,rk-pwm";
 840                 reg = <0xff680020 0x10>;
 841                 #pwm-cells = <2>;
 842                 pinctrl-names = "default";
 843                 pinctrl-0 = <&pwm2_pin>;
 844                 clocks = <&clk_gates11 11>;
 845                 clock-names = "pclk_pwm";
 846                 status = "disabled";
 847         };
 848
 849         pwm3: pwm@ff680030 {
 850                 compatible = "rockchip,rk-pwm";
 851                 reg = <0xff680030 0x10>;
 852                 #pwm-cells = <2>;
 853                 pinctrl-names = "default";
 854                 pinctrl-0 = <&pwm3_pin>;
 855                 clocks = <&clk_gates11 11>;
 856                 clock-names = "pclk_pwm";
 857                 status = "disabled";
 858         };
 859         dvfs {
 860                 vd_arm:
 861                 vd_arm {
 862                         regulator_name="vdd_arm";
 863                         suspend_volt=<1000>; //mV
 864                         pd_core {
 865                                 clk_core_dvfs_table:
 866                                 clk_core {
 867                                         operating-points = <
 868                                                 /* KHz    uV */
 869                                                 312000 1100000
 870                                                 504000 1100000
 871                                                 816000 1100000
 872                                                 1008000 1100000
 873                                                 >;
 874                                         //temp-channel=<1>;
 875                                         temp-limit = <
 876                                                 /*temp    freq*/
 877                                                 50      1608000
 878                                                 70      1416000
 879                                                 80      1200000
 880                                                 100     1008000
 881                                                 >;
 882                                         status = "okay";
 883                                 };
 884                         };
 885                 };
 886
 887                 vd_logic:
 888                 vd_logic {
 889                         regulator_name="vdd_logic";
 890                         suspend_volt=<1000>; //mV
 891                         pd_ddr {
 892                                 clk_ddr_dvfs_table:
 893                                 clk_ddr {
 894                                         operating-points = <
 895                                                 /* KHz    uV */
 896                                                 200000 1200000
 897                                                 300000 1200000
 898                                                 400000 1200000
 899                                                 >;
 900                                         status = "disable";
 901                                 };
 902                         };
 903
 904                         pd_vpu {
 905                                 clk_ddr_vepu_table:
 906                                 clk_vepu {
 907                                         operating-points = <
 908                                                 /* KHz    uV */
 909                                                 200000 1300000
 910                                                 300000 1300000
 911                                                 400000 1300000
 912                                                 >;
 913                                         status = "disable";
 914                                 };
 915                         };
 916                 };
 917
 918                 vd_gpu:
 919                 vd_gpu {
 920                         regulator_name="vdd_gpu";
 921                         suspend_volt=<1000>; //mV
 922                         pd_gpu {
 923                                 clk_gpu_dvfs_table:
 924                                 clk_gpu {
 925                                         operating-points = <
 926                                                 /* KHz    uV */
 927                                                 200000 1200000
 928                                                 300000 1200000
 929                                                 400000 1200000
 930                                                 >;
 931                                         //temp-channel=<2>;
 932                                         temp-limit = <
 933                                                 /*temp    freq*/
 934                                                 50      600000
 935                                                 70      500000
 936                                                 80      400000
 937                                                 100     300000
 938                                                 >;
 939                                         status = "okay";
 940                                 };
 941                         };
 942                 };
 943         };
 944
 945         ion {
 946                 compatible = "rockchip,ion";
 947                 #address-cells = <1>;
 948                 #size-cells = <0>;
 949                 rockchip,ion-heap@1 { /* CMA HEAP */
 950                         compatible = "rockchip,ion-reserve";
 951                         reg = <1>;
 952                         memory-reservation = <0x00000000 0x18000000>; /* 384MB */
 953                 };
 954                 rockchip,ion-heap@3 { /* SYSTEM HEAP */
 955                         reg = <3>;
 956                 };
 957         };
 958
 959
 960         vpu: vpu_service@ff9a0000 {
 961                 compatible = "vpu_service";
 962                 reg = <0xff9a0000 0x800>;
 963                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 964                 interrupt-names = "irq_enc", "irq_dec";
 965                 clocks = <&clk_vdpu>, <&hclk_vdpu>;
 966                 clock-names = "aclk_vcodec", "hclk_vcodec";
 967                 name = "vpu_service";
 968                 //status = "disabled";
 969         };
 970
 971         hevc: hevc_service@ff9c0000 {
 972                 compatible = "rockchip,hevc_service";
 973                 reg = <0xff9c0000 0x800>;
 974                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 975                 interrupt-names = "irq_dec";
 976                 clocks = <&aclk_hevc>, <&hclk_hevc>, <&clk_hevc_core>, <&clk_hevc_cabac>;
 977                 clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core", "clk_cabac";
 978                 name = "hevc_service";
 979                 //status = "disabled";
 980         };
 981
 982         iep: iep@ff900000 {
 983                 compatible = "rockchip,iep";
 984                 reg = <0xff900000 0x800>;
 985                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 986                 clocks = <&clk_gates15 2>, <&clk_gates15 3>;
 987                 clock-names = "aclk_iep", "hclk_iep";
 988                 status = "okay";
 989         };
 990
 991         dwc_control_usb: dwc-control-usb@ff770284 {
 992                 compatible = "rockchip,rk3288-dwc-control-usb";
 993                 reg = <0xff770284 0x04>, <0xff770288 0x04>,
 994                       <0xff7702cc 0x04>, <0xff7702d4 0x04>,
 995                       <0xff770320 0x14>, <0xff770334 0x14>,
 996                       <0xff770348 0x10>, <0xff770358 0x08>,
 997                       <0xff770360 0x08>;
 998                 reg-names = "GRF_SOC_STATUS1" ,"GRF_SOC_STATUS2",
 999                     "GRF_SOC_STATUS19", "GRF_SOC_STATUS21",
1000                     "GRF_UOC0_BASE", "GRF_UOC1_BASE",
1001                     "GRF_UOC2_BASE", "GRF_UOC3_BASE",
1002                     "GRF_UOC4_BASE";
1003                 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
1004                      <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
1005                      <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
1006                 interrupt-names = "otg_id", "otg_bvalid",
1007                           "otg_linestate", "host0_linestate",
1008                           "host1_linestate";
1009                 gpios = <&gpio0 GPIO_B6 GPIO_ACTIVE_LOW>,/*HOST_VBUS_DRV*/
1010                         <&gpio0 GPIO_B4 GPIO_ACTIVE_LOW>;/*OTG_VBUS_DRV*/
1011                 clocks = <&clk_gates7 9>;
1012                 clock-names = "hclk_usb_peri";
1013                 rockchip,remote_wakeup;
1014                 rockchip,usb_irq_wakeup;
1015
1016                 usb_bc{
1017                         compatible = "synopsys,phy";
1018                                         /* offset bit mask */
1019                         rk_usb,bvalid     = <0x288 14 1>;
1020                         rk_usb,dcdenb     = <0x328 14 1>;
1021                         rk_usb,vdatsrcenb = <0x328  7 1>;
1022                         rk_usb,vdatdetenb = <0x328  6 1>;
1023                         rk_usb,chrgsel    = <0x328  5 1>;
1024                         rk_usb,chgdet     = <0x2cc 23 1>;
1025                         rk_usb,fsvminus   = <0x2cc 25 1>;
1026                         rk_usb,fsvplus    = <0x2cc 24 1>;
1027                 };
1028         };
1029
1030         usb0: usb@ff580000 {
1031                 compatible = "rockchip,rk3288_usb20_otg";
1032                 reg = <0xff580000 0x40000>;
1033                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
1034                 clocks = <&clk_gates13 4>, <&clk_gates7 4>;
1035                 clock-names = "clk_usbphy0", "hclk_usb0";
1036                 /*0 - Normal, 1 - Force Host, 2 - Force Device*/
1037                 rockchip,usb-mode = <0>;
1038         };
1039
1040         usb1: usb@ff540000 {
1041                 compatible = "rockchip,rk3288_usb20_host";
1042                 reg = <0xff540000 0x40000>;
1043                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
1044                 clocks = <&clk_gates13 6>, <&clk_gates7 7>;
1045                 clock-names = "clk_usbphy1", "hclk_usb1";
1046         };
1047
1048         usb2: usb@ff500000 {
1049                 compatible = "rockchip,rk3288_rk_ehci_host";
1050                 reg = <0xff500000 0x20000>;
1051                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
1052                 clocks = <&clk_gates13 5>, <&clk_gates7 6>;
1053                 clock-names = "clk_usbphy2", "hclk_usb2";
1054         };
1055
1056         usb3: usb@ff520000 {
1057                 compatible = "rockchip,rk3288_rk_ohci_host";
1058                 reg = <0xff520000 0x20000>;
1059                 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
1060                 clocks = <&clk_gates13 5>, <&clk_gates7 6>;
1061                 clock-names = "clk_usbphy3", "hclk_usb3";
1062         };
1063
1064         hsic: hsic@ff5c0000 {
1065                 compatible = "rockchip,rk3288_rk_hsic_host";
1066                 reg = <0xff5c0000 0x40000>;
1067                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
1068                 clocks = <&hsicphy_480m>, <&clk_gates7 8>,
1069                          <&hsicphy_12m>, <&usbphy_480m>,
1070                          <&otgphy1_480m>, <&otgphy2_480m>;
1071                 clock-names = "hsicphy_480m", "hclk_hsic",
1072                               "hsicphy_12m", "usbphy_480m",
1073                               "hsic_usbphy1", "hsic_usbphy2";
1074         };
1075
1076         gmac: eth@ff290000 {
1077                 compatible = "rockchip,gmac";
1078                 reg = <0xff290000 0x10000>;
1079                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;  /*irq=59*/
1080                 interrupt-names = "macirq";
1081                 //phy-mode = "rmii";
1082                 phy-mode = "rgmii";
1083                 pinctrl-names = "default";
1084                 pinctrl-0 = <&mac_clk &mac_txpins &mac_rxpins &mac_mdpins>;
1085         };
1086     gpu{
1087         compatible = "arm,malit764",
1088                      "arm,malit76x",
1089                      "arm,malit7xx",
1090                      "arm,mali-midgard";
1091         reg = <0xffa30000 0x10000>;
1092         interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
1093                      <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
1094                      <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1095         interrupt-names = "JOB",
1096                           "MMU",
1097                           "GPU";
1098     };
1099
1100     iep_mmu{
1101         dbgname = "iep";
1102         compatible = "iommu,iep_mmu";
1103         reg = <0xff900800 0x100>;
1104         interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1105         interrupt-names = "iep_mmu";
1106     };
1107
1108     vip_mmu{
1109         dbgname = "vip";
1110         compatible = "iommu,vip_mmu";
1111         reg = <0xff950800 0x100>;
1112         interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
1113         interrupt-names = "vip_mmu";
1114     };
1115     vopb_mmu{
1116         dbgname = "vopb";
1117         compatible = "iommu,vopb_mmu";
1118         reg = <0xff930300 0x100>;
1119         interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1120         interrupt-names = "vopb_mmu";
1121     };
1122
1123     vopl_mmu{
1124         dbgname = "vopl";
1125         compatible = "iommu,vopl_mmu";
1126         reg = <0xff940300 0x100>;
1127         interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1128         interrupt-names = "vopl_mmu";
1129     };
1130
1131     hevc_mmu{
1132         dbgname = "hevc";
1133         compatible = "iommu,hevc_mmu";
1134         reg = <0xff9c0440 0x100>,
1135                           <0xff9c0480 0x100>;
1136         interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
1137         interrupt-names = "hevc_mmu";
1138     };
1139
1140                 vpu_mmu{
1141         dbgname = "vpu";
1142         compatible = "iommu,vpu_mmu";
1143         reg = <0xff9a0800 0x100>;
1144         interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
1145         interrupt-names = "vpu_mmu";
1146     };
1147
1148         isp_mmu{
1149        dbgname = "isp_mmu";
1150        compatible = "iommu,isp_mmu";
1151        reg = <0xff914000 0x100>,
1152                          <0xff915000 0x100>;
1153        interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1154        interrupt-names = "isp_mmu";
1155     };
1156
1157
1158     rockchip_suspend {
1159                   rockchip,ctrbits = <
1160                                             (0
1161                                             |RKPM_CTR_PWR_DMNS
1162                                             |RKPM_CTR_GTCLKS
1163                                             |RKPM_CTR_PLLS
1164                                             //|RKPM_CTR_SYSCLK_DIV
1165                                             //|RKPM_CTR_IDLEAUTO_MD
1166                                            // |RKPM_CTR_ARMOFF_LPMD
1167                                             |RKPM_CTR_ARMOFF_LOGDP_LPMD
1168                                             )
1169                                         >;
1170                   rockchip,pmic-gpios=<
1171                                                     RKPM_PINGPIO_BITS_OUTPUT(GPIO0_A0,RKPM_GPIO_OUT_L)
1172                                                     RKPM_PINGPIO_BITS_INTPUT(GPIO0_A1,RKPM_GPIO_PULL_UP)
1173                                                     >;
1174             };
1175
1176            isp:isp@ff910000{
1177                 compatible = "rockchip,isp";
1178                 reg = <0xff910000 0x10000>;
1179                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1180                 clocks = <&clk_gates16 2>, <&clk_gates16 1>, <&clk_isp>, <&clk_isp_jpe>, <&clkin_isp>, <&clk_cif_out>,<&clk_gates5 15>;
1181                         clock-names = "aclk_isp", "hclk_isp", "clk_isp", "clk_isp_jpe", "pclkin_isp", "clk_vipout","clk_mipi_24m";
1182                         pinctrl-names = "default", "isp_dvp8bit","isp_dvp10bit","isp_dvp12bit";
1183                         pinctrl-0 = <&isp_mipi>;
1184                         pinctrl-1 = <&isp_mipi &isp_dvp_sync_d2d9>;
1185                         pinctrl-2 = <&isp_mipi &isp_dvp_sync_d2d9 &isp_dvp_d0d1>;
1186                         pinctrl-3 = <&isp_mipi &isp_dvp_sync_d2d9 &isp_dvp_d0d1 &isp_dvpd10d11>;
1187
1188                         status = "okay";
1189         };
1190
1191         tsadc: tsadc@ff280000{
1192                         compatible = "rockchip,tsadc";
1193                         reg = <0xff280000 0x100>;
1194                         interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
1195                         #io-channel-cells = <1>;
1196                         io-channel-ranges;
1197                         clock-frequency = <50000>;
1198                         clocks = <&clk_tsadc>, <&clk_gates7 2>;
1199                         clock-names = "tsadc", "pclk_tsadc";
1200                         status = "okay";
1201         };
1202
1203         lcdc_vdd_domain: lcdc-vdd-domain{
1204                         compatible = "rockchip,io_vol_domain";
1205                         pinctrl-names = "default", "1.8V", "3.3V";
1206                         pinctrl-0 = <&lcdc_vcc>;
1207                         pinctrl-1 = <&lcdc_vcc_18>;
1208                         pinctrl-2 = <&lcdc_vcc_33>;
1209         };
1210         dpio_vdd_domain: dpio-vdd-domain{
1211                         compatible = "rockchip,io_vol_domain";
1212                         pinctrl-names = "default", "1.8V", "3.3V";
1213                         pinctrl-0 = <&dvp_vcc>;
1214                         pinctrl-1 = <&dvp_vcc_18>;
1215                         pinctrl-2 = <&dvp_vcc_33>;
1216         };
1217         flash0_vdd_domain: flash0-vdd-domain{
1218                         compatible = "rockchip,io_vol_domain";
1219                         pinctrl-names = "default", "1.8V", "3.3V";
1220                         pinctrl-0 = <&flash0_vcc>;
1221                         pinctrl-1 = <&flash0_vcc_18>;
1222                         pinctrl-2 = <&flash0_vcc_33>;
1223         };
1224         flash1_vdd_domain: flash1-vdd-domain{
1225                         compatible = "rockchip,io_vol_domain";
1226                         pinctrl-names = "default", "1.8V", "3.3V";
1227                         pinctrl-0 = <&flash1_vcc>;
1228                         pinctrl-1 = <&flash1_vcc_18>;
1229                         pinctrl-2 = <&flash1_vcc_33>;
1230         };
1231         apio3_vdd_domain: apio3-vdd-domain{
1232                         compatible = "rockchip,io_vol_domain";
1233                         pinctrl-names = "default", "1.8V", "3.3V";
1234                         pinctrl-0 = <&wifi_vcc>;
1235                         pinctrl-1 = <&wifi_vcc_18>;
1236                         pinctrl-2 = <&wifi_vcc_33>;
1237         };
1238         apio5_vdd_domain: apio5-vdd-domain{
1239                         compatible = "rockchip,io_vol_domain";
1240                         pinctrl-names = "default", "1.8V", "3.3V";
1241                         pinctrl-0 = <&bb_vcc>;
1242                         pinctrl-1 = <&bb_vcc_18>;
1243                         pinctrl-2 = <&bb_vcc_33>;
1244         };
1245         apio4_vdd_domain: apio4-vdd-domain{
1246                         compatible = "rockchip,io_vol_domain";
1247                         pinctrl-names = "default", "1.8V", "3.3V";
1248                         pinctrl-0 = <&audio_vcc>;
1249                         pinctrl-1 = <&audio_vcc_18>;
1250                         pinctrl-2 = <&audio_vcc_33>;
1251         };
1252         apio1_vdd_domain: apio0-vdd-domain{
1253                         compatible = "rockchip,io_vol_domain";
1254                         pinctrl-names = "default", "1.8V", "3.3V";
1255                         pinctrl-0 = <&gpio30_vcc>;
1256                         pinctrl-1 = <&gpio30_vcc_18>;
1257                         pinctrl-2 = <&gpio30_vcc_33>;
1258         };
1259         apio2_vdd_domain: apio2-vdd-domain{
1260                         compatible = "rockchip,io_vol_domain";
1261                         pinctrl-names = "default", "1.8V", "3.3V";
1262                         pinctrl-0 = <&gpio1830_vcc>;
1263                         pinctrl-1 = <&gpio1830_vcc_18>;
1264                         pinctrl-2 = <&gpio1830_vcc_33>;
1265         };
1266         sdmmc0_vdd_domain: sdmmc0-vdd-domain{
1267                         compatible = "rockchip,io_vol_domain";
1268                         pinctrl-names = "default", "1.8V", "3.3V";
1269                         pinctrl-0 = <&sdcard_vcc>;
1270                         pinctrl-1 = <&sdcard_vcc_18>;
1271                         pinctrl-2 = <&sdcard_vcc_33>;
1272         };
1273
1274 };