1 #include <dt-bindings/clock/ddr.h>
2 #include <dt-bindings/interrupt-controller/arm-gic.h>
3 #include <dt-bindings/rkfb/rk_fb.h>
4 #include <dt-bindings/rkmipi/mipi_dsi.h>
5 #include <dt-bindings/suspend/rockchip-pm.h>
6 #include <dt-bindings/sensor-dev.h>
8 #include "skeleton.dtsi"
9 #include "rk3288-pinctrl.dtsi"
10 #include "rk3288-clocks.dtsi"
13 compatible = "rockchip,rk3288";
14 rockchip,sram = <&sram>;
15 interrupt-parent = <&gic>;
42 compatible = "arm,cortex-a15";
47 compatible = "arm,cortex-a15";
52 compatible = "arm,cortex-a15";
57 compatible = "arm,cortex-a15";
62 gic: interrupt-controller@ffc01000 {
63 compatible = "arm,cortex-a15-gic";
65 #interrupt-cells = <3>;
67 reg = <0xffc01000 0x1000>,
72 compatible = "arm,cortex-a12-pmu";
73 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
74 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
75 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
76 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
79 cpu_axi_bus: cpu_axi_bus {
80 compatible = "rockchip,cpu_axi_bus";
91 reg = <0xffa80000 0x20>;
94 reg = <0xffa80080 0x20>;
97 reg = <0xffa80100 0x20>;
101 reg = <0xffa90000 0x20>;
104 reg = <0xffa90080 0x20>;
107 reg = <0xffa90100 0x20>;
110 reg = <0xffa90180 0x20>;
113 reg = <0xffa90200 0x20>;
117 reg = <0xffaa0000 0x20>;
120 reg = <0xffaa0080 0x20>;
124 reg = <0xffab0000 0x20>;
128 reg = <0xffad0000 0x20>;
129 rockchip,priority = <2 2>;
132 reg = <0xffad0100 0x20>;
135 reg = <0xffad0180 0x20>;
138 reg = <0xffad0400 0x20>;
139 rockchip,priority = <2 2>;
142 reg = <0xffad0480 0x20>;
145 reg = <0xffad0500 0x20>;
148 reg = <0xffad0800 0x20>;
151 reg = <0xffad0880 0x20>;
154 reg = <0xffad0900 0x20>;
158 reg = <0xffae0000 0x20>;
162 reg = <0xffaf0000 0x20>;
165 reg = <0xffaf0080 0x20>;
170 #address-cells = <1>;
175 reg = <0xffac0000 0x40>;
176 rockchip,read-latency = <0xff>;
179 reg = <0xffac0080 0x40>;
180 rockchip,read-latency = <0xff>;
185 sram: sram@ff710000 {
186 compatible = "mmio-sram";
187 reg = <0xff710000 0x8000>; /* 32k */
192 compatible = "arm,armv7-timer";
193 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
194 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
195 clock-frequency = <24000000>;
199 compatible = "rockchip,timer";
200 reg = <0xff810000 0x20>;
201 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
202 rockchip,broadcast = <1>;
205 watchdog: wdt@2004c000 {
206 compatible = "rockchip,watch dog";
207 reg = <0xff800000 0x100>;
208 clocks = <&pclk_pd_alive>;
209 clock-names = "pclk_wdt";
210 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
212 rockchip,timeout = <60>;
213 rockchip,atboot = <1>;
214 rockchip,debug = <0>;
219 #address-cells = <1>;
221 compatible = "arm,amba-bus";
222 interrupt-parent = <&gic>;
225 pdma0: pdma@ffb20000 {
226 compatible = "arm,pl330", "arm,primecell";
227 reg = <0xffb20000 0x4000>;
228 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
229 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
233 pdma1: pdma@ff250000 {
234 compatible = "arm,pl330", "arm,primecell";
235 reg = <0xff250000 0x4000>;
236 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
237 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
242 nandc0: nandc@0xff400000 {
243 compatible = "rockchip,rk-nandc";
244 reg = <0xff400000 0x4000>;
245 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
247 clocks = <&clk_nandc0>, <&clk_gates5 5>, <&clk_gates7 14>;
248 clock-names = "clk_nandc", "g_clk_nandc", "hclk_nandc";
252 nandc1: nandc@0xff410000 {
253 compatible = "rockchip,rk-nandc";
254 reg = <0xff410000 0x4000>;
255 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
257 clocks = <&clk_nandc1>, <&clk_gates5 6>, <&clk_gates7 15>;
258 clock-names = "clk_nandc", "g_clk_nandc", "hclk_nandc";
262 emmc: rksdmmc@ff0f0000 {
263 compatible = "rockchip,rk_mmc", "rockchip,rk32xx-sdmmc";
264 reg = <0xff0f0000 0x4000>;
265 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
266 #address-cells = <1>;
268 //pinctrl-names = "default",,"suspend";
269 //pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_wp &sd0_pwr &sd0_bus1 &sd0_bus4>;
270 clocks = <&clk_emmc>, <&clk_gates8 6>;
271 clock-names = "clk_mmc", "hclk_mmc";
273 fifo-depth = <0x100>;
277 sdmmc: rksdmmc@ff0c0000 {
278 compatible = "rockchip,rk_mmc", "rockchip,rk32xx-sdmmc";
279 reg = <0xff0c0000 0x4000>;
280 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
281 #address-cells = <1>;
283 pinctrl-names = "default", "idle";
284 pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_dectn &sdmmc0_bus4>;
285 pinctrl-1 = <&sdmmc0_gpio>;
286 cd-gpios = <&gpio6 GPIO_C6 GPIO_ACTIVE_HIGH>;/*CD GPIO*/
287 clocks = <&clk_sdmmc>, <&clk_gates8 3>;
288 clock-names = "clk_mmc", "hclk_mmc";
290 fifo-depth = <0x100>;
294 sdio: rksdmmc@ff0d0000 {
295 compatible = "rockchip,rk_mmc", "rockchip,rk32xx-sdmmc";
296 reg = <0xff0d0000 0x4000>;
297 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
298 #address-cells = <1>;
300 pinctrl-names = "default","idle";
301 pinctrl-0 = <&sdio0_clk &sdio0_cmd &sdio0_wrprt &sdio0_pwr &sdio0_bkpwr
302 &sdio0_intn &sdio0_bus4>;
303 pinctrl-1 = <&sdio0_gpio>;
304 clocks = <&clk_sdio0>, <&clk_gates8 4>;
305 clock-names = "clk_mmc", "hclk_mmc";
307 fifo-depth = <0x100>;
311 sdio1: rksdmmc@ff0e0000 {
312 compatible = "rockchip,rk_mmc", "rockchip,rk32xx-sdmmc";
313 reg = <0xff0e0000 0x4000>;
314 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
315 #address-cells = <1>;
317 //pinctrl-names = "default","suspend";
318 //pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_cd &sd1_wp &sd1_bus1 &sd1_bus4>;
319 /*gate8_0 --hclk_sdmmc_ahb_arbi_gate_en, gate13_2 --clk_sdio1_src_gate_en*/
320 clocks = <&clk_sdio1>, <&clk_gates8 5>;
321 clock-names = "clk_mmc", "hclk_mmc";
323 fifo-depth = <0x100>;
329 compatible = "rockchip,rockchip-spi";
330 reg = <0xff110000 0x1000>;
331 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
332 #address-cells = <1>;
334 pinctrl-names = "default";
335 pinctrl-0 = <&spi0_txd &spi0_rxd &spi0_clk &spi0_cs0 &spi0_cs1>;
336 rockchip,spi-src-clk = <0>;
338 clocks =<&clk_spi0>, <&clk_gates6 4>;
339 clock-names = "spi","pclk_spi0";
340 //dmas = <&pdma1 11>, <&pdma1 12>;
342 //dma-names = "tx", "rx";
347 compatible = "rockchip,rockchip-spi";
348 reg = <0xff120000 0x1000>;
349 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
350 #address-cells = <1>;
352 pinctrl-names = "default";
353 pinctrl-0 = <&spi1_txd &spi1_rxd &spi1_clk &spi1_cs0>;
354 rockchip,spi-src-clk = <1>;
356 clocks = <&clk_spi1>, <&clk_gates6 5>;
357 clock-names = "spi","pclk_spi1";
358 //dmas = <&pdma1 13>, <&pdma1 14>;
360 //dma-names = "tx", "rx";
365 compatible = "rockchip,rockchip-spi";
366 reg = <0xff130000 0x1000>;
367 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
368 #address-cells = <1>;
370 pinctrl-names = "default";
371 pinctrl-0 = <&spi2_txd &spi2_rxd &spi2_clk &spi2_cs0 &spi2_cs1>;
372 rockchip,spi-src-clk = <2>;
374 clocks = <&clk_spi2>, <&clk_gates6 6>;
375 clock-names = "spi","pclk_spi2";
376 //dmas = <&pdma1 15>, <&pdma1 16>;
378 //dma-names = "tx", "rx";
382 uart_bt: serial@ff180000 {
383 compatible = "rockchip,serial";
384 reg = <0xff180000 0x100>;
385 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
386 clock-frequency = <24000000>;
387 clocks = <&clk_uart0>, <&clk_gates6 8>;
388 clock-names = "sclk_uart", "pclk_uart";
391 dmas = <&pdma1 1>, <&pdma1 2>;
393 pinctrl-names = "default";
394 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
398 uart_bb: serial@ff190000 {
399 compatible = "rockchip,serial";
400 reg = <0xff190000 0x100>;
401 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
402 clock-frequency = <24000000>;
403 clocks = <&clk_uart1>, <&clk_gates6 9>;
404 clock-names = "sclk_uart", "pclk_uart";
407 dmas = <&pdma1 3>, <&pdma1 4>;
409 pinctrl-names = "default";
410 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
414 uart_dbg: serial@ff690000 {
415 compatible = "rockchip,serial";
416 reg = <0xff690000 0x100>;
417 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
418 clock-frequency = <24000000>;
419 clocks = <&clk_uart2>, <&clk_gates11 9>;
420 clock-names = "sclk_uart", "pclk_uart";
423 dmas = <&pdma0 4>, <&pdma0 5>;
425 pinctrl-names = "default";
426 pinctrl-0 = <&uart2_xfer>;
430 uart_gps: serial@ff1b0000 {
431 compatible = "rockchip,serial";
432 reg = <0xff1b0000 0x100>;
433 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
434 clock-frequency = <24000000>;
435 clocks = <&clk_uart3>, <&clk_gates6 11>;
436 clock-names = "sclk_uart", "pclk_uart";
437 current-speed = <115200>;
440 dmas = <&pdma1 7>, <&pdma1 8>;
442 pinctrl-names = "default";
443 pinctrl-0 = <&uart3_xfer &uart3_cts &uart3_rts>;
447 uart_exp: serial@ff1c0000 {
448 compatible = "rockchip,serial";
449 reg = <0xff1c0000 0x100>;
450 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
451 clock-frequency = <24000000>;
452 clocks = <&clk_uart4>, <&clk_gates6 12>;
453 clock-names = "sclk_uart", "pclk_uart";
456 dmas = <&pdma1 9>, <&pdma1 10>;
458 pinctrl-names = "default";
459 pinctrl-0 = <&uart4_xfer &uart4_cts &uart4_rts>;
464 compatible = "rockchip,fiq-debugger";
465 rockchip,serial-id = <2>;
466 rockchip,signal-irq = <106>;
467 rockchip,wake-irq = <0>;
472 compatible = "rockchip,clocks-init";
473 rockchip,clocks-init-parent =
474 <&clk_core &clk_apll>, <&aclk_bus_src &clk_gpll>,
475 <&aclk_peri &clk_gpll>, <&uart_pll_mux &clk_gpll>,
476 <&clk_i2s_pll &clk_gpll>, <&clk_spdif_pll &clk_gpll>,
477 <&usbphy_480m &otgphy2_480m>;
478 rockchip,clocks-init-rate =
479 <&clk_core 792000000>, <&clk_gpll 297000000>,
480 /*<&clk_cpll 47000000>,*/ <&clk_npll 1250000000>,
481 <&aclk_bus_src 300000000>, <&aclk_bus 300000000>,
482 <&hclk_bus 150000000>, <&pclk_bus 75000000>,
483 <&clk_crypto 150000000>, <&aclk_peri 300000000>,
484 <&hclk_peri 150000000>, <&pclk_peri 75000000>,
485 <&clk_gpu 200000000>, <&aclk_vio0 300000000>,
486 <&aclk_vio1 300000000>, <&hclk_vio 75000000>,
487 <&pclk_pd_alive 100000000>, <&pclk_pd_pmu 100000000>,
488 <&aclk_hevc 400000000>, <&hclk_hevc 200000000>,
489 <&clk_hevc_cabac 300000000>, <&clk_hevc_core 300000000>,
490 <&aclk_rga 300000000>, <&clk_rga 300000000>,
491 <&clk_vepu 300000000>, <&clk_vdpu 300000000>,
492 <&clk_edp 200000000>, <&clk_isp 200000000>,
493 <&clk_isp_jpe 400000000>, <&clk_tsp 80000000>,
494 <&clk_tspout 80000000>, <&clk_mac 125000000>;
498 compatible = "rockchip,clocks-enable";
501 <&clk_gates0 2>, <&clk_core0>,
502 <&clk_core1>, <&clk_core2>,
503 <&clk_core3>, <&clk_l2ram>,
504 <&aclk_core_m0>, <&aclk_core_mp>,
505 <&atclk_core>, <&pclk_dbg_src>,
506 <&clk_gates12 9>, <&clk_gates12 10>,
510 <&aclk_bus>, <&clk_gates0 3>,
511 <&hclk_bus>, <&pclk_bus>,
512 <&clk_gates13 8>, <&clk_crypto>,
516 <&clk_gates1 0>, <&clk_gates1 1>,
517 <&clk_gates1 2>, <&clk_gates1 3>,
518 <&clk_gates1 4>, <&clk_gates1 5>,
520 <&pclk_pd_alive>, <&pclk_pd_pmu>,
523 <&aclk_peri>, <&hclk_peri>,
527 /*<&clk_gates4 14>,*/
530 <&clk_gates10 5>,/*aclk_intmem0*/
531 <&clk_gates10 6>,/*aclk_intmem1*/
532 <&clk_gates10 7>,/*aclk_intmem2*/
533 <&clk_gates10 12>,/*aclk_dma1*/
534 <&clk_gates10 13>,/*aclk_strc_sys*/
535 <&clk_gates10 4>,/*aclk_intmem*/
536 <&clk_gates11 6>,/*aclk_crypto*/
537 <&clk_gates11 8>,/*aclk_ccp*/
540 <&clk_gates11 7>,/*hclk_crypto*/
541 <&clk_gates10 9>,/*hclk_rom*/
544 <&clk_gates10 1>,/*pclk_timer*/
545 <&clk_gates10 9>,/*rom*/
546 <&clk_gates10 13>,/*aclk strc*/
548 <&clk_gates12 8>,/*aclk strc*/
551 <&clk_gates6 2>,/*aclk_peri_axi_matrix*/
552 <&clk_gates6 3>,/*aclk_dmac2*/
553 <&clk_gates7 11>,/*aclk_peri_niu*/
554 <&clk_gates8 12>,/*aclk_peri_mmu*/
557 <&clk_gates6 0>,/*hclk_peri_matrix*/
558 <&clk_gates7 10>,/*hclk_peri_ahb_arbi*/
559 <&clk_gates7 12>,/*hclk_emem_peri*/
560 <&clk_gates7 13>,/*hclk_mem_peri*/
563 <&clk_gates6 1>,/*pclk_peri_axi_matrix*/
566 <&clk_gates14 11>,/*pclk_grf*/
567 <&clk_gates14 12>,/*pclk_alive_niu*/
570 <&clk_gates17 0>,/*pclk_pmu*/
571 <&clk_gates17 1>,/*pclk_intmem1*/
572 <&clk_gates17 2>,/*pclk_pmu_niu*/
573 <&clk_gates17 3>,/*pclk_sgrf*/
576 <&clk_gates15 9>,/*hclk_vio_ahb_arbi*/
577 <&clk_gates15 10>,/*hclk_vio_niu*/
578 <&clk_gates16 10>,/*hclk_vio2_h2p*/
579 <&clk_gates16 11>,/*pclk_vio2_h2p*/
582 <&clk_gates15 11>,/*aclk_vio0_niu*/
585 <&clk_gates15 12>,/*aclk_vio1_niu*/
588 //<&clk_gates5 12>,/*hdmi_hdcp_clk*/
591 <&clk_gates11 9>,/*pclk_uart2*/
598 compatible = "rockchip,rk30-i2c";
599 reg = <0xff650000 0x1000>;
600 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
601 #address-cells = <1>;
603 pinctrl-names = "default", "gpio";
604 pinctrl-0 = <&i2c0_sda &i2c0_scl>;
605 pinctrl-1 = <&i2c0_gpio>;
606 gpios = <&gpio0 GPIO_B7 GPIO_ACTIVE_LOW>, <&gpio0 GPIO_C0 GPIO_ACTIVE_LOW>;
607 clocks = <&clk_gates10 2>;
608 rockchip,check-idle = <1>;
613 compatible = "rockchip,rk30-i2c";
614 reg = <0xff140000 0x1000>;
615 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
616 #address-cells = <1>;
618 pinctrl-names = "default", "gpio";
619 pinctrl-0 = <&i2c1_sda &i2c1_scl>;
620 pinctrl-1 = <&i2c1_gpio>;
621 gpios = <&gpio8 GPIO_A4 GPIO_ACTIVE_LOW>, <&gpio8 GPIO_A5 GPIO_ACTIVE_LOW>;
622 clocks = <&clk_gates10 3>;
623 rockchip,check-idle = <1>;
628 compatible = "rockchip,rk30-i2c";
629 reg = <0xff660000 0x1000>;
630 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
631 #address-cells = <1>;
633 pinctrl-names = "default", "gpio";
634 pinctrl-0 = <&i2c2_sda &i2c2_scl>;
635 pinctrl-1 = <&i2c2_gpio>;
636 gpios = <&gpio6 GPIO_B1 GPIO_ACTIVE_LOW>, <&gpio6 GPIO_B2 GPIO_ACTIVE_LOW>;
637 clocks = <&clk_gates6 13>;
638 rockchip,check-idle = <1>;
643 compatible = "rockchip,rk30-i2c";
644 reg = <0xff150000 0x1000>;
645 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
646 #address-cells = <1>;
648 pinctrl-names = "default", "gpio";
649 pinctrl-0 = <&i2c3_sda &i2c3_scl>;
650 pinctrl-1 = <&i2c3_gpio>;
651 gpios = <&gpio2 GPIO_C1 GPIO_ACTIVE_LOW>, <&gpio2 GPIO_C0 GPIO_ACTIVE_LOW>;
652 clocks = <&clk_gates6 14>;
653 rockchip,check-idle = <1>;
658 compatible = "rockchip,rk30-i2c";
659 reg = <0xff160000 0x1000>;
660 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
661 #address-cells = <1>;
663 pinctrl-names = "default", "gpio";
664 pinctrl-0 = <&i2c4_sda &i2c4_scl>;
665 pinctrl-1 = <&i2c4_gpio>;
666 gpios = <&gpio7 GPIO_C1 GPIO_ACTIVE_LOW>, <&gpio7 GPIO_C2 GPIO_ACTIVE_LOW>;
667 clocks = <&clk_gates6 15>;
668 rockchip,check-idle = <1>;
673 compatible = "rockchip,rk30-i2c";
674 reg = <0xff170000 0x1000>;
675 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
676 #address-cells = <1>;
678 pinctrl-names = "default", "gpio";
679 pinctrl-0 = <&i2c5_sda &i2c5_scl>;
680 pinctrl-1 = <&i2c5_gpio>;
681 gpios = <&gpio7 GPIO_C3 GPIO_ACTIVE_LOW>, <&gpio7 GPIO_C4 GPIO_ACTIVE_LOW>;
682 clocks = <&clk_gates7 0>;
683 rockchip,check-idle = <1>;
688 compatible = "rockchip,rk-fb";
689 rockchip,disp-mode = <DUAL>;
692 rk_screen: rk_screen{
693 compatible = "rockchip,screen";
696 dsihost0: mipi@ff960000{
697 compatible = "rockchip,rk32-dsi";
699 reg = <0xff960000 0x4000>;
700 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
701 clocks = <&clk_gates5 15>, <&clk_gates16 4> , <&pd_mipidsi>;
702 clock-names = "clk_mipi_24m", "pclk_mipi_dsi", "pd_mipi_dsi";
706 dsihost1: mipi@ff964000{
707 compatible = "rockchip,rk32-dsi";
709 reg = <0xff964000 0x4000>;
710 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
711 clocks = <&clk_gates5 15>, <&clk_gates16 5>, <&pd_mipidsi>;
712 clock-names = "clk_mipi_24m", "pclk_mipi_dsi", "pd_mipi_dsi";
716 lvds: lvds@ff96c000 {
717 compatible = "rockchip,rk32-lvds";
718 reg = <0xff96c000 0x4000>;
719 clocks = <&clk_gates16 7>;
720 clock-names = "pclk_lvds";
724 compatible = "rockchip,rk32-edp";
725 reg = <0xff970000 0x4000>;
726 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
727 clocks = <&clk_edp>, <&clk_edp_24m>, <&clk_gates16 8>;
728 clock-names = "clk_edp", "clk_edp_24m", "pclk_edp";
731 hdmi: hdmi@ff980000 {
732 compatible = "rockchip,rk3288-hdmi";
733 reg = <0xff980000 0x20000>;
734 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
735 pinctrl-names = "default", "gpio";
736 pinctrl-0 = <&i2c5_sda &i2c5_scl>;
737 pinctrl-1 = <&i2c5_gpio>;
738 clocks = <&clk_gates16 9>, <&clk_gates5 12>;
739 clock-names = "pclk_hdmi", "hdcp_clk_hdmi";
743 lcdc1: lcdc@ff940000 {
744 compatible = "rockchip,rk3288-lcdc";
745 rockchip,prop = <PRMRY>;
746 rochchip,pwr18 = <0>;
747 reg = <0xff940000 0x10000>;
748 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
749 pinctrl-names = "default", "gpio";
750 pinctrl-0 = <&lcdc0_lcdc>;
751 pinctrl-1 = <&lcdc0_gpio>;
753 clocks = <&clk_gates15 7>, <&dclk_lcdc1>, <&clk_gates15 8>, <&pd_vop1>;
754 clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc", "pd_lcdc";
757 lcdc0: lcdc@ff930000 {
758 compatible = "rockchip,rk3288-lcdc";
759 rockchip,prop = <EXTEND>;
760 rockchip,pwr18 = <0>;
761 reg = <0xff930000 0x10000>;
762 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
763 //pinctrl-names = "default", "gpio";
764 //pinctrl-0 = <&lcdc0_lcdc>;
765 //pinctrl-1 = <&lcdc0_gpio>;
767 clocks = <&clk_gates15 5>, <&dclk_lcdc0>, <&clk_gates15 6>, <&pd_vop0>;
768 clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc", "pd_lcdc";
772 compatible = "rockchip,saradc";
773 reg = <0xff100000 0x100>;
774 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
775 #io-channel-cells = <1>;
777 rockchip,adc-vref = <1800>;
778 clock-frequency = <1000000>;
779 clocks = <&clk_saradc>, <&clk_gates7 1>;
780 clock-names = "saradc", "pclk_saradc";
785 compatible = "rockchip,rga";
786 reg = <0xff920000 0x1000>;
787 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
788 clocks = <&clk_gates15 1>, <&aclk_rga>, <&clk_rga>;
789 clock-names = "hclk_rga", "aclk_rga", "clk_rga";
792 i2s: rockchip-i2s@0xff890000 {
793 compatible = "rockchip-i2s";
794 reg = <0xff890000 0x10000>;
796 clocks = <&clk_i2s>, <&clk_i2s_out>, <&clk_gates10 8>;
797 clock-names = "i2s_clk","i2s_mclk", "i2s_hclk";
798 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
799 dmas = <&pdma0 0>, <&pdma0 1>;
801 dma-names = "tx", "rx";
802 pinctrl-names = "default", "sleep";
803 pinctrl-0 = <&i2s_mclk &i2s_sclk &i2s_lrckrx &i2s_lrcktx &i2s_sdi &i2s_sdo0 &i2s_sdo1 &i2s_sdo2 &i2s_sdo3>;
804 pinctrl-1 = <&i2s_gpio>;
807 spdif: rockchip-spdif@0xff8b0000 {
808 compatible = "rockchip-spdif";
809 reg = <0xff8b0000 0x10000>; //8channel
810 //reg = <ff880000 0x10000>;//2channel
811 clocks = <&clk_spdif>, <&clk_spdif_8ch>;
812 clock-names = "spdif_mclk","spdif_8ch_mclk";
813 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
815 //dmas = <&pdma0 2>; //2channel
818 pinctrl-names = "default";
819 pinctrl-0 = <&spdif_tx>;
822 vop1pwm: pwm@ff9401a0 {
823 compatible = "rockchip,vop-pwm";
824 reg = <0xff9401a0 0x10>;
826 pinctrl-names = "default";
827 pinctrl-0 = <&vop1_pwm_pin>;
828 clocks = <&clk_gates13 11>;
829 clock-names = "pclk_pwm";
833 vop0pwm: pwm@ff9301a0 {
834 compatible = "rockchip,vop-pwm";
835 reg = <0xff9301a0 0x10>;
837 pinctrl-names = "default";
838 pinctrl-0 = <&vop0_pwm_pin>;
839 clocks = <&clk_gates13 10>;
840 clock-names = "pclk_pwm";
845 compatible = "rockchip,rk-pwm";
846 reg = <0xff680000 0x10>;
848 pinctrl-names = "default";
849 pinctrl-0 = <&pwm0_pin>;
850 clocks = <&clk_gates11 11>;
851 clock-names = "pclk_pwm";
856 compatible = "rockchip,rk-pwm";
857 reg = <0xff680010 0x10>;
859 pinctrl-names = "default";
860 pinctrl-0 = <&pwm1_pin>;
861 clocks = <&clk_gates11 11>;
862 clock-names = "pclk_pwm";
867 compatible = "rockchip,rk-pwm";
868 reg = <0xff680020 0x10>;
870 pinctrl-names = "default";
871 pinctrl-0 = <&pwm2_pin>;
872 clocks = <&clk_gates11 11>;
873 clock-names = "pclk_pwm";
878 compatible = "rockchip,rk-pwm";
879 reg = <0xff680030 0x10>;
881 pinctrl-names = "default";
882 pinctrl-0 = <&pwm3_pin>;
883 clocks = <&clk_gates11 11>;
884 clock-names = "pclk_pwm";
889 temp-limit-enable = <1>;
893 regulator_name = "vdd_arm";
894 suspend_volt = <1000>; //mV
896 clk_core_dvfs_table: clk_core {
905 normal-temp-limit = <
906 /*delta-temp delta-freq*/
912 performance-temp-limit = <
922 regulator_name = "vdd_logic";
923 suspend_volt = <1000>; //mV
925 clk_ddr_dvfs_table: clk_ddr {
937 clk_ddr_vepu_table: clk_vepu {
950 regulator_name = "vdd_gpu";
951 suspend_volt = <1000>; //mV
953 clk_gpu_dvfs_table: clk_gpu {
975 compatible = "rockchip,ion";
976 #address-cells = <1>;
979 rockchip,ion-heap@1 { /* CMA HEAP */
980 compatible = "rockchip,ion-reserve";
981 rockchip,ion_heap = <1>;
982 reg = <0x00000000 0x20000000>; /* 512MB */
984 rockchip,ion-heap@3 { /* VMALLOC HEAP */
985 rockchip,ion_heap = <3>;
989 vpu: vpu_service@ff9a0000 {
990 compatible = "vpu_service";
991 reg = <0xff9a0000 0x800>;
992 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
993 interrupt-names = "irq_enc", "irq_dec";
994 clocks = <&clk_vdpu>, <&hclk_vdpu>;
995 clock-names = "aclk_vcodec", "hclk_vcodec";
996 name = "vpu_service";
997 //status = "disabled";
1000 hevc: hevc_service@ff9c0000 {
1001 compatible = "rockchip,hevc_service";
1002 reg = <0xff9c0000 0x800>;
1003 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
1004 interrupt-names = "irq_dec";
1005 clocks = <&aclk_hevc>, <&hclk_hevc>, <&clk_hevc_core>, <&clk_hevc_cabac>;
1006 clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core", "clk_cabac";
1007 name = "hevc_service";
1008 //status = "disabled";
1012 compatible = "rockchip,iep";
1013 reg = <0xff900000 0x800>;
1014 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1015 clocks = <&clk_gates15 2>, <&clk_gates15 3>;
1016 clock-names = "aclk_iep", "hclk_iep";
1020 dwc_control_usb: dwc-control-usb@ff770284 {
1021 compatible = "rockchip,rk3288-dwc-control-usb";
1022 reg = <0xff770284 0x04>, <0xff770288 0x04>,
1023 <0xff7702cc 0x04>, <0xff7702d4 0x04>,
1024 <0xff770320 0x14>, <0xff770334 0x14>,
1025 <0xff770348 0x10>, <0xff770358 0x08>,
1027 reg-names = "GRF_SOC_STATUS1" ,"GRF_SOC_STATUS2",
1028 "GRF_SOC_STATUS19", "GRF_SOC_STATUS21",
1029 "GRF_UOC0_BASE", "GRF_UOC1_BASE",
1030 "GRF_UOC2_BASE", "GRF_UOC3_BASE",
1032 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
1033 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
1034 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
1035 interrupt-names = "otg_id", "otg_bvalid",
1036 "otg_linestate", "host0_linestate",
1038 clocks = <&clk_gates7 9>, <&usbphy_480m>,
1039 <&otgphy1_480m>, <&otgphy2_480m>;
1040 clock-names = "hclk_usb_peri", "usbphy_480m",
1041 "usbphy1_480m", "usbphy2_480m";
1044 compatible = "synopsys,phy";
1045 /* offset bit mask */
1046 rk_usb,bvalid = <0x288 14 1>;
1047 rk_usb,dcdenb = <0x328 14 1>;
1048 rk_usb,vdatsrcenb = <0x328 7 1>;
1049 rk_usb,vdatdetenb = <0x328 6 1>;
1050 rk_usb,chrgsel = <0x328 5 1>;
1051 rk_usb,chgdet = <0x2cc 23 1>;
1052 rk_usb,fsvminus = <0x2cc 25 1>;
1053 rk_usb,fsvplus = <0x2cc 24 1>;
1057 usb0: usb@ff580000 {
1058 compatible = "rockchip,rk3288_usb20_otg";
1059 reg = <0xff580000 0x40000>;
1060 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
1061 clocks = <&clk_gates13 4>, <&clk_gates7 4>;
1062 clock-names = "clk_usbphy0", "hclk_usb0";
1063 /*0 - Normal, 1 - Force Host, 2 - Force Device*/
1064 rockchip,usb-mode = <0>;
1067 usb1: usb@ff540000 {
1068 compatible = "rockchip,rk3288_usb20_host";
1069 reg = <0xff540000 0x40000>;
1070 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
1071 clocks = <&clk_gates13 6>, <&clk_gates7 7>,
1073 clock-names = "clk_usbphy1", "hclk_usb1",
1077 usb2: usb@ff500000 {
1078 compatible = "rockchip,rk3288_rk_ehci_host";
1079 reg = <0xff500000 0x20000>;
1080 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
1081 clocks = <&clk_gates13 5>, <&clk_gates7 6>;
1082 clock-names = "clk_usbphy2", "hclk_usb2";
1085 usb3: usb@ff520000 {
1086 compatible = "rockchip,rk3288_rk_ohci_host";
1087 reg = <0xff520000 0x20000>;
1088 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
1089 clocks = <&clk_gates13 5>, <&clk_gates7 6>;
1090 clock-names = "clk_usbphy3", "hclk_usb3";
1093 hsic: hsic@ff5c0000 {
1094 compatible = "rockchip,rk3288_rk_hsic_host";
1095 reg = <0xff5c0000 0x40000>;
1096 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
1097 clocks = <&hsicphy_480m>, <&clk_gates7 8>,
1098 <&hsicphy_12m>, <&usbphy_480m>,
1099 <&otgphy1_480m>, <&otgphy2_480m>;
1100 clock-names = "hsicphy_480m", "hclk_hsic",
1101 "hsicphy_12m", "usbphy_480m",
1102 "hsic_usbphy1", "hsic_usbphy2";
1105 gmac: eth@ff290000 {
1106 compatible = "rockchip,gmac";
1107 reg = <0xff290000 0x10000>;
1108 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; /*irq=59*/
1109 interrupt-names = "macirq";
1110 clocks = <&clk_mac>, <&clk_gates5 0>,
1111 <&clk_gates5 1>, <&clk_gates5 2>,
1112 <&clk_gates5 3>, <&clk_gates8 0>,
1114 clock-names = "clk_mac", "mac_clk_rx",
1115 "mac_clk_tx", "clk_mac_ref",
1116 "clk_mac_refout", "aclk_mac",
1118 //phy-mode = "rmii";
1120 pinctrl-names = "default";
1121 pinctrl-0 = <&mac_clk &mac_txpins &mac_rxpins &mac_mdpins>;
1125 compatible = "arm,malit764",
1129 reg = <0xffa30000 0x10000>;
1130 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
1131 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
1132 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1133 interrupt-names = "JOB", "MMU", "GPU";
1138 compatible = "iommu,iep_mmu";
1139 reg = <0xff900800 0x100>;
1140 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1141 interrupt-names = "iep_mmu";
1146 compatible = "iommu,vip_mmu";
1147 reg = <0xff950800 0x100>;
1148 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
1149 interrupt-names = "vip_mmu";
1154 compatible = "iommu,vopb_mmu";
1155 reg = <0xff930300 0x100>;
1156 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1157 interrupt-names = "vopb_mmu";
1162 compatible = "iommu,vopl_mmu";
1163 reg = <0xff940300 0x100>;
1164 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1165 interrupt-names = "vopl_mmu";
1170 compatible = "iommu,hevc_mmu";
1171 reg = <0xff9c0440 0x100>,
1173 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
1174 interrupt-names = "hevc_mmu";
1179 compatible = "iommu,vpu_mmu";
1180 reg = <0xff9a0800 0x100>;
1181 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
1182 interrupt-names = "vpu_mmu";
1186 dbgname = "isp_mmu";
1187 compatible = "iommu,isp_mmu";
1188 reg = <0xff914000 0x100>,
1190 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1191 interrupt-names = "isp_mmu";
1195 rockchip,ctrbits = <
1200 // |RKPM_CTR_SYSCLK_DIV
1201 // |RKPM_CTR_IDLEAUTO_MD
1202 // |RKPM_CTR_ARMOFF_LPMD
1203 |RKPM_CTR_ARMOFF_LOGDP_LPMD
1206 rockchip,pmic-gpios = <
1207 RKPM_PINGPIO_BITS_OUTPUT(GPIO0_A0,RKPM_GPIO_OUT_L)
1208 RKPM_PINGPIO_BITS_INTPUT(GPIO0_A1,RKPM_GPIO_PULL_UP)
1213 compatible = "rockchip,isp";
1214 reg = <0xff910000 0x10000>;
1215 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1216 clocks = <&clk_gates16 2>, <&clk_gates16 1>, <&clk_isp>, <&clk_isp_jpe>, <&clkin_isp>, <&clk_cif_out>, <&clk_gates5 15>, <&clk_cif_pll>, <&pd_isp>, <&clk_gates16 6>;
1217 clock-names = "aclk_isp", "hclk_isp", "clk_isp", "clk_isp_jpe", "pclkin_isp", "clk_cif_out", "clk_mipi_24m", "clk_cif_pll", "pd_isp", "hclk_mipiphy1";
1218 pinctrl-names = "default", "isp_dvp8bit2", "isp_dvp10bit", "isp_dvp12bit", "isp_dvp8bit0", "isp_mipi_fl", "isp_mipi_fl_prefl";
1219 pinctrl-0 = <&isp_mipi>;
1220 pinctrl-1 = <&isp_mipi &isp_dvp_d2d9>;
1221 pinctrl-2 = <&isp_mipi &isp_dvp_d2d9 &isp_dvp_d0d1>;
1222 pinctrl-3 = <&isp_mipi &isp_dvp_d2d9 &isp_dvp_d0d1 &isp_dvp_d10d11>;
1223 pinctrl-4 = <&isp_mipi &isp_dvp_d0d7>;
1224 pinctrl-5 = <&isp_mipi &isp_flash_trigger>;
1225 pinctrl-6 = <&isp_mipi &isp_flash_trigger &isp_prelight>;
1226 rockchip,isp,mipiphy = <2>;
1227 rockchip,isp,cifphy = <1>;
1228 rockchip,isp,mipiphy1,reg = <0xff968000 0x4000>;
1232 tsadc: tsadc@ff280000 {
1233 compatible = "rockchip,tsadc";
1234 reg = <0xff280000 0x100>;
1235 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
1236 #io-channel-cells = <1>;
1238 clock-frequency = <50000>;
1239 clocks = <&clk_tsadc>, <&clk_gates7 2>;
1240 clock-names = "tsadc", "pclk_tsadc";
1244 lcdc_vdd_domain: lcdc-vdd-domain {
1245 compatible = "rockchip,io_vol_domain";
1246 pinctrl-names = "default", "1.8V", "3.3V";
1247 pinctrl-0 = <&lcdc_vcc>;
1248 pinctrl-1 = <&lcdc_vcc_18>;
1249 pinctrl-2 = <&lcdc_vcc_33>;
1252 dpio_vdd_domain: dpio-vdd-domain {
1253 compatible = "rockchip,io_vol_domain";
1254 pinctrl-names = "default", "1.8V", "3.3V";
1255 pinctrl-0 = <&dvp_vcc>;
1256 pinctrl-1 = <&dvp_vcc_18>;
1257 pinctrl-2 = <&dvp_vcc_33>;
1260 flash0_vdd_domain: flash0-vdd-domain {
1261 compatible = "rockchip,io_vol_domain";
1262 pinctrl-names = "default", "1.8V", "3.3V";
1263 pinctrl-0 = <&flash0_vcc>;
1264 pinctrl-1 = <&flash0_vcc_18>;
1265 pinctrl-2 = <&flash0_vcc_33>;
1268 flash1_vdd_domain: flash1-vdd-domain {
1269 compatible = "rockchip,io_vol_domain";
1270 pinctrl-names = "default", "1.8V", "3.3V";
1271 pinctrl-0 = <&flash1_vcc>;
1272 pinctrl-1 = <&flash1_vcc_18>;
1273 pinctrl-2 = <&flash1_vcc_33>;
1276 apio3_vdd_domain: apio3-vdd-domain {
1277 compatible = "rockchip,io_vol_domain";
1278 pinctrl-names = "default", "1.8V", "3.3V";
1279 pinctrl-0 = <&wifi_vcc>;
1280 pinctrl-1 = <&wifi_vcc_18>;
1281 pinctrl-2 = <&wifi_vcc_33>;
1284 apio5_vdd_domain: apio5-vdd-domain {
1285 compatible = "rockchip,io_vol_domain";
1286 pinctrl-names = "default", "1.8V", "3.3V";
1287 pinctrl-0 = <&bb_vcc>;
1288 pinctrl-1 = <&bb_vcc_18>;
1289 pinctrl-2 = <&bb_vcc_33>;
1292 apio4_vdd_domain: apio4-vdd-domain {
1293 compatible = "rockchip,io_vol_domain";
1294 pinctrl-names = "default", "1.8V", "3.3V";
1295 pinctrl-0 = <&audio_vcc>;
1296 pinctrl-1 = <&audio_vcc_18>;
1297 pinctrl-2 = <&audio_vcc_33>;
1300 apio1_vdd_domain: apio0-vdd-domain {
1301 compatible = "rockchip,io_vol_domain";
1302 pinctrl-names = "default", "1.8V", "3.3V";
1303 pinctrl-0 = <&gpio30_vcc>;
1304 pinctrl-1 = <&gpio30_vcc_18>;
1305 pinctrl-2 = <&gpio30_vcc_33>;
1308 apio2_vdd_domain: apio2-vdd-domain {
1309 compatible = "rockchip,io_vol_domain";
1310 pinctrl-names = "default", "1.8V", "3.3V";
1311 pinctrl-0 = <&gpio1830_vcc>;
1312 pinctrl-1 = <&gpio1830_vcc_18>;
1313 pinctrl-2 = <&gpio1830_vcc_33>;
1316 sdmmc0_vdd_domain: sdmmc0-vdd-domain {
1317 compatible = "rockchip,io_vol_domain";
1318 pinctrl-names = "default", "1.8V", "3.3V";
1319 pinctrl-0 = <&sdcard_vcc>;
1320 pinctrl-1 = <&sdcard_vcc_18>;
1321 pinctrl-2 = <&sdcard_vcc_33>;