arch/arm/boot/dts/rk3288.dtsi

   1 #include <dt-bindings/clock/rk_system_status.h>
   2 #include <dt-bindings/interrupt-controller/arm-gic.h>
   3 #include <dt-bindings/rkfb/rk_fb.h>
   4 #include <dt-bindings/rkmipi/mipi_dsi.h>
   5 #include <dt-bindings/suspend/rockchip-pm.h>
   6 #include <dt-bindings/sensor-dev.h>
   7
   8 #include "skeleton.dtsi"
   9 #include "rk3288-pinctrl.dtsi"
  10 #include "rk3288-clocks.dtsi"
  11
  12 / {
  13         compatible = "rockchip,rk3288";
  14         rockchip,sram = <&sram>;
  15         interrupt-parent = <&gic>;
  16
  17         aliases {
  18                 serial0 = &uart_bt;
  19                 serial1 = &uart_bb;
  20                 serial2 = &uart_dbg;
  21                 serial3 = &uart_gps;
  22                 serial4 = &uart_exp;
  23                 i2c0 = &i2c0;
  24                 i2c1 = &i2c1;
  25                 i2c2 = &i2c2;
  26                 i2c3 = &i2c3;
  27                 i2c4 = &i2c4;
  28                 i2c5 = &i2c5;
  29                 lcdc0 = &lcdc0;
  30                 lcdc1 = &lcdc1;
  31                 spi0 = &spi0;
  32                 spi1 = &spi1;
  33                 spi2 = &spi2;
  34         };
  35
  36         cpus {
  37                 #address-cells = <1>;
  38                 #size-cells = <0>;
  39
  40                 cpu@0 {
  41                         device_type = "cpu";
  42                         compatible = "arm,cortex-a15";
  43                         reg = <0x500>;
  44                 };
  45                 cpu@1 {
  46                         device_type = "cpu";
  47                         compatible = "arm,cortex-a15";
  48                         reg = <0x501>;
  49                 };
  50                 cpu@2 {
  51                         device_type = "cpu";
  52                         compatible = "arm,cortex-a15";
  53                         reg = <0x502>;
  54                 };
  55                 cpu@3 {
  56                         device_type = "cpu";
  57                         compatible = "arm,cortex-a15";
  58                         reg = <0x503>;
  59                 };
  60         };
  61
  62         gic: interrupt-controller@ffc01000 {
  63                 compatible = "arm,cortex-a15-gic";
  64                 interrupt-controller;
  65                 #interrupt-cells = <3>;
  66                 #address-cells = <0>;
  67                 reg = <0xffc01000 0x1000>,
  68                       <0xffc02000 0x1000>;
  69         };
  70
  71         arm-pmu {
  72                 compatible = "arm,cortex-a12-pmu";
  73                 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
  74                              <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
  75                              <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
  76                              <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
  77         };
  78
  79         cpu_axi_bus: cpu_axi_bus {
  80                 compatible = "rockchip,cpu_axi_bus";
  81                 #address-cells = <1>;
  82                 #size-cells = <1>;
  83                 ranges;
  84
  85                 qos {
  86                         #address-cells = <1>;
  87                         #size-cells = <1>;
  88                         ranges;
  89                         /* service core */
  90                         cpup {
  91                                 reg = <0xffa80000 0x20>;
  92                         };
  93                         cpum_r {
  94                                 reg = <0xffa80080 0x20>;
  95                         };
  96                         cpum_w {
  97                                 reg = <0xffa80100 0x20>;
  98                         };
  99                         /* service dmac */
 100                         bus_dmac {
 101                                 reg = <0xffa90000 0x20>;
 102                         };
 103                         host {
 104                                 reg = <0xffa90080 0x20>;
 105                         };
 106                         crypto {
 107                                 reg = <0xffa90100 0x20>;
 108                         };
 109                         ccp {
 110                                 reg = <0xffa90180 0x20>;
 111                         };
 112                         ccs {
 113                                 reg = <0xffa90200 0x20>;
 114                         };
 115                         /* service gpu */
 116                         gpu_r {
 117                                 reg = <0xffaa0000 0x20>;
 118                         };
 119                         gpu_w {
 120                                 reg = <0xffaa0080 0x20>;
 121                         };
 122                         /* service peri */
 123                         peri {
 124                                 reg = <0xffab0000 0x20>;
 125                         };
 126                         /* service vio */
 127                         vio1_vop {
 128                                 reg = <0xffad0000 0x20>;
 129                                 rockchip,priority = <2 2>;
 130                         };
 131                         vio1_isp_w0 {
 132                                 reg = <0xffad0100 0x20>;
 133                                 rockchip,priority = <2 2>;
 134                         };
 135                         vio1_isp_w1 {
 136                                 reg = <0xffad0180 0x20>;
 137                         };
 138                         vio0_vop {
 139                                 reg = <0xffad0400 0x20>;
 140                                 rockchip,priority = <2 2>;
 141                         };
 142                         vio0_vip {
 143                                 reg = <0xffad0480 0x20>;
 144                         };
 145                         vio0_iep {
 146                                 reg = <0xffad0500 0x20>;
 147                         };
 148                         vio2_rga_r {
 149                                 reg = <0xffad0800 0x20>;
 150                         };
 151                         vio2_rga_w {
 152                                 reg = <0xffad0880 0x20>;
 153                         };
 154                         vio1_isp_r {
 155                                 reg = <0xffad0900 0x20>;
 156                         };
 157                         /* service video */
 158                         video {
 159                                 reg = <0xffae0000 0x20>;
 160                         };
 161                         /* service hevc */
 162                         hevc_r {
 163                                 reg = <0xffaf0000 0x20>;
 164                         };
 165                         hevc_w {
 166                                 reg = <0xffaf0080 0x20>;
 167                         };
 168                 };
 169
 170                 msch {
 171                         #address-cells = <1>;
 172                         #size-cells = <1>;
 173                         ranges;
 174
 175                         msch@0 {
 176                                 reg = <0xffac0000 0x40>;
 177                                 rockchip,read-latency = <0x34>;
 178                         };
 179                         msch@1 {
 180                                 reg = <0xffac0080 0x40>;
 181                                 rockchip,read-latency = <0x34>;
 182                         };
 183                 };
 184         };
 185
 186         sram: sram@ff710000 {
 187                 compatible = "mmio-sram";
 188                 reg = <0xff710000 0x8000>; /* 32k */
 189                 map-exec;
 190         };
 191
 192         timer {
 193                 compatible = "arm,armv7-timer";
 194                 interrupts = <GIC_PPI 13
 195                               (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 196                              <GIC_PPI 14
 197                               (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 198                 clock-frequency = <24000000>;
 199         };
 200
 201         timer@ff810000 {
 202                 compatible = "rockchip,timer";
 203                 reg = <0xff810000 0x20>;
 204                 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
 205                 rockchip,broadcast = <1>;
 206         };
 207
 208         watchdog: wdt@2004c000 {
 209                 compatible = "rockchip,watch dog";
 210                 reg = <0xff800000 0x100>;
 211                 clocks = <&pclk_pd_alive>;
 212                 clock-names = "pclk_wdt";
 213                 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
 214                 rockchip,irq = <1>;
 215                 rockchip,timeout = <60>;
 216                 rockchip,atboot = <1>;
 217                 rockchip,debug = <0>;
 218                 status = "disabled";
 219         };
 220
 221         amba {
 222                 #address-cells = <1>;
 223                 #size-cells = <1>;
 224                 compatible = "arm,amba-bus";
 225                 interrupt-parent = <&gic>;
 226                 ranges;
 227
 228                 pdma0: pdma@ffb20000 {
 229                         compatible = "arm,pl330", "arm,primecell";
 230                         reg = <0xffb20000 0x4000>;
 231                         clocks = <&clk_gates10 12>;
 232                         clock-names = "apb_pclk";
 233                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 234                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 235                         #dma-cells = <1>;
 236                 };
 237
 238                 pdma1: pdma@ff250000 {
 239                         compatible = "arm,pl330", "arm,primecell";
 240                         reg = <0xff250000 0x4000>;
 241                         clocks = <&clk_gates6 3>;
 242                         clock-names = "apb_pclk";
 243                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
 244                                      <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 245                         #dma-cells = <1>;
 246                 };
 247         };
 248
 249         reset: reset@ff7601b8{
 250                 compatible = "rockchip,reset";
 251                 reg = <0xff7601b8 0x30>;
 252                 rockchip,reset-flag = <ROCKCHIP_RESET_HIWORD_MASK>;
 253                 #reset-cells = <1>;
 254         };
 255
 256         nandc0: nandc@0xff400000 {
 257                 compatible = "rockchip,rk-nandc";
 258                 reg = <0xff400000 0x4000>;
 259                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 260                 nandc_id = <0>;
 261                 clocks = <&clk_nandc0>, <&clk_gates5 5>, <&clk_gates7 14>;
 262                 clock-names = "clk_nandc", "g_clk_nandc", "hclk_nandc";
 263         };
 264
 265         nandc1: nandc@0xff410000 {
 266             compatible = "rockchip,rk-nandc";
 267                 reg = <0xff410000 0x4000>;
 268                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 269                 nandc_id = <1>;
 270                 clocks = <&clk_nandc1>, <&clk_gates5 6>, <&clk_gates7 15>;
 271                 clock-names = "clk_nandc", "g_clk_nandc", "hclk_nandc";
 272         };
 273
 274         nandc0reg: nandc0@0xff400000 {
 275                 compatible = "rockchip,rk-nandc";
 276                 reg = <0xff400000 0x4000>;
 277         };
 278
 279         emmc: rksdmmc@ff0f0000 {
 280                 compatible = "rockchip,rk_mmc", "rockchip,rk32xx-sdmmc";
 281                 reg = <0xff0f0000 0x4000>;
 282                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 283                 #address-cells = <1>;
 284                 #size-cells = <0>;
 285                 //pinctrl-names = "default",,"suspend";
 286                 //pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_wp &sd0_pwr
 287                 //              &sd0_bus1 &sd0_bus4>;
 288                 clocks = <&clk_emmc>, <&clk_gates8 6>;
 289                 clock-names = "clk_mmc", "hclk_mmc";
 290                 num-slots = <1>;
 291                 fifo-depth = <0x100>;
 292                 bus-width = <8>;
 293                 tune_regsbase = <0x218>;
 294                 cru_regsbase = <0x1d8>;
 295                 cru_reset_offset = <3>;
 296         };
 297
 298         sdmmc: rksdmmc@ff0c0000 {
 299                 compatible = "rockchip,rk_mmc", "rockchip,rk32xx-sdmmc";
 300                 reg = <0xff0c0000 0x4000>;
 301                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 302                 #address-cells = <1>;
 303                 #size-cells = <0>;
 304                 pinctrl-names = "default", "idle";
 305                 pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_dectn
 306                              &sdmmc0_bus4>;
 307                 pinctrl-1 = <&sdmmc0_gpio>;
 308                 cd-gpios = <&gpio6 GPIO_C6 GPIO_ACTIVE_HIGH>;/*CD GPIO*/
 309                 clocks = <&clk_sdmmc>, <&clk_gates8 3>;
 310                 clock-names = "clk_mmc", "hclk_mmc";
 311                 num-slots = <1>;
 312                 fifo-depth = <0x100>;
 313                 bus-width = <4>;
 314                 tune_regsbase = <0x200>;
 315                 cru_regsbase = <0x1d8>;
 316                 cru_reset_offset = <0>;
 317         };
 318
 319         sdio: rksdmmc@ff0d0000 {
 320                 compatible = "rockchip,rk_mmc", "rockchip,rk32xx-sdmmc";
 321                 reg = <0xff0d0000 0x4000>;
 322                 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 323                 #address-cells = <1>;
 324                 #size-cells = <0>;
 325                 pinctrl-names = "default","idle";
 326                 pinctrl-0 = <&sdio0_clk &sdio0_cmd &sdio0_wrprt &sdio0_pwr
 327                              &sdio0_bkpwr &sdio0_intn &sdio0_bus4>;
 328                 pinctrl-1 = <&sdio0_gpio>;
 329                 clocks = <&clk_sdio0>, <&clk_gates8 4>;
 330                 clock-names = "clk_mmc", "hclk_mmc";
 331                 num-slots = <1>;
 332                 fifo-depth = <0x100>;
 333                 bus-width = <4>;
 334                 tune_regsbase = <0x208>;
 335                 cru_regsbase = <0x1d8>;
 336                 cru_reset_offset = <1>;
 337         };
 338
 339         sdio1: rksdmmc@ff0e0000 {
 340                 compatible = "rockchip,rk_mmc", "rockchip,rk32xx-sdmmc";
 341                 reg = <0xff0e0000 0x4000>;
 342                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 343                 #address-cells = <1>;
 344                 #size-cells = <0>;
 345                 //pinctrl-names = "default","suspend";
 346                 //pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_cd
 347                 //          &sd1_wp &sd1_bus1 &sd1_bus4>;
 348
 349                 /* gate8_0 --hclk_sdmmc_ahb_arbi_gate_en,
 350                  * gate13_2 --clk_sdio1_src_gate_en
 351                  */
 352                 clocks = <&clk_sdio1>, <&clk_gates8 5>;
 353                 clock-names = "clk_mmc", "hclk_mmc";
 354                 num-slots = <1>;
 355                 fifo-depth = <0x100>;
 356                 bus-width = <4>;
 357                 cru_regsbase = <0x1d8>;
 358                 cru_reset_offset = <2>;
 359                 status = "disabled";
 360         };
 361
 362         spi0: spi@ff110000 {
 363                 compatible = "rockchip,rockchip-spi";
 364                 reg = <0xff110000 0x1000>;
 365                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 366                 #address-cells = <1>;
 367                 #size-cells = <0>;
 368                 pinctrl-names = "default";
 369                 pinctrl-0 = <&spi0_txd &spi0_rxd &spi0_clk &spi0_cs0 &spi0_cs1>;
 370                 rockchip,spi-src-clk = <0>;
 371                 num-cs = <2>;
 372                 clocks =<&clk_spi0>, <&clk_gates6 4>;
 373                 clock-names = "spi","pclk_spi0";
 374                 dmas = <&pdma1 11>, <&pdma1 12>;
 375                 #dma-cells = <2>;
 376                 dma-names = "tx", "rx";
 377                 status = "disabled";
 378         };
 379
 380         spi1: spi@ff120000 {
 381                 compatible = "rockchip,rockchip-spi";
 382                 reg = <0xff120000 0x1000>;
 383                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 384                 #address-cells = <1>;
 385                 #size-cells = <0>;
 386                 pinctrl-names = "default";
 387                 pinctrl-0 = <&spi1_txd &spi1_rxd &spi1_clk &spi1_cs0>;
 388                 rockchip,spi-src-clk = <1>;
 389                 num-cs = <1>;
 390                 clocks = <&clk_spi1>, <&clk_gates6 5>;
 391                 clock-names = "spi","pclk_spi1";
 392                 dmas = <&pdma1 13>, <&pdma1 14>;
 393                 #dma-cells = <2>;
 394                 dma-names = "tx", "rx";
 395                 status = "disabled";
 396         };
 397
 398         spi2: spi@ff130000 {
 399                 compatible = "rockchip,rockchip-spi";
 400                 reg = <0xff130000 0x1000>;
 401                 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 402                 #address-cells = <1>;
 403                 #size-cells = <0>;
 404                 pinctrl-names = "default";
 405                 pinctrl-0 = <&spi2_txd &spi2_rxd &spi2_clk &spi2_cs0 &spi2_cs1>;
 406                 rockchip,spi-src-clk = <2>;
 407                 num-cs = <2>;
 408                 clocks = <&clk_spi2>, <&clk_gates6 6>;
 409                 clock-names = "spi","pclk_spi2";
 410                 dmas = <&pdma1 15>, <&pdma1 16>;
 411                 #dma-cells = <2>;
 412                 dma-names = "tx", "rx";
 413                 status = "disabled";
 414         };
 415
 416         uart_bt: serial@ff180000 {
 417                 compatible = "rockchip,serial";
 418                 reg = <0xff180000 0x100>;
 419                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 420                 clock-frequency = <24000000>;
 421                 clocks = <&clk_uart0>, <&clk_gates6 8>;
 422                 clock-names = "sclk_uart", "pclk_uart";
 423                 reg-shift = <2>;
 424                 reg-io-width = <4>;
 425                 dmas = <&pdma1 1>, <&pdma1 2>;
 426                 #dma-cells = <2>;
 427                 pinctrl-names = "default";
 428                 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
 429                 status = "disabled";
 430         };
 431
 432         uart_bb: serial@ff190000 {
 433                 compatible = "rockchip,serial";
 434                 reg = <0xff190000 0x100>;
 435                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 436                 clock-frequency = <24000000>;
 437                 clocks = <&clk_uart1>, <&clk_gates6 9>;
 438                 clock-names = "sclk_uart", "pclk_uart";
 439                 reg-shift = <2>;
 440                 reg-io-width = <4>;
 441                 dmas = <&pdma1 3>, <&pdma1 4>;
 442                 #dma-cells = <2>;
 443                 pinctrl-names = "default";
 444                 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
 445                 status = "disabled";
 446         };
 447
 448         uart_dbg: serial@ff690000 {
 449                 compatible = "rockchip,serial";
 450                 reg = <0xff690000 0x100>;
 451                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 452                 clock-frequency = <24000000>;
 453                 clocks = <&clk_uart2>, <&clk_gates11 9>;
 454                 clock-names = "sclk_uart", "pclk_uart";
 455                 reg-shift = <2>;
 456                 reg-io-width = <4>;
 457                 dmas = <&pdma0 4>, <&pdma0 5>;
 458                 #dma-cells = <2>;
 459                 pinctrl-names = "default";
 460                 pinctrl-0 = <&uart2_xfer>;
 461                 status = "disabled";
 462         };
 463
 464         uart_gps: serial@ff1b0000 {
 465                 compatible = "rockchip,serial";
 466                 reg = <0xff1b0000 0x100>;
 467                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 468                 clock-frequency = <24000000>;
 469                 clocks = <&clk_uart3>, <&clk_gates6 11>;
 470                 clock-names = "sclk_uart", "pclk_uart";
 471                 current-speed = <115200>;
 472                 reg-shift = <2>;
 473                 reg-io-width = <4>;
 474                 dmas = <&pdma1 7>, <&pdma1 8>;
 475                 #dma-cells = <2>;
 476                 pinctrl-names = "default";
 477                 pinctrl-0 = <&uart3_xfer &uart3_cts &uart3_rts>;
 478                 status = "disabled";
 479         };
 480
 481         uart_exp: serial@ff1c0000 {
 482                 compatible = "rockchip,serial";
 483                 reg = <0xff1c0000 0x100>;
 484                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 485                 clock-frequency = <24000000>;
 486                 clocks = <&clk_uart4>, <&clk_gates6 12>;
 487                 clock-names = "sclk_uart", "pclk_uart";
 488                 reg-shift = <2>;
 489                 reg-io-width = <4>;
 490                 dmas = <&pdma1 9>, <&pdma1 10>;
 491                 #dma-cells = <2>;
 492                 pinctrl-names = "default";
 493                 pinctrl-0 = <&uart4_xfer &uart4_cts &uart4_rts>;
 494                 status = "disabled";
 495         };
 496
 497         fiq-debugger {
 498                 compatible = "rockchip,fiq-debugger";
 499                 rockchip,serial-id = <2>;
 500                 rockchip,signal-irq = <106>;
 501                 rockchip,wake-irq = <0>;
 502                 status = "disabled";
 503         };
 504
 505         rockchip_clocks_init: clocks-init{
 506                 compatible = "rockchip,clocks-init";
 507                 rockchip,clocks-init-parent =
 508                         <&clk_core &clk_apll>,  <&aclk_bus_src &clk_gpll>,
 509                         <&aclk_peri &clk_gpll>, <&uart_pll_mux &clk_gpll>,
 510                         <&clk_i2s_pll &clk_gpll>, <&clk_spdif_pll &clk_gpll>,
 511                         <&usbphy_480m &otgphy2_480m>;
 512                 rockchip,clocks-init-rate =
 513                         <&clk_core 792000000>, <&clk_gpll 594000000>,
 514                         /*<&clk_cpll 47000000>,*/ <&clk_npll 1250000000>,
 515                         <&aclk_bus_src 300000000>, <&aclk_bus 300000000>,
 516                         <&hclk_bus 150000000>, <&pclk_bus 75000000>,
 517                         <&clk_crypto 150000000>, <&aclk_peri 300000000>,
 518                         <&hclk_peri 150000000>, <&pclk_peri 75000000>,
 519                         <&clk_gpu 200000000>, /*<&aclk_vio0 300000000>,
 520                         <&aclk_vio1 300000000>, <&hclk_vio 75000000>,*/
 521                         <&pclk_pd_alive 100000000>, <&pclk_pd_pmu 100000000>,
 522                         <&aclk_hevc 400000000>, <&hclk_hevc 200000000>,
 523                         <&clk_hevc_cabac 300000000>, <&clk_hevc_core 300000000>,
 524                         <&aclk_rga 300000000>, <&clk_rga 300000000>,
 525                         <&clk_vepu 300000000>, <&clk_vdpu 300000000>,
 526                         <&clk_edp 200000000>, <&clk_isp 200000000>,
 527                         <&clk_isp_jpe 400000000>, <&clk_tsp 80000000>,
 528                         <&clk_tspout 80000000>, <&clk_mac 125000000>;
 529                 /* rockchip,clocks-uboot-has-init = <&aclk_vio0>; */
 530         };
 531
 532         clocks-enable {
 533                 compatible = "rockchip,clocks-enable";
 534                 clocks =
 535                                 /* PLL */
 536                                 <&clk_dpll>, <&clk_gpll>,
 537
 538                                 /* PD_CORE */
 539                                 <&clk_gates0 2>, <&clk_core0>,
 540                                 <&clk_core1>, <&clk_core2>,
 541                                 <&clk_core3>, <&clk_l2ram>,
 542                                 <&aclk_core_m0>, <&aclk_core_mp>,
 543                                 <&atclk_core>, <&pclk_dbg_src>,
 544                                 <&clk_gates12 9>, <&clk_gates12 10>,
 545                                 <&clk_gates12 11>,
 546
 547                                 /* PD_BUS */
 548                                 <&aclk_bus>, <&clk_gates0 3>,
 549                                 <&hclk_bus>, <&pclk_bus>,
 550                                 <&clk_gates13 8>,
 551                                 <&clk_gates0 7>,
 552
 553                                 /* TIMER */
 554                                 <&clk_gates1 0>, <&clk_gates1 1>,
 555                                 <&clk_gates1 2>, <&clk_gates1 3>,
 556                                 <&clk_gates1 4>, <&clk_gates1 5>,
 557
 558                                 <&pclk_pd_alive>, <&pclk_pd_pmu>,
 559
 560                                 /* PD_PERI */
 561                                 <&aclk_peri>, <&hclk_peri>,
 562                                 <&pclk_peri>,
 563
 564                                 /* JTAG */
 565                                 /* <&clk_gates4 14>, */
 566
 567                                 /* aclk_bus */
 568                                 <&clk_gates10 5>,/* aclk_intmem0 */
 569                                 <&clk_gates10 6>,/* aclk_intmem1 */
 570                                 <&clk_gates10 7>,/* aclk_intmem2 */
 571                                 /* <&clk_gates10 12>, */ /* aclk_dma1 */
 572                                 <&clk_gates10 13>,/* aclk_strc_sys */
 573                                 <&clk_gates10 4>,/* aclk_intmem */
 574
 575                                 /* hclk_bus */
 576                                 <&clk_gates10 9>,/* hclk_rom */
 577
 578                                 /* pclk_bus */
 579                                 <&clk_gates10 1>,/* pclk_timer */
 580                                 <&clk_gates10 9>,/* rom */
 581                                 <&clk_gates10 13>,/* aclk strc */
 582
 583                                 <&clk_gates12 8>,/* aclk strc */
 584
 585                                 /* aclk_peri */
 586                                 <&clk_gates6 2>,/* aclk_peri_axi_matrix */
 587                                 /* <&clk_gates6 3>, */ /* aclk_dmac2 */
 588                                 <&clk_gates7 11>,/* aclk_peri_niu */
 589                                 <&clk_gates8 12>,/* aclk_peri_mmu */
 590
 591                                 /* hclk_peri */
 592                                 <&clk_gates6 0>,/* hclk_peri_matrix */
 593                                 <&clk_gates7 10>,/* hclk_peri_ahb_arbi */
 594                                 <&clk_gates7 12>,/* hclk_emem_peri */
 595                                 <&clk_gates7 13>,/* hclk_mem_peri */
 596
 597                                 /* pclk_peri */
 598                                 <&clk_gates6 1>,/* pclk_peri_axi_matrix */
 599
 600                                 /* pclk_pd_alive */
 601                                 <&clk_gates14 11>,/* pclk_grf */
 602                                 <&clk_gates14 12>,/* pclk_alive_niu */
 603
 604                                 /* pclk_pd_pmu */
 605                                 <&clk_gates17 0>,/* pclk_pmu */
 606                                 <&clk_gates17 1>,/* pclk_intmem1 */
 607                                 <&clk_gates17 2>,/* pclk_pmu_niu */
 608                                 <&clk_gates17 3>,/* pclk_sgrf */
 609
 610                                 /* UART */
 611                                 <&clk_gates11 9>,/* pclk_uart2 */
 612
 613                                 /* 480M */
 614                                 <&usbphy_480m>;
 615         };
 616
 617         i2c0: i2c@ff650000 {
 618                 compatible = "rockchip,rk30-i2c";
 619                 reg = <0xff650000 0x1000>;
 620                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 621                 #address-cells = <1>;
 622                 #size-cells = <0>;
 623                 pinctrl-names = "default", "gpio";
 624                 pinctrl-0 = <&i2c0_sda &i2c0_scl>;
 625                 pinctrl-1 = <&i2c0_gpio>;
 626                 gpios = <&gpio0 GPIO_B7 GPIO_ACTIVE_LOW>,
 627                         <&gpio0 GPIO_C0 GPIO_ACTIVE_LOW>;
 628                 clocks = <&clk_gates10 2>;
 629                 rockchip,check-idle = <1>;
 630                 status = "disabled";
 631         };
 632
 633         i2c1: i2c@ff140000 {
 634                 compatible = "rockchip,rk30-i2c";
 635                 reg = <0xff140000 0x1000>;
 636                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 637                 #address-cells = <1>;
 638                 #size-cells = <0>;
 639                 pinctrl-names = "default", "gpio";
 640                 pinctrl-0 = <&i2c1_sda &i2c1_scl>;
 641                 pinctrl-1 = <&i2c1_gpio>;
 642                 gpios = <&gpio8 GPIO_A4 GPIO_ACTIVE_LOW>,
 643                         <&gpio8 GPIO_A5 GPIO_ACTIVE_LOW>;
 644                 clocks = <&clk_gates6 13>;
 645                 rockchip,check-idle = <1>;
 646                 status = "disabled";
 647         };
 648
 649         i2c2: i2c@ff660000 {
 650                 compatible = "rockchip,rk30-i2c";
 651                 reg = <0xff660000 0x1000>;
 652                 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 653                 #address-cells = <1>;
 654                 #size-cells = <0>;
 655                 pinctrl-names = "default", "gpio";
 656                 pinctrl-0 = <&i2c2_sda &i2c2_scl>;
 657                 pinctrl-1 = <&i2c2_gpio>;
 658                 gpios = <&gpio6 GPIO_B1 GPIO_ACTIVE_LOW>,
 659                         <&gpio6 GPIO_B2 GPIO_ACTIVE_LOW>;
 660                 clocks = <&clk_gates10 3>;
 661                 rockchip,check-idle = <1>;
 662                 status = "disabled";
 663         };
 664
 665         i2c3: i2c@ff150000 {
 666                 compatible = "rockchip,rk30-i2c";
 667                 reg = <0xff150000 0x1000>;
 668                 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 669                 #address-cells = <1>;
 670                 #size-cells = <0>;
 671                 pinctrl-names = "default", "gpio";
 672                 pinctrl-0 = <&i2c3_sda &i2c3_scl>;
 673                 pinctrl-1 = <&i2c3_gpio>;
 674                 gpios = <&gpio2 GPIO_C1 GPIO_ACTIVE_LOW>,
 675                         <&gpio2 GPIO_C0 GPIO_ACTIVE_LOW>;
 676                 clocks = <&clk_gates6 14>;
 677                 rockchip,check-idle = <1>;
 678                 status = "disabled";
 679         };
 680
 681         i2c4: i2c@ff160000 {
 682                 compatible = "rockchip,rk30-i2c";
 683                 reg = <0xff160000 0x1000>;
 684                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 685                 #address-cells = <1>;
 686                 #size-cells = <0>;
 687                 pinctrl-names = "default", "gpio";
 688                 pinctrl-0 = <&i2c4_sda &i2c4_scl>;
 689                 pinctrl-1 = <&i2c4_gpio>;
 690                 gpios = <&gpio7 GPIO_C1 GPIO_ACTIVE_LOW>,
 691                         <&gpio7 GPIO_C2 GPIO_ACTIVE_LOW>;
 692                 clocks = <&clk_gates6 15>;
 693                 rockchip,check-idle = <1>;
 694                 status = "disabled";
 695         };
 696
 697         i2c5: i2c@ff170000 {
 698                 compatible = "rockchip,rk30-i2c";
 699                 reg = <0xff170000 0x1000>;
 700                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 701                 #address-cells = <1>;
 702                 #size-cells = <0>;
 703                 pinctrl-names = "default", "gpio";
 704                 pinctrl-0 = <&i2c5_sda &i2c5_scl>;
 705                 pinctrl-1 = <&i2c5_gpio>;
 706                 gpios = <&gpio7 GPIO_C3 GPIO_ACTIVE_LOW>,
 707                         <&gpio7 GPIO_C4 GPIO_ACTIVE_LOW>;
 708                 clocks = <&clk_gates7 0>;
 709                 rockchip,check-idle = <1>;
 710                 status = "disabled";
 711         };
 712
 713         fb: fb{
 714                 compatible = "rockchip,rk-fb";
 715                 rockchip,disp-mode = <DUAL>;
 716         };
 717
 718         rk_screen: rk_screen{
 719                         compatible = "rockchip,screen";
 720         };
 721
 722         dsihost0: mipi@ff960000{
 723                 compatible = "rockchip,rk32-dsi";
 724                 rockchip,prop = <0>;
 725                 reg = <0xff960000 0x4000>;
 726                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 727                 clocks = <&clk_gates5 15>, <&clk_gates16 4> , <&pd_mipidsi>;
 728                 clock-names = "clk_mipi_24m", "pclk_mipi_dsi", "pd_mipi_dsi";
 729                 status = "disabled";
 730         };
 731
 732         dsihost1: mipi@ff964000{
 733                 compatible = "rockchip,rk32-dsi";
 734                 rockchip,prop = <1>;
 735                 reg = <0xff964000 0x4000>;
 736                 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 737                 clocks = <&clk_gates5 15>, <&clk_gates16 5>, <&pd_mipidsi>;
 738                 clock-names = "clk_mipi_24m", "pclk_mipi_dsi", "pd_mipi_dsi";
 739                 status = "disabled";
 740         };
 741
 742         lvds: lvds@ff96c000 {
 743                 compatible = "rockchip,rk32-lvds";
 744                 reg = <0xff96c000 0x4000>;
 745                 clocks = <&clk_gates16 7>;
 746                 clock-names = "pclk_lvds";
 747         };
 748
 749         edp: edp@ff970000 {
 750                 compatible = "rockchip,rk32-edp";
 751                 reg = <0xff970000 0x4000>;
 752                 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
 753                 clocks = <&clk_edp>, <&clk_edp_24m>, <&clk_gates16 8>;
 754                 clock-names = "clk_edp", "clk_edp_24m", "pclk_edp";
 755         };
 756
 757         hdmi: hdmi@ff980000 {
 758                 compatible = "rockchip,rk3288-hdmi";
 759                 reg = <0xff980000 0x20000>;
 760                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
 761                 pinctrl-names = "default", "sleep";
 762                 pinctrl-0 = <&i2c5_sda &i2c5_scl &hdmi_cec>;
 763                 pinctrl-1 = <&i2c5_gpio>;
 764                 clocks = <&clk_gates16 9>, <&clk_gates5 12>, <&clk_gates5 11>;
 765                 clock-names = "pclk_hdmi", "hdcp_clk_hdmi", "cec_clk_hdmi";
 766                 rockchip,hdmi_video_source = <DISPLAY_SOURCE_LCDC0>;
 767                 rockchip,hdmi_audio_source = <0>;
 768                 rockchip,hdcp_enable = <0>;
 769                 rockchip,cec_enable = <0>;
 770                 status = "disabled";
 771         };
 772
 773         lcdc0: lcdc@ff930000 {
 774                 compatible = "rockchip,rk3288-lcdc";
 775                 rockchip,prop = <PRMRY>;
 776                 rockchip,pwr18 = <0>;
 777                 rockchip,iommu-enabled = <0>;
 778                 reg = <0xff930000 0x10000>;
 779                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 780                 pinctrl-names = "default", "gpio";
 781                 pinctrl-0 = <&lcdc0_lcdc>;
 782                 pinctrl-1 = <&lcdc0_gpio>;
 783                 status = "disabled";
 784                 clocks = <&clk_gates15 5>, <&dclk_lcdc0>, <&clk_gates15 6>,
 785                          <&pd_vop0>;
 786                 clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc", "pd_lcdc";
 787         };
 788
 789         lcdc1: lcdc@ff940000 {
 790                 compatible = "rockchip,rk3288-lcdc";
 791                 rockchip,prop = <EXTEND>;
 792                 rockchip,pwr18 = <0>;
 793                 rockchip,iommu-enabled = <0>;
 794                 reg = <0xff940000 0x10000>;
 795                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 796                 status = "disabled";
 797                 clocks = <&clk_gates15 7>, <&dclk_lcdc1>, <&clk_gates15 8>,
 798                          <&pd_vop1>;
 799                 clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc", "pd_lcdc";
 800         };
 801
 802         adc: adc@ff100000 {
 803                 compatible = "rockchip,saradc";
 804                 reg = <0xff100000 0x100>;
 805                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 806                 #io-channel-cells = <1>;
 807                 io-channel-ranges;
 808                 rockchip,adc-vref = <1800>;
 809                 clock-frequency = <1000000>;
 810                 clocks = <&clk_saradc>, <&clk_gates7 1>;
 811                 clock-names = "saradc", "pclk_saradc";
 812                 status = "disabled";
 813         };
 814
 815         rga@ff920000 {
 816                 compatible = "rockchip,rga2";
 817                 reg = <0xff920000 0x1000>;
 818                 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
 819                 clocks = <&clk_gates15 1>, <&aclk_rga>, <&clk_rga>;
 820                 clock-names = "hclk_rga", "aclk_rga", "clk_rga";
 821         };
 822
 823         i2s: rockchip-i2s@0xff890000 {
 824                 compatible = "rockchip-i2s";
 825                 reg = <0xff890000 0x10000>;
 826                 i2s-id = <0>;
 827                 clocks = <&clk_i2s>, <&clk_i2s_out>, <&clk_gates10 8>;
 828                 clock-names = "i2s_clk","i2s_mclk", "i2s_hclk";
 829                 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 830                 dmas = <&pdma0 0>, <&pdma0 1>;
 831                 //#dma-cells = <2>;
 832                 dma-names = "tx", "rx";
 833                 pinctrl-names = "default", "sleep";
 834                 pinctrl-0 = <&i2s_mclk &i2s_sclk &i2s_lrckrx &i2s_lrcktx
 835                              &i2s_sdi &i2s_sdo0 &i2s_sdo1 &i2s_sdo2 &i2s_sdo3>;
 836                 pinctrl-1 = <&i2s_gpio>;
 837         };
 838
 839         spdif: rockchip-spdif@0xff8b0000 {
 840                 compatible = "rockchip-spdif";
 841                 reg = <0xff8b0000 0x10000>;//8channel
 842                 //reg = <ff880000 0x10000>;//2channel
 843                 clocks = <&clk_spdif>, <&clk_spdif_8ch>,<&clk_gates10 11>;
 844                 clock-names = "spdif_mclk","spdif_8ch_mclk","spdif_hclk";
 845                 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 846                 dmas = <&pdma0 3>;
 847                 //dmas = <&pdma0 2>; //2channel
 848                 //#dma-cells = <1>;
 849                 dma-names = "tx";
 850                 pinctrl-names = "default";
 851                 pinctrl-0 = <&spdif_tx>;
 852         };
 853
 854         vop1pwm: pwm@ff9401a0 {
 855                 compatible = "rockchip,vop-pwm";
 856                 reg = <0xff9401a0 0x10>;
 857
 858                 #pwm-cells = <2>;
 859                 pinctrl-names = "default";
 860                 pinctrl-0 = <&vop1_pwm_pin>;
 861                 clocks = <&clk_gates13 11>, <&clk_gates15 7>, <&clk_gates15 8>;
 862                 clock-names = "pclk_pwm", "aclk_lcdc", "hclk_lcdc";
 863                 status = "disabled";
 864         };
 865
 866         vop0pwm: pwm@ff9301a0 {
 867                 compatible = "rockchip,vop-pwm";
 868                 reg = <0xff9301a0 0x10>;
 869
 870                 #pwm-cells = <2>;
 871                 pinctrl-names = "default";
 872                 pinctrl-0 = <&vop0_pwm_pin>;
 873                 clocks = <&clk_gates13 10>, <&clk_gates15 5>, <&clk_gates15 6>;
 874                 clock-names = "pclk_pwm", "aclk_lcdc", "hclk_lcdc";
 875                 status = "disabled";
 876         };
 877
 878         pwm0: pwm@ff680000 {
 879                 compatible = "rockchip,rk-pwm";
 880                 reg = <0xff680000 0x10>;
 881
 882                 /* used by driver on remotectl'pwm */
 883                 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
 884                 #pwm-cells = <2>;
 885                 pinctrl-names = "default";
 886                 pinctrl-0 = <&pwm0_pin>;
 887                 clocks = <&clk_gates11 11>;
 888                 clock-names = "pclk_pwm";
 889                 status = "disabled";
 890         };
 891
 892         pwm1: pwm@ff680010 {
 893                 compatible = "rockchip,rk-pwm";
 894                 reg = <0xff680010 0x10>;
 895
 896                 /* used by driver on remotectl'pwm */
 897                 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
 898                 #pwm-cells = <2>;
 899                 pinctrl-names = "default";
 900                 pinctrl-0 = <&pwm1_pin>;
 901                 clocks = <&clk_gates11 11>;
 902                 clock-names = "pclk_pwm";
 903                 status = "disabled";
 904         };
 905
 906         pwm2: pwm@ff680020 {
 907                 compatible = "rockchip,rk-pwm";
 908                 reg = <0xff680020 0x10>;
 909
 910                 /* used by driver on remotectl'pwm */
 911                 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
 912                 #pwm-cells = <2>;
 913                 pinctrl-names = "default";
 914                 pinctrl-0 = <&pwm2_pin>;
 915                 clocks = <&clk_gates11 11>;
 916                 clock-names = "pclk_pwm";
 917                 status = "disabled";
 918         };
 919
 920         pwm3: pwm@ff680030 {
 921                 compatible = "rockchip,rk-pwm";
 922                 reg = <0xff680030 0x10>;
 923
 924                 /* used by driver on remotectl'pwm */
 925                 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
 926                 #pwm-cells = <2>;
 927                 pinctrl-names = "default";
 928                 pinctrl-0 = <&pwm3_pin>;
 929                 clocks = <&clk_gates11 11>;
 930                 clock-names = "pclk_pwm";
 931                 status = "disabled";
 932         };
 933
 934         dvfs {
 935                 vd_arm: vd_arm {
 936                         regulator_name = "vdd_arm";
 937                         suspend_volt = <1000>; //mV
 938                         pd_core {
 939                                 clk_core_dvfs_table: clk_core {
 940                                         operating-points = <
 941                                                 /* KHz uV */
 942                                                 312000 1100000
 943                                                 504000 1100000
 944                                                 816000 1100000
 945                                                 1008000 1100000
 946                                                 >;
 947
 948                                         channel = <0>;
 949                                         temp-limit-enable = <1>;
 950                                         target-temp = <80>;
 951                                         min_temp_limit = <48>;
 952
 953                                         normal-temp-limit = <
 954                                         /* delta-temp delta-freq */
 955                                                 3       96000
 956                                                 6       144000
 957                                                 9       192000
 958                                                 15      384000
 959                                                 >;
 960
 961                                         performance-temp-limit = <
 962                                                 /* temp freq */
 963                                                 100     816000
 964                                                 >;
 965
 966                                         regu-mode-table = <
 967                                                 /* freq mode */
 968                                                 1008000    4
 969                                                 0          3
 970                                                 >;
 971
 972                                         regu-mode-en = <0>;
 973                                         status = "okay";
 974                                 };
 975                         };
 976                 };
 977
 978                 vd_logic: vd_logic {
 979                         regulator_name = "vdd_logic";
 980                         suspend_volt = <1000>; //mV
 981                         pd_ddr {
 982                                 clk_ddr_dvfs_table: clk_ddr {
 983                                         operating-points = <
 984                                                 /* KHz uV */
 985                                                 200000 1200000
 986                                                 300000 1200000
 987                                                 400000 1200000
 988                                                 >;
 989
 990                                         bd-freq-table = <
 991                                                 /* bandwidth freq */
 992                                                 5000           800000
 993                                                 3500           456000
 994                                                 2600           396000
 995                                                 2000           324000
 996                                                 >;
 997
 998                                         channel = <2>;
 999                                         status = "disabled";
1000                                 };
1001                         };
1002
1003                         pd_vio {
1004                                 aclk_vio1_dvfs_table: aclk_vio1 {
1005                                         operating-points = <
1006                                                 /* KHz uV */
1007                                                 100000 1100000
1008                                                 500000 1100000
1009                                                 >;
1010
1011                                         status = "okay";
1012                                 };
1013                         };
1014                 };
1015
1016                 vd_gpu: vd_gpu {
1017                         regulator_name = "vdd_gpu";
1018                         suspend_volt = <1000>; //mV
1019                         pd_gpu {
1020                                 clk_gpu_dvfs_table: clk_gpu {
1021                                         operating-points = <
1022                                                 /* KHz uV */
1023                                                 200000 1200000
1024                                                 300000 1200000
1025                                                 400000 1200000
1026                                                 >;
1027
1028                                         channel = <1>;
1029                                         temp-limit-enable = <0>;
1030                                         target-temp = <90>;
1031                                         min_temp_limit = <200>;
1032
1033                                         normal-temp-limit = <
1034                                         /*delta-temp delta-freq*/
1035                                                 3       50000
1036                                                 6       150000
1037                                                 15      250000
1038                                                 >;
1039
1040                                         regu-mode-table = <
1041                                                 /*freq mode*/
1042                                                 200000     4
1043                                                 0          3
1044                                         >;
1045
1046                                         regu-mode-en = <0>;
1047                                         status = "okay";
1048                                 };
1049                         };
1050                 };
1051         };
1052
1053         ion {
1054                 compatible = "rockchip,ion";
1055                 #address-cells = <1>;
1056                 #size-cells = <0>;
1057
1058                 ion_drm: rockchip,ion-heap@5 {
1059                         compatible = "rockchip,ion-heap";
1060                         rockchip,ion_heap = <5>;
1061                         reg = <0x00000000 0x00000000>;
1062                 };
1063                 ion_cma: rockchip,ion-heap@4 {
1064                         /* CMA HEAP */
1065                         compatible = "rockchip,ion-heap";
1066                         rockchip,ion_heap = <4>;
1067                         reg = <0x00000000 0x28000000>; /* 640MB */
1068                 };
1069                 rockchip,ion-heap@0 {
1070                          /* VMALLOC HEAP */
1071                         compatible = "rockchip,ion-heap";
1072                         rockchip,ion_heap = <0>;
1073                 };
1074         };
1075
1076         vpu: vpu_service@ff9a0000 {
1077                 compatible = "vpu_service";
1078                 iommu_enabled = <0>;
1079                 reg = <0xff9a0000 0x800>;
1080                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
1081                              <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1082                 interrupt-names = "irq_enc", "irq_dec";
1083                 clocks = <&clk_vdpu>, <&hclk_vdpu>;
1084                 clock-names = "aclk_vcodec", "hclk_vcodec";
1085                 resets = <&reset RK3288_SOFT_RST_VCODEC_H>,
1086                          <&reset RK3288_SOFT_RST_VCODEC_A>;
1087                 reset-names = "video_h", "video_a";
1088                 name = "vpu_service";
1089                 dev_mode = <0>;
1090                 //status = "disabled";
1091         };
1092
1093         hevc: hevc_service@ff9c0000 {
1094                 compatible = "rockchip,hevc_service";
1095                 iommu_enabled = <0>;
1096                 reg = <0xff9c0000 0x800>;
1097                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
1098                 interrupt-names = "irq_dec";
1099                 clocks = <&aclk_hevc>, <&hclk_hevc>, <&clk_hevc_core>,
1100                          <&clk_hevc_cabac>;
1101                 clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core",
1102                               "clk_cabac";
1103                 resets = <&reset RK3288_SOFT_RST_VCODEC_H>,
1104                          <&reset RK3288_SOFT_RST_VCODEC_A>,
1105                          <&reset RK3288_SOFT_RST_HEVC>;
1106                 reset-names = "video_h", "video_a", "video";
1107                 dev_mode = <1>;
1108                 name = "hevc_service";
1109                 //status = "disabled";
1110         };
1111
1112         iep: iep@ff900000 {
1113                 compatible = "rockchip,iep";
1114                 iommu_enabled = <0>;
1115                 reg = <0xff900000 0x800>;
1116                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1117                 clocks = <&clk_gates15 2>, <&clk_gates15 3>;
1118                 clock-names = "aclk_iep", "hclk_iep";
1119                 status = "okay";
1120         };
1121
1122         dwc_control_usb: dwc-control-usb@ff770284 {
1123                 compatible = "rockchip,rk3288-dwc-control-usb";
1124                 reg = <0xff770284 0x04>, <0xff770288 0x04>,
1125                       <0xff7702cc 0x04>, <0xff7702d4 0x04>,
1126                       <0xff770320 0x14>, <0xff770334 0x14>,
1127                       <0xff770348 0x10>, <0xff770358 0x08>,
1128                       <0xff770360 0x08>;
1129                 reg-names = "GRF_SOC_STATUS1" ,"GRF_SOC_STATUS2",
1130                             "GRF_SOC_STATUS19", "GRF_SOC_STATUS21",
1131                             "GRF_UOC0_BASE", "GRF_UOC1_BASE",
1132                             "GRF_UOC2_BASE", "GRF_UOC3_BASE",
1133                             "GRF_UOC4_BASE";
1134
1135                 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
1136                              <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
1137                              <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
1138                              <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
1139                              <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
1140                 interrupt-names = "otg_id", "otg_bvalid",
1141                                   "otg_linestate", "host0_linestate",
1142                                   "host1_linestate";
1143
1144                 clocks = <&clk_gates7 9>, <&usbphy_480m>,
1145                          <&otgphy1_480m>, <&otgphy2_480m>;
1146                 clock-names = "hclk_usb_peri", "usbphy_480m",
1147                               "usbphy1_480m", "usbphy2_480m";
1148
1149                 usb_bc {
1150                         compatible = "synopsys,phy";
1151                                         /* offset bit mask */
1152                         rk_usb,bvalid     = <0x288 14 1>;
1153                         rk_usb,iddig      = <0x288 17 1>;
1154                         rk_usb,dcdenb     = <0x328 14 1>;
1155                         rk_usb,vdatsrcenb = <0x328  7 1>;
1156                         rk_usb,vdatdetenb = <0x328  6 1>;
1157                         rk_usb,chrgsel    = <0x328  5 1>;
1158                         rk_usb,chgdet     = <0x2cc 23 1>;
1159                         rk_usb,fsvminus   = <0x2cc 25 1>;
1160                         rk_usb,fsvplus    = <0x2cc 24 1>;
1161                 };
1162         };
1163
1164         usb0: usb@ff580000 {
1165                 compatible = "rockchip,rk3288_usb20_otg";
1166                 reg = <0xff580000 0x40000>;
1167                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
1168                 clocks = <&clk_gates13 4>, <&clk_gates7 4>;
1169                 clock-names = "clk_usbphy0", "hclk_usb0";
1170                 resets = <&reset RK3288_SOFT_RST_USBOTG_H>,
1171                          <&reset RK3288_SOFT_RST_USBOTGPHY>,
1172                          <&reset RK3288_SOFT_RST_USBOTGC>;
1173                 reset-names = "otg_ahb", "otg_phy", "otg_controller";
1174                 /*0 - Normal, 1 - Force Host, 2 - Force Device*/
1175                 rockchip,usb-mode = <0>;
1176         };
1177
1178         usb1: usb@ff540000 {
1179                 compatible = "rockchip,rk3288_usb20_host";
1180                 reg = <0xff540000 0x40000>;
1181                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
1182                 clocks = <&clk_gates13 6>, <&clk_gates7 7>,
1183                          <&usbphy_480m>;
1184                 clock-names = "clk_usbphy1", "hclk_usb1",
1185                               "usbphy_480m";
1186                 resets = <&reset RK3288_SOFT_RST_USBHOST1_H>,
1187                          <&reset RK3288_SOFT_RST_USBHOST1PHY>,
1188                          <&reset RK3288_SOFT_RST_USBHOST1C>;
1189                 reset-names = "host1_ahb", "host1_phy", "host1_controller";
1190         };
1191
1192         usb2: usb@ff500000 {
1193                 compatible = "rockchip,rk3288_rk_ehci_host";
1194                 reg = <0xff500000 0x20000>;
1195                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
1196                 clocks = <&clk_gates13 5>, <&clk_gates7 6>;
1197                 clock-names = "clk_usbphy2", "hclk_usb2";
1198                 resets = <&reset RK3288_SOFT_RST_USBHOST0_H>,
1199                          <&reset RK3288_SOFT_RST_USBHOST0PHY>,
1200                          <&reset RK3288_SOFT_RST_USBHOST0C>,
1201                          <&reset RK3288_SOFT_RST_USB_HOST0>;
1202                 reset-names = "ehci_ahb", "ehci_phy", "ehci_controller", "ehci";
1203         };
1204
1205         usb3: usb@ff520000 {
1206                 compatible = "rockchip,rk3288_rk_ohci_host";
1207                 reg = <0xff520000 0x20000>;
1208                 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
1209                 clocks = <&clk_gates13 5>, <&clk_gates7 6>;
1210                 clock-names = "clk_usbphy3", "hclk_usb3";
1211                 status = "disabled";
1212         };
1213
1214         usb4: usb@ff5c0000 {
1215                 compatible = "rockchip,rk3288_rk_ehci1_host";
1216                 reg = <0xff5c0000 0x40000>;
1217                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
1218                 clocks = <&ehci1phy_480m>, <&clk_gates7 8>,
1219                          <&ehci1phy_12m>, <&usbphy_480m>,
1220                          <&otgphy1_480m>, <&otgphy2_480m>;
1221                 clock-names = "ehci1phy_480m", "hclk_ehci1",
1222                               "ehci1phy_12m", "usbphy_480m",
1223                               "ehci1_usbphy1", "ehci1_usbphy2";
1224                 resets = <&reset RK3288_SOFT_RST_EHCI1>,
1225                          <&reset RK3288_SOFT_RST_EHCI1_AUX>,
1226                          <&reset RK3288_SOFT_RST_EHCI1PHY>;
1227                 reset-names = "ehci1_ahb", "ehci1_aux", "ehci1_phy";
1228         };
1229
1230         gmac: eth@ff290000 {
1231                 compatible = "rockchip,rk3288-gmac";
1232                 reg = <0xff290000 0x10000>;
1233                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;  /*irq=59*/
1234                 interrupt-names = "macirq";
1235                 clocks = <&clk_mac>, <&clk_gates5 0>,
1236                          <&clk_gates5 1>, <&clk_gates5 2>,
1237                          <&clk_gates5 3>, <&clk_gates8 0>,
1238                          <&clk_gates8 1>;
1239                 clock-names = "clk_mac", "mac_clk_rx",
1240                               "mac_clk_tx", "clk_mac_ref",
1241                               "clk_mac_refout", "aclk_mac",
1242                               "pclk_mac";
1243                 phy-mode = "rgmii";
1244                 pinctrl-names = "default";
1245                 pinctrl-0 = <&mac_clk &mac_txpins &mac_rxpins &mac_mdpins>;
1246         };
1247
1248         gpu {
1249                 compatible = "arm,malit764",
1250                              "arm,malit76x",
1251                              "arm,malit7xx",
1252                              "arm,mali-midgard";
1253                 reg = <0xffa30000 0x10000>;
1254                 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
1255                              <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
1256                              <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1257                 interrupt-names = "JOB", "MMU", "GPU";
1258         };
1259
1260         iep_mmu {
1261                 dbgname = "iep";
1262                 compatible = "rockchip,iep_mmu";
1263                 reg = <0xff900800 0x100>;
1264                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1265                 interrupt-names = "iep_mmu";
1266         };
1267
1268         vip_mmu {
1269                 dbgname = "vip";
1270                 compatible = "rockchip,vip_mmu";
1271                 reg = <0xff950800 0x100>;
1272                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
1273                 interrupt-names = "vip_mmu";
1274         };
1275
1276         vopb_mmu {
1277                 dbgname = "vopb";
1278                 compatible = "rockchip,vopb_mmu";
1279                 reg = <0xff930300 0x100>;
1280                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1281                 interrupt-names = "vopb_mmu";
1282         };
1283
1284         vopl_mmu {
1285                 dbgname = "vopl";
1286                 compatible = "rockchip,vopl_mmu";
1287                 reg = <0xff940300 0x100>;
1288                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1289                 interrupt-names = "vopl_mmu";
1290         };
1291
1292         hevc_mmu {
1293                 dbgname = "hevc";
1294                 compatible = "rockchip,hevc_mmu";
1295                 reg = <0xff9c0440 0x40>,
1296                       <0xff9c0480 0x40>;
1297                 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
1298                 interrupt-names = "hevc_mmu";
1299         };
1300
1301         vpu_mmu {
1302                 dbgname = "vpu";
1303                 compatible = "rockchip,vpu_mmu";
1304                 reg = <0xff9a0800 0x100>;
1305                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
1306                 interrupt-names = "vpu_mmu";
1307         };
1308
1309         isp_mmu {
1310                 dbgname = "isp_mmu";
1311                 compatible = "rockchip,isp_mmu";
1312                 reg = <0xff914000 0x100>,
1313                       <0xff915000 0x100>;
1314                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1315                 interrupt-names = "isp_mmu";
1316         };
1317
1318         rockchip_suspend: rockchip_suspend {
1319                 rockchip,ctrbits = <
1320                         (0
1321                          |RKPM_CTR_PWR_DMNS
1322                          |RKPM_CTR_GTCLKS
1323                          |RKPM_CTR_PLLS
1324                  //      |RKPM_CTR_GPIOS
1325                 //       |RKPM_CTR_SYSCLK_DIV
1326                 //       |RKPM_CTR_IDLEAUTO_MD
1327                 //       |RKPM_CTR_ARMOFF_LPMD
1328                          |RKPM_CTR_ARMOFF_LOGDP_LPMD
1329                         )
1330                         >;
1331                 rockchip,pmic-suspend_gpios = <
1332                         RKPM_PINGPIO_BITS_OUTPUT(GPIO7_A1,RKPM_GPIO_OUT_H)
1333                         >;
1334                 rockchip,pmic-resume_gpios = <
1335                         RKPM_PINGPIO_BITS_FUN(PWM1,RKPM_GPIO_PULL_DN)
1336                         >;
1337         };
1338
1339         isp: isp@ff910000{
1340                 compatible = "rockchip,isp";
1341                 reg = <0xff910000 0x10000>;
1342                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1343                 clocks = <&clk_gates16 2>, <&clk_gates16 1>, <&clk_isp>,
1344                          <&clk_isp_jpe>, <&clkin_isp>, <&clk_cif_out>,
1345                          <&clk_gates5 15>, <&clk_cif_pll>, <&pd_isp>,
1346                          <&clk_gates16 6>;
1347                 clock-names = "aclk_isp", "hclk_isp", "clk_isp",
1348                               "clk_isp_jpe", "pclkin_isp", "clk_cif_out",
1349                               "clk_mipi_24m", "clk_cif_pll", "pd_isp",
1350                               "hclk_mipiphy1";
1351                 pinctrl-names = "default", "isp_dvp8bit2", "isp_dvp10bit",
1352                                 "isp_dvp12bit", "isp_dvp8bit0", "isp_mipi_fl",
1353                                 "isp_mipi_fl_prefl","isp_flash_as_gpio",
1354                                 "isp_flash_as_trigger_out";
1355                 pinctrl-0 = <&isp_mipi>;
1356                 pinctrl-1 = <&isp_mipi &isp_dvp_d2d9>;
1357                 pinctrl-2 = <&isp_mipi &isp_dvp_d2d9 &isp_dvp_d0d1>;
1358                 pinctrl-3 = <&isp_mipi &isp_dvp_d2d9 &isp_dvp_d0d1
1359                              &isp_dvp_d10d11>;
1360                 pinctrl-4 = <&isp_mipi &isp_dvp_d0d7>;
1361                 pinctrl-5 = <&isp_mipi>;
1362                 pinctrl-6 = <&isp_mipi &isp_prelight>;
1363                 pinctrl-7 = <&isp_flash_trigger_as_gpio>;
1364                 pinctrl-8 = <&isp_flash_trigger>;
1365                 rockchip,isp,mipiphy = <2>;
1366                 rockchip,isp,cifphy = <1>;
1367                 rockchip,isp,mipiphy1,reg = <0xff968000 0x4000>;
1368                 rockchip,gpios = <&gpio7 GPIO_B5 GPIO_ACTIVE_HIGH>;
1369                 rockchip,isp,iommu_enable = <1>;
1370                 status = "okay";
1371         };
1372
1373         cif: cif@ff950000 {
1374                 compatible = "rockchip,cif";
1375                 reg = <0xff950000 0x10000>;
1376                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
1377                 clocks = <&pd_isp>,<&clk_gates15 14>,<&clk_gates15 15>,
1378                          <&clkin_cif>,<&clk_gates16 0>,<&clk_cif_out>;
1379                 clock-names = "pd_cif0", "aclk_cif0","hclk_cif0",
1380                               "cif0_in","g_pclkin_cif","cif0_out";
1381                 pinctrl-names = "cif_pin_all";
1382                 pinctrl-0 = <&isp_mipi &isp_dvp_d2d9 &isp_dvp_d10d11>;
1383                 status = "okay";
1384         };
1385
1386         tsadc: tsadc@ff280000 {
1387                 compatible = "rockchip,tsadc";
1388                 reg = <0xff280000 0x100>;
1389                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
1390                 #io-channel-cells = <1>;
1391                 io-channel-ranges;
1392                 clock-frequency = <10000>;
1393                 clocks = <&clk_tsadc>, <&clk_gates7 2>;
1394                 clock-names = "tsadc", "pclk_tsadc";
1395                 pinctrl-names = "default", "tsadc_int";
1396                 pinctrl-0 = <&tsadc_gpio>;
1397                 pinctrl-1 = <&tsadc_int>;
1398                 tsadc-ht-temp = <120>;
1399                 tsadc-ht-reset-cru = <1>;
1400                 tsadc-ht-pull-gpio = <0>;
1401                 status = "okay";
1402         };
1403
1404         lcdc_vdd_domain: lcdc-vdd-domain {
1405                 compatible = "rockchip,io_vol_domain";
1406                 pinctrl-names = "default", "1.8V", "3.3V";
1407                 pinctrl-0 = <&lcdc_vcc>;
1408                 pinctrl-1 = <&lcdc_vcc_18>;
1409                 pinctrl-2 = <&lcdc_vcc_33>;
1410         };
1411
1412         dpio_vdd_domain: dpio-vdd-domain {
1413                 compatible = "rockchip,io_vol_domain";
1414                 pinctrl-names = "default", "1.8V", "3.3V";
1415                 pinctrl-0 = <&dvp_vcc>;
1416                 pinctrl-1 = <&dvp_vcc_18>;
1417                 pinctrl-2 = <&dvp_vcc_33>;
1418         };
1419
1420         flash0_vdd_domain: flash0-vdd-domain {
1421                 compatible = "rockchip,io_vol_domain";
1422                 pinctrl-names = "default", "1.8V", "3.3V";
1423                 pinctrl-0 = <&flash0_vcc>;
1424                 pinctrl-1 = <&flash0_vcc_18>;
1425                 pinctrl-2 = <&flash0_vcc_33>;
1426         };
1427
1428         flash1_vdd_domain: flash1-vdd-domain {
1429                 compatible = "rockchip,io_vol_domain";
1430                 pinctrl-names = "default", "1.8V", "3.3V";
1431                 pinctrl-0 = <&flash1_vcc>;
1432                 pinctrl-1 = <&flash1_vcc_18>;
1433                 pinctrl-2 = <&flash1_vcc_33>;
1434         };
1435
1436         apio3_vdd_domain: apio3-vdd-domain {
1437                 compatible = "rockchip,io_vol_domain";
1438                 pinctrl-names = "default", "1.8V", "3.3V";
1439                 pinctrl-0 = <&wifi_vcc>;
1440                 pinctrl-1 = <&wifi_vcc_18>;
1441                 pinctrl-2 = <&wifi_vcc_33>;
1442         };
1443
1444         apio5_vdd_domain: apio5-vdd-domain {
1445                 compatible = "rockchip,io_vol_domain";
1446                 pinctrl-names = "default", "1.8V", "3.3V";
1447                 pinctrl-0 = <&bb_vcc>;
1448                 pinctrl-1 = <&bb_vcc_18>;
1449                 pinctrl-2 = <&bb_vcc_33>;
1450         };
1451
1452         apio4_vdd_domain: apio4-vdd-domain {
1453                 compatible = "rockchip,io_vol_domain";
1454                 pinctrl-names = "default", "1.8V", "3.3V";
1455                 pinctrl-0 = <&audio_vcc>;
1456                 pinctrl-1 = <&audio_vcc_18>;
1457                 pinctrl-2 = <&audio_vcc_33>;
1458         };
1459
1460         apio1_vdd_domain: apio0-vdd-domain {
1461                 compatible = "rockchip,io_vol_domain";
1462                 pinctrl-names = "default", "1.8V", "3.3V";
1463                 pinctrl-0 = <&gpio30_vcc>;
1464                 pinctrl-1 = <&gpio30_vcc_18>;
1465                 pinctrl-2 = <&gpio30_vcc_33>;
1466         };
1467
1468         apio2_vdd_domain: apio2-vdd-domain {
1469                 compatible = "rockchip,io_vol_domain";
1470                 pinctrl-names = "default", "1.8V", "3.3V";
1471                 pinctrl-0 = <&gpio1830_vcc>;
1472                 pinctrl-1 = <&gpio1830_vcc_18>;
1473                 pinctrl-2 = <&gpio1830_vcc_33>;
1474         };
1475
1476         sdmmc0_vdd_domain: sdmmc0-vdd-domain {
1477                 compatible = "rockchip,io_vol_domain";
1478                 pinctrl-names = "default", "1.8V", "3.3V";
1479                 pinctrl-0 = <&sdcard_vcc>;
1480                 pinctrl-1 = <&sdcard_vcc_18>;
1481                 pinctrl-2 = <&sdcard_vcc_33>;
1482         };
1483
1484         chosen {
1485                 bootargs = "vmalloc=496M";
1486         };
1487 };