2 * This program is free software; you can redistribute it and/or modify
3 * it under the terms of the GNU General Public License as published by
4 * the Free Software Foundation; either version 2 of the License, or
5 * (at your option) any later version.
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
13 #include <dt-bindings/gpio/gpio.h>
14 #include <dt-bindings/interrupt-controller/irq.h>
15 #include <dt-bindings/interrupt-controller/arm-gic.h>
16 #include <dt-bindings/pinctrl/rockchip.h>
17 #include <dt-bindings/clock/rk3288-cru.h>
18 #include "skeleton.dtsi"
21 compatible = "rockchip,rk3288";
23 interrupt-parent = <&gic>;
52 compatible = "arm,cortex-a12";
57 compatible = "arm,cortex-a12";
62 compatible = "arm,cortex-a12";
67 compatible = "arm,cortex-a12";
73 compatible = "arm,amba-bus";
78 dmac_peri: dma-controller@ff250000 {
79 compatible = "arm,pl330", "arm,primecell";
80 reg = <0xff250000 0x4000>;
81 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
82 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
84 clocks = <&cru ACLK_DMAC2>;
85 clock-names = "apb_pclk";
88 dmac_bus_ns: dma-controller@ff600000 {
89 compatible = "arm,pl330", "arm,primecell";
90 reg = <0xff600000 0x4000>;
91 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
92 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
94 clocks = <&cru ACLK_DMAC1>;
95 clock-names = "apb_pclk";
99 dmac_bus_s: dma-controller@ffb20000 {
100 compatible = "arm,pl330", "arm,primecell";
101 reg = <0xffb20000 0x4000>;
102 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
103 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
105 clocks = <&cru ACLK_DMAC1>;
106 clock-names = "apb_pclk";
111 compatible = "fixed-clock";
112 clock-frequency = <24000000>;
113 clock-output-names = "xin24m";
118 compatible = "arm,armv7-timer";
119 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
120 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
121 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
122 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
123 clock-frequency = <24000000>;
126 sdmmc: dwmmc@ff0c0000 {
127 compatible = "rockchip,rk3288-dw-mshc";
128 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
129 clock-names = "biu", "ciu";
130 fifo-depth = <0x100>;
131 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
132 reg = <0xff0c0000 0x4000>;
136 sdio0: dwmmc@ff0d0000 {
137 compatible = "rockchip,rk3288-dw-mshc";
138 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>;
139 clock-names = "biu", "ciu";
140 fifo-depth = <0x100>;
141 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
142 reg = <0xff0d0000 0x4000>;
146 sdio1: dwmmc@ff0e0000 {
147 compatible = "rockchip,rk3288-dw-mshc";
148 clocks = <&cru HCLK_SDIO1>, <&cru SCLK_SDIO1>;
149 clock-names = "biu", "ciu";
150 fifo-depth = <0x100>;
151 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
152 reg = <0xff0e0000 0x4000>;
156 emmc: dwmmc@ff0f0000 {
157 compatible = "rockchip,rk3288-dw-mshc";
158 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>;
159 clock-names = "biu", "ciu";
160 fifo-depth = <0x100>;
161 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
162 reg = <0xff0f0000 0x4000>;
166 saradc: saradc@ff100000 {
167 compatible = "rockchip,saradc";
168 reg = <0xff100000 0x100>;
169 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
170 #io-channel-cells = <1>;
171 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
172 clock-names = "saradc", "apb_pclk";
177 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
178 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
179 clock-names = "spiclk", "apb_pclk";
180 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
181 pinctrl-names = "default";
182 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
183 reg = <0xff110000 0x1000>;
184 #address-cells = <1>;
190 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
191 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
192 clock-names = "spiclk", "apb_pclk";
193 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
194 pinctrl-names = "default";
195 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
196 reg = <0xff120000 0x1000>;
197 #address-cells = <1>;
203 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
204 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
205 clock-names = "spiclk", "apb_pclk";
206 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
207 pinctrl-names = "default";
208 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
209 reg = <0xff130000 0x1000>;
210 #address-cells = <1>;
216 compatible = "rockchip,rk3288-i2c";
217 reg = <0xff140000 0x1000>;
218 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
219 #address-cells = <1>;
222 clocks = <&cru PCLK_I2C1>;
223 pinctrl-names = "default";
224 pinctrl-0 = <&i2c1_xfer>;
229 compatible = "rockchip,rk3288-i2c";
230 reg = <0xff150000 0x1000>;
231 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
232 #address-cells = <1>;
235 clocks = <&cru PCLK_I2C3>;
236 pinctrl-names = "default";
237 pinctrl-0 = <&i2c3_xfer>;
242 compatible = "rockchip,rk3288-i2c";
243 reg = <0xff160000 0x1000>;
244 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
245 #address-cells = <1>;
248 clocks = <&cru PCLK_I2C4>;
249 pinctrl-names = "default";
250 pinctrl-0 = <&i2c4_xfer>;
255 compatible = "rockchip,rk3288-i2c";
256 reg = <0xff170000 0x1000>;
257 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
258 #address-cells = <1>;
261 clocks = <&cru PCLK_I2C5>;
262 pinctrl-names = "default";
263 pinctrl-0 = <&i2c5_xfer>;
267 uart0: serial@ff180000 {
268 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
269 reg = <0xff180000 0x100>;
270 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
273 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
274 clock-names = "baudclk", "apb_pclk";
275 pinctrl-names = "default";
276 pinctrl-0 = <&uart0_xfer>;
280 uart1: serial@ff190000 {
281 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
282 reg = <0xff190000 0x100>;
283 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
286 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
287 clock-names = "baudclk", "apb_pclk";
288 pinctrl-names = "default";
289 pinctrl-0 = <&uart1_xfer>;
293 uart2: serial@ff690000 {
294 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
295 reg = <0xff690000 0x100>;
296 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
299 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
300 clock-names = "baudclk", "apb_pclk";
301 pinctrl-names = "default";
302 pinctrl-0 = <&uart2_xfer>;
306 uart3: serial@ff1b0000 {
307 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
308 reg = <0xff1b0000 0x100>;
309 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
312 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
313 clock-names = "baudclk", "apb_pclk";
314 pinctrl-names = "default";
315 pinctrl-0 = <&uart3_xfer>;
319 uart4: serial@ff1c0000 {
320 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
321 reg = <0xff1c0000 0x100>;
322 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
325 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
326 clock-names = "baudclk", "apb_pclk";
327 pinctrl-names = "default";
328 pinctrl-0 = <&uart4_xfer>;
332 usb_host0_ehci: usb@ff500000 {
333 compatible = "generic-ehci";
334 reg = <0xff500000 0x100>;
335 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
336 clocks = <&cru HCLK_USBHOST0>;
337 clock-names = "usbhost";
341 /* NOTE: ohci@ff520000 doesn't actually work on hardware */
343 usb_host1: usb@ff540000 {
344 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
346 reg = <0xff540000 0x40000>;
347 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
348 clocks = <&cru HCLK_USBHOST1>;
353 usb_otg: usb@ff580000 {
354 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
356 reg = <0xff580000 0x40000>;
357 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
358 clocks = <&cru HCLK_OTG0>;
363 usb_hsic: usb@ff5c0000 {
364 compatible = "generic-ehci";
365 reg = <0xff5c0000 0x100>;
366 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
367 clocks = <&cru HCLK_HSIC>;
368 clock-names = "usbhost";
373 compatible = "rockchip,rk3288-i2c";
374 reg = <0xff650000 0x1000>;
375 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
376 #address-cells = <1>;
379 clocks = <&cru PCLK_I2C0>;
380 pinctrl-names = "default";
381 pinctrl-0 = <&i2c0_xfer>;
386 compatible = "rockchip,rk3288-i2c";
387 reg = <0xff660000 0x1000>;
388 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
389 #address-cells = <1>;
392 clocks = <&cru PCLK_I2C2>;
393 pinctrl-names = "default";
394 pinctrl-0 = <&i2c2_xfer>;
399 compatible = "rockchip,rk3288-pwm";
400 reg = <0xff680000 0x10>;
402 pinctrl-names = "default";
403 pinctrl-0 = <&pwm0_pin>;
404 clocks = <&cru PCLK_PWM>;
410 compatible = "rockchip,rk3288-pwm";
411 reg = <0xff680010 0x10>;
413 pinctrl-names = "default";
414 pinctrl-0 = <&pwm1_pin>;
415 clocks = <&cru PCLK_PWM>;
421 compatible = "rockchip,rk3288-pwm";
422 reg = <0xff680020 0x10>;
424 pinctrl-names = "default";
425 pinctrl-0 = <&pwm2_pin>;
426 clocks = <&cru PCLK_PWM>;
432 compatible = "rockchip,rk3288-pwm";
433 reg = <0xff680030 0x10>;
435 pinctrl-names = "default";
436 pinctrl-0 = <&pwm3_pin>;
437 clocks = <&cru PCLK_PWM>;
442 pmu: power-management@ff730000 {
443 compatible = "rockchip,rk3288-pmu", "syscon";
444 reg = <0xff730000 0x100>;
447 sgrf: syscon@ff740000 {
448 compatible = "rockchip,rk3288-sgrf", "syscon";
449 reg = <0xff740000 0x1000>;
452 cru: clock-controller@ff760000 {
453 compatible = "rockchip,rk3288-cru";
454 reg = <0xff760000 0x1000>;
455 rockchip,grf = <&grf>;
460 grf: syscon@ff770000 {
461 compatible = "rockchip,rk3288-grf", "syscon";
462 reg = <0xff770000 0x1000>;
465 wdt: watchdog@ff800000 {
466 compatible = "rockchip,rk3288-wdt", "snps,dw-wdt";
467 reg = <0xff800000 0x100>;
468 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
472 gic: interrupt-controller@ffc01000 {
473 compatible = "arm,gic-400";
474 interrupt-controller;
475 #interrupt-cells = <3>;
476 #address-cells = <0>;
478 reg = <0xffc01000 0x1000>,
482 interrupts = <GIC_PPI 9 0xf04>;
486 compatible = "rockchip,rk3288-pinctrl";
487 rockchip,grf = <&grf>;
488 rockchip,pmu = <&pmu>;
489 #address-cells = <1>;
493 gpio0: gpio0@ff750000 {
494 compatible = "rockchip,gpio-bank";
495 reg = <0xff750000 0x100>;
496 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
497 clocks = <&cru PCLK_GPIO0>;
502 interrupt-controller;
503 #interrupt-cells = <2>;
506 gpio1: gpio1@ff780000 {
507 compatible = "rockchip,gpio-bank";
508 reg = <0xff780000 0x100>;
509 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
510 clocks = <&cru PCLK_GPIO1>;
515 interrupt-controller;
516 #interrupt-cells = <2>;
519 gpio2: gpio2@ff790000 {
520 compatible = "rockchip,gpio-bank";
521 reg = <0xff790000 0x100>;
522 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
523 clocks = <&cru PCLK_GPIO2>;
528 interrupt-controller;
529 #interrupt-cells = <2>;
532 gpio3: gpio3@ff7a0000 {
533 compatible = "rockchip,gpio-bank";
534 reg = <0xff7a0000 0x100>;
535 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
536 clocks = <&cru PCLK_GPIO3>;
541 interrupt-controller;
542 #interrupt-cells = <2>;
545 gpio4: gpio4@ff7b0000 {
546 compatible = "rockchip,gpio-bank";
547 reg = <0xff7b0000 0x100>;
548 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
549 clocks = <&cru PCLK_GPIO4>;
554 interrupt-controller;
555 #interrupt-cells = <2>;
558 gpio5: gpio5@ff7c0000 {
559 compatible = "rockchip,gpio-bank";
560 reg = <0xff7c0000 0x100>;
561 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
562 clocks = <&cru PCLK_GPIO5>;
567 interrupt-controller;
568 #interrupt-cells = <2>;
571 gpio6: gpio6@ff7d0000 {
572 compatible = "rockchip,gpio-bank";
573 reg = <0xff7d0000 0x100>;
574 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
575 clocks = <&cru PCLK_GPIO6>;
580 interrupt-controller;
581 #interrupt-cells = <2>;
584 gpio7: gpio7@ff7e0000 {
585 compatible = "rockchip,gpio-bank";
586 reg = <0xff7e0000 0x100>;
587 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
588 clocks = <&cru PCLK_GPIO7>;
593 interrupt-controller;
594 #interrupt-cells = <2>;
597 gpio8: gpio8@ff7f0000 {
598 compatible = "rockchip,gpio-bank";
599 reg = <0xff7f0000 0x100>;
600 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
601 clocks = <&cru PCLK_GPIO8>;
606 interrupt-controller;
607 #interrupt-cells = <2>;
610 pcfg_pull_up: pcfg-pull-up {
614 pcfg_pull_down: pcfg-pull-down {
618 pcfg_pull_none: pcfg-pull-none {
623 i2c0_xfer: i2c0-xfer {
624 rockchip,pins = <0 15 RK_FUNC_1 &pcfg_pull_none>,
625 <0 16 RK_FUNC_1 &pcfg_pull_none>;
630 i2c1_xfer: i2c1-xfer {
631 rockchip,pins = <8 4 RK_FUNC_1 &pcfg_pull_none>,
632 <8 5 RK_FUNC_1 &pcfg_pull_none>;
637 i2c2_xfer: i2c2-xfer {
638 rockchip,pins = <6 9 RK_FUNC_1 &pcfg_pull_none>,
639 <6 10 RK_FUNC_1 &pcfg_pull_none>;
644 i2c3_xfer: i2c3-xfer {
645 rockchip,pins = <2 16 RK_FUNC_1 &pcfg_pull_none>,
646 <2 17 RK_FUNC_1 &pcfg_pull_none>;
651 i2c4_xfer: i2c4-xfer {
652 rockchip,pins = <7 17 RK_FUNC_1 &pcfg_pull_none>,
653 <7 18 RK_FUNC_1 &pcfg_pull_none>;
658 i2c5_xfer: i2c5-xfer {
659 rockchip,pins = <7 19 RK_FUNC_1 &pcfg_pull_none>,
660 <7 20 RK_FUNC_1 &pcfg_pull_none>;
665 sdmmc_clk: sdmmc-clk {
666 rockchip,pins = <6 20 RK_FUNC_1 &pcfg_pull_none>;
669 sdmmc_cmd: sdmmc-cmd {
670 rockchip,pins = <6 21 RK_FUNC_1 &pcfg_pull_up>;
674 rockchip,pins = <6 22 RK_FUNC_1 &pcfg_pull_up>;
677 sdmmc_bus1: sdmmc-bus1 {
678 rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>;
681 sdmmc_bus4: sdmmc-bus4 {
682 rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>,
683 <6 17 RK_FUNC_1 &pcfg_pull_up>,
684 <6 18 RK_FUNC_1 &pcfg_pull_up>,
685 <6 19 RK_FUNC_1 &pcfg_pull_up>;
690 sdio0_bus1: sdio0-bus1 {
691 rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>;
694 sdio0_bus4: sdio0-bus4 {
695 rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>,
696 <4 21 RK_FUNC_1 &pcfg_pull_up>,
697 <4 22 RK_FUNC_1 &pcfg_pull_up>,
698 <4 23 RK_FUNC_1 &pcfg_pull_up>;
701 sdio0_cmd: sdio0-cmd {
702 rockchip,pins = <4 24 RK_FUNC_1 &pcfg_pull_up>;
705 sdio0_clk: sdio0-clk {
706 rockchip,pins = <4 25 RK_FUNC_1 &pcfg_pull_none>;
710 rockchip,pins = <4 26 RK_FUNC_1 &pcfg_pull_up>;
714 rockchip,pins = <4 27 RK_FUNC_1 &pcfg_pull_up>;
717 sdio0_pwr: sdio0-pwr {
718 rockchip,pins = <4 28 RK_FUNC_1 &pcfg_pull_up>;
721 sdio0_bkpwr: sdio0-bkpwr {
722 rockchip,pins = <4 29 RK_FUNC_1 &pcfg_pull_up>;
725 sdio0_int: sdio0-int {
726 rockchip,pins = <4 30 RK_FUNC_1 &pcfg_pull_up>;
731 sdio1_bus1: sdio1-bus1 {
732 rockchip,pins = <3 24 4 &pcfg_pull_up>;
735 sdio1_bus4: sdio1-bus4 {
736 rockchip,pins = <3 24 4 &pcfg_pull_up>,
737 <3 25 4 &pcfg_pull_up>,
738 <3 26 4 &pcfg_pull_up>,
739 <3 27 4 &pcfg_pull_up>;
743 rockchip,pins = <3 28 4 &pcfg_pull_up>;
747 rockchip,pins = <3 29 4 &pcfg_pull_up>;
750 sdio1_bkpwr: sdio1-bkpwr {
751 rockchip,pins = <3 30 4 &pcfg_pull_up>;
754 sdio1_int: sdio1-int {
755 rockchip,pins = <3 31 4 &pcfg_pull_up>;
758 sdio1_cmd: sdio1-cmd {
759 rockchip,pins = <4 6 4 &pcfg_pull_up>;
762 sdio1_clk: sdio1-clk {
763 rockchip,pins = <4 7 4 &pcfg_pull_none>;
766 sdio1_pwr: sdio1-pwr {
767 rockchip,pins = <4 9 4 &pcfg_pull_up>;
773 rockchip,pins = <3 18 RK_FUNC_2 &pcfg_pull_none>;
777 rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_up>;
781 rockchip,pins = <3 9 RK_FUNC_2 &pcfg_pull_up>;
784 emmc_bus1: emmc-bus1 {
785 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>;
788 emmc_bus4: emmc-bus4 {
789 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>,
790 <3 1 RK_FUNC_2 &pcfg_pull_up>,
791 <3 2 RK_FUNC_2 &pcfg_pull_up>,
792 <3 3 RK_FUNC_2 &pcfg_pull_up>;
795 emmc_bus8: emmc-bus8 {
796 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>,
797 <3 1 RK_FUNC_2 &pcfg_pull_up>,
798 <3 2 RK_FUNC_2 &pcfg_pull_up>,
799 <3 3 RK_FUNC_2 &pcfg_pull_up>,
800 <3 4 RK_FUNC_2 &pcfg_pull_up>,
801 <3 5 RK_FUNC_2 &pcfg_pull_up>,
802 <3 6 RK_FUNC_2 &pcfg_pull_up>,
803 <3 7 RK_FUNC_2 &pcfg_pull_up>;
809 rockchip,pins = <5 12 RK_FUNC_1 &pcfg_pull_up>;
812 rockchip,pins = <5 13 RK_FUNC_1 &pcfg_pull_up>;
815 rockchip,pins = <5 14 RK_FUNC_1 &pcfg_pull_up>;
818 rockchip,pins = <5 15 RK_FUNC_1 &pcfg_pull_up>;
821 rockchip,pins = <5 16 RK_FUNC_1 &pcfg_pull_up>;
826 rockchip,pins = <7 12 RK_FUNC_2 &pcfg_pull_up>;
829 rockchip,pins = <7 13 RK_FUNC_2 &pcfg_pull_up>;
832 rockchip,pins = <7 14 RK_FUNC_2 &pcfg_pull_up>;
835 rockchip,pins = <7 15 RK_FUNC_2 &pcfg_pull_up>;
841 rockchip,pins = <8 3 RK_FUNC_1 &pcfg_pull_up>;
844 rockchip,pins = <8 6 RK_FUNC_1 &pcfg_pull_up>;
847 rockchip,pins = <8 7 RK_FUNC_1 &pcfg_pull_up>;
850 rockchip,pins = <8 8 RK_FUNC_1 &pcfg_pull_up>;
853 rockchip,pins = <8 9 RK_FUNC_1 &pcfg_pull_up>;
858 uart0_xfer: uart0-xfer {
859 rockchip,pins = <4 16 RK_FUNC_1 &pcfg_pull_up>,
860 <4 17 RK_FUNC_1 &pcfg_pull_none>;
863 uart0_cts: uart0-cts {
864 rockchip,pins = <4 18 RK_FUNC_1 &pcfg_pull_none>;
867 uart0_rts: uart0-rts {
868 rockchip,pins = <4 19 RK_FUNC_1 &pcfg_pull_none>;
873 uart1_xfer: uart1-xfer {
874 rockchip,pins = <5 8 RK_FUNC_1 &pcfg_pull_up>,
875 <5 9 RK_FUNC_1 &pcfg_pull_none>;
878 uart1_cts: uart1-cts {
879 rockchip,pins = <5 10 RK_FUNC_1 &pcfg_pull_none>;
882 uart1_rts: uart1-rts {
883 rockchip,pins = <5 11 RK_FUNC_1 &pcfg_pull_none>;
888 uart2_xfer: uart2-xfer {
889 rockchip,pins = <7 22 RK_FUNC_1 &pcfg_pull_up>,
890 <7 23 RK_FUNC_1 &pcfg_pull_none>;
892 /* no rts / cts for uart2 */
896 uart3_xfer: uart3-xfer {
897 rockchip,pins = <7 7 RK_FUNC_1 &pcfg_pull_up>,
898 <7 8 RK_FUNC_1 &pcfg_pull_none>;
901 uart3_cts: uart3-cts {
902 rockchip,pins = <7 9 RK_FUNC_1 &pcfg_pull_none>;
905 uart3_rts: uart3-rts {
906 rockchip,pins = <7 10 RK_FUNC_1 &pcfg_pull_none>;
911 uart4_xfer: uart4-xfer {
912 rockchip,pins = <5 12 3 &pcfg_pull_up>,
913 <5 13 3 &pcfg_pull_none>;
916 uart4_cts: uart4-cts {
917 rockchip,pins = <5 14 3 &pcfg_pull_none>;
920 uart4_rts: uart4-rts {
921 rockchip,pins = <5 15 3 &pcfg_pull_none>;
927 rockchip,pins = <7 0 RK_FUNC_1 &pcfg_pull_none>;
933 rockchip,pins = <7 1 RK_FUNC_1 &pcfg_pull_none>;
939 rockchip,pins = <7 22 3 &pcfg_pull_none>;
945 rockchip,pins = <7 23 3 &pcfg_pull_none>;