1 #include <dt-bindings/clock/ddr.h>
2 #include <dt-bindings/interrupt-controller/arm-gic.h>
3 #include <dt-bindings/rkfb/rk_fb.h>
4 #include <dt-bindings/rkmipi/mipi_dsi.h>
5 #include <dt-bindings/suspend/rockchip-pm.h>
6 #include <dt-bindings/sensor-dev.h>
8 #include "skeleton.dtsi"
9 #include "rk3288-pinctrl.dtsi"
10 #include "rk3288-clocks.dtsi"
13 compatible = "rockchip,rk3288";
14 rockchip,sram = <&sram>;
15 interrupt-parent = <&gic>;
43 compatible = "arm,cortex-a15";
48 compatible = "arm,cortex-a15";
53 compatible = "arm,cortex-a15";
58 compatible = "arm,cortex-a15";
63 gic: interrupt-controller@ffc01000 {
64 compatible = "arm,cortex-a15-gic";
66 #interrupt-cells = <3>;
68 reg = <0xffc01000 0x1000>,
73 compatible = "arm,cortex-a12-pmu";
74 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
75 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
76 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
77 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
80 cpu_axi_bus: cpu_axi_bus {
81 compatible = "rockchip,cpu_axi_bus";
91 reg = <0xffa80000 0x20>;
94 reg = <0xffa80080 0x20>;
97 reg = <0xffa80100 0x20>;
101 reg = <0xffa90000 0x20>;
104 reg = <0xffa90080 0x20>;
107 reg = <0xffa90100 0x20>;
110 reg = <0xffa90180 0x20>;
113 reg = <0xffa90200 0x20>;
117 reg = <0xffaa0000 0x20>;
120 reg = <0xffaa0080 0x20>;
124 reg = <0xffab0000 0x20>;
128 reg = <0xffad0000 0x20>;
129 rockchip,priority = <2 2>;
132 reg = <0xffad0100 0x20>;
135 reg = <0xffad0180 0x20>;
138 reg = <0xffad0400 0x20>;
139 rockchip,priority = <2 2>;
142 reg = <0xffad0480 0x20>;
145 reg = <0xffad0500 0x20>;
148 reg = <0xffad0800 0x20>;
151 reg = <0xffad0880 0x20>;
154 reg = <0xffad0900 0x20>;
158 reg = <0xffae0000 0x20>;
162 reg = <0xffaf0000 0x20>;
165 reg = <0xffaf0080 0x20>;
169 #address-cells = <1>;
173 reg = <0xffac0000 0x40>;
174 rockchip,read-latency = <0xff>;
177 reg = <0xffac0080 0x40>;
178 rockchip,read-latency = <0xff>;
183 sram: sram@ff710000 {
184 compatible = "mmio-sram";
185 reg = <0xff710000 0x8000>; /* 32k */
190 compatible = "arm,armv7-timer";
191 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
192 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
193 clock-frequency = <24000000>;
197 compatible = "rockchip,timer";
198 reg = <0xff810000 0x20>;
199 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
200 rockchip,broadcast = <1>;
203 watchdog:wdt@2004c000 {
204 compatible = "rockchip,watch dog";
205 reg = <0xff800000 0x100>;
206 clocks = <&pclk_pd_alive>;
207 clock-names = "pclk_wdt";
208 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
210 rockchip,timeout = <60>;
211 rockchip,atboot = <1>;
212 rockchip,debug = <0>;
217 #address-cells = <1>;
219 compatible = "arm,amba-bus";
220 interrupt-parent = <&gic>;
223 pdma0: pdma@ffb20000 {
224 compatible = "arm,pl330", "arm,primecell";
225 reg = <0xffb20000 0x4000>;
226 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
227 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
231 pdma1: pdma@ff250000 {
232 compatible = "arm,pl330", "arm,primecell";
233 reg = <0xff250000 0x4000>;
234 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
235 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
241 nandc0: nandc@0xff400000 {
242 compatible = "rockchip,rk-nandc";
243 reg = <0xff400000 0x4000>;
244 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;/*irq=70*/
246 clocks = <&clk_nandc0>, <&clk_gates5 5>, <&clk_gates7 14>;
247 clock-names = "clk_nandc", "g_clk_nandc","hclk_nandc";
251 nandc1: nandc@0xff410000 {
252 compatible = "rockchip,rk-nandc";
253 reg = <0xff410000 0x4000>;
254 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; /*irq=72*/
256 clocks = <&clk_nandc1>, <&clk_gates5 6>, <&clk_gates7 15>;
257 clock-names = "clk_nandc","g_clk_nandc","hclk_nandc";
261 emmc: rksdmmc@ff0f0000 {
262 compatible = "rockchip,rk_mmc","rockchip,rk32xx-sdmmc";
263 reg = <0xff0f0000 0x4000>;
264 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;/*irq=67*/
265 #address-cells = <1>;
267 //pinctrl-names = "default",,"suspend";
268 //pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_wp &sd0_pwr &sd0_bus1 &sd0_bus4>;
270 clocks = <&clk_emmc>, <&clk_gates8 6>;
271 clock-names = "clk_mmc", "hclk_mmc";
273 fifo-depth = <0x100>;
277 sdmmc: rksdmmc@ff0c0000 {
278 compatible = "rockchip,rk_mmc","rockchip,rk32xx-sdmmc";
279 reg = <0xff0c0000 0x4000>;
280 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; /*irq=64*/
281 #address-cells = <1>;
284 pinctrl-names = "default","idle";
285 pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_dectn &sdmmc0_bus4>;
286 pinctrl-1 = <&sdmmc0_gpio>;
288 clocks = <&clk_sdmmc>, <&clk_gates8 3>;
289 clock-names = "clk_mmc", "hclk_mmc";
291 fifo-depth = <0x100>;
296 sdio: rksdmmc@ff0d0000 {
297 compatible = "rockchip,rk_mmc","rockchip,rk32xx-sdmmc";
298 reg = <0xff0d0000 0x4000>;
299 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
300 #address-cells = <1>;
302 pinctrl-names = "default","idle";
303 pinctrl-0 = <&sdio0_clk &sdio0_cmd &sdio0_wrprt &sdio0_pwr &sdio0_bkpwr
304 &sdio0_intn &sdio0_bus4>;
305 pinctrl-1 = <&sdio0_gpio>;
307 clocks = <&clk_sdio0>, <&clk_gates8 4>;
308 clock-names = "clk_mmc", "hclk_mmc";
311 fifo-depth = <0x100>;
315 sdio1: rksdmmc@ff0e0000 {
316 compatible = "rockchip,rk_mmc","rockchip,rk32xx-sdmmc";
317 reg = <0xff0e0000 0x4000>;
318 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
319 #address-cells = <1>;
321 //pinctrl-names = "default","suspend";
322 //pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_cd &sd1_wp &sd1_bus1 &sd1_bus4>;
324 /*gate8_0 --hclk_sdmmc_ahb_arbi_gate_en, gate13_2 --clk_sdio1_src_gate_en*/
325 clocks = <&clk_sdio1>, <&clk_gates8 5>;
326 clock-names = "clk_mmc", "hclk_mmc";
329 fifo-depth = <0x100>;
335 compatible = "rockchip,rockchip-spi";
336 reg = <0xff110000 0x1000>;
337 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
338 #address-cells = <1>;
340 pinctrl-names = "default";
341 pinctrl-0 = <&spi0_txd &spi0_rxd &spi0_clk &spi0_cs0 &spi0_cs1>;
342 rockchip,spi-src-clk = <0>;
344 clocks =<&clk_spi0>, <&clk_gates6 4>;
345 clock-names = "spi","pclk_spi0";
346 //dmas = <&pdma1 11>, <&pdma1 12>;
348 //dma-names = "tx", "rx";
353 compatible = "rockchip,rockchip-spi";
354 reg = <0xff120000 0x1000>;
355 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
356 #address-cells = <1>;
358 pinctrl-names = "default";
359 pinctrl-0 = <&spi1_txd &spi1_rxd &spi1_clk &spi1_cs0>;
360 rockchip,spi-src-clk = <1>;
362 clocks = <&clk_spi1>, <&clk_gates6 5>;
363 clock-names = "spi","pclk_spi1";
364 //dmas = <&pdma1 13>, <&pdma1 14>;
366 //dma-names = "tx", "rx";
371 compatible = "rockchip,rockchip-spi";
372 reg = <0xff130000 0x1000>;
373 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
374 #address-cells = <1>;
376 pinctrl-names = "default";
377 pinctrl-0 = <&spi2_txd &spi2_rxd &spi2_clk &spi2_cs0 &spi2_cs1>;
378 rockchip,spi-src-clk = <2>;
380 clocks = <&clk_spi2>, <&clk_gates6 6>;
381 clock-names = "spi","pclk_spi2";
382 //dmas = <&pdma1 15>, <&pdma1 16>;
384 //dma-names = "tx", "rx";
388 uart_bt: serial@ff180000 {
389 compatible = "rockchip,serial";
390 reg = <0xff180000 0x100>;
391 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
392 clock-frequency = <24000000>;
393 clocks = <&clk_uart0>, <&clk_gates6 8>;
394 clock-names = "sclk_uart", "pclk_uart";
397 dmas = <&pdma1 1>, <&pdma1 2>;
399 pinctrl-names = "default";
400 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
404 uart_bb: serial@ff190000 {
405 compatible = "rockchip,serial";
406 reg = <0xff190000 0x100>;
407 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
408 clock-frequency = <24000000>;
409 clocks = <&clk_uart1>, <&clk_gates6 9>;
410 clock-names = "sclk_uart", "pclk_uart";
413 dmas = <&pdma1 3>, <&pdma1 4>;
415 pinctrl-names = "default";
416 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
420 uart_dbg: serial@ff690000 {
421 compatible = "rockchip,serial";
422 reg = <0xff690000 0x100>;
423 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
424 clock-frequency = <24000000>;
425 clocks = <&clk_uart2>, <&clk_gates11 9>;
426 clock-names = "sclk_uart", "pclk_uart";
429 dmas = <&pdma0 4>, <&pdma0 5>;
431 pinctrl-names = "default";
432 pinctrl-0 = <&uart2_xfer>;
436 uart_gps: serial@ff1b0000 {
437 compatible = "rockchip,serial";
438 reg = <0xff1b0000 0x100>;
439 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
440 clock-frequency = <24000000>;
441 clocks = <&clk_uart3>, <&clk_gates6 11>;
442 clock-names = "sclk_uart", "pclk_uart";
443 current-speed = <115200>;
446 dmas = <&pdma1 7>, <&pdma1 8>;
448 pinctrl-names = "default";
449 pinctrl-0 = <&uart3_xfer &uart3_cts &uart3_rts>;
453 uart_exp: serial@ff1c0000 {
454 compatible = "rockchip,serial";
455 reg = <0xff1c0000 0x100>;
456 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
457 clock-frequency = <24000000>;
458 clocks = <&clk_uart4>, <&clk_gates6 12>;
459 clock-names = "sclk_uart", "pclk_uart";
462 dmas = <&pdma1 9>, <&pdma1 10>;
464 pinctrl-names = "default";
465 pinctrl-0 = <&uart4_xfer &uart4_cts &uart4_rts>;
470 compatible = "rockchip,fiq-debugger";
471 rockchip,serial-id = <2>;
472 rockchip,signal-irq = <106>;
473 rockchip,wake-irq = <0>;
478 compatible = "rockchip,clocks-init";
479 rockchip,clocks-init-parent =
480 <&clk_core &clk_apll>, <&aclk_bus_src &clk_gpll>,
481 <&aclk_peri &clk_gpll>, <&uart_pll_mux &clk_gpll>,
482 <&clk_i2s_pll &clk_gpll>, <&clk_spdif_pll &clk_gpll>,
483 <&usbphy_480m &otgphy2_480m>;
484 rockchip,clocks-init-rate =
485 <&clk_core 792000000>, <&clk_gpll 297000000>,
486 /*<&clk_cpll 47000000>,*/ <&clk_npll 1250000000>,
487 <&aclk_bus_src 300000000>, <&aclk_bus 300000000>,
488 <&hclk_bus 150000000>, <&pclk_bus 75000000>,
489 <&clk_crypto 150000000>, <&aclk_peri 300000000>,
490 <&hclk_peri 150000000>, <&pclk_peri 75000000>,
491 <&clk_gpu 200000000>, <&aclk_vio0 300000000>,
492 <&aclk_vio1 300000000>, <&hclk_vio 75000000>,
493 <&pclk_pd_alive 100000000>, <&pclk_pd_pmu 100000000>,
494 <&aclk_hevc 400000000>, <&hclk_hevc 200000000>,
495 <&clk_hevc_cabac 300000000>, <&clk_hevc_core 300000000>,
496 <&aclk_rga 300000000>, <&clk_rga 300000000>,
497 <&clk_vepu 300000000>, <&clk_vdpu 300000000>,
498 <&clk_edp 200000000>, <&clk_isp 200000000>,
499 <&clk_isp_jpe 400000000>, <&clk_tsp 80000000>,
500 <&clk_tspout 80000000>, <&clk_mac 125000000>;
504 compatible = "rockchip,clocks-enable";
507 <&clk_gates0 2>, <&clk_core0>,
508 <&clk_core1>, <&clk_core2>,
509 <&clk_core3>, <&clk_l2ram>,
510 <&aclk_core_m0>, <&aclk_core_mp>,
511 <&atclk_core>, <&pclk_dbg_src>,
512 <&clk_gates12 9>, <&clk_gates12 10>,
516 <&aclk_bus>, <&clk_gates0 3>,
517 <&hclk_bus>, <&pclk_bus>,
518 <&clk_gates13 8>, <&clk_crypto>,
522 <&clk_gates1 0>, <&clk_gates1 1>,
523 <&clk_gates1 2>, <&clk_gates1 3>,
524 <&clk_gates1 4>, <&clk_gates1 5>,
526 <&pclk_pd_alive>, <&pclk_pd_pmu>,
529 <&aclk_peri>, <&hclk_peri>,
533 /*<&clk_gates4 14>,*/
536 <&clk_gates10 5>,/*aclk_intmem0*/
537 <&clk_gates10 6>,/*aclk_intmem1*/
538 <&clk_gates10 7>,/*aclk_intmem2*/
539 <&clk_gates10 12>,/*aclk_dma1*/
540 <&clk_gates10 13>,/*aclk_strc_sys*/
541 <&clk_gates10 4>,/*aclk_intmem*/
542 <&clk_gates11 6>,/*aclk_crypto*/
543 <&clk_gates11 8>,/*aclk_ccp*/
546 <&clk_gates11 7>,/*hclk_crypto*/
547 <&clk_gates10 9>,/*hclk_rom*/
550 <&clk_gates10 1>,/*pclk_timer*/
551 <&clk_gates10 9>,/*rom*/
552 <&clk_gates10 13>,/*aclk strc*/
554 <&clk_gates12 8>,/*aclk strc*/
557 <&clk_gates6 2>,/*aclk_peri_axi_matrix*/
558 <&clk_gates6 3>,/*aclk_dmac2*/
559 <&clk_gates7 11>,/*aclk_peri_niu*/
560 <&clk_gates8 12>,/*aclk_peri_mmu*/
563 <&clk_gates6 0>,/*hclk_peri_matrix*/
564 <&clk_gates7 10>,/*hclk_peri_ahb_arbi*/
565 <&clk_gates7 12>,/*hclk_emem_peri*/
566 <&clk_gates7 13>,/*hclk_mem_peri*/
569 <&clk_gates6 1>,/*pclk_peri_axi_matrix*/
572 <&clk_gates14 11>,/*pclk_grf*/
573 <&clk_gates14 12>,/*pclk_alive_niu*/
576 <&clk_gates17 0>,/*pclk_pmu*/
577 <&clk_gates17 1>,/*pclk_intmem1*/
578 <&clk_gates17 2>,/*pclk_pmu_niu*/
579 <&clk_gates17 3>,/*pclk_sgrf*/
582 <&clk_gates15 9>,/*hclk_vio_ahb_arbi*/
583 <&clk_gates15 10>,/*hclk_vio_niu*/
584 <&clk_gates16 10>,/*hclk_vio2_h2p*/
585 <&clk_gates16 11>,/*pclk_vio2_h2p*/
588 <&clk_gates15 11>,/*aclk_vio0_niu*/
591 <&clk_gates15 12>,/*aclk_vio1_niu*/
594 //<&clk_gates5 12>,/*hdmi_hdcp_clk*/
597 <&clk_gates11 9>,/*pclk_uart2*/
604 compatible = "rockchip,rk30-i2c";
605 reg = <0xff650000 0x1000>;
606 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
607 #address-cells = <1>;
609 pinctrl-names = "default", "gpio";
610 pinctrl-0 = <&i2c0_sda &i2c0_scl>;
611 pinctrl-1 = <&i2c0_gpio>;
612 gpios = <&gpio0 GPIO_B7 GPIO_ACTIVE_LOW>, <&gpio0 GPIO_C0 GPIO_ACTIVE_LOW>;
613 clocks = <&clk_gates10 2>;
614 rockchip,check-idle = <1>;
619 compatible = "rockchip,rk30-i2c";
620 reg = <0xff140000 0x1000>;
621 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
622 #address-cells = <1>;
624 pinctrl-names = "default", "gpio";
625 pinctrl-0 = <&i2c1_sda &i2c1_scl>;
626 pinctrl-1 = <&i2c1_gpio>;
627 gpios = <&gpio8 GPIO_A4 GPIO_ACTIVE_LOW>, <&gpio8 GPIO_A5 GPIO_ACTIVE_LOW>;
628 clocks = <&clk_gates10 3>;
629 rockchip,check-idle = <1>;
634 compatible = "rockchip,rk30-i2c";
635 reg = <0xff660000 0x1000>;
636 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
637 #address-cells = <1>;
639 pinctrl-names = "default", "gpio";
640 pinctrl-0 = <&i2c2_sda &i2c2_scl>;
641 pinctrl-1 = <&i2c2_gpio>;
642 gpios = <&gpio6 GPIO_B1 GPIO_ACTIVE_LOW>, <&gpio6 GPIO_B2 GPIO_ACTIVE_LOW>;
643 clocks = <&clk_gates6 13>;
644 rockchip,check-idle = <1>;
649 compatible = "rockchip,rk30-i2c";
650 reg = <0xff150000 0x1000>;
651 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
652 #address-cells = <1>;
654 pinctrl-names = "default", "gpio";
655 pinctrl-0 = <&i2c3_sda &i2c3_scl>;
656 pinctrl-1 = <&i2c3_gpio>;
657 gpios = <&gpio2 GPIO_C1 GPIO_ACTIVE_LOW>, <&gpio2 GPIO_C0 GPIO_ACTIVE_LOW>;
658 clocks = <&clk_gates6 14>;
659 rockchip,check-idle = <1>;
664 compatible = "rockchip,rk30-i2c";
665 reg = <0xff160000 0x1000>;
666 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
667 #address-cells = <1>;
669 pinctrl-names = "default", "gpio";
670 pinctrl-0 = <&i2c4_sda &i2c4_scl>;
671 pinctrl-1 = <&i2c4_gpio>;
672 gpios = <&gpio7 GPIO_C1 GPIO_ACTIVE_LOW>, <&gpio7 GPIO_C2 GPIO_ACTIVE_LOW>;
673 clocks = <&clk_gates6 15>;
674 rockchip,check-idle = <1>;
679 compatible = "rockchip,rk30-i2c";
680 reg = <0xff170000 0x1000>;
681 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
682 #address-cells = <1>;
684 pinctrl-names = "default", "gpio";
685 pinctrl-0 = <&i2c5_sda &i2c5_scl>;
686 pinctrl-1 = <&i2c5_gpio>;
687 gpios = <&gpio7 GPIO_C3 GPIO_ACTIVE_LOW>, <&gpio7 GPIO_C4 GPIO_ACTIVE_LOW>;
688 clocks = <&clk_gates7 0>;
689 rockchip,check-idle = <1>;
695 compatible = "rockchip,rk-fb";
696 rockchip,disp-mode = <DUAL>;
699 rk_screen: rk_screen{
700 compatible = "rockchip,screen";
703 dsihost0: mipi@ff960000{
704 compatible = "rockchip,rk32-dsi";
706 reg = <0xff960000 0x4000>;
707 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
708 clocks = <&clk_gates5 15>, <&clk_gates16 4> , <&pd_mipidsi>;
709 clock-names = "clk_mipi_24m", "pclk_mipi_dsi", "pd_mipi_dsi";
713 dsihost1: mipi@ff964000{
714 compatible = "rockchip,rk32-dsi";
716 reg = <0xff964000 0x4000>;
717 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
718 clocks = <&clk_gates5 15>, <&clk_gates16 5>, <&pd_mipidsi>;
719 clock-names = "clk_mipi_24m", "pclk_mipi_dsi", "pd_mipi_dsi";
723 lvds: lvds@ff96c000 {
724 compatible = "rockchip,rk32-lvds";
725 reg = <0xff96c000 0x4000>;
726 clocks = <&clk_gates16 7>;
727 clock-names = "pclk_lvds";
731 compatible = "rockchip,rk32-edp";
732 reg = <0xff970000 0x4000>;
733 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
734 clocks = <&clk_edp>, <&clk_edp_24m>, <&clk_gates16 8>;
735 clock-names = "clk_edp", "clk_edp_24m", "pclk_edp";
738 hdmi: hdmi@ff980000 {
739 compatible = "rockchip,rk3288-hdmi";
740 reg = <0xff980000 0x20000>;
741 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
742 pinctrl-names = "default", "gpio";
743 pinctrl-0 = <&i2c5_sda &i2c5_scl>;
744 pinctrl-1 = <&i2c5_gpio>;
745 clocks = <&clk_gates16 9>, <&clk_gates5 12>;
746 clock-names = "pclk_hdmi", "hdcp_clk_hdmi";
750 lcdc1: lcdc@ff940000 {
751 compatible = "rockchip,rk3288-lcdc";
752 rockchip,prop = <PRMRY>;
753 rochchip,pwr18 = <0>;
754 reg = <0xff940000 0x10000>;
755 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
756 pinctrl-names = "default", "gpio";
757 pinctrl-0 = <&lcdc0_lcdc>;
758 pinctrl-1 = <&lcdc0_gpio>;
760 clocks = <&clk_gates15 7>, <&dclk_lcdc1>, <&clk_gates15 8>, <&pd_vop1>;
761 clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc", "pd_lcdc";
764 lcdc0: lcdc@ff930000 {
765 compatible = "rockchip,rk3288-lcdc";
766 rockchip,prop = <EXTEND>;
767 rockchip,pwr18 = <0>;
768 reg = <0xff930000 0x10000>;
769 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
770 //pinctrl-names = "default", "gpio";
771 //pinctrl-0 = <&lcdc0_lcdc>;
772 //pinctrl-1 = <&lcdc0_gpio>;
774 clocks = <&clk_gates15 5>, <&dclk_lcdc0>, <&clk_gates15 6>, <&pd_vop0>;
775 clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc", "pd_lcdc";
779 compatible = "rockchip,saradc";
780 reg = <0xff100000 0x100>;
781 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
782 #io-channel-cells = <1>;
784 rockchip,adc-vref = <1800>;
785 clock-frequency = <1000000>;
786 clocks = <&clk_saradc>, <&clk_gates7 1>;
787 clock-names = "saradc", "pclk_saradc";
792 compatible = "rockchip,rga";
793 reg = <0xff920000 0x1000>;
794 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
795 clocks = <&clk_gates15 1>, <&aclk_rga>, <&clk_rga>;
796 clock-names = "hclk_rga", "aclk_rga", "clk_rga";
799 i2s: rockchip-i2s@0xff890000 {
800 compatible = "rockchip-i2s";
801 reg = <0xff890000 0x10000>;
803 clocks = <&clk_i2s>, <&clk_i2s_out>, <&clk_gates10 8>;
804 clock-names = "i2s_clk","i2s_mclk", "i2s_hclk";
805 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
809 dma-names = "tx", "rx";
810 pinctrl-names = "default", "sleep";
811 pinctrl-0 = <&i2s_mclk &i2s_sclk &i2s_lrckrx &i2s_lrcktx &i2s_sdi &i2s_sdo0 &i2s_sdo1 &i2s_sdo2 &i2s_sdo3>;
812 pinctrl-1 = <&i2s_gpio>;
815 spdif: rockchip-spdif@0xff8b0000 {
816 compatible = "rockchip-spdif";
817 reg = <0xff8b0000 0x10000>; //8channel
818 //reg = <ff880000 0x10000>;//2channel
819 clocks = <&clk_spdif>, <&clk_spdif_8ch>;
820 clock-names = "spdif_mclk","spdif_8ch_mclk";
821 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
823 //dmas = <&pdma0 2>; //2channel
826 pinctrl-names = "default";
827 pinctrl-0 = <&spdif_tx>;
830 vop1pwm: pwm@ff9401a0 {
831 compatible = "rockchip,vop-pwm";
832 reg = <0xff9401a0 0x10>;
834 pinctrl-names = "default";
835 pinctrl-0 = <&vop1_pwm_pin>;
836 clocks = <&clk_gates13 11>;
837 clock-names = "pclk_pwm";
841 vop0pwm: pwm@ff9301a0 {
842 compatible = "rockchip,vop-pwm";
843 reg = <0xff9301a0 0x10>;
845 pinctrl-names = "default";
846 pinctrl-0 = <&vop0_pwm_pin>;
847 clocks = <&clk_gates13 10>;
848 clock-names = "pclk_pwm";
853 compatible = "rockchip,rk-pwm";
854 reg = <0xff680000 0x10>;
856 pinctrl-names = "default";
857 pinctrl-0 = <&pwm0_pin>;
858 clocks = <&clk_gates11 11>;
859 clock-names = "pclk_pwm";
864 compatible = "rockchip,rk-pwm";
865 reg = <0xff680010 0x10>;
867 pinctrl-names = "default";
868 pinctrl-0 = <&pwm1_pin>;
869 clocks = <&clk_gates11 11>;
870 clock-names = "pclk_pwm";
875 compatible = "rockchip,rk-pwm";
876 reg = <0xff680020 0x10>;
878 pinctrl-names = "default";
879 pinctrl-0 = <&pwm2_pin>;
880 clocks = <&clk_gates11 11>;
881 clock-names = "pclk_pwm";
886 compatible = "rockchip,rk-pwm";
887 reg = <0xff680030 0x10>;
889 pinctrl-names = "default";
890 pinctrl-0 = <&pwm3_pin>;
891 clocks = <&clk_gates11 11>;
892 clock-names = "pclk_pwm";
896 temp-limit-enable=<1>;
901 regulator_name="vdd_arm";
902 suspend_volt=<1000>; //mV
914 normal-temp-limit = <
915 /*delta-temp delta-freq*/
921 performance-temp-limit = <
932 regulator_name="vdd_logic";
933 suspend_volt=<1000>; //mV
963 regulator_name="vdd_gpu";
964 suspend_volt=<1000>; //mV
989 compatible = "rockchip,ion";
990 #address-cells = <1>;
992 rockchip,ion-heap@1 { /* CMA HEAP */
993 compatible = "rockchip,ion-reserve";
994 rockchip,ion_heap = <1>;
995 reg = <0x00000000 0x20000000>; /* 512MB */
997 rockchip,ion-heap@3 { /* VMALLOC HEAP */
998 rockchip,ion_heap = <3>;
1003 vpu: vpu_service@ff9a0000 {
1004 compatible = "vpu_service";
1005 reg = <0xff9a0000 0x800>;
1006 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1007 interrupt-names = "irq_enc", "irq_dec";
1008 clocks = <&clk_vdpu>, <&hclk_vdpu>;
1009 clock-names = "aclk_vcodec", "hclk_vcodec";
1010 name = "vpu_service";
1011 //status = "disabled";
1014 hevc: hevc_service@ff9c0000 {
1015 compatible = "rockchip,hevc_service";
1016 reg = <0xff9c0000 0x800>;
1017 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
1018 interrupt-names = "irq_dec";
1019 clocks = <&aclk_hevc>, <&hclk_hevc>, <&clk_hevc_core>, <&clk_hevc_cabac>;
1020 clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core", "clk_cabac";
1021 name = "hevc_service";
1022 //status = "disabled";
1026 compatible = "rockchip,iep";
1027 reg = <0xff900000 0x800>;
1028 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1029 clocks = <&clk_gates15 2>, <&clk_gates15 3>;
1030 clock-names = "aclk_iep", "hclk_iep";
1034 dwc_control_usb: dwc-control-usb@ff770284 {
1035 compatible = "rockchip,rk3288-dwc-control-usb";
1036 reg = <0xff770284 0x04>, <0xff770288 0x04>,
1037 <0xff7702cc 0x04>, <0xff7702d4 0x04>,
1038 <0xff770320 0x14>, <0xff770334 0x14>,
1039 <0xff770348 0x10>, <0xff770358 0x08>,
1041 reg-names = "GRF_SOC_STATUS1" ,"GRF_SOC_STATUS2",
1042 "GRF_SOC_STATUS19", "GRF_SOC_STATUS21",
1043 "GRF_UOC0_BASE", "GRF_UOC1_BASE",
1044 "GRF_UOC2_BASE", "GRF_UOC3_BASE",
1046 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
1047 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
1048 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
1049 interrupt-names = "otg_id", "otg_bvalid",
1050 "otg_linestate", "host0_linestate",
1052 clocks = <&clk_gates7 9>, <&usbphy_480m>,
1053 <&otgphy1_480m>, <&otgphy2_480m>;
1054 clock-names = "hclk_usb_peri", "usbphy_480m",
1055 "usbphy1_480m", "usbphy2_480m";
1058 compatible = "synopsys,phy";
1059 /* offset bit mask */
1060 rk_usb,bvalid = <0x288 14 1>;
1061 rk_usb,dcdenb = <0x328 14 1>;
1062 rk_usb,vdatsrcenb = <0x328 7 1>;
1063 rk_usb,vdatdetenb = <0x328 6 1>;
1064 rk_usb,chrgsel = <0x328 5 1>;
1065 rk_usb,chgdet = <0x2cc 23 1>;
1066 rk_usb,fsvminus = <0x2cc 25 1>;
1067 rk_usb,fsvplus = <0x2cc 24 1>;
1071 usb0: usb@ff580000 {
1072 compatible = "rockchip,rk3288_usb20_otg";
1073 reg = <0xff580000 0x40000>;
1074 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
1075 clocks = <&clk_gates13 4>, <&clk_gates7 4>;
1076 clock-names = "clk_usbphy0", "hclk_usb0";
1077 /*0 - Normal, 1 - Force Host, 2 - Force Device*/
1078 rockchip,usb-mode = <0>;
1081 usb1: usb@ff540000 {
1082 compatible = "rockchip,rk3288_usb20_host";
1083 reg = <0xff540000 0x40000>;
1084 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
1085 clocks = <&clk_gates13 6>, <&clk_gates7 7>,
1087 clock-names = "clk_usbphy1", "hclk_usb1",
1091 usb2: usb@ff500000 {
1092 compatible = "rockchip,rk3288_rk_ehci_host";
1093 reg = <0xff500000 0x20000>;
1094 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
1095 clocks = <&clk_gates13 5>, <&clk_gates7 6>;
1096 clock-names = "clk_usbphy2", "hclk_usb2";
1099 usb3: usb@ff520000 {
1100 compatible = "rockchip,rk3288_rk_ohci_host";
1101 reg = <0xff520000 0x20000>;
1102 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
1103 clocks = <&clk_gates13 5>, <&clk_gates7 6>;
1104 clock-names = "clk_usbphy3", "hclk_usb3";
1107 hsic: hsic@ff5c0000 {
1108 compatible = "rockchip,rk3288_rk_hsic_host";
1109 reg = <0xff5c0000 0x40000>;
1110 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
1111 clocks = <&hsicphy_480m>, <&clk_gates7 8>,
1112 <&hsicphy_12m>, <&usbphy_480m>,
1113 <&otgphy1_480m>, <&otgphy2_480m>;
1114 clock-names = "hsicphy_480m", "hclk_hsic",
1115 "hsicphy_12m", "usbphy_480m",
1116 "hsic_usbphy1", "hsic_usbphy2";
1119 gmac: eth@ff290000 {
1120 compatible = "rockchip,gmac";
1121 reg = <0xff290000 0x10000>;
1122 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; /*irq=59*/
1123 interrupt-names = "macirq";
1124 clocks = <&clk_mac>, <&clk_gates5 0>,
1125 <&clk_gates5 1>, <&clk_gates5 2>,
1126 <&clk_gates5 3>, <&clk_gates8 0>,
1128 clock-names = "clk_mac", "mac_clk_rx",
1129 "mac_clk_tx", "clk_mac_ref",
1130 "clk_mac_refout", "aclk_mac",
1132 //phy-mode = "rmii";
1134 pinctrl-names = "default";
1135 pinctrl-0 = <&mac_clk &mac_txpins &mac_rxpins &mac_mdpins>;
1138 compatible = "arm,malit764",
1142 reg = <0xffa30000 0x10000>;
1143 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
1144 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
1145 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1146 interrupt-names = "JOB",
1153 compatible = "iommu,iep_mmu";
1154 reg = <0xff900800 0x100>;
1155 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1156 interrupt-names = "iep_mmu";
1161 compatible = "iommu,vip_mmu";
1162 reg = <0xff950800 0x100>;
1163 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
1164 interrupt-names = "vip_mmu";
1168 compatible = "iommu,vopb_mmu";
1169 reg = <0xff930300 0x100>;
1170 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1171 interrupt-names = "vopb_mmu";
1176 compatible = "iommu,vopl_mmu";
1177 reg = <0xff940300 0x100>;
1178 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1179 interrupt-names = "vopl_mmu";
1184 compatible = "iommu,hevc_mmu";
1185 reg = <0xff9c0440 0x100>,
1187 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
1188 interrupt-names = "hevc_mmu";
1193 compatible = "iommu,vpu_mmu";
1194 reg = <0xff9a0800 0x100>;
1195 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
1196 interrupt-names = "vpu_mmu";
1200 dbgname = "isp_mmu";
1201 compatible = "iommu,isp_mmu";
1202 reg = <0xff914000 0x100>,
1204 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1205 interrupt-names = "isp_mmu";
1210 rockchip,ctrbits = <
1215 //|RKPM_CTR_SYSCLK_DIV
1216 //|RKPM_CTR_IDLEAUTO_MD
1217 // |RKPM_CTR_ARMOFF_LPMD
1218 |RKPM_CTR_ARMOFF_LOGDP_LPMD
1221 rockchip,pmic-gpios=<
1222 RKPM_PINGPIO_BITS_OUTPUT(GPIO0_A0,RKPM_GPIO_OUT_L)
1223 RKPM_PINGPIO_BITS_INTPUT(GPIO0_A1,RKPM_GPIO_PULL_UP)
1228 compatible = "rockchip,isp";
1229 reg = <0xff910000 0x10000>;
1230 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1231 clocks = <&clk_gates16 2>, <&clk_gates16 1>, <&clk_isp>, <&clk_isp_jpe>, <&clkin_isp>, <&clk_cif_out>,<&clk_gates5 15>,<&clk_cif_pll>,<&pd_isp>,<&clk_gates16 6>;
1232 clock-names = "aclk_isp", "hclk_isp", "clk_isp", "clk_isp_jpe", "pclkin_isp", "clk_cif_out","clk_mipi_24m","clk_cif_pll","pd_isp","hclk_mipiphy1";
1233 pinctrl-names = "default", "isp_dvp8bit2","isp_dvp10bit","isp_dvp12bit","isp_dvp8bit0","isp_mipi_fl","isp_mipi_fl_prefl";
1234 pinctrl-0 = <&isp_mipi>;
1235 pinctrl-1 = <&isp_mipi &isp_dvp_d2d9>;
1236 pinctrl-2 = <&isp_mipi &isp_dvp_d2d9 &isp_dvp_d0d1>;
1237 pinctrl-3 = <&isp_mipi &isp_dvp_d2d9 &isp_dvp_d0d1 &isp_dvp_d10d11>;
1238 pinctrl-4 = <&isp_mipi &isp_dvp_d0d7>;
1239 pinctrl-5 = <&isp_mipi &isp_flash_trigger>;
1240 pinctrl-6 = <&isp_mipi &isp_flash_trigger &isp_prelight>;
1242 rockchip,isp,mipiphy = <2>;
1243 rockchip,isp,cifphy = <1>;
1245 rockchip,isp,mipiphy1,reg = <0xff968000 0x4000>;
1249 tsadc: tsadc@ff280000{
1250 compatible = "rockchip,tsadc";
1251 reg = <0xff280000 0x100>;
1252 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
1253 #io-channel-cells = <1>;
1255 clock-frequency = <50000>;
1256 clocks = <&clk_tsadc>, <&clk_gates7 2>;
1257 clock-names = "tsadc", "pclk_tsadc";
1261 lcdc_vdd_domain: lcdc-vdd-domain{
1262 compatible = "rockchip,io_vol_domain";
1263 pinctrl-names = "default", "1.8V", "3.3V";
1264 pinctrl-0 = <&lcdc_vcc>;
1265 pinctrl-1 = <&lcdc_vcc_18>;
1266 pinctrl-2 = <&lcdc_vcc_33>;
1268 dpio_vdd_domain: dpio-vdd-domain{
1269 compatible = "rockchip,io_vol_domain";
1270 pinctrl-names = "default", "1.8V", "3.3V";
1271 pinctrl-0 = <&dvp_vcc>;
1272 pinctrl-1 = <&dvp_vcc_18>;
1273 pinctrl-2 = <&dvp_vcc_33>;
1275 flash0_vdd_domain: flash0-vdd-domain{
1276 compatible = "rockchip,io_vol_domain";
1277 pinctrl-names = "default", "1.8V", "3.3V";
1278 pinctrl-0 = <&flash0_vcc>;
1279 pinctrl-1 = <&flash0_vcc_18>;
1280 pinctrl-2 = <&flash0_vcc_33>;
1282 flash1_vdd_domain: flash1-vdd-domain{
1283 compatible = "rockchip,io_vol_domain";
1284 pinctrl-names = "default", "1.8V", "3.3V";
1285 pinctrl-0 = <&flash1_vcc>;
1286 pinctrl-1 = <&flash1_vcc_18>;
1287 pinctrl-2 = <&flash1_vcc_33>;
1289 apio3_vdd_domain: apio3-vdd-domain{
1290 compatible = "rockchip,io_vol_domain";
1291 pinctrl-names = "default", "1.8V", "3.3V";
1292 pinctrl-0 = <&wifi_vcc>;
1293 pinctrl-1 = <&wifi_vcc_18>;
1294 pinctrl-2 = <&wifi_vcc_33>;
1296 apio5_vdd_domain: apio5-vdd-domain{
1297 compatible = "rockchip,io_vol_domain";
1298 pinctrl-names = "default", "1.8V", "3.3V";
1299 pinctrl-0 = <&bb_vcc>;
1300 pinctrl-1 = <&bb_vcc_18>;
1301 pinctrl-2 = <&bb_vcc_33>;
1303 apio4_vdd_domain: apio4-vdd-domain{
1304 compatible = "rockchip,io_vol_domain";
1305 pinctrl-names = "default", "1.8V", "3.3V";
1306 pinctrl-0 = <&audio_vcc>;
1307 pinctrl-1 = <&audio_vcc_18>;
1308 pinctrl-2 = <&audio_vcc_33>;
1310 apio1_vdd_domain: apio0-vdd-domain{
1311 compatible = "rockchip,io_vol_domain";
1312 pinctrl-names = "default", "1.8V", "3.3V";
1313 pinctrl-0 = <&gpio30_vcc>;
1314 pinctrl-1 = <&gpio30_vcc_18>;
1315 pinctrl-2 = <&gpio30_vcc_33>;
1317 apio2_vdd_domain: apio2-vdd-domain{
1318 compatible = "rockchip,io_vol_domain";
1319 pinctrl-names = "default", "1.8V", "3.3V";
1320 pinctrl-0 = <&gpio1830_vcc>;
1321 pinctrl-1 = <&gpio1830_vcc_18>;
1322 pinctrl-2 = <&gpio1830_vcc_33>;
1324 sdmmc0_vdd_domain: sdmmc0-vdd-domain{
1325 compatible = "rockchip,io_vol_domain";
1326 pinctrl-names = "default", "1.8V", "3.3V";
1327 pinctrl-0 = <&sdcard_vcc>;
1328 pinctrl-1 = <&sdcard_vcc_18>;
1329 pinctrl-2 = <&sdcard_vcc_33>;