arch/arm/boot/dts/rk3288.dtsi

   1 #include <dt-bindings/interrupt-controller/arm-gic.h>
   2 #include "skeleton.dtsi"
   3 #include "rk3288-pinctrl.dtsi"
   4 #include <dt-bindings/rkfb/rk_fb.h>
   5
   6 / {
   7         compatible = "rockchip,rk3288";
   8         interrupt-parent = <&gic>;
   9
  10         aliases {
  11                 serial2 = &uart_dbg;
  12                 i2c0 = &i2c0;
  13                 i2c1 = &i2c1;
  14                 i2c2 = &i2c2;
  15                 i2c3 = &i2c3;
  16                 i2c4 = &i2c4;
  17                 i2c5 = &i2c5;
  18                 lcdc0 = &lcdc0;
  19                 lcdc1 = &lcdc1;
  20         };
  21
  22         cpus {
  23                 #address-cells = <1>;
  24                 #size-cells = <0>;
  25
  26                 cpu@0 {
  27                         device_type = "cpu";
  28                         compatible = "arm,cortex-a15";
  29                         reg = <0x500>;
  30                 };
  31                 cpu@1 {
  32                         device_type = "cpu";
  33                         compatible = "arm,cortex-a15";
  34                         reg = <0x501>;
  35                 };
  36                 cpu@2 {
  37                         device_type = "cpu";
  38                         compatible = "arm,cortex-a15";
  39                         reg = <0x502>;
  40                 };
  41                 cpu@3 {
  42                         device_type = "cpu";
  43                         compatible = "arm,cortex-a15";
  44                         reg = <0x503>;
  45                 };
  46         };
  47
  48         gic: interrupt-controller@ffc01000 {
  49                 compatible = "arm,cortex-a15-gic";
  50                 interrupt-controller;
  51                 #interrupt-cells = <3>;
  52                 #address-cells = <0>;
  53                 reg = <0xffc01000 0x1000>,
  54                       <0xffc02000 0x1000>;
  55         };
  56
  57         sram: sram@ff710000 {
  58                 compatible = "mmio-sram";
  59                 reg = <0xff710000 0x8000>; /* 32k */
  60                 map-exec;
  61         };
  62
  63         timer {
  64                 compatible = "arm,armv7-timer";
  65                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
  66                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
  67                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
  68                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
  69                 clock-frequency = <24000000>;
  70         };
  71
  72         timer@ff810000 {
  73                 compatible = "rockchip,timer";
  74                 reg = <0xff810000 0x20>;
  75                 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
  76                 rockchip,broadcast = <1>;
  77         };
  78
  79         timer@ff810020 {
  80                 compatible = "rockchip,timer";
  81                 reg = <0xff810020 0x20>;
  82                 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
  83                 rockchip,clocksource = <1>;
  84                 rockchip,count-up = <1>;
  85         };
  86
  87         uart_dbg: serial@ff690000 {
  88                 compatible = "rockchip,serial";
  89                 reg = <0xff690000 0x100>;
  90                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
  91                 clock-frequency = <24000000>;
  92                 reg-shift = <2>;
  93                 reg-io-width = <4>;
  94                 status = "disabled";
  95         };
  96
  97         fiq-debugger {
  98                 compatible = "rockchip,fiq-debugger";
  99                 rockchip,serial-id = <2>;
 100                 rockchip,signal-irq = <106>;
 101                 rockchip,wake-irq = <0>;
 102                 status = "disabled";
 103         };
 104
 105         i2c0: i2c@ff650000 {
 106                 compatible = "rockchip,rk30-i2c";
 107                 reg = <0xff650000 0x1000>;
 108                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 109                 #address-cells = <1>;
 110                 #size-cells = <0>;
 111                 //pinctrl-names = "default", "gpio";
 112                 //pinctrl-0 = <&i2c0_sda &i2c0_scl>;
 113                 //pinctrl-1 = <&i2c0_gpio>;
 114                 //gpios = <&gpio0 GPIO_B7 GPIO_ACTIVE_LOW>, <&gpio0 GPIO_C0 GPIO_ACTIVE_LOW>;
 115                 //clocks = <&clk_gates8 4>;
 116                 rockchip,check-idle = <1>;
 117                 status = "disabled";
 118         };
 119
 120         i2c1: i2c@ff140000 {
 121                 compatible = "rockchip,rk30-i2c";
 122                 reg = <0xff140000 0x1000>;
 123                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 124                 #address-cells = <1>;
 125                 #size-cells = <0>;
 126                 //pinctrl-names = "default", "gpio";
 127                 //pinctrl-0 = <&i2c1_sda &i2c1_scl>;
 128                 //pinctrl-1 = <&i2c1_gpio>;
 129                 //gpios = <&gpio8 GPIO_A4 GPIO_ACTIVE_LOW>, <&gpio8 GPIO_A5 GPIO_ACTIVE_LOW>;
 130                 //clocks = <&clk_gates8 5>;
 131         rockchip,check-idle = <1>;
 132         status = "disabled";
 133         };
 134
 135         i2c2: i2c@ff660000 {
 136                 compatible = "rockchip,rk30-i2c";
 137                 reg = <0xff660000 0x1000>;
 138                 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 139                 #address-cells = <1>;
 140                 #size-cells = <0>;
 141                 //pinctrl-names = "default", "gpio";
 142                 //pinctrl-0 = <&i2c2_sda &i2c2_scl>;
 143                 //pinctrl-1 = <&i2c2_gpio>;
 144                 //gpios = <&gpio6 GPIO_B1 GPIO_ACTIVE_LOW>, <&gpio6 GPIO_B2 GPIO_ACTIVE_LOW>;
 145                 //clocks = <&clk_gates8 6>;
 146                 rockchip,check-idle = <1>;
 147                 status = "disabled";
 148         };
 149
 150         i2c3: i2c@ff150000 {
 151                 compatible = "rockchip,rk30-i2c";
 152                 reg = <0xff150000 0x1000>;
 153                 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 154                 #address-cells = <1>;
 155                 #size-cells = <0>;
 156                 //pinctrl-names = "default", "gpio";
 157                 //pinctrl-0 = <&i2c3_sda &i2c3_scl>;
 158                 //pinctrl-1 = <&i2c3_gpio>;
 159                 //gpios = <&gpio2 GPIO_C1 GPIO_ACTIVE_LOW>, <&gpio2 GPIO_C0 GPIO_ACTIVE_LOW>;
 160                 //clocks = <&clk_gates8 7>;
 161                 rockchip,check-idle = <1>;
 162                 status = "disabled";
 163         };
 164
 165         i2c4: i2c@ff160000 {
 166                 compatible = "rockchip,rk30-i2c";
 167                 reg = <0xff160000 0x1000>;
 168                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 169                 #address-cells = <1>;
 170                 #size-cells = <0>;
 171                 //pinctrl-names = "default", "gpio";
 172                 //pinctrl-0 = <&i2c4_sda &i2c4_scl>;
 173                 //pinctrl-1 = <&i2c4_gpio>;
 174                 //gpios = <&gpio7 GPIO_C1 GPIO_ACTIVE_LOW>, <&gpio7 GPIO_C2 GPIO_ACTIVE_LOW>;
 175                 //clocks = <&clk_gates8 8>;
 176                 rockchip,check-idle = <1>;
 177                 status = "disabled";
 178         };
 179
 180         i2c5: i2c@ff170000 {
 181                 compatible = "rockchip,rk30-i2c";
 182                 reg = <0xff170000 0x1000>;
 183                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 184                 #address-cells = <1>;
 185                 #size-cells = <0>;
 186                 //pinctrl-names = "default", "gpio";
 187                 //pinctrl-0 = <&i2c5_sda &i2c5_scl>;
 188                 //pinctrl-1 = <&i2c5_gpio>;
 189                 //gpios = <&gpio7 GPIO_C3 GPIO_ACTIVE_LOW>, <&gpio7 GPIO_C4 GPIO_ACTIVE_LOW>;
 190                 //clocks = <&clk_gates8 8>;
 191                 rockchip,check-idle = <1>;
 192                 status = "disabled";
 193         };
 194
 195         edp: edp@ff970000 {
 196                 compatible = "rockchip,rk32-edp";
 197                 reg = <0xff970000 0x4000>;
 198                 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
 199                 status = "disabled";
 200         };
 201
 202         hdmi: hdmi@ff980000 {
 203                 compatible = "rockchip,rk3288-hdmi";
 204                 reg = <0xff980000 0x20000>;
 205                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
 206                 rockchip,hdmi_lcdc_source = <1>;
 207                 pinctrl-names = "default", "gpio";
 208                 pinctrl-0 = <&i2c5_sda &i2c5_scl>;
 209                 pinctrl-1 = <&i2c5_gpio>;
 210                 status = "disabled";
 211         };
 212         fb: fb{
 213                 compatible = "rockchip,rk-fb";
 214                 rockchip,disp-mode = <DUAL>;
 215         };
 216
 217         lcdc0: lcdc@ff940000 {
 218                 compatible = "rockchip,rk3288-lcdc";
 219                 rockchip,prop = <PRMRY>;
 220                 rochchip,pwr18 = <0>;
 221                 reg = <0xff940000 0x10000>;
 222                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 223                 //pinctrl-names = "default", "gpio";
 224                 //pinctrl-0 = <&lcdc0_lcdc>;
 225                 //pinctrl-1 = <&lcdc0_gpio>;
 226                 status = "disabled";
 227         };
 228
 229         lcdc1: lcdc@ff930000 {
 230                 compatible = "rockchip,rk3288-lcdc";
 231                 rockchip,prop = <EXTEND>;
 232                 rockchip,pwr18 = <0>;
 233                 reg = <0xff930000 0x10000>;
 234                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 235                 pinctrl-names = "default", "gpio";
 236                 pinctrl-0 = <&lcdc0_lcdc>;
 237                 pinctrl-1 = <&lcdc0_gpio>;
 238                 status = "disabled";
 239         };
 240
 241         adc: adc@ff100000 {
 242                 compatible = "rockchip,saradc";
 243                 reg = <0xff100000 0x100>;
 244                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 245                 #io-channel-cells = <1>;
 246                 io-channel-ranges;
 247                 rockchip,adc-vref = <1800>;
 248                 clock-frequency = <1000000>;
 249                 clock-names = "saradc", "pclk_saradc";
 250                 status = "disabled";
 251         };
 252
 253         rga@ff920000 {
 254                 compatible = "rockchip,rga";
 255                 reg = <0xff920000 0x1000>;
 256                 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
 257                 clock-names = "hclk_rga", "aclk_rga";
 258         };
 259
 260         i2s: rockchip-i2s@0xff890000 {
 261                 compatible = "rockchip-i2s";
 262                 reg = <0xff890000 0x10000>;
 263                 i2s-id = <0>;
 264         //      clocks = <&clk_i2s>;
 265         //      clock-names = "i2s_clk","i2s_mclk";
 266                 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 267         //      dmas = <&pdma0 0>,
 268         //              <&pdma0 1>;
 269                 //#dma-cells = <2>;
 270         //      dma-names = "tx", "rx";
 271         //      pinctrl-names = "default", "sleep";
 272         //      pinctrl-0 = <&i2s0_mclk &i2s0_sclk &i2s0_lrckrx &i2s0_lrcktx &i2s0_sdi &i2s0_sdo0 &i2s0_sdo1 &i2s0_sdo2 &i2s0_sdo3>;
 273         //      pinctrl-1 = <&i2s0_gpio>;
 274         };
 275
 276         spdif: rockchip-spdif@0xff8b0000 {
 277                 compatible = "rockchip-spdif";
 278                 reg = <0xff8b0000 0x10000>;     //8channel
 279                 //reg = <ff880000 0x2000>;//2channel
 280         //      clocks = <&clk_spdif>;
 281         //      clock-names = "spdif_mclk";
 282                 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 283         //      dmas = <&pdma0 8>;
 284                 //#dma-cells = <1>;
 285         //      dma-names = "tx";
 286         //      pinctrl-names = "default";
 287         //      pinctrl-0 = <&spdif_tx>;
 288         };
 289
 290         ion: ion {
 291                 compatible = "rockchip,ion";
 292                 #address-cells = <1>;
 293                 #size-cells = <0>;
 294                 rockchip,ion-heap@1 { /* CMA HEAP */
 295                         compatible = "rockchip,ion-reserve";
 296                         reg = <1>;
 297                         memory-reservation = <0x00000000 0x10000000>; /* 256MB */
 298                 };
 299                 rockchip,ion-heap@3 { /* SYSTEM HEAP */
 300                         reg = <3>;
 301                 };
 302         };
 303
 304         mmc: mshc@ff0c0000 {
 305                 compatible = "rockchip,rk_mmc";
 306                 reg = <0xff0c0000 0x4000>;
 307                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; /*irq=64*/
 308                 #address-cells = <1>;
 309                 #size-cells = <0>;
 310                 //pinctrl-names = "default","suspend";
 311                 //pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_cd &sdmmc0_wp &sdmmc0_pwr &sdmmc0_bus1 &sdmmc0_bus4>;
 312                 //pinctrl-1 = <&sd0_cd_gpio>; //for int gpio?
 313                 //clocks = <&clk_gatesX XX> , <&clk_gatesY YY>;
 314                 //clock-names = "hclk_mmc","mmc";
 315                 clock-frequency = <50000000>;
 316                 clock-freq-min-max = <400000 50000000>;
 317                 num-slots = <1>;
 318                 supports-highspeed;
 319                 broken-cd;
 320                 card-detect-delay = <200>;
 321                 pwr-gpios = <&gpio3 GPIO_A1 GPIO_ACTIVE_LOW>; /*pwr_en = GPIO3_A1*/
 322                 fifo-depth = <0x100>;
 323                 emmc-compatible = <0>;
 324                 status = "okay";
 325         };
 326
 327         sdio0: mshc@ff0d0000 {
 328                 compatible = "rockchip,rk_mmc";
 329                 reg = <0xff0d0000 0x4000>;
 330                 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; /*irq=65*/
 331                 #address-cells = <1>;
 332                 #size-cells = <0>;
 333                 //pinctrl-names = "default";
 334                 //pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_cd &sd1_wp &sd1_bus1 &sd1_bus4>;
 335                 //clocks = <&clk_gatesX XX> , <&clk_gatesY YY>;
 336                 //clock-names = "hclk_sdio0","sdio0";
 337                 clock-frequency = <50000000>;
 338                 clock-freq-min-max = <400000 50000000>;
 339                 num-slots = <1>;
 340                 supports-highspeed;
 341                 fifo-depth = <0x100>;
 342                 emmc-compatible = <0>;
 343                 status = "disabled";
 344         };
 345
 346         sdio1: mshc@ff0e0000 {
 347                 compatible = "rockchip,rk_mmc";
 348                 reg = <0xff0e0000 0x4000>;
 349                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; /*irq=66*/
 350                 #address-cells = <1>;
 351                 #size-cells = <0>;
 352                 //pinctrl-names = "default";
 353                 //pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_cd &sd1_wp &sd1_bus1 &sd1_bus4>;
 354                 //clocks = <&clk_gatesX XX> , <&clk_gatesY YY>;
 355                 //clock-names = "hclk_sdio1","sdio1";
 356                 clock-frequency = <50000000>;
 357                 clock-freq-min-max = <400000 50000000>;
 358                 num-slots = <1>;
 359                 supports-highspeed;
 360                 fifo-depth = <0x100>;
 361                 emmc-compatible = <0>;
 362                 status = "disabled";
 363         };
 364
 365         emmc: mshc@ff0f0000 {
 366                 compatible = "rockchip,rk_mmc";
 367                 reg = <0xff0f0000 0x4000>;
 368                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; /*irq=67*/
 369                 #address-cells = <1>;
 370                 #size-cells = <0>;
 371                 //pinctrl-names = "default";
 372                 //pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_cd &sd1_wp &sd1_bus1 &sd1_bus4>;
 373                 //clocks = <&clk_gatesX XX> , <&clk_gatesY YY>;
 374                 //clock-names = "hclk_sdio1","sdio1";
 375                 clock-frequency = <50000000>;
 376                 clock-freq-min-max = <400000 50000000>;
 377                 num-slots = <1>;
 378                 supports-highspeed;
 379                 fifo-depth = <0x100>;
 380                 emmc-compatible = <1>;
 381                 status = "disabled";
 382         };
 383
 384         vpu: vpu_service@ff9a0000 {
 385                 compatible = "vpu_service";
 386                 reg = <0xff9a0000 0x800>;
 387                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 388                 interrupt-names = "irq_enc", "irq_dec";
 389                 /*clocks = <&clk_gates3 9>, <&clk_gates3 10>;
 390                 clock-names = "aclk_vcodec", "hclk_vcodec"; */
 391                 name = "vpu_service";
 392                 status = "disabled";
 393         };
 394
 395         hevc: hevc_service@ff9c0000 {
 396                 compatible = "rockchip,hevc_service";
 397                 reg = <0xff9c0000 0x800>;
 398                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 399                 interrupt-names = "irq_dec";
 400                 /*clocks = <&clk_gates3 9>, <&clk_gates3 10>;
 401                 clock-names = "aclk_vcodec", "hclk_vcodec";*/
 402                 name = "hevc_service";
 403                 status = "disabled";
 404         };
 405
 406         iep: iep@ff900000 {
 407                 compatible = "rockchip,iep";
 408                 reg = <0xff900000 0x800>;
 409                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 410                 /*clocks = <&clk_gate3 9>, <&clk_gate3 10>;
 411                 clock_names = "aclk_iep", "hclk_iep";*/
 412                 status = "disabled";
 413         };
 414
 415         dwc_control_usb: dwc-control-usb@ff770284 {
 416                 compatible = "rockchip,rk3288-dwc-control-usb";
 417                 reg = <0xff770284 0x04>, <0xff770288 0x04>,
 418                       <0xff7702cc 0x04>, <0xff7702d4 0x04>,
 419                       <0xff770320 0x14>, <0xff770334 0x14>,
 420                       <0xff770348 0x10>, <0xff770358 0x08>,
 421                       <0xff770360 0x08>;
 422                 reg-names = "GRF_SOC_STATUS1" ,"GRF_SOC_STATUS2",
 423                             "GRF_SOC_STATUS19", "GRF_SOC_STATUS21",
 424                             "GRF_UOC0_BASE", "GRF_UOC1_BASE",
 425                             "GRF_UOC2_BASE", "GRF_UOC3_BASE",
 426                             "GRF_UOC4_BASE";
 427                 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
 428                              <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
 429                              <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
 430                 interrupt-names = "otg_id", "bvalid",
 431                                   "otg_linestate", "host0_linestate",
 432                                   "host1_linestate";
 433                 /*gpios = <&gpio0 GPIO_B6 GPIO_ACTIVE_LOW>,*//*HOST_VBUS_DRV*/
 434                 /*      <&gpio0 GPIO_B4 GPIO_ACTIVE_LOW>;*//*OTG_VBUS_DRV*/
 435                 /*clocks = <&clk_gates4 5>;*/
 436                 /*clock-names = "hclk_usb_peri";*/
 437         };
 438
 439         usb1: usb@ff580000 {
 440                 compatible = "rockchip,rk3288_usb20_otg";
 441                 reg = <0xff580000 0x40000>;
 442                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 443                 /*clocks = <&clk_otgphy0_480m>, <&clk_gates5 13>;*/
 444                 /*clock-names = "otgphy0", "hclk_otg0";*/
 445         };
 446
 447         usb2: usb@ff540000 {
 448                 compatible = "rockchip,rk3288_usb20_host";
 449                 reg = <0xff540000 0x40000>;
 450                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 451                 /*clocks = <&clk_otgphy1_480m>, <&clk_gates7 3>;*/
 452                 /*clock-names = "otgphy1", "hclk_otg1";*/
 453         };
 454
 455         usb3: usb@ff520000 {
 456                 compatible = "rockchip,rk3288_rk_ohci_host";
 457                 reg = <0xff520000 0x20000>;
 458                 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 459                 /*clocks = ;*/
 460                 /*clock-names = ;*/
 461         };
 462
 463         usb4: usb@ff500000 {
 464                 compatible = "rockchip,rk3288_rk_ehci_host";
 465                 reg = <0xff500000 0x20000>;
 466                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 467                 /*clocks = ;*/
 468                 /*clock-names = ;*/
 469         };
 470
 471         usb5: hsic@ff5c0000 {
 472                 compatible = "rockchip,rk3288_rk_hsic_host";
 473                 reg = <0xff5c0000 0x40000>;
 474                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 475                 /*clocks = <&clk_hsicphy480m>, <&clk_gates7 4>,*/
 476                 /*       <&clk_hsicphy12m>, <&clk_otgphy1_480m>;*/
 477                 /*clock-names = "hsicphy480m", "hclk_hsic",*/
 478                 /*            "hsicphy12m", "hsic_otgphy1";*/
 479         };
 480 };