2 * This program is free software; you can redistribute it and/or modify
3 * it under the terms of the GNU General Public License as published by
4 * the Free Software Foundation; either version 2 of the License, or
5 * (at your option) any later version.
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
13 #include <dt-bindings/gpio/gpio.h>
14 #include <dt-bindings/interrupt-controller/irq.h>
15 #include <dt-bindings/interrupt-controller/arm-gic.h>
16 #include <dt-bindings/pinctrl/rockchip.h>
17 #include <dt-bindings/clock/rk3288-cru.h>
18 #include <dt-bindings/thermal/thermal.h>
19 #include "skeleton.dtsi"
22 compatible = "rockchip,rk3288";
24 interrupt-parent = <&gic>;
50 enable-method = "rockchip,rk3066-smp";
51 rockchip,pmu = <&pmu>;
55 compatible = "arm,cortex-a12";
57 resets = <&cru SRST_CORE0>;
73 #cooling-cells = <2>; /* min followed by max */
74 clock-latency = <40000>;
75 clocks = <&cru ARMCLK>;
79 compatible = "arm,cortex-a12";
81 resets = <&cru SRST_CORE1>;
85 compatible = "arm,cortex-a12";
87 resets = <&cru SRST_CORE2>;
91 compatible = "arm,cortex-a12";
93 resets = <&cru SRST_CORE3>;
98 compatible = "arm,amba-bus";
103 dmac_peri: dma-controller@ff250000 {
104 compatible = "arm,pl330", "arm,primecell";
105 reg = <0xff250000 0x4000>;
106 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
107 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
109 clocks = <&cru ACLK_DMAC2>;
110 clock-names = "apb_pclk";
113 dmac_bus_ns: dma-controller@ff600000 {
114 compatible = "arm,pl330", "arm,primecell";
115 reg = <0xff600000 0x4000>;
116 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
117 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
119 clocks = <&cru ACLK_DMAC1>;
120 clock-names = "apb_pclk";
124 dmac_bus_s: dma-controller@ffb20000 {
125 compatible = "arm,pl330", "arm,primecell";
126 reg = <0xffb20000 0x4000>;
127 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
128 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
130 clocks = <&cru ACLK_DMAC1>;
131 clock-names = "apb_pclk";
136 compatible = "fixed-clock";
137 clock-frequency = <24000000>;
138 clock-output-names = "xin24m";
143 compatible = "arm,armv7-timer";
144 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
145 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
146 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
147 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
148 clock-frequency = <24000000>;
151 sdmmc: dwmmc@ff0c0000 {
152 compatible = "rockchip,rk3288-dw-mshc";
153 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
154 clock-names = "biu", "ciu";
155 fifo-depth = <0x100>;
156 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
157 reg = <0xff0c0000 0x4000>;
161 sdio0: dwmmc@ff0d0000 {
162 compatible = "rockchip,rk3288-dw-mshc";
163 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>;
164 clock-names = "biu", "ciu";
165 fifo-depth = <0x100>;
166 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
167 reg = <0xff0d0000 0x4000>;
171 sdio1: dwmmc@ff0e0000 {
172 compatible = "rockchip,rk3288-dw-mshc";
173 clocks = <&cru HCLK_SDIO1>, <&cru SCLK_SDIO1>;
174 clock-names = "biu", "ciu";
175 fifo-depth = <0x100>;
176 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
177 reg = <0xff0e0000 0x4000>;
181 emmc: dwmmc@ff0f0000 {
182 compatible = "rockchip,rk3288-dw-mshc";
183 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>;
184 clock-names = "biu", "ciu";
185 fifo-depth = <0x100>;
186 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
187 reg = <0xff0f0000 0x4000>;
191 saradc: saradc@ff100000 {
192 compatible = "rockchip,saradc";
193 reg = <0xff100000 0x100>;
194 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
195 #io-channel-cells = <1>;
196 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
197 clock-names = "saradc", "apb_pclk";
202 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
203 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
204 clock-names = "spiclk", "apb_pclk";
205 dmas = <&dmac_peri 11>, <&dmac_peri 12>;
206 dma-names = "tx", "rx";
207 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
208 pinctrl-names = "default";
209 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
210 reg = <0xff110000 0x1000>;
211 #address-cells = <1>;
217 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
218 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
219 clock-names = "spiclk", "apb_pclk";
220 dmas = <&dmac_peri 13>, <&dmac_peri 14>;
221 dma-names = "tx", "rx";
222 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
223 pinctrl-names = "default";
224 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
225 reg = <0xff120000 0x1000>;
226 #address-cells = <1>;
232 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
233 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
234 clock-names = "spiclk", "apb_pclk";
235 dmas = <&dmac_peri 15>, <&dmac_peri 16>;
236 dma-names = "tx", "rx";
237 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
238 pinctrl-names = "default";
239 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
240 reg = <0xff130000 0x1000>;
241 #address-cells = <1>;
247 compatible = "rockchip,rk3288-i2c";
248 reg = <0xff140000 0x1000>;
249 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
250 #address-cells = <1>;
253 clocks = <&cru PCLK_I2C1>;
254 pinctrl-names = "default";
255 pinctrl-0 = <&i2c1_xfer>;
260 compatible = "rockchip,rk3288-i2c";
261 reg = <0xff150000 0x1000>;
262 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
263 #address-cells = <1>;
266 clocks = <&cru PCLK_I2C3>;
267 pinctrl-names = "default";
268 pinctrl-0 = <&i2c3_xfer>;
273 compatible = "rockchip,rk3288-i2c";
274 reg = <0xff160000 0x1000>;
275 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
276 #address-cells = <1>;
279 clocks = <&cru PCLK_I2C4>;
280 pinctrl-names = "default";
281 pinctrl-0 = <&i2c4_xfer>;
286 compatible = "rockchip,rk3288-i2c";
287 reg = <0xff170000 0x1000>;
288 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
289 #address-cells = <1>;
292 clocks = <&cru PCLK_I2C5>;
293 pinctrl-names = "default";
294 pinctrl-0 = <&i2c5_xfer>;
298 uart0: serial@ff180000 {
299 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
300 reg = <0xff180000 0x100>;
301 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
304 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
305 clock-names = "baudclk", "apb_pclk";
306 pinctrl-names = "default";
307 pinctrl-0 = <&uart0_xfer>;
311 uart1: serial@ff190000 {
312 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
313 reg = <0xff190000 0x100>;
314 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
317 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
318 clock-names = "baudclk", "apb_pclk";
319 pinctrl-names = "default";
320 pinctrl-0 = <&uart1_xfer>;
324 uart2: serial@ff690000 {
325 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
326 reg = <0xff690000 0x100>;
327 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
330 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
331 clock-names = "baudclk", "apb_pclk";
332 pinctrl-names = "default";
333 pinctrl-0 = <&uart2_xfer>;
337 uart3: serial@ff1b0000 {
338 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
339 reg = <0xff1b0000 0x100>;
340 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
343 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
344 clock-names = "baudclk", "apb_pclk";
345 pinctrl-names = "default";
346 pinctrl-0 = <&uart3_xfer>;
350 uart4: serial@ff1c0000 {
351 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
352 reg = <0xff1c0000 0x100>;
353 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
356 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
357 clock-names = "baudclk", "apb_pclk";
358 pinctrl-names = "default";
359 pinctrl-0 = <&uart4_xfer>;
364 #include "rk3288-thermal.dtsi"
367 tsadc: tsadc@ff280000 {
368 compatible = "rockchip,rk3288-tsadc";
369 reg = <0xff280000 0x100>;
370 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
371 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
372 clock-names = "tsadc", "apb_pclk";
373 resets = <&cru SRST_TSADC>;
374 reset-names = "tsadc-apb";
375 pinctrl-names = "default";
376 pinctrl-0 = <&otp_out>;
377 #thermal-sensor-cells = <1>;
378 rockchip,hw-tshut-temp = <95000>;
382 usb_host0_ehci: usb@ff500000 {
383 compatible = "generic-ehci";
384 reg = <0xff500000 0x100>;
385 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
386 clocks = <&cru HCLK_USBHOST0>;
387 clock-names = "usbhost";
391 /* NOTE: ohci@ff520000 doesn't actually work on hardware */
393 usb_host1: usb@ff540000 {
394 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
396 reg = <0xff540000 0x40000>;
397 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
398 clocks = <&cru HCLK_USBHOST1>;
403 usb_otg: usb@ff580000 {
404 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
406 reg = <0xff580000 0x40000>;
407 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
408 clocks = <&cru HCLK_OTG0>;
413 usb_hsic: usb@ff5c0000 {
414 compatible = "generic-ehci";
415 reg = <0xff5c0000 0x100>;
416 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
417 clocks = <&cru HCLK_HSIC>;
418 clock-names = "usbhost";
423 compatible = "rockchip,rk3288-i2c";
424 reg = <0xff650000 0x1000>;
425 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
426 #address-cells = <1>;
429 clocks = <&cru PCLK_I2C0>;
430 pinctrl-names = "default";
431 pinctrl-0 = <&i2c0_xfer>;
436 compatible = "rockchip,rk3288-i2c";
437 reg = <0xff660000 0x1000>;
438 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
439 #address-cells = <1>;
442 clocks = <&cru PCLK_I2C2>;
443 pinctrl-names = "default";
444 pinctrl-0 = <&i2c2_xfer>;
449 compatible = "rockchip,rk3288-pwm";
450 reg = <0xff680000 0x10>;
452 pinctrl-names = "default";
453 pinctrl-0 = <&pwm0_pin>;
454 clocks = <&cru PCLK_PWM>;
460 compatible = "rockchip,rk3288-pwm";
461 reg = <0xff680010 0x10>;
463 pinctrl-names = "default";
464 pinctrl-0 = <&pwm1_pin>;
465 clocks = <&cru PCLK_PWM>;
471 compatible = "rockchip,rk3288-pwm";
472 reg = <0xff680020 0x10>;
474 pinctrl-names = "default";
475 pinctrl-0 = <&pwm2_pin>;
476 clocks = <&cru PCLK_PWM>;
482 compatible = "rockchip,rk3288-pwm";
483 reg = <0xff680030 0x10>;
485 pinctrl-names = "default";
486 pinctrl-0 = <&pwm3_pin>;
487 clocks = <&cru PCLK_PWM>;
492 bus_intmem@ff700000 {
493 compatible = "mmio-sram";
494 reg = <0xff700000 0x18000>;
495 #address-cells = <1>;
497 ranges = <0 0xff700000 0x18000>;
499 compatible = "rockchip,rk3066-smp-sram";
504 pmu: power-management@ff730000 {
505 compatible = "rockchip,rk3288-pmu", "syscon";
506 reg = <0xff730000 0x100>;
509 sgrf: syscon@ff740000 {
510 compatible = "rockchip,rk3288-sgrf", "syscon";
511 reg = <0xff740000 0x1000>;
514 cru: clock-controller@ff760000 {
515 compatible = "rockchip,rk3288-cru";
516 reg = <0xff760000 0x1000>;
517 rockchip,grf = <&grf>;
520 assigned-clocks = <&cru PLL_GPLL>, <&cru PLL_CPLL>,
521 <&cru PLL_NPLL>, <&cru ACLK_CPU>,
522 <&cru HCLK_CPU>, <&cru PCLK_CPU>,
523 <&cru ACLK_PERI>, <&cru HCLK_PERI>,
525 assigned-clock-rates = <594000000>, <400000000>,
526 <500000000>, <300000000>,
527 <150000000>, <75000000>,
528 <300000000>, <150000000>,
532 grf: syscon@ff770000 {
533 compatible = "rockchip,rk3288-grf", "syscon";
534 reg = <0xff770000 0x1000>;
537 wdt: watchdog@ff800000 {
538 compatible = "rockchip,rk3288-wdt", "snps,dw-wdt";
539 reg = <0xff800000 0x100>;
540 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
545 compatible = "rockchip,rk3288-i2s", "rockchip,rk3066-i2s";
546 reg = <0xff890000 0x10000>;
547 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
548 #address-cells = <1>;
550 dmas = <&dmac_bus_s 0>, <&dmac_bus_s 1>;
551 dma-names = "tx", "rx";
552 clock-names = "i2s_hclk", "i2s_clk";
553 clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>;
554 pinctrl-names = "default";
555 pinctrl-0 = <&i2s0_bus>;
559 vopb_mmu: iommu@ff930300 {
560 compatible = "rockchip,iommu";
561 reg = <0xff930300 0x100>;
562 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
563 interrupt-names = "vopb_mmu";
568 vopl_mmu: iommu@ff940300 {
569 compatible = "rockchip,iommu";
570 reg = <0xff940300 0x100>;
571 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
572 interrupt-names = "vopl_mmu";
577 gic: interrupt-controller@ffc01000 {
578 compatible = "arm,gic-400";
579 interrupt-controller;
580 #interrupt-cells = <3>;
581 #address-cells = <0>;
583 reg = <0xffc01000 0x1000>,
587 interrupts = <GIC_PPI 9 0xf04>;
591 compatible = "rockchip,rk3288-pinctrl";
592 rockchip,grf = <&grf>;
593 rockchip,pmu = <&pmu>;
594 #address-cells = <1>;
598 gpio0: gpio0@ff750000 {
599 compatible = "rockchip,gpio-bank";
600 reg = <0xff750000 0x100>;
601 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
602 clocks = <&cru PCLK_GPIO0>;
607 interrupt-controller;
608 #interrupt-cells = <2>;
611 gpio1: gpio1@ff780000 {
612 compatible = "rockchip,gpio-bank";
613 reg = <0xff780000 0x100>;
614 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
615 clocks = <&cru PCLK_GPIO1>;
620 interrupt-controller;
621 #interrupt-cells = <2>;
624 gpio2: gpio2@ff790000 {
625 compatible = "rockchip,gpio-bank";
626 reg = <0xff790000 0x100>;
627 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
628 clocks = <&cru PCLK_GPIO2>;
633 interrupt-controller;
634 #interrupt-cells = <2>;
637 gpio3: gpio3@ff7a0000 {
638 compatible = "rockchip,gpio-bank";
639 reg = <0xff7a0000 0x100>;
640 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
641 clocks = <&cru PCLK_GPIO3>;
646 interrupt-controller;
647 #interrupt-cells = <2>;
650 gpio4: gpio4@ff7b0000 {
651 compatible = "rockchip,gpio-bank";
652 reg = <0xff7b0000 0x100>;
653 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
654 clocks = <&cru PCLK_GPIO4>;
659 interrupt-controller;
660 #interrupt-cells = <2>;
663 gpio5: gpio5@ff7c0000 {
664 compatible = "rockchip,gpio-bank";
665 reg = <0xff7c0000 0x100>;
666 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
667 clocks = <&cru PCLK_GPIO5>;
672 interrupt-controller;
673 #interrupt-cells = <2>;
676 gpio6: gpio6@ff7d0000 {
677 compatible = "rockchip,gpio-bank";
678 reg = <0xff7d0000 0x100>;
679 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
680 clocks = <&cru PCLK_GPIO6>;
685 interrupt-controller;
686 #interrupt-cells = <2>;
689 gpio7: gpio7@ff7e0000 {
690 compatible = "rockchip,gpio-bank";
691 reg = <0xff7e0000 0x100>;
692 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
693 clocks = <&cru PCLK_GPIO7>;
698 interrupt-controller;
699 #interrupt-cells = <2>;
702 gpio8: gpio8@ff7f0000 {
703 compatible = "rockchip,gpio-bank";
704 reg = <0xff7f0000 0x100>;
705 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
706 clocks = <&cru PCLK_GPIO8>;
711 interrupt-controller;
712 #interrupt-cells = <2>;
715 pcfg_pull_up: pcfg-pull-up {
719 pcfg_pull_down: pcfg-pull-down {
723 pcfg_pull_none: pcfg-pull-none {
728 i2c0_xfer: i2c0-xfer {
729 rockchip,pins = <0 15 RK_FUNC_1 &pcfg_pull_none>,
730 <0 16 RK_FUNC_1 &pcfg_pull_none>;
735 i2c1_xfer: i2c1-xfer {
736 rockchip,pins = <8 4 RK_FUNC_1 &pcfg_pull_none>,
737 <8 5 RK_FUNC_1 &pcfg_pull_none>;
742 i2c2_xfer: i2c2-xfer {
743 rockchip,pins = <6 9 RK_FUNC_1 &pcfg_pull_none>,
744 <6 10 RK_FUNC_1 &pcfg_pull_none>;
749 i2c3_xfer: i2c3-xfer {
750 rockchip,pins = <2 16 RK_FUNC_1 &pcfg_pull_none>,
751 <2 17 RK_FUNC_1 &pcfg_pull_none>;
756 i2c4_xfer: i2c4-xfer {
757 rockchip,pins = <7 17 RK_FUNC_1 &pcfg_pull_none>,
758 <7 18 RK_FUNC_1 &pcfg_pull_none>;
763 i2c5_xfer: i2c5-xfer {
764 rockchip,pins = <7 19 RK_FUNC_1 &pcfg_pull_none>,
765 <7 20 RK_FUNC_1 &pcfg_pull_none>;
771 rockchip,pins = <6 0 RK_FUNC_1 &pcfg_pull_none>,
772 <6 1 RK_FUNC_1 &pcfg_pull_none>,
773 <6 2 RK_FUNC_1 &pcfg_pull_none>,
774 <6 3 RK_FUNC_1 &pcfg_pull_none>,
775 <6 4 RK_FUNC_1 &pcfg_pull_none>,
776 <6 8 RK_FUNC_1 &pcfg_pull_none>;
781 sdmmc_clk: sdmmc-clk {
782 rockchip,pins = <6 20 RK_FUNC_1 &pcfg_pull_none>;
785 sdmmc_cmd: sdmmc-cmd {
786 rockchip,pins = <6 21 RK_FUNC_1 &pcfg_pull_up>;
790 rockchip,pins = <6 22 RK_FUNC_1 &pcfg_pull_up>;
793 sdmmc_bus1: sdmmc-bus1 {
794 rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>;
797 sdmmc_bus4: sdmmc-bus4 {
798 rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>,
799 <6 17 RK_FUNC_1 &pcfg_pull_up>,
800 <6 18 RK_FUNC_1 &pcfg_pull_up>,
801 <6 19 RK_FUNC_1 &pcfg_pull_up>;
806 sdio0_bus1: sdio0-bus1 {
807 rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>;
810 sdio0_bus4: sdio0-bus4 {
811 rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>,
812 <4 21 RK_FUNC_1 &pcfg_pull_up>,
813 <4 22 RK_FUNC_1 &pcfg_pull_up>,
814 <4 23 RK_FUNC_1 &pcfg_pull_up>;
817 sdio0_cmd: sdio0-cmd {
818 rockchip,pins = <4 24 RK_FUNC_1 &pcfg_pull_up>;
821 sdio0_clk: sdio0-clk {
822 rockchip,pins = <4 25 RK_FUNC_1 &pcfg_pull_none>;
826 rockchip,pins = <4 26 RK_FUNC_1 &pcfg_pull_up>;
830 rockchip,pins = <4 27 RK_FUNC_1 &pcfg_pull_up>;
833 sdio0_pwr: sdio0-pwr {
834 rockchip,pins = <4 28 RK_FUNC_1 &pcfg_pull_up>;
837 sdio0_bkpwr: sdio0-bkpwr {
838 rockchip,pins = <4 29 RK_FUNC_1 &pcfg_pull_up>;
841 sdio0_int: sdio0-int {
842 rockchip,pins = <4 30 RK_FUNC_1 &pcfg_pull_up>;
847 sdio1_bus1: sdio1-bus1 {
848 rockchip,pins = <3 24 4 &pcfg_pull_up>;
851 sdio1_bus4: sdio1-bus4 {
852 rockchip,pins = <3 24 4 &pcfg_pull_up>,
853 <3 25 4 &pcfg_pull_up>,
854 <3 26 4 &pcfg_pull_up>,
855 <3 27 4 &pcfg_pull_up>;
859 rockchip,pins = <3 28 4 &pcfg_pull_up>;
863 rockchip,pins = <3 29 4 &pcfg_pull_up>;
866 sdio1_bkpwr: sdio1-bkpwr {
867 rockchip,pins = <3 30 4 &pcfg_pull_up>;
870 sdio1_int: sdio1-int {
871 rockchip,pins = <3 31 4 &pcfg_pull_up>;
874 sdio1_cmd: sdio1-cmd {
875 rockchip,pins = <4 6 4 &pcfg_pull_up>;
878 sdio1_clk: sdio1-clk {
879 rockchip,pins = <4 7 4 &pcfg_pull_none>;
882 sdio1_pwr: sdio1-pwr {
883 rockchip,pins = <4 9 4 &pcfg_pull_up>;
889 rockchip,pins = <3 18 RK_FUNC_2 &pcfg_pull_none>;
893 rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_up>;
897 rockchip,pins = <3 9 RK_FUNC_2 &pcfg_pull_up>;
900 emmc_bus1: emmc-bus1 {
901 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>;
904 emmc_bus4: emmc-bus4 {
905 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>,
906 <3 1 RK_FUNC_2 &pcfg_pull_up>,
907 <3 2 RK_FUNC_2 &pcfg_pull_up>,
908 <3 3 RK_FUNC_2 &pcfg_pull_up>;
911 emmc_bus8: emmc-bus8 {
912 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>,
913 <3 1 RK_FUNC_2 &pcfg_pull_up>,
914 <3 2 RK_FUNC_2 &pcfg_pull_up>,
915 <3 3 RK_FUNC_2 &pcfg_pull_up>,
916 <3 4 RK_FUNC_2 &pcfg_pull_up>,
917 <3 5 RK_FUNC_2 &pcfg_pull_up>,
918 <3 6 RK_FUNC_2 &pcfg_pull_up>,
919 <3 7 RK_FUNC_2 &pcfg_pull_up>;
925 rockchip,pins = <5 12 RK_FUNC_1 &pcfg_pull_up>;
928 rockchip,pins = <5 13 RK_FUNC_1 &pcfg_pull_up>;
931 rockchip,pins = <5 14 RK_FUNC_1 &pcfg_pull_up>;
934 rockchip,pins = <5 15 RK_FUNC_1 &pcfg_pull_up>;
937 rockchip,pins = <5 16 RK_FUNC_1 &pcfg_pull_up>;
942 rockchip,pins = <7 12 RK_FUNC_2 &pcfg_pull_up>;
945 rockchip,pins = <7 13 RK_FUNC_2 &pcfg_pull_up>;
948 rockchip,pins = <7 14 RK_FUNC_2 &pcfg_pull_up>;
951 rockchip,pins = <7 15 RK_FUNC_2 &pcfg_pull_up>;
957 rockchip,pins = <8 3 RK_FUNC_1 &pcfg_pull_up>;
960 rockchip,pins = <8 6 RK_FUNC_1 &pcfg_pull_up>;
963 rockchip,pins = <8 7 RK_FUNC_1 &pcfg_pull_up>;
966 rockchip,pins = <8 8 RK_FUNC_1 &pcfg_pull_up>;
969 rockchip,pins = <8 9 RK_FUNC_1 &pcfg_pull_up>;
974 uart0_xfer: uart0-xfer {
975 rockchip,pins = <4 16 RK_FUNC_1 &pcfg_pull_up>,
976 <4 17 RK_FUNC_1 &pcfg_pull_none>;
979 uart0_cts: uart0-cts {
980 rockchip,pins = <4 18 RK_FUNC_1 &pcfg_pull_none>;
983 uart0_rts: uart0-rts {
984 rockchip,pins = <4 19 RK_FUNC_1 &pcfg_pull_none>;
989 uart1_xfer: uart1-xfer {
990 rockchip,pins = <5 8 RK_FUNC_1 &pcfg_pull_up>,
991 <5 9 RK_FUNC_1 &pcfg_pull_none>;
994 uart1_cts: uart1-cts {
995 rockchip,pins = <5 10 RK_FUNC_1 &pcfg_pull_none>;
998 uart1_rts: uart1-rts {
999 rockchip,pins = <5 11 RK_FUNC_1 &pcfg_pull_none>;
1004 uart2_xfer: uart2-xfer {
1005 rockchip,pins = <7 22 RK_FUNC_1 &pcfg_pull_up>,
1006 <7 23 RK_FUNC_1 &pcfg_pull_none>;
1008 /* no rts / cts for uart2 */
1012 uart3_xfer: uart3-xfer {
1013 rockchip,pins = <7 7 RK_FUNC_1 &pcfg_pull_up>,
1014 <7 8 RK_FUNC_1 &pcfg_pull_none>;
1017 uart3_cts: uart3-cts {
1018 rockchip,pins = <7 9 RK_FUNC_1 &pcfg_pull_none>;
1021 uart3_rts: uart3-rts {
1022 rockchip,pins = <7 10 RK_FUNC_1 &pcfg_pull_none>;
1027 uart4_xfer: uart4-xfer {
1028 rockchip,pins = <5 12 3 &pcfg_pull_up>,
1029 <5 13 3 &pcfg_pull_none>;
1032 uart4_cts: uart4-cts {
1033 rockchip,pins = <5 14 3 &pcfg_pull_none>;
1036 uart4_rts: uart4-rts {
1037 rockchip,pins = <5 15 3 &pcfg_pull_none>;
1043 rockchip,pins = <0 10 RK_FUNC_1 &pcfg_pull_none>;
1048 pwm0_pin: pwm0-pin {
1049 rockchip,pins = <7 0 RK_FUNC_1 &pcfg_pull_none>;
1054 pwm1_pin: pwm1-pin {
1055 rockchip,pins = <7 1 RK_FUNC_1 &pcfg_pull_none>;
1060 pwm2_pin: pwm2-pin {
1061 rockchip,pins = <7 22 3 &pcfg_pull_none>;
1066 pwm3_pin: pwm3-pin {
1067 rockchip,pins = <7 23 3 &pcfg_pull_none>;