arch/arm/boot/dts/rk3288.dtsi

   1 #include <dt-bindings/clock/ddr.h>
   2 #include <dt-bindings/interrupt-controller/arm-gic.h>
   3 #include <dt-bindings/rkfb/rk_fb.h>
   4 #include <dt-bindings/rkmipi/mipi_dsi.h>
   5 #include <dt-bindings/suspend/rockchip-pm.h>
   6 #include <dt-bindings/sensor-dev.h>
   7
   8 #include "skeleton.dtsi"
   9 #include "rk3288-pinctrl.dtsi"
  10 #include "rk3288-clocks.dtsi"
  11
  12 / {
  13         compatible = "rockchip,rk3288";
  14         rockchip,sram = <&sram>;
  15         interrupt-parent = <&gic>;
  16
  17         aliases {
  18                 serial0 = &uart_bt;
  19                 serial1 = &uart_bb;
  20                 serial2 = &uart_dbg;
  21                 serial3 = &uart_gps;
  22                 serial4 = &uart_exp;
  23                 i2c0 = &i2c0;
  24                 i2c1 = &i2c1;
  25                 i2c2 = &i2c2;
  26                 i2c3 = &i2c3;
  27                 i2c4 = &i2c4;
  28                 i2c5 = &i2c5;
  29                 lcdc0 = &lcdc0;
  30                 lcdc1 = &lcdc1;
  31                 spi0 = &spi0;
  32                 spi1 = &spi1;
  33                 spi2 = &spi2;
  34
  35         };
  36
  37         cpus {
  38                 #address-cells = <1>;
  39                 #size-cells = <0>;
  40
  41                 cpu@0 {
  42                         device_type = "cpu";
  43                         compatible = "arm,cortex-a15";
  44                         reg = <0x500>;
  45                 };
  46                 cpu@1 {
  47                         device_type = "cpu";
  48                         compatible = "arm,cortex-a15";
  49                         reg = <0x501>;
  50                 };
  51                 cpu@2 {
  52                         device_type = "cpu";
  53                         compatible = "arm,cortex-a15";
  54                         reg = <0x502>;
  55                 };
  56                 cpu@3 {
  57                         device_type = "cpu";
  58                         compatible = "arm,cortex-a15";
  59                         reg = <0x503>;
  60                 };
  61         };
  62
  63         gic: interrupt-controller@ffc01000 {
  64                 compatible = "arm,cortex-a15-gic";
  65                 interrupt-controller;
  66                 #interrupt-cells = <3>;
  67                 #address-cells = <0>;
  68                 reg = <0xffc01000 0x1000>,
  69                       <0xffc02000 0x1000>;
  70         };
  71
  72         cpu_axi_bus: cpu_axi_bus {
  73                 compatible = "rockchip,cpu_axi_bus";
  74                 #address-cells = <1>;
  75                 #size-cells = <1>;
  76                 ranges;
  77                 qos {
  78                         #address-cells = <1>;
  79                         #size-cells = <1>;
  80                         ranges;
  81                         /* service core */
  82                         cpup {
  83                                 reg = <0xffa80000 0x20>;
  84                         };
  85                         cpum_r {
  86                                 reg = <0xffa80080 0x20>;
  87                         };
  88                         cpum_w {
  89                                 reg = <0xffa80100 0x20>;
  90                         };
  91                         /* service dmac */
  92                         bus_dmac {
  93                                 reg = <0xffa90000 0x20>;
  94                         };
  95                         host {
  96                                 reg = <0xffa90080 0x20>;
  97                         };
  98                         crypto {
  99                                 reg = <0xffa90100 0x20>;
 100                         };
 101                         ccp {
 102                                 reg = <0xffa90180 0x20>;
 103                         };
 104                         ccs {
 105                                 reg = <0xffa90200 0x20>;
 106                         };
 107                         /* service gpu */
 108                         gpu_r {
 109                                 reg = <0xffaa0000 0x20>;
 110                         };
 111                         gpu_w {
 112                                 reg = <0xffaa0080 0x20>;
 113                         };
 114                         /* service peri */
 115                         peri {
 116                                 reg = <0xffab0000 0x20>;
 117                         };
 118                         /* service vio */
 119                         vio1_vop {
 120                                 reg = <0xffad0000 0x20>;
 121                                 rockchip,priority = <2 2>;
 122                         };
 123                         vio1_isp_w0 {
 124                                 reg = <0xffad0100 0x20>;
 125                         };
 126                         vio1_isp_w1 {
 127                                 reg = <0xffad0180 0x20>;
 128                         };
 129                         vio0_vop {
 130                                 reg = <0xffad0400 0x20>;
 131                                 rockchip,priority = <2 2>;
 132                         };
 133                         vio0_vip {
 134                                 reg = <0xffad0480 0x20>;
 135                         };
 136                         vio0_iep {
 137                                 reg = <0xffad0500 0x20>;
 138                         };
 139                         vio2_rga_r {
 140                                 reg = <0xffad0800 0x20>;
 141                         };
 142                         vio2_rga_w {
 143                                 reg = <0xffad0880 0x20>;
 144                         };
 145                         vio1_isp_r {
 146                                 reg = <0xffad0900 0x20>;
 147                         };
 148                         /* service video */
 149                         video {
 150                                 reg = <0xffae0000 0x20>;
 151                         };
 152                         /* service hevc */
 153                         hevc_r {
 154                                 reg = <0xffaf0000 0x20>;
 155                         };
 156                         hevc_w {
 157                                 reg = <0xffaf0080 0x20>;
 158                         };
 159                 };
 160                 msch {
 161                         #address-cells = <1>;
 162                         #size-cells = <1>;
 163                         ranges;
 164                         msch@0 {
 165                                 reg = <0xffac0000 0x40>;
 166                                 rockchip,read-latency = <0xff>;
 167                         };
 168                         msch@1 {
 169                                 reg = <0xffac0080 0x40>;
 170                                 rockchip,read-latency = <0xff>;
 171                         };
 172                 };
 173         };
 174
 175         sram: sram@ff710000 {
 176                 compatible = "mmio-sram";
 177                 reg = <0xff710000 0x8000>; /* 32k */
 178                 map-exec;
 179         };
 180
 181         timer {
 182                 compatible = "arm,armv7-timer";
 183                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 184                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 185                 clock-frequency = <24000000>;
 186         };
 187
 188         timer@ff810000 {
 189                 compatible = "rockchip,timer";
 190                 reg = <0xff810000 0x20>;
 191                 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
 192                 rockchip,broadcast = <1>;
 193         };
 194
 195         watchdog:wdt@2004c000 {
 196                 compatible = "rockchip,watch dog";
 197                 reg = <0xff800000 0x100>;
 198                 clocks = <&pclk_pd_alive>;
 199                 clock-names = "pclk_wdt";
 200                 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
 201                 rockchip,irq = <0>;
 202                 rockchip,timeout = <60>;
 203                 rockchip,atboot = <1>;
 204                 rockchip,debug = <0>;
 205                 status = "disable";
 206         };
 207
 208     amba {
 209                 #address-cells = <1>;
 210                 #size-cells = <1>;
 211                 compatible = "arm,amba-bus";
 212                 interrupt-parent = <&gic>;
 213                 ranges;
 214
 215                 pdma0: pdma@ffb20000 {
 216                         compatible = "arm,pl330", "arm,primecell";
 217                         reg = <0xffb20000 0x4000>;
 218                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 219                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 220                         #dma-cells = <1>;
 221                 };
 222
 223                 pdma1: pdma@ff250000 {
 224                         compatible = "arm,pl330", "arm,primecell";
 225                         reg = <0xff250000 0x4000>;
 226                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
 227                                      <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 228                         #dma-cells = <1>;
 229                 };
 230         };
 231
 232
 233         emmc: rksdmmc@ff0f0000 {
 234                 compatible = "rockchip,rk_mmc";
 235                 reg = <0xff0f0000 0x4000>;
 236                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;/*irq=67*/
 237                 #address-cells = <1>;
 238                 #size-cells = <0>;
 239                 //pinctrl-names = "default",,"suspend";
 240                 //pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_wp &sd0_pwr &sd0_bus1 &sd0_bus4>;
 241
 242                 clocks = <&clk_emmc>, <&clk_gates8 6>;
 243                 clock-names = "clk_mmc", "hclk_mmc";
 244                 num-slots = <1>;
 245                 fifo-depth = <0x80>;
 246                 bus-width = <4>;
 247         };
 248
 249         sdmmc: rksdmmc@ff0c0000 {
 250           compatible = "rockchip,rk_mmc";
 251                 reg = <0xff0c0000 0x4000>;
 252                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; /*irq=64*/
 253           #address-cells = <1>;
 254           #size-cells = <0>;
 255
 256                 pinctrl-names = "default","idle";
 257           pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_dectn &sdmmc0_bus4>;
 258           pinctrl-1 = <&sdmmc0_gpio>;
 259
 260                 clocks = <&clk_sdmmc>, <&clk_gates8 3>;
 261                 clock-names = "clk_mmc", "hclk_mmc";
 262         num-slots = <1>;
 263           fifo-depth = <0x100>;
 264           bus-width = <4>;
 265
 266         };
 267
 268         sdio: rksdmmc@ff0d0000 {
 269                 compatible = "rockchip,rk_mmc";
 270           reg = <0xff0d0000 0x4000>;
 271           interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 272           #address-cells = <1>;
 273           #size-cells = <0>;
 274           pinctrl-names = "default","idle";
 275           pinctrl-0 = <&sdio0_clk &sdio0_cmd &sdio0_dectn  &sdio0_wrprt &sdio0_pwr &sdio0_bkpwr
 276                                          &sdio0_intn &sdio0_bus4>;
 277           pinctrl-1 = <&sdio0_gpio>;
 278
 279                 clocks = <&clk_sdio0>, <&clk_gates8 4>;
 280                 clock-names = "clk_mmc", "hclk_mmc";
 281     num-slots = <1>;
 282
 283           fifo-depth = <0x100>;
 284           bus-width = <4>;
 285         };
 286
 287         sdio1: rksdmmc@ff0e0000 {
 288                 compatible = "rockchip,rk_mmc";
 289                 reg = <0xff0e0000 0x4000>;
 290                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 291                 #address-cells = <1>;
 292                 #size-cells = <0>;
 293                 //pinctrl-names = "default","suspend";
 294                 //pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_cd &sd1_wp &sd1_bus1 &sd1_bus4>;
 295
 296                 /*gate8_0 --hclk_sdmmc_ahb_arbi_gate_en, gate13_2 --clk_sdio1_src_gate_en*/
 297                 clocks = <&clk_sdio1>, <&clk_gates8 5>;
 298                 clock-names = "clk_mmc", "hclk_mmc";
 299                 num-slots = <1>;
 300
 301                 fifo-depth = <0x100>;
 302                 bus-width = <4>;
 303                 status = "disabled";
 304         };
 305
 306         spi0: spi@ff110000 {
 307                 compatible = "rockchip,rockchip-spi";
 308                 reg = <0xff110000 0x1000>;
 309                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 310                 #address-cells = <1>;
 311                 #size-cells = <0>;
 312                 pinctrl-names = "default";
 313                 pinctrl-0 = <&spi0_txd &spi0_rxd &spi0_clk &spi0_cs0 &spi0_cs1>;
 314                 rockchip,spi-src-clk = <0>;
 315                 num-cs = <2>;
 316                 clocks =<&clk_spi0>, <&clk_gates6 4>;
 317                 clock-names = "spi","pclk_spi0";
 318                 //dmas = <&pdma1 11>, <&pdma1 12>;
 319                 //#dma-cells = <2>;
 320                 //dma-names = "tx", "rx";
 321                 status = "disabled";
 322         };
 323
 324         spi1: spi@ff120000 {
 325                 compatible = "rockchip,rockchip-spi";
 326                 reg = <0xff120000 0x1000>;
 327                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 328                 #address-cells = <1>;
 329                 #size-cells = <0>;
 330                 pinctrl-names = "default";
 331                 pinctrl-0 = <&spi1_txd &spi1_rxd &spi1_clk &spi1_cs0>;
 332                 rockchip,spi-src-clk = <1>;
 333                 num-cs = <1>;
 334                 clocks = <&clk_spi1>, <&clk_gates6 5>;
 335                 clock-names = "spi","pclk_spi1";
 336                 //dmas = <&pdma1 13>, <&pdma1 14>;
 337                 //#dma-cells = <2>;
 338                 //dma-names = "tx", "rx";
 339                 status = "disabled";
 340         };
 341
 342         spi2: spi@ff130000 {
 343                 compatible = "rockchip,rockchip-spi";
 344                 reg = <0xff130000 0x1000>;
 345                 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 346                 #address-cells = <1>;
 347                 #size-cells = <0>;
 348                 pinctrl-names = "default";
 349                 pinctrl-0 = <&spi2_txd &spi2_rxd &spi2_clk &spi2_cs0 &spi2_cs1>;
 350                 rockchip,spi-src-clk = <2>;
 351                 num-cs = <2>;
 352                 clocks = <&clk_spi2>, <&clk_gates6 6>;
 353                 clock-names = "spi","pclk_spi2";
 354                 //dmas = <&pdma1 15>, <&pdma1 16>;
 355                 //#dma-cells = <2>;
 356                 //dma-names = "tx", "rx";
 357                 status = "disabled";
 358         };
 359
 360         uart_bt: serial@ff180000 {
 361                 compatible = "rockchip,serial";
 362                 reg = <0xff180000 0x100>;
 363                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 364                 clock-frequency = <24000000>;
 365                 clocks = <&clk_uart0>, <&clk_gates6 8>;
 366                 clock-names = "sclk_uart", "pclk_uart";
 367                 reg-shift = <2>;
 368                 reg-io-width = <4>;
 369                 dmas = <&pdma1 1>, <&pdma1 2>;
 370                 #dma-cells = <2>;
 371                 pinctrl-names = "default";
 372                 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
 373                 status = "disabled";
 374         };
 375
 376         uart_bb: serial@ff190000 {
 377                 compatible = "rockchip,serial";
 378                 reg = <0xff190000 0x100>;
 379                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 380                 clock-frequency = <24000000>;
 381                 clocks = <&clk_uart1>, <&clk_gates6 9>;
 382                 clock-names = "sclk_uart", "pclk_uart";
 383                 reg-shift = <2>;
 384                 reg-io-width = <4>;
 385                 dmas = <&pdma1 3>, <&pdma1 4>;
 386                 #dma-cells = <2>;
 387                 pinctrl-names = "default";
 388                 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
 389                 status = "disabled";
 390         };
 391
 392         uart_dbg: serial@ff690000 {
 393                 compatible = "rockchip,serial";
 394                 reg = <0xff690000 0x100>;
 395                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 396                 clock-frequency = <24000000>;
 397                 clocks = <&clk_uart2>, <&clk_gates11 9>;
 398                 clock-names = "sclk_uart", "pclk_uart";
 399                 reg-shift = <2>;
 400                 reg-io-width = <4>;
 401                 dmas = <&pdma0 4>, <&pdma0 5>;
 402                 #dma-cells = <2>;
 403                 pinctrl-names = "default";
 404                 pinctrl-0 = <&uart2_xfer>;
 405                 status = "disabled";
 406         };
 407
 408         uart_gps: serial@ff1b0000 {
 409                 compatible = "rockchip,serial";
 410                 reg = <0xff1b0000 0x100>;
 411                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 412                 clock-frequency = <24000000>;
 413                 clocks = <&clk_uart3>, <&clk_gates6 11>;
 414                 clock-names = "sclk_uart", "pclk_uart";
 415                 current-speed = <115200>;
 416                 reg-shift = <2>;
 417                 reg-io-width = <4>;
 418                 dmas = <&pdma1 7>, <&pdma1 8>;
 419                 #dma-cells = <2>;
 420                 pinctrl-names = "default";
 421                 pinctrl-0 = <&uart3_xfer &uart3_cts &uart3_rts>;
 422                 status = "disabled";
 423         };
 424
 425         uart_exp: serial@ff1c0000 {
 426                 compatible = "rockchip,serial";
 427                 reg = <0xff1c0000 0x100>;
 428                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 429                 clock-frequency = <24000000>;
 430                 clocks = <&clk_uart4>, <&clk_gates6 12>;
 431                 clock-names = "sclk_uart", "pclk_uart";
 432                 reg-shift = <2>;
 433                 reg-io-width = <4>;
 434                 dmas = <&pdma1 9>, <&pdma1 10>;
 435                 #dma-cells = <2>;
 436                 pinctrl-names = "default";
 437                 pinctrl-0 = <&uart4_xfer &uart4_cts &uart4_rts>;
 438                 status = "disabled";
 439         };
 440
 441         fiq-debugger {
 442                 compatible = "rockchip,fiq-debugger";
 443                 rockchip,serial-id = <2>;
 444                 rockchip,signal-irq = <106>;
 445                 rockchip,wake-irq = <0>;
 446                 status = "disabled";
 447         };
 448
 449         clocks-init{
 450                 compatible = "rockchip,clocks-init";
 451                 rockchip,clocks-init-parent =
 452                         <&clk_core &clk_apll>,  <&aclk_bus_src &clk_gpll>,
 453                         <&aclk_peri &clk_gpll>, <&uart_pll_mux &clk_gpll>,
 454                         <&clk_i2s_pll &clk_cpll>;
 455                 rockchip,clocks-init-rate =
 456                         <&clk_core 792000000>,  <&clk_gpll 594000000>,
 457                         <&clk_cpll 384000000>,  <&clk_npll 500000000>,
 458                         <&aclk_bus_src 300000000>,      <&aclk_bus 300000000>,
 459                         <&hclk_bus 150000000>,  <&pclk_bus 75000000>,
 460                         <&clk_crypto 150000000>,        <&aclk_peri 300000000>,
 461                         <&hclk_peri 150000000>, <&pclk_peri 75000000>,
 462                         <&clk_gpu 200000000>,   <&aclk_vio0 300000000>,
 463                         <&aclk_vio1 300000000>, <&hclk_vio 75000000>,
 464                         <&pclk_pd_alive 100000000>,     <&pclk_pd_pmu 100000000>,
 465                         <&aclk_hevc 400000000>, <&hclk_hevc 200000000>,
 466                         <&clk_hevc_cabac 300000000>, <&clk_hevc_core 300000000>,
 467                         <&aclk_rga 300000000>, <&clk_rga 300000000>,
 468                         <&clk_vepu 300000000>, <&clk_vdpu 300000000>,
 469                         <&clk_edp 200000000>, <&clk_isp 200000000>,
 470                         <&clk_isp_jpe 400000000>, <&clk_tsp 80000000>,
 471                         <&clk_tspout 80000000>, <&clk_mac 125000000>;
 472         };
 473
 474         i2c0: i2c@ff650000 {
 475                 compatible = "rockchip,rk30-i2c";
 476                 reg = <0xff650000 0x1000>;
 477                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 478                 #address-cells = <1>;
 479                 #size-cells = <0>;
 480                 pinctrl-names = "default", "gpio";
 481                 pinctrl-0 = <&i2c0_sda &i2c0_scl>;
 482                 pinctrl-1 = <&i2c0_gpio>;
 483                 gpios = <&gpio0 GPIO_B7 GPIO_ACTIVE_LOW>, <&gpio0 GPIO_C0 GPIO_ACTIVE_LOW>;
 484                 clocks = <&clk_gates10 2>;
 485                 rockchip,check-idle = <1>;
 486                 status = "disabled";
 487         };
 488
 489         i2c1: i2c@ff140000 {
 490                 compatible = "rockchip,rk30-i2c";
 491                 reg = <0xff140000 0x1000>;
 492                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 493                 #address-cells = <1>;
 494                 #size-cells = <0>;
 495                 pinctrl-names = "default", "gpio";
 496                 pinctrl-0 = <&i2c1_sda &i2c1_scl>;
 497                 pinctrl-1 = <&i2c1_gpio>;
 498                 gpios = <&gpio8 GPIO_A4 GPIO_ACTIVE_LOW>, <&gpio8 GPIO_A5 GPIO_ACTIVE_LOW>;
 499                 clocks = <&clk_gates10 3>;
 500                 rockchip,check-idle = <1>;
 501                 status = "disabled";
 502         };
 503
 504         i2c2: i2c@ff660000 {
 505                 compatible = "rockchip,rk30-i2c";
 506                 reg = <0xff660000 0x1000>;
 507                 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 508                 #address-cells = <1>;
 509                 #size-cells = <0>;
 510                 pinctrl-names = "default", "gpio";
 511                 pinctrl-0 = <&i2c2_sda &i2c2_scl>;
 512                 pinctrl-1 = <&i2c2_gpio>;
 513                 gpios = <&gpio6 GPIO_B1 GPIO_ACTIVE_LOW>, <&gpio6 GPIO_B2 GPIO_ACTIVE_LOW>;
 514                 clocks = <&clk_gates6 13>;
 515                 rockchip,check-idle = <1>;
 516                 status = "disabled";
 517         };
 518
 519         i2c3: i2c@ff150000 {
 520                 compatible = "rockchip,rk30-i2c";
 521                 reg = <0xff150000 0x1000>;
 522                 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 523                 #address-cells = <1>;
 524                 #size-cells = <0>;
 525                 pinctrl-names = "default", "gpio";
 526                 pinctrl-0 = <&i2c3_sda &i2c3_scl>;
 527                 pinctrl-1 = <&i2c3_gpio>;
 528                 gpios = <&gpio2 GPIO_C1 GPIO_ACTIVE_LOW>, <&gpio2 GPIO_C0 GPIO_ACTIVE_LOW>;
 529                 clocks = <&clk_gates6 14>;
 530                 rockchip,check-idle = <1>;
 531                 status = "disabled";
 532         };
 533
 534         i2c4: i2c@ff160000 {
 535                 compatible = "rockchip,rk30-i2c";
 536                 reg = <0xff160000 0x1000>;
 537                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 538                 #address-cells = <1>;
 539                 #size-cells = <0>;
 540                 pinctrl-names = "default", "gpio";
 541                 pinctrl-0 = <&i2c4_sda &i2c4_scl>;
 542                 pinctrl-1 = <&i2c4_gpio>;
 543                 gpios = <&gpio7 GPIO_C1 GPIO_ACTIVE_LOW>, <&gpio7 GPIO_C2 GPIO_ACTIVE_LOW>;
 544                 clocks = <&clk_gates6 15>;
 545                 rockchip,check-idle = <1>;
 546                 status = "disabled";
 547         };
 548
 549         i2c5: i2c@ff170000 {
 550                 compatible = "rockchip,rk30-i2c";
 551                 reg = <0xff170000 0x1000>;
 552                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 553                 #address-cells = <1>;
 554                 #size-cells = <0>;
 555                 pinctrl-names = "default", "gpio";
 556                 pinctrl-0 = <&i2c5_sda &i2c5_scl>;
 557                 pinctrl-1 = <&i2c5_gpio>;
 558                 gpios = <&gpio7 GPIO_C3 GPIO_ACTIVE_LOW>, <&gpio7 GPIO_C4 GPIO_ACTIVE_LOW>;
 559                 clocks = <&clk_gates7 0>;
 560                 rockchip,check-idle = <1>;
 561                 status = "disabled";
 562         };
 563
 564
 565         fb: fb{
 566                 compatible = "rockchip,rk-fb";
 567                 rockchip,disp-mode = <DUAL>;
 568         };
 569
 570         rk_screen: rk_screen{
 571                         compatible = "rockchip,screen";
 572         };
 573
 574         dsihost0: mipi@ff960000{
 575                 compatible = "rockchip,rk32-dsi";
 576                 rockchip,prop = <0>;
 577                 reg = <0xff960000 0x4000>;
 578                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 579                 status = "okay";
 580         };
 581
 582         dsihost1: mipi@ff964000{
 583                 compatible = "rockchip,rk32-dsi";
 584                 rockchip,prop = <1>;
 585                 reg = <0xff964000 0x4000>;
 586                 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 587                 status = "disabled";
 588         };
 589
 590         lvds: lvds@ff96c000 {
 591                 compatible = "rockchip,rk32-lvds";
 592                 reg = <0xff96c000 0x4000>;
 593                 clocks = <&clk_gates16 7>;
 594                 clock-names = "pclk_lvds";
 595         };
 596
 597         edp: edp@ff970000 {
 598                 compatible = "rockchip,rk32-edp";
 599                 reg = <0xff970000 0x4000>;
 600                 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
 601                 clocks = <&clk_edp>, <&clk_edp_24m>, <&clk_gates16 8>;
 602                 clock-names = "clk_edp", "clk_edp_24m", "pclk_edp";
 603         };
 604
 605         hdmi: hdmi@ff980000 {
 606                 compatible = "rockchip,rk3288-hdmi";
 607                 reg = <0xff980000 0x20000>;
 608                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
 609                 pinctrl-names = "default", "gpio";
 610                 pinctrl-0 = <&i2c5_sda &i2c5_scl>;
 611                 pinctrl-1 = <&i2c5_gpio>;
 612                 clocks = <&clk_gates16 9>;
 613                 clock-names = "pclk_hdmi";
 614                 status = "disabled";
 615         };
 616
 617         lcdc1: lcdc@ff940000 {
 618                 compatible = "rockchip,rk3288-lcdc";
 619                 rockchip,prop = <PRMRY>;
 620                 rochchip,pwr18 = <0>;
 621                 reg = <0xff940000 0x10000>;
 622                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 623                 pinctrl-names = "default", "gpio";
 624                 pinctrl-0 = <&lcdc0_lcdc>;
 625                 pinctrl-1 = <&lcdc0_gpio>;
 626                 status = "disabled";
 627                 clocks = <&clk_gates15 7>, <&dclk_lcdc1>, <&clk_gates15 8>;
 628                 clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc";
 629         };
 630
 631         lcdc0: lcdc@ff930000 {
 632                 compatible = "rockchip,rk3288-lcdc";
 633                 rockchip,prop = <EXTEND>;
 634                 rockchip,pwr18 = <0>;
 635                 reg = <0xff930000 0x10000>;
 636                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 637                 //pinctrl-names = "default", "gpio";
 638                 //pinctrl-0 = <&lcdc0_lcdc>;
 639                 //pinctrl-1 = <&lcdc0_gpio>;
 640                 status = "disabled";
 641                 clocks = <&clk_gates15 5>, <&dclk_lcdc0>, <&clk_gates15 6>;
 642                 clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc";
 643         };
 644
 645         adc: adc@ff100000 {
 646                 compatible = "rockchip,saradc";
 647                 reg = <0xff100000 0x100>;
 648                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 649                 #io-channel-cells = <1>;
 650                 io-channel-ranges;
 651                 rockchip,adc-vref = <1800>;
 652                 clock-frequency = <1000000>;
 653                 clocks = <&clk_saradc>, <&clk_gates7 1>;
 654                 clock-names = "saradc", "pclk_saradc";
 655                 status = "disabled";
 656         };
 657
 658         rga@ff920000 {
 659                 compatible = "rockchip,rga";
 660                 reg = <0xff920000 0x1000>;
 661                 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
 662                 clocks = <&clk_gates15 1>, <&aclk_rga>, <&clk_rga>;
 663                 clock-names = "hclk_rga", "aclk_rga", "clk_rga";
 664         };
 665
 666         i2s: rockchip-i2s@0xff890000 {
 667                 compatible = "rockchip-i2s";
 668                 reg = <0xff890000 0x10000>;
 669                 i2s-id = <0>;
 670                 clocks = <&clk_i2s>, <&clk_i2s_out>;
 671                 clock-names = "i2s_clk","i2s_mclk";
 672                 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 673                 dmas = <&pdma0 0>,
 674                         <&pdma0 1>;
 675                 //#dma-cells = <2>;
 676                 dma-names = "tx", "rx";
 677                 pinctrl-names = "default", "sleep";
 678                 pinctrl-0 = <&i2s_mclk &i2s_sclk &i2s_lrckrx &i2s_lrcktx &i2s_sdi &i2s_sdo0 &i2s_sdo1 &i2s_sdo2 &i2s_sdo3>;
 679                 pinctrl-1 = <&i2s_gpio>;
 680         };
 681
 682         spdif: rockchip-spdif@0xff8b0000 {
 683                 compatible = "rockchip-spdif";
 684                 reg = <0xff8b0000 0x10000>;     //8channel
 685                 //reg = <ff880000 0x10000>;//2channel
 686                 clocks = <&clk_spdif>, <&clk_spdif_8ch>;
 687                 clock-names = "spdif_mclk","spdif_8ch_mclk";
 688                 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 689                 dmas = <&pdma0 3>;
 690                 //dmas = <&pdma0 2>; //2channel
 691                 //#dma-cells = <1>;
 692                 dma-names = "tx";
 693                 pinctrl-names = "default";
 694                 pinctrl-0 = <&spdif_tx>;
 695         };
 696
 697         pwm0: pwm@ff680000 {
 698                 compatible = "rockchip,rk-pwm";
 699                 reg = <0xff680000 0x10>;
 700                 #pwm-cells = <2>;
 701                 pinctrl-names = "default";
 702                 pinctrl-0 = <&pwm0_pin>;
 703                 clocks = <&clk_gates11 11>;
 704                 clock-names = "pclk_pwm";
 705                 status = "okay";
 706         };
 707
 708         pwm1: pwm@ff680010 {
 709                 compatible = "rockchip,rk-pwm";
 710                 reg = <0xff680010 0x10>;
 711                 #pwm-cells = <2>;
 712                 pinctrl-names = "default";
 713                 pinctrl-0 = <&pwm1_pin>;
 714                 clocks = <&clk_gates11 11>;
 715                 clock-names = "pclk_pwm";
 716                 status = "disabled";
 717         };
 718
 719         pwm2: pwm@ff680020 {
 720                 compatible = "rockchip,rk-pwm";
 721                 reg = <0xff680020 0x10>;
 722                 #pwm-cells = <2>;
 723                 pinctrl-names = "default";
 724                 pinctrl-0 = <&pwm2_pin>;
 725                 clocks = <&clk_gates11 11>;
 726                 clock-names = "pclk_pwm";
 727                 status = "disabled";
 728         };
 729
 730         pwm3: pwm@ff680030 {
 731                 compatible = "rockchip,rk-pwm";
 732                 reg = <0xff680030 0x10>;
 733                 #pwm-cells = <2>;
 734                 pinctrl-names = "default";
 735                 pinctrl-0 = <&pwm3_pin>;
 736                 clocks = <&clk_gates11 11>;
 737                 clock-names = "pclk_pwm";
 738                 status = "disabled";
 739         };
 740         dvfs {
 741                 vd_arm:
 742                 vd_arm {
 743                         regulator_name="vdd_arm";
 744                         suspend_volt=<1000>; //mV
 745                         pd_core {
 746                                 clk_core_dvfs_table:
 747                                 clk_core {
 748                                         operating-points = <
 749                                                 /* KHz    uV */
 750                                                 312000 1100000
 751                                                 504000 1100000
 752                                                 816000 1100000
 753                                                 1008000 1100000
 754                                                 >;
 755                                         temp-channel=<1>;
 756                                         temp-limit = <
 757                                                 /*temp    freq*/
 758                                                 50      1608000
 759                                                 70      1416000
 760                                                 80      1200000
 761                                                 100     1008000
 762                                                 >;
 763                                         status = "okay";
 764                                 };
 765                         };
 766                 };
 767
 768                 vd_logic:
 769                 vd_logic {
 770                         regulator_name="vdd_logic";
 771                         suspend_volt=<1000>; //mV
 772                         pd_ddr {
 773                                 clk_ddr_dvfs_table:
 774                                 clk_ddr {
 775                                         operating-points = <
 776                                                 /* KHz    uV */
 777                                                 200000 1200000
 778                                                 300000 1200000
 779                                                 400000 1200000
 780                                                 >;
 781                                         status = "disable";
 782                                 };
 783                         };
 784
 785                         pd_vpu {
 786                                 clk_ddr_vepu_table:
 787                                 clk_vepu {
 788                                         operating-points = <
 789                                                 /* KHz    uV */
 790                                                 200000 1300000
 791                                                 300000 1300000
 792                                                 400000 1300000
 793                                                 >;
 794                                         status = "okay";
 795                                 };
 796                         };
 797                 };
 798
 799                 vd_gpu:
 800                 vd_gpu {
 801                         regulator_name="vdd_gpu";
 802                         suspend_volt=<1000>; //mV
 803                         pd_gpu {
 804                                 clk_gpu_dvfs_table:
 805                                 clk_gpu {
 806                                         operating-points = <
 807                                                 /* KHz    uV */
 808                                                 200000 1200000
 809                                                 300000 1200000
 810                                                 400000 1200000
 811                                                 >;
 812                                         temp-channel=<2>;
 813                                         temp-limit = <
 814                                                 /*temp    freq*/
 815                                                 50      600000
 816                                                 70      500000
 817                                                 80      400000
 818                                                 100     300000
 819                                                 >;
 820                                         status = "okay";
 821                                 };
 822                         };
 823                 };
 824         };
 825
 826         ion {
 827                 compatible = "rockchip,ion";
 828                 #address-cells = <1>;
 829                 #size-cells = <0>;
 830                 rockchip,ion-heap@1 { /* CMA HEAP */
 831                         compatible = "rockchip,ion-reserve";
 832                         reg = <1>;
 833                         memory-reservation = <0x00000000 0x18000000>; /* 384MB */
 834                 };
 835                 rockchip,ion-heap@3 { /* SYSTEM HEAP */
 836                         reg = <3>;
 837                 };
 838         };
 839
 840
 841         vpu: vpu_service@ff9a0000 {
 842                 compatible = "vpu_service";
 843                 reg = <0xff9a0000 0x800>;
 844                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 845                 interrupt-names = "irq_enc", "irq_dec";
 846                 clocks = <&clk_vdpu>, <&hclk_vdpu>;
 847                 clock-names = "aclk_vcodec", "hclk_vcodec";
 848                 name = "vpu_service";
 849                 //status = "disabled";
 850         };
 851
 852         hevc: hevc_service@ff9c0000 {
 853                 compatible = "rockchip,hevc_service";
 854                 reg = <0xff9c0000 0x800>;
 855                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 856                 interrupt-names = "irq_dec";
 857                 clocks = <&aclk_hevc>, <&hclk_hevc>, <&clk_hevc_core>, <&clk_hevc_cabac>;
 858                 clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core", "clk_cabac";
 859                 name = "hevc_service";
 860                 //status = "disabled";
 861         };
 862
 863         iep: iep@ff900000 {
 864                 compatible = "rockchip,iep";
 865                 reg = <0xff900000 0x800>;
 866                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 867                 clocks = <&clk_gates15 2>, <&clk_gates15 3>;
 868                 clock_names = "aclk_iep", "hclk_iep";
 869                 status = "okay";
 870         };
 871
 872         dwc_control_usb: dwc-control-usb@ff770284 {
 873                 compatible = "rockchip,rk3288-dwc-control-usb";
 874                 reg = <0xff770284 0x04>, <0xff770288 0x04>,
 875                       <0xff7702cc 0x04>, <0xff7702d4 0x04>,
 876                       <0xff770320 0x14>, <0xff770334 0x14>,
 877                       <0xff770348 0x10>, <0xff770358 0x08>,
 878                       <0xff770360 0x08>;
 879                 reg-names = "GRF_SOC_STATUS1" ,"GRF_SOC_STATUS2",
 880                     "GRF_SOC_STATUS19", "GRF_SOC_STATUS21",
 881                     "GRF_UOC0_BASE", "GRF_UOC1_BASE",
 882                     "GRF_UOC2_BASE", "GRF_UOC3_BASE",
 883                     "GRF_UOC4_BASE";
 884                 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
 885                      <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
 886                      <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
 887                 interrupt-names = "otg_id", "otg_bvalid",
 888                           "otg_linestate", "host0_linestate",
 889                           "host1_linestate";
 890                 gpios = <&gpio0 GPIO_B6 GPIO_ACTIVE_LOW>,/*HOST_VBUS_DRV*/
 891                         <&gpio0 GPIO_B4 GPIO_ACTIVE_LOW>;/*OTG_VBUS_DRV*/
 892                 clocks = <&clk_gates7 9>;
 893                 clock-names = "hclk_usb_peri";
 894                 rockchip,remote_wakeup;
 895                 rockchip,usb_irq_wakeup;
 896
 897                 usb_bc{
 898                         compatible = "synopsys,phy";
 899                                         /* offset bit mask */
 900                         rk_usb,bvalid     = <0x288 14 1>;
 901                         rk_usb,dcdenb     = <0x328 14 1>;
 902                         rk_usb,vdatsrcenb = <0x328  7 1>;
 903                         rk_usb,vdatdetenb = <0x328  6 1>;
 904                         rk_usb,chrgsel    = <0x328  5 1>;
 905                         rk_usb,chgdet     = <0x2cc 23 1>;
 906                         rk_usb,fsvminus   = <0x2cc 25 1>;
 907                         rk_usb,fsvplus    = <0x2cc 24 1>;
 908                 };
 909         };
 910
 911         usb0: usb@ff580000 {
 912                 compatible = "rockchip,rk3288_usb20_otg";
 913                 reg = <0xff580000 0x40000>;
 914                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 915                 clocks = <&clk_gates13 4>, <&clk_gates7 4>;
 916                 clock-names = "clk_usbphy0", "hclk_usb0";
 917                 /*0 - Normal, 1 - Force Host, 2 - Force Device*/
 918                 rockchip,usb-mode = <0>;
 919         };
 920
 921         usb1: usb@ff540000 {
 922                 compatible = "rockchip,rk3288_usb20_host";
 923                 reg = <0xff540000 0x40000>;
 924                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 925                 clocks = <&clk_gates13 6>, <&clk_gates7 7>;
 926                 clock-names = "clk_usbphy1", "hclk_usb1";
 927         };
 928
 929         usb2: usb@ff500000 {
 930                 compatible = "rockchip,rk3288_rk_ehci_host";
 931                 reg = <0xff500000 0x20000>;
 932                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 933                 clocks = <&clk_gates13 5>, <&clk_gates7 6>;
 934                 clock-names = "clk_usbphy2", "hclk_usb2";
 935         };
 936
 937         usb3: usb@ff520000 {
 938                 compatible = "rockchip,rk3288_rk_ohci_host";
 939                 reg = <0xff520000 0x20000>;
 940                 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 941                 clocks = <&clk_gates13 5>, <&clk_gates7 6>;
 942                 clock-names = "clk_usbphy3", "hclk_usb3";
 943         };
 944
 945         hsic: hsic@ff5c0000 {
 946                 compatible = "rockchip,rk3288_rk_hsic_host";
 947                 reg = <0xff5c0000 0x40000>;
 948                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 949                 clocks = <&hsicphy_480m>, <&clk_gates7 8>,
 950                          <&hsicphy_12m>, <&usbphy_480m>,
 951                          <&otgphy1_480m>, <&otgphy2_480m>;
 952                 clock-names = "hsicphy_480m", "hclk_hsic",
 953                               "hsicphy_12m", "usbphy_480m",
 954                               "hsic_usbphy1", "hsic_usbphy2";
 955         };
 956
 957         gmac: eth@ff290000 {
 958                 compatible = "rockchip,gmac";
 959                 reg = <0xff290000 0x10000>;
 960                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;  /*irq=59*/
 961                 interrupt-names = "macirq";
 962                 //phy-mode = "rmii";
 963                 phy-mode = "rgmii";
 964                 pinctrl-names = "default";
 965                 pinctrl-0 = <&mac_clk &mac_txpins &mac_rxpins &mac_mdpins>;
 966         };
 967     gpu{
 968         compatible = "arm,malit764",
 969                      "arm,malit76x",
 970                      "arm,malit7xx",
 971                      "arm,mali-midgard";
 972         reg = <0xffa30000 0x10000>;
 973         interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
 974                      <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
 975                      <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
 976         interrupt-names = "JOB",
 977                           "MMU",
 978                           "GPU";
 979     };
 980
 981     iep_mmu{
 982         dbgname = "iep";
 983         compatible = "iommu,iep_mmu";
 984         reg = <0xff900800 0x100>;
 985         interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 986         interrupt-names = "iep_mmu";
 987     };
 988
 989     vip_mmu{
 990         dbgname = "vip";
 991         compatible = "iommu,vip_mmu";
 992         reg = <0xff950800 0x100>;
 993         interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
 994         interrupt-names = "vip_mmu";
 995     };
 996
 997     isp_mmu0{
 998         dbgname = "isp_mmu0";
 999         compatible = "iommu,isp_mmu0";
1000         reg = <0xff914000 0x100>;
1001         interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1002         interrupt-names = "isp_mmu0";
1003     };
1004
1005     isp_mmu1{
1006         dbgname = "isp_mmu1";
1007         compatible = "iommu,isp_mmu1";
1008         reg = <0xff915000 0x100>;
1009         interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1010         interrupt-names = "isp_mmu1";
1011     };
1012
1013     vopb_mmu{
1014         dbgname = "vopb";
1015         compatible = "iommu,vopb_mmu";
1016         reg = <0xff930300 0x100>;
1017         interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1018         interrupt-names = "vopb_mmu";
1019     };
1020
1021     vopl_mmu{
1022         dbgname = "vopl";
1023         compatible = "iommu,vopl_mmu";
1024         reg = <0xff940300 0x100>;
1025         interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1026         interrupt-names = "vopl_mmu";
1027     };
1028
1029     hevc_mmu{
1030         dbgname = "hevc";
1031         compatible = "iommu,hevc_mmu";
1032         reg = <0xff9c0800 0x100>;
1033         interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
1034         interrupt-names = "hevc_mmu";
1035     };
1036
1037                 vpu_mmu{
1038         dbgname = "vpu";
1039         compatible = "iommu,vpu_mmu";
1040         reg = <0xff9a0800 0x100>;
1041         interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
1042         interrupt-names = "vpu_mmu";
1043     };
1044
1045     rockchip_suspend {
1046                   rockchip,ctrbits = <
1047                                             (0
1048                                             |RKPM_CTR_PWR_DMNS
1049                                             |RKPM_CTR_GTCLKS
1050                                             |RKPM_CTR_PLLS
1051                                             //|RKPM_CTR_SYSCLK_DIV
1052                                             //|RKPM_CTR_IDLEAUTO_MD
1053                                             //|RKPM_CTR_ARMDP_LPMD
1054                                             |RKPM_CTR_ARMOFF_LPMD
1055                                             )
1056                                         >;
1057                   rockchip,pmic-gpios=<
1058                                                     RKPM_PINGPIO_BITS_OUTPUT(GPIO0_A0,RKPM_GPIO_OUT_L)
1059                                                     RKPM_PINGPIO_BITS_INTPUT(GPIO0_A1,RKPM_GPIO_PULL_UP)
1060                                                     >;
1061             };
1062
1063            isp:isp@ff910000{
1064                 compatible = "rockchip,isp";
1065                 reg = <0xff910000 0x10000>;
1066                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1067                 clocks = <&clk_gates16 2>, <&clk_gates16 1>, <&clk_isp>, <&clk_isp_jpe>, <&dummy>, <&clk_cif_out>;
1068                         clock_names = "aclk_isp", "hclk_isp", "clk_isp", "clk_isp_jpe", "pclkin_isp", "clk_vipout";
1069                         pinctrl-names = "default", "isp_dvp8bit","isp_dvp10bit","isp_dvp12bit";
1070                         pinctrl-0 = <&isp_mipi>;
1071                         pinctrl-1 = <&isp_mipi &isp_dvp_sync_d2d9>;
1072                         pinctrl-2 = <&isp_mipi &isp_dvp_sync_d2d9 &isp_dvp_d0d1>;
1073                         pinctrl-3 = <&isp_mipi &isp_dvp_sync_d2d9 &isp_dvp_d0d1 &isp_dvpd10d11>;
1074
1075                         status = "okay";
1076         };
1077
1078         tsadc: tsadc@ff280000{
1079                         compatible = "rockchip,tsadc";
1080                         reg = <0xff280000 0x100>;
1081                         interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
1082                         #io-channel-cells = <1>;
1083                         io-channel-ranges;
1084                         clock-frequency = <50000>;
1085                         clocks = <&clk_tsadc>, <&clk_gates7 2>;
1086                         clock-names = "tsadc", "pclk_tsadc";
1087                         status = "okay";
1088         };
1089
1090
1091 };