3 DWC3- USB3 CONTROLLER. Complies to the generic USB binding properties
4 as described in 'usb/generic.txt'
7 - compatible: must be "snps,dwc3"
8 - reg : Address and length of the register set for the device
9 - interrupts: Interrupts used by the dwc3 controller.
12 - usb-phy : array of phandle for the PHY device. The first element
13 in the array is expected to be a handle to the USB2/HS PHY and
14 the second element is expected to be a handle to the USB3/SS PHY
15 - phys: from the *Generic PHY* bindings
16 - phy-names: from the *Generic PHY* bindings
17 - tx-fifo-resize: determines if the FIFO *has* to be reallocated.
18 - snps,usb3_lpm_capable: determines if platform is USB3 LPM capable
19 - snps,disable_scramble_quirk: true when SW should disable data scrambling.
20 Only really useful for FPGA builds.
21 - snps,has-lpm-erratum: true when DWC3 was configured with LPM Erratum enabled
22 - snps,lpm-nyet-threshold: LPM NYET threshold
23 - snps,phyif_utmi_16_bits: true when configure the core to support
24 UTMI+ PHY with an 16-bit interface.
25 - snps,u2exit_lfps_quirk: set if we want to enable u2exit lfps quirk
26 - snps,u2ss_inp3_quirk: set if we enable P3 OK for U2/SS Inactive quirk
27 - snps,req_p1p2p3_quirk: when set, the core will always request for
28 P1/P2/P3 transition sequence.
29 - snps,del_p1p2p3_quirk: when set core will delay P1/P2/P3 until a certain
30 amount of 8B10B errors occur.
31 - snps,del_phy_power_chg_quirk: when set core will delay PHY power change
33 - snps,lfps_filter_quirk: when set core will filter LFPS reception.
34 - snps,rx_detect_poll_quirk: when set core will disable a 400us delay to start
35 Polling LFPS after RX.Detect.
36 - snps,tx_de_emphasis_quirk: when set core will set Tx de-emphasis value.
37 - snps,tx_de_emphasis: the value driven to the PHY is controlled by the
38 LTSSM during USB3 Compliance mode.
39 - snps,dis_u3_susphy_quirk: when set core will disable USB3 suspend phy.
40 - snps,dis_u2_susphy_quirk: when set core will disable USB2 suspend phy.
41 - snps,dis_enblslpm_quirk: when set clears the enblslpm in GUSB2PHYCFG,
42 disabling the suspend signal to the PHY.
43 - snps,dis_u2_freeclk_exists_quirk: when set, clear the u2_freeclk_exists
44 in GUSB2PHYCFG, specify that USB2 PHY doesn't provide
45 a free-running PHY clock.
46 - snps,is-utmi-l1-suspend: true when DWC3 asserts output signal
47 utmi_l1_suspend_n, false when asserts utmi_sleep_n
48 - snps,hird-threshold: HIRD threshold
49 - snps,hsphy_interface: High-Speed PHY interface selection between "utmi" for
50 UTMI+ and "ulpi" for ULPI when the DWC_USB3_HSPHY_INTERFACE has value 3.
51 - snps,quirk-frame-length-adjustment: Value for GFLADJ_30MHZ field of GFLADJ
52 register for post-silicon frame length adjustment when the
53 fladj_30mhz_sdbnd signal is invalid or incorrect.
55 This is usually a subnode to DWC3 glue to which it is connected.
58 compatible = "snps,dwc3";
59 reg = <0x4a030000 0xcfff>;
61 usb-phy = <&usb2_phy>, <&usb3,phy>;