1 This file is a partial list of people who have contributed to the LLVM
2 project. If you have contributed a patch or made some other contribution to
3 LLVM, please submit a patch to this file to add yourself, and it will be
6 The list is sorted by surname and formatted to allow easy grepping and
7 beautification by scripts. The fields are: name (N), email (E), web-address
8 (W), PGP key ID and fingerprint (P), description (D), snail-mail address
9 (S), and (I) IRC handle.
14 W: http://www.cs.uiuc.edu/~vadve/
15 D: The Sparc64 backend, provider of much wisdom, and motivator for LLVM
19 D: LCSSA pass and related LoopUnswitch work
20 D: GVNPRE pass, DataLayout refactoring, random improvements
23 D: MingW Win32 API portability layer
26 E: aaron@aaronballman.com
27 D: __declspec attributes, Windows support, general bug fixing
30 E: natebegeman@mac.com
31 D: PowerPC backend developer
32 D: Target-independent code generator and analysis improvements
35 E: dberlin@dberlin.org
36 D: ET-Forest implementation.
41 D: General bug fixing/fit & finish, mostly in Clang
44 E: neil@daikokuya.co.uk
45 D: APFloat implementation.
48 E: brukman+llvm@uiuc.edu
49 W: http://misha.brukman.net
50 D: Portions of X86 and Sparc JIT compilers, PowerPC backend
51 D: Incremental bitcode loader
55 D: The `mem2reg' pass - promotes values stored in memory to registers
58 E: bcahoon@codeaurora.org
59 D: Loop unrolling with run-time trip counts.
62 E: chandlerc@gmail.com
63 E: chandlerc@google.com
64 D: Hashing algorithms and interfaces
65 D: Inline cost analysis
66 D: Machine block placement pass
71 D: Fixes to the Reassociation pass, various improvement patches
74 E: evan.cheng@apple.com
75 D: ARM and X86 backends
76 D: Instruction scheduler improvements
77 D: Register allocator improvements
78 D: Loop optimizer improvements
79 D: Target-independent code generator improvements
81 N: Dan Villiom Podlaski Christiansen
85 D: LLVM Makefile improvements
86 D: Clang diagnostic & driver tweaks
90 E: jeffc@jolt-lang.org
91 W: http://jolt-lang.org
92 D: Native Win32 API portability layer
96 D: Original Autoconf support, documentation improvements, bug fixes
99 E: adasgupt@codeaurora.org
100 D: Deterministic finite automaton based infrastructure for VLIW packetization
103 E: stefanus.dutoit@rapidmind.com
104 D: Bug fixes and minor improvements
106 N: Rafael Avila de Espindola
107 E: rafael.espindola@gmail.com
111 E: alkis@evlogimenos.com
112 D: Linear scan register allocator, many codegen improvements, Java frontend
116 D: Basic-block autovectorization, PowerPC backend improvements
119 E: pizza@parseerror.com
120 D: Miscellaneous bug fixes
124 W: http://www.students.uiuc.edu/~gaeke/
125 D: Portions of X86 static and JIT compilers; initial SparcV8 backend
126 D: Dynamic trace optimizer
127 D: FreeBSD/X86 compatibility fixes, the llvm-nm tool
130 E: nicolas.geoffray@lip6.fr
131 W: http://www-src.lip6.fr/homepages/Nicolas.Geoffray/
132 D: PPC backend fixes for Linux
135 D: Portions of the PowerPC backend
138 E: saemghani@gmail.com
139 D: Callgraph class cleanups
141 N: Mikhail Glushenkov
142 E: foldr@codedgers.com
147 D: Miscellaneous bug fixes
150 E: david@goodwinz.net
151 D: Thumb-2 code generator
154 E: greened@obbligato.org
155 D: Miscellaneous bug fixes
156 D: Register allocation refactoring
160 D: Improvements for space efficiency
163 E: grosbach@apple.com
164 D: SjLj exception handling support
165 D: General fixes and improvements for the ARM back-end
167 D: ARM integrated assembler and assembly parser
171 D: PBQP-based register allocator
174 E: gordonhenriksen@mac.com
175 D: Pluggable GC support
179 N: Raul Fernandes Herbster
180 E: raul@dsc.ufcg.edu.br
181 D: JIT support for ARM
184 E: arathorn@fastwebnet.it
185 D: Visual C++ compatibility fixes
188 E: patjenk@wam.umd.edu
193 D: ARM constant islands improvements
194 D: Tail merging improvements
195 D: Rewrite X87 back end
196 D: Use APFloat for floating point constants widely throughout compiler
197 D: Implement X87 long double
200 E: kungfoomaster@nondot.org
201 D: Support for packed types
205 D: Author of LLVM Ada bindings
208 W: http://randomhacks.net/
209 D: llvm-config script
211 N: Anton Korobeynikov
213 D: Mingw32 fixes, cross-compiling support, stdcall/fastcall calling conv.
214 D: x86/linux PIC codegen, aliases, regparm/visibility attributes
215 D: Switch lowering refactoring
219 D: Author of the original C backend
222 E: benny.kra@gmail.com
223 D: Miscellaneous bug fixes
226 E: sundeepk@codeaurora.org
227 D: Implemented DFA-based target independent VLIW packetizer
230 E: christopher.lamb@gmail.com
231 D: aligned load/store support, parts of noalias and restrict support
232 D: vreg subreg infrastructure, X86 codegen improvements based on subregs
237 D: Improvements to the PPC backend, instruction scheduling
238 D: Debug and Dwarf implementation
239 D: Auto upgrade mangler
240 D: llvm-gcc4 svn wrangler
244 W: http://nondot.org/~sabre/
245 D: Primary architect of LLVM
247 N: Tanya Lattner (Tanya Brethour)
249 W: http://nondot.org/~tonic/
250 D: The initial llvm-ar tool, converted regression testsuite to dejagnu
251 D: Modulo scheduling in the SparcV9 backend
252 D: Release manager (1.7+)
255 E: alenhar2@cs.uiuc.edu
256 W: http://www.lenharth.org/~andrewl/
258 D: Sampling based profiling
262 D: PredicateSimplifier pass
264 N: Tony Linthicum, et. al.
265 E: tlinth@codeaurora.org
266 D: Backend for Qualcomm's Hexagon VLIW processor.
268 N: Bruno Cardoso Lopes
269 E: bruno.cardoso@gmail.com
270 W: http://www.brunocardoso.org
274 E: duraid@octopus.com.au
275 W: http://kinoko.c.u-tokyo.ac.jp/~duraid/
276 D: IA64 backend, BigBlock register allocator
279 E: rjmccall@apple.com
280 D: Clang semantic analysis and IR generation
283 E: michael.mccracken@gmail.com
284 D: Line number support for llvmgcc
286 N: Vladimir Merzliakov
288 D: Test suite fixes for FreeBSD
292 D: Added STI Cell SPU backend.
296 D: Support for implicit TLS model used with MS VC runtime
299 E: geek4civic@gmail.com
300 E: chapuni@hf.rim.or.jp
301 D: Cygwin and MinGW support.
305 N: Edward O'Callaghan
306 E: eocallaghan@auroraux.org
307 W: http://www.auroraux.org
308 D: Add Clang support with various other improvements to utils/NewNightlyTest.pl
309 D: Fix and maintain Solaris & AuroraUX support for llvm, various build warnings
310 D: and error clean ups.
314 D: Visual C++ compatibility fixes
316 N: Jakob Stoklund Olesen
318 D: Machine code verifier
320 D: Fast register allocator
321 D: Greedy register allocator
329 D: LTO tool, PassManager rewrite, Loop Pass Manager, Loop Rotate
330 D: GCC PCH Integration (llvm-gcc), llvm-gcc improvements
331 D: Optimizer improvements, Loop Index Split
334 E: peckw@wesleypeck.com
335 W: http://wesleypeck.com/
336 D: MicroBlaze backend
339 E: pichet2000@gmail.com
343 W: http://vladimir_prus.blogspot.com
345 D: Made inst_iterator behave like a proper iterator, LowerConstantExprs pass
348 E: kalle.rasikila@nokia.com
349 D: Some bugfixes to CellSPU
353 D: Cmake dependency chain and various bug fixes
356 E: alexr@leftfield.org
358 D: ARM calling conventions rewrite, hard float support
361 E: mcrosier@apple.com
362 D: ARM fast-isel improvements
363 D: Performance monitoring
367 D: X86 code generation improvements, Loop Vectorizer.
370 E: roman@codedgers.com
376 D: Ada support in llvm-gcc
378 D: Exception handling improvements
379 D: Type legalizer rewrite
383 D: Graph coloring register allocator for the Sparc64 backend
385 N: Arnold Schwaighofer
386 E: arnold.schwaighofer@gmail.com
387 D: Tail call optimization for the x86 backend
391 D: Miscellaneous bug fixes
394 E: ashukla@cs.uiuc.edu
397 N: Michael J. Spencer
398 E: bigcheesegs@gmail.com
399 D: Shepherding Windows COFF support into MC.
400 D: Lots of Windows stuff.
403 E: rspencer@reidspencer.com
404 W: http://reidspencer.com/
405 D: Lots of stuff, see: http://wiki.llvm.org/index.php/User:Reid
408 E: craig.topper@gmail.com
409 D: X86 codegen and disassembler improvements. AVX2 support.
412 E: edwintorok@gmail.com
413 D: Miscellaneous bug fixes
417 D: C++ bugs filed, and C++ front-end bug fixes.
419 N: Lauro Ramos Venancio
420 E: lauro.venancio@indt.org.br
421 D: ARM backend improvements
422 D: Thread Local Storage implementation
425 E: wendling@apple.com
426 D: Exception handling
430 E: bob.wilson@acm.org
431 D: Advanced SIMD (NEON) support in the ARM backend