1 This file is a partial list of people who have contributed to the LLVM
2 project. If you have contributed a patch or made some other contribution to
3 LLVM, please submit a patch to this file to add yourself, and it will be
6 The list is sorted by surname and formatted to allow easy grepping and
7 beautification by scripts. The fields are: name (N), email (E), web-address
8 (W), PGP key ID and fingerprint (P), description (D), snail-mail address
9 (S), and (I) IRC handle.
14 W: http://www.cs.uiuc.edu/~vadve/
15 D: The Sparc64 backend, provider of much wisdom, and motivator for LLVM
19 D: LCSSA pass and related LoopUnswitch work
20 D: GVNPRE pass, DataLayout refactoring, random improvements
23 D: MingW Win32 API portability layer
26 E: aaron@aaronballman.com
27 D: __declspec attributes, Windows support, general bug fixing
30 E: natebegeman@mac.com
31 D: PowerPC backend developer
32 D: Target-independent code generator and analysis improvements
35 E: dberlin@dberlin.org
36 D: ET-Forest implementation.
41 D: General bug fixing/fit & finish, mostly in Clang
44 E: neil@daikokuya.co.uk
45 D: APFloat implementation.
48 E: brukman+llvm@uiuc.edu
49 W: http://misha.brukman.net
50 D: Portions of X86 and Sparc JIT compilers, PowerPC backend
51 D: Incremental bitcode loader
55 D: The `mem2reg' pass - promotes values stored in memory to registers
58 E: bcahoon@codeaurora.org
59 D: Loop unrolling with run-time trip counts.
62 E: chandlerc@gmail.com
63 E: chandlerc@google.com
64 D: Hashing algorithms and interfaces
65 D: Inline cost analysis
66 D: Machine block placement pass
71 D: Fixes to the Reassociation pass, various improvement patches
74 E: evan.cheng@apple.com
75 D: ARM and X86 backends
76 D: Instruction scheduler improvements
77 D: Register allocator improvements
78 D: Loop optimizer improvements
79 D: Target-independent code generator improvements
81 N: Dan Villiom Podlaski Christiansen
85 D: LLVM Makefile improvements
86 D: Clang diagnostic & driver tweaks
90 E: jeffc@jolt-lang.org
91 W: http://jolt-lang.org
92 D: Native Win32 API portability layer
96 D: Original Autoconf support, documentation improvements, bug fixes
99 E: adasgupt@codeaurora.org
100 D: Deterministic finite automaton based infrastructure for VLIW packetization
103 E: stefanus.du.toit@intel.com
104 D: Bug fixes and minor improvements
106 N: Rafael Avila de Espindola
107 E: rafael.espindola@gmail.com
111 E: alkis@evlogimenos.com
112 D: Linear scan register allocator, many codegen improvements, Java frontend
116 D: Basic-block autovectorization, PowerPC backend improvements
119 E: pizza@parseerror.com
120 D: Miscellaneous bug fixes
124 W: http://www.students.uiuc.edu/~gaeke/
125 D: Portions of X86 static and JIT compilers; initial SparcV8 backend
126 D: Dynamic trace optimizer
127 D: FreeBSD/X86 compatibility fixes, the llvm-nm tool
130 E: nicolas.geoffray@lip6.fr
131 W: http://www-src.lip6.fr/homepages/Nicolas.Geoffray/
132 D: PPC backend fixes for Linux
136 D: Portions of the PowerPC backend
139 E: saemghani@gmail.com
140 D: Callgraph class cleanups
142 N: Mikhail Glushenkov
143 E: foldr@codedgers.com
147 E: dan433584@gmail.com
148 D: Miscellaneous bug fixes
151 E: david@goodwinz.net
152 D: Thumb-2 code generator
155 E: greened@obbligato.org
156 D: Miscellaneous bug fixes
157 D: Register allocation refactoring
161 D: Improvements for space efficiency
164 E: grosbach@apple.com
166 D: SjLj exception handling support
167 D: General fixes and improvements for the ARM back-end
169 D: ARM integrated assembler and assembly parser
170 D: Led effort for the backend formerly known as ARM64
174 D: PBQP-based register allocator
177 E: gordonhenriksen@mac.com
178 D: Pluggable GC support
182 N: Raul Fernandes Herbster
183 E: raul@dsc.ufcg.edu.br
184 D: JIT support for ARM
187 E: arathorn@fastwebnet.it
188 D: Visual C++ compatibility fixes
191 E: patjenk@wam.umd.edu
196 D: ARM constant islands improvements
197 D: Tail merging improvements
198 D: Rewrite X87 back end
199 D: Use APFloat for floating point constants widely throughout compiler
200 D: Implement X87 long double
203 E: kungfoomaster@nondot.org
204 D: Support for packed types
208 D: Author of LLVM Ada bindings
211 W: http://randomhacks.net/
212 D: llvm-config script
214 N: Anton Korobeynikov
216 D: Mingw32 fixes, cross-compiling support, stdcall/fastcall calling conv.
217 D: x86/linux PIC codegen, aliases, regparm/visibility attributes
218 D: Switch lowering refactoring
222 D: Author of the original C backend
225 E: benny.kra@gmail.com
226 D: Miscellaneous bug fixes
229 E: sundeepk@codeaurora.org
230 D: Implemented DFA-based target independent VLIW packetizer
233 E: christopher.lamb@gmail.com
234 D: aligned load/store support, parts of noalias and restrict support
235 D: vreg subreg infrastructure, X86 codegen improvements based on subregs
240 D: Improvements to the PPC backend, instruction scheduling
241 D: Debug and Dwarf implementation
242 D: Auto upgrade mangler
243 D: llvm-gcc4 svn wrangler
247 W: http://nondot.org/~sabre/
248 D: Primary architect of LLVM
250 N: Tanya Lattner (Tanya Brethour)
252 W: http://nondot.org/~tonic/
253 D: The initial llvm-ar tool, converted regression testsuite to dejagnu
254 D: Modulo scheduling in the SparcV9 backend
255 D: Release manager (1.7+)
258 E: sylvestre@debian.org
259 W: http://sylvestre.ledru.info/
260 W: http://llvm.org/apt/
261 D: Debian and Ubuntu packaging
262 D: Continuous integration with jenkins
265 E: alenhar2@cs.uiuc.edu
266 W: http://www.lenharth.org/~andrewl/
268 D: Sampling based profiling
272 D: PredicateSimplifier pass
274 N: Tony Linthicum, et. al.
275 E: tlinth@codeaurora.org
276 D: Backend for Qualcomm's Hexagon VLIW processor.
278 N: Bruno Cardoso Lopes
279 E: bruno.cardoso@gmail.com
280 W: http://www.brunocardoso.org
284 E: duraid@octopus.com.au
285 W: http://kinoko.c.u-tokyo.ac.jp/~duraid/
286 D: IA64 backend, BigBlock register allocator
289 E: rjmccall@apple.com
290 D: Clang semantic analysis and IR generation
293 E: michael.mccracken@gmail.com
294 D: Line number support for llvmgcc
296 N: Vladimir Merzliakov
298 D: Test suite fixes for FreeBSD
302 D: Added STI Cell SPU backend.
306 D: Support for implicit TLS model used with MS VC runtime
307 D: Dumping of Win64 EH structures
310 E: geek4civic@gmail.com
311 E: chapuni@hf.rim.or.jp
312 D: Cygwin and MinGW support.
316 N: Edward O'Callaghan
317 E: eocallaghan@auroraux.org
318 W: http://www.auroraux.org
319 D: Add Clang support with various other improvements to utils/NewNightlyTest.pl
320 D: Fix and maintain Solaris & AuroraUX support for llvm, various build warnings
321 D: and error clean ups.
325 D: Visual C++ compatibility fixes
327 N: Jakob Stoklund Olesen
329 D: Machine code verifier
331 D: Fast register allocator
332 D: Greedy register allocator
340 D: LTO tool, PassManager rewrite, Loop Pass Manager, Loop Rotate
341 D: GCC PCH Integration (llvm-gcc), llvm-gcc improvements
342 D: Optimizer improvements, Loop Index Split
345 E: peckw@wesleypeck.com
346 W: http://wesleypeck.com/
347 D: MicroBlaze backend
350 E: pichet2000@gmail.com
354 W: http://vladimir_prus.blogspot.com
356 D: Made inst_iterator behave like a proper iterator, LowerConstantExprs pass
359 E: kalle.rasikila@nokia.com
360 D: Some bugfixes to CellSPU
364 D: Cmake dependency chain and various bug fixes
367 E: alexr@leftfield.org
369 D: ARM calling conventions rewrite, hard float support
372 E: mcrosier@codeaurora.org
373 D: ARM fast-isel improvements
374 D: Performance monitoring
378 D: X86 code generation improvements, Loop Vectorizer.
381 E: roman@codedgers.com
387 D: Ada support in llvm-gcc
389 D: Exception handling improvements
390 D: Type legalizer rewrite
394 D: Graph coloring register allocator for the Sparc64 backend
396 N: Arnold Schwaighofer
397 E: arnold.schwaighofer@gmail.com
398 D: Tail call optimization for the x86 backend
402 D: Miscellaneous bug fixes
405 E: ashukla@cs.uiuc.edu
408 N: Michael J. Spencer
409 E: bigcheesegs@gmail.com
410 D: Shepherding Windows COFF support into MC.
411 D: Lots of Windows stuff.
414 E: rspencer@reidspencer.com
415 W: http://reidspencer.com/
416 D: Lots of stuff, see: http://wiki.llvm.org/index.php/User:Reid
420 W: http://atoker.com/
421 D: C++ frontend next generation standards implementation
424 E: craig.topper@gmail.com
425 D: X86 codegen and disassembler improvements. AVX2 support.
428 E: edwintorok@gmail.com
429 D: Miscellaneous bug fixes
433 D: C++ bugs filed, and C++ front-end bug fixes.
435 N: Lauro Ramos Venancio
436 E: lauro.venancio@indt.org.br
437 D: ARM backend improvements
438 D: Thread Local Storage implementation
442 E: isanbard@gmail.com
443 D: Release manager, IR Linker, LTO
447 E: bob.wilson@acm.org
448 D: Advanced SIMD (NEON) support in the ARM backend.