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AMDGPU/SI: Fix read2 merging into a super register.
2015-07-14 Matt ArsenaultAMDGPU/SI: Fix read2 merging into a super register.
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2015-07-13 Matt ArsenaultAMDGPU: Minor cleanups to always inline pass
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2015-07-10 Matt ArsenaultAMDGPU: Fix chains for memory ops dependent on argument...
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2015-07-10 Matt ArsenaultAMDGPU: Use requested chain when lowering arguments
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2015-07-10 Matt ArsenaultDAGCombiner: Assume invariant load cannot alias a store
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2015-07-09 Matt ArsenaultAMDGPU/R600: Return correct chain when lowering loads
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2015-07-06 Matt ArsenaultAMDGPU: Run SIInsertWaits as pre-emit pass
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2015-07-06 Matt ArsenaultAMDGPU/SI: Add debugging subtarget feature for DS offsets
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2015-07-03 Matt ArsenaultAMDGPU: Fix indentation of switch
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2015-06-28 Matt ArsenaultAMDGPU/SI: Fix extra space when printing v_div_fmas_*
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2015-06-26 Matt ArsenaultShow invariant loads in MMO dumping
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2015-06-25 Matt ArsenaultDAGCombiner: Use pop_back_val()
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2015-06-25 Matt ArsenaultDAGCombiner: Remove redundant check
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2015-06-23 Matt ArsenaultAMDGPU: Use getAsInteger instead of atoi
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2015-06-19 Matt ArsenaultAMDGPU: Fix filename in comment
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2015-06-19 Matt ArsenaultAMDGPU: Fix some places missed in rename
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2015-06-17 Matt ArsenaultAMDGPU: Change unreachable into reported error
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2015-06-16 Matt ArsenaultRevert "Revert "Fix merges of non-zero vector stores""
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2015-06-11 Matt ArsenaultSLSR: Pass address space to isLegalAddressingMode
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2015-06-11 Matt ArsenaultFix merges of non-zero vector stores
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2015-06-09 Matt ArsenaultImplement computeKnownBits for min/max nodes
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2015-06-09 Matt ArsenaultR600: Switch to using generic min / max nodes.
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2015-06-09 Matt ArsenaultMC: Add target hook to control symbol quoting
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2015-06-07 Matt ArsenaultSeparateConstOffsetFromGEP: Pass address space to isLegalAdd...
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2015-06-07 Matt ArsenaultMake NaryReassociate pass the address space to isLegalAddres...
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2015-06-07 Matt ArsenaultAdd isLegalAddressingMode address space argument to TTI
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2015-06-04 Matt ArsenaultR600/SI: Reimplement isLegalAddressingMode
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2015-06-04 Matt ArsenaultCodeGenPrepare: Provide address space to isLegalAddressingMode
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2015-06-04 Matt ArsenaultPass address space to isLegalAddressingMode in DAGCombiner
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2015-06-04 Matt ArsenaultR600/SI: Fix some cases for load / store of half
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2015-06-03 Matt ArsenaultR600/SI: Fix tests with triples in them
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2015-06-01 Matt ArsenaultR600/SI: Don't hardcode pointer type
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2015-06-01 Matt ArsenaultAdd address space argument to isLegalAddressingMode
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2015-05-26 Matt ArsenaultMake EmitFunctionHeader virtual
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2015-05-26 Matt ArsenaultForgot to add lit.local.cfg for new R600 directory
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2015-05-26 Matt ArsenaultCodeGenPrepare: Don't match addressing modes through...
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2015-05-24 Matt ArsenaultAdd target hook to allow merging stores of nonzero...
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2015-05-07 Matt ArsenaultR600: Fix comment that mentions AMDIL
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2015-05-06 Matt ArsenaultAdd ChangeTo* to MachineOperand for symbols
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2015-04-30 Matt ArsenaultFix typo
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2015-04-30 Matt ArsenaultMips: Remove dead declaration
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2015-04-30 Matt ArsenaultMachineVerifier: Don't crash if MachineOperand has...
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2015-04-26 Matt ArsenaultR600: Remove / merge redundant testcases
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2015-04-24 Matt ArsenaultR600/SI: Fix verifier error when producing v_madmk_f32
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2015-04-23 Matt ArsenaultRevert accidentally committed "MC: Allow targets to...
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2015-04-23 Matt ArsenaultR600/SI: Special case v_mov_b32 as really rematerializable
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2015-04-23 Matt ArsenaultMC: Allow targets to stop symbol name quoting
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2015-04-22 Matt ArsenaultR600: Fix always inline pass breaking noinline functions
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2015-03-23 Matt ArsenaultR600/SI: Merge tables for commuting
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2015-03-23 Matt ArsenaultR600/SI: Only use one range of isCommutable for compares
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2015-03-23 Matt ArsenaultR600/SI: Remove redundant unsetting of hasSideEffects
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2015-03-23 Matt ArsenaultR600/SI: Move hasSideEffects setting into VOPCX classes
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2015-03-23 Matt ArsenaultR600/SI: Allow commuting compares
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2015-03-23 Matt ArsenaultR600/SI: Use right class for cmpsx f64 instructions
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2015-03-23 Matt ArsenaultR600/SI: Remove cond operand to VOPCX classes
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2015-03-21 Matt ArsenaultR600: Cleanup test with multiple check prefixes
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2015-03-13 Matt ArsenaultR600/SI: Add test for min / max with immediate
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2015-02-21 Matt ArsenaultR600/SI: Use v_madmk_f32
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2015-02-21 Matt ArsenaultR600/SI: Try to use v_madak_f32
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2015-02-21 Matt ArsenaultR600/SI: Don't crash when getting immediate operand...
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2015-02-21 Matt ArsenaultR600/SI: Fix mad*k definitions
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2015-02-20 Matt ArsenaultR600/SI: Remove v_sub_f64 pseudo
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2015-02-20 Matt ArsenaultR600: Use new fmad node.
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2015-02-20 Matt ArsenaultAdd generic fmad DAG node.
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2015-02-18 Matt ArsenaultR600/SI: Rename dst encoding field to be consistent...
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2015-02-18 Matt ArsenaultR600/SI: Consistently capitalize encoding field names
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2015-02-18 Matt ArsenaultR600/SI: Set noNamedPositionallyEncodedOperands
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2015-02-18 Matt ArsenaultR600/SI: Fix src1_modifiers for class instructions
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2015-02-18 Matt ArsenaultR600/SI: Fix not setting clamp / omod for v_cndmask_b32_e64
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2015-02-18 Matt ArsenaultR600: Fix operand encoding error
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2015-02-18 Matt ArsenaultR600/SI: Fix encoding error from glc bit on VI SMRD...
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2015-02-18 Matt ArsenaultR600/SI: Fix operand encoding for flat instructions
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2015-02-18 Matt ArsenaultR600/SI: Fix error from vdst on no return atomics
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2015-02-18 Matt ArsenaultR600/SI: Add missing offset operand to buffer bothen
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2015-02-18 Matt ArsenaultR600/SI: Add missing soffset operand to global atomics
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2015-02-18 Matt ArsenaultR600/SI: Fix brace identation
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2015-02-14 Matt ArsenaultR600/SI: Implement correct f64 fdiv
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2015-02-14 Matt ArsenaultR600/SI: Use complex operand folding for div_scale
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2015-02-14 Matt ArsenaultR600/SI: Add tests for div_fmas with inline immediate...
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2015-02-14 Matt ArsenaultR600/SI: Fix implicit vcc operand to v_div_fmas_*
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2015-02-14 Matt ArsenaultR600/SI: Fix schedule model for v_div_scale_{f32|f64}
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2015-02-14 Matt ArsenaultR600/SI: Really fix size of VReg_1
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2015-02-14 Matt ArsenaultR600/SI: Rename encoding field to match docs for VOP3b
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2015-02-14 Matt ArsenaultR600/SI: Fix not encoding src2 for v_div_scale_{f32...
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2015-02-14 Matt ArsenaultR600/SI: Fix VOP3b encoding on VI
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2015-02-14 Matt ArsenaultR600/SI: Fix phys reg copies in SIFoldOperands
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2015-02-14 Matt ArsenaultR600/SI: Fix copies from SGPR to VCC
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2015-02-14 Matt ArsenaultR600/SI: Add hack to copy from a VGPR to VCC
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2015-02-14 Matt ArsenaultR600/SI: Fix size of VReg_1
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2015-02-13 Matt ArsenaultR600/SI: Remove handling of fpimm
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2015-02-13 Matt ArsenaultR600/SI: Allow f64 inline immediates in i64 operands
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2015-02-13 Matt ArsenaultR600/SI: Minor test scheduling fixes
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2015-02-13 Matt ArsenaultR600/SI: Remove unnecessary check for fpimm
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2015-02-05 Matt ArsenaultR600/SI: Fix i64 truncate to i1
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2015-02-05 Matt ArsenaultAdd addrspacecast node to tablegen
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2015-02-05 Matt ArsenaultAdd support for double / float to EndianStream
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2015-01-31 Matt ArsenaultFix typo
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2015-01-31 Matt ArsenaultR600/SI: Only select cvt_flr/cvt_rpi with no NaNs.
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2015-01-29 Matt ArsenaultR600/SI: Implement enableAggressiveFMAFusion
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2015-01-29 Matt ArsenaultR600/SI: Add subtarget feature for if f32 fma is fast
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C/C++ LLVM-based compilers that forbids OOTA behaviors